1 |
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2 | #ifndef _PHY_REG_
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3 | #define _PHY_REG_
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4 |
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5 | #include <target_syssvc.h>
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6 |
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7 | /* Generic MII registers */
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8 | #define MII_BMCR 0x00 /* Basic mode control register */
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9 | #define MII_BMSR 0x01 /* Basic mode status register */
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10 | #define MII_PHYSID1 0x02 /* PHYS ID 1 */
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11 | #define MII_PHYSID2 0x03 /* PHYS ID 2 */
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12 | #define MII_ADVERTISE 0x04 /* Advertisement control reg */
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13 | #define MII_LPA 0x05 /* Link partner ability reg */
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14 | #define MII_EXPANSION 0x06 /* Expansion register */
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15 | #define MII_CTRL1000 0x09 /* 1000BASE-T control */
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16 | #define MII_STAT1000 0x0a /* 1000BASE-T status */
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17 | #define MII_ESTATUS 0x0f /* Extended Status */
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18 | #define MII_SPECIFICCR 0x10 /* Specific control register */
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19 | #define MII_DCOUNTER 0x12 /* Disconnect counter */
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20 | #define MII_FCSCOUNTER 0x13 /* False carrier counter */
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21 | #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
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22 | #define MII_RERRCOUNTER 0x15 /* Receive error counter */
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23 | #define MII_SREVISION 0x16 /* Silicon revision */
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24 | #define MII_RESV1 0x17 /* Reserved... */
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25 | #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
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26 | #define MII_PHYADDR 0x19 /* PHY address */
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27 | #define MII_RESV2 0x1a /* Reserved... */
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28 | #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
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29 | #define MII_NCONFIG 0x1c /* Network interface config */
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30 |
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31 | /* Basic mode control register. */
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32 | #define BMCR_RESV 0x003f /* Unused... */
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33 | #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
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34 | #define BMCR_CTST 0x0080 /* Collision test */
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35 | #define BMCR_FULLDPLX 0x0100 /* Full duplex */
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36 | #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
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37 | #define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
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38 | #define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
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39 | #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
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40 | #define BMCR_SPEED100 0x2000 /* Select 100Mbps */
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41 | #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
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42 | #define BMCR_RESET 0x8000 /* Reset the DP83840 */
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43 | #define BMCR_SPEED10 0x0000 /* Select 10Mbps */
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44 |
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45 | /* Basic mode status register. */
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46 | #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
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47 | #define BMSR_JCD 0x0002 /* Jabber detected */
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48 | #define BMSR_LSTATUS 0x0004 /* Link status */
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49 | #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
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50 | #define BMSR_RFAULT 0x0010 /* Remote fault detected */
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51 | #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
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52 | #define BMSR_RESV 0x00c0 /* Unused... */
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53 | #define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
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54 | #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
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55 | #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
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56 | #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
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57 | #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
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58 | #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
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59 | #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
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60 | #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
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61 |
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62 | /* Advertisement control register. */
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63 | #define ADVERTISE_SLCT 0x001f /* Selector bits */
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64 | #define ADVERTISE_CSMA 0x0001 /* Only selector supported */
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65 | #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
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66 | #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
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67 | #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
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68 | #define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
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69 | #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
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70 | #define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
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71 | #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
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72 | #define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
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73 | #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
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74 | #define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
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75 | #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
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76 | #define ADVERTISE_RESV 0x1000 /* Unused... */
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77 | #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
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78 | #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
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79 | #define ADVERTISE_NPAGE 0x8000 /* Next page bit */
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80 |
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81 | /* 1000BASE-T Control register */
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82 | #define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
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83 | #define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
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84 |
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85 | /* Link partner ability register. */
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86 | #define LPA_SLCT 0x001f /* Same as advertise selector */
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87 | #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
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88 | #define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
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89 | #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
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90 | #define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
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91 | #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
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92 | #define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
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93 | #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
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94 | #define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym */
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95 | #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
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96 | #define LPA_PAUSE_CAP 0x0400 /* Can pause */
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97 | #define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
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98 | #define LPA_RESV 0x1000 /* Unused... */
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99 | #define LPA_RFAULT 0x2000 /* Link partner faulted */
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100 | #define LPA_LPACK 0x4000 /* Link partner acked us */
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101 | #define LPA_NPAGE 0x8000 /* Next page bit */
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102 |
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103 | #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
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104 | #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
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105 |
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106 | /* 1000BASE-T Status register */
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107 | #define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
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108 | #define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
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109 | #define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
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110 | #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
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111 |
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112 | /* Expansion register for auto-negotiation. */
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113 | #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
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114 | #define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
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115 | #define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
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116 | #define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
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117 | #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
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118 | #define EXPANSION_RESV 0xffe0 /* Unused... */
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119 |
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120 | #define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
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121 | #define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
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122 |
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123 | /* Specific control register */
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124 | #define SPECIFICCR_CROSS_MASK 0x0060 /* Crossover mode mask */
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125 | #define SPECIFICCR_CROSS_MDI 0x0000 /* Manual MDI configuration */
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126 | #define SPECIFICCR_CROSS_MDIX 0x0020 /* Manual MDIX configuration */
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127 | #define SPECIFICCR_CROSS_AUTO 0x0060 /* Enable automatic crossover */
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128 | #define SPECIFICCR_INT_DISABLE 0x1000 /* Interrupt Disable */
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129 |
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130 | /* Externded PHY Specific Control Register */
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131 | #define NWAYTEST_RGMII_RTC 0x0080 /* RGMII Receive Timing Control */
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132 | #define NWAYTEST_RGMII_TTC 0x0002 /* RGMII Transmit Timing Control */
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133 |
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134 | #endif /* _PHY_REG_ */
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