source: azure_iot_hub_f767zi/trunk/asp_baseplatform/monitor/arch/armv7m.c@ 457

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1/*
2 * TOPPERS/ASP Kernel
3 * Toyohashi Open Platform for Embedded Real-Time Systems/
4 * Advanced Standard Profile Kernel
5 *
6 * Copyright (C) 2003-2016 by Ryosuke Takeuchi
7 * GJ Business Division RICOH COMPANY,LTD. JAPAN
8 * Copyright (C) 2017-2019 by TOPPERS PROJECT Educational Working Group.
9 *
10 * 上記著作権者は，Free Software Foundation によって公表されている
11 * GNU General Public License の Version 2 に記述されている条件か，以
12 * 下の(1)～(4)の条件を満たす場合に限り，本ソフトウェア（本ソフトウェ
13 * アを改変したものを含む．以下同じ）を使用・複製・改変・再配布（以下，
14 * 利用と呼ぶ）することを無償で許諾する．
15 * (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
16 * 権表示，この利用条件および下記の無保証規定が，そのままの形でソー
17 * スコード中に含まれていること．
18 * (2) 本ソフトウェアを再利用可能なバイナリコード（リロケータブルオブ
19 * ジェクトファイルやライブラリなど）の形で利用する場合には，利用
20 * に伴うドキュメント（利用者マニュアルなど）に，上記の著作権表示，
21 * この利用条件および下記の無保証規定を掲載すること．
22 * (3) 本ソフトウェアを再利用不可能なバイナリコードの形または機器に組
23 * み込んだ形で利用する場合には，次のいずれかの条件を満たすこと．
24 * (a) 利用に伴うドキュメント（利用者マニュアルなど）に，上記の著作
25 * 権表示，この利用条件および下記の無保証規定を掲載すること．
26 * (b) 利用の形態を，別に定める方法によって，上記著作権者に報告する
27 * こと．
28 * (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
29 * 害からも，上記著作権者を免責すること．
30 *
31 * 本ソフトウェアは，無保証で提供されているものである．上記著作権者は，
32 * 本ソフトウェアに関して，その適用可能性も含めて，いかなる保証も行わ
33 * ない．また，本ソフトウェアの利用により直接的または間接的に生じたい
34 * かなる損害に関しても，その責任を負わない．
35 *
36 * @(#) $Id$
37 */
38
39/*
40 * TOPPERS/ASP用タスクモニタCPU依存プログラム．
41 *
42 */
43
44#include <itron.h>
45#include <sil.h>
46#include <stdio.h>
47#include "kernel_impl.h"
48#include "task.h"
49#include "task_expansion.h"
50#include "monitor.h"
51
52extern void dispatch_r(void);
53
54#define set_align(a, b) ((ulong_t)a & ~(b-1))
55
56/*
57 * レジスタの構造体
58 */
59typedef struct t_reg{
60 uint32_t r4;
61 uint32_t r5;
62 uint32_t r6;
63 uint32_t r7;
64 uint32_t r8;
65 uint32_t r9;
66 uint32_t r10;
67 uint32_t r11;
68 uint32_t pc;
69}T_REG;
70
71/*
72 * メモリのマッピング定義構造体
73 */
74
75typedef struct t_memdef{
76 uint32_t mstart;
77 uint32_t mend;
78 uint8_t mtype;
79 uint8_t mstate;
80}T_MEMDEF;
81
82/*
83 * ARMv7のメモリマッピング
84 */
85
86static T_MEMDEF const memdefine[] = {
87#if defined(TOPPERS_CQ_FRK_FM3)
88 {0x00000000, 0x000FFFFF, MEMORY_AREA, MREAD_ONLY },
89 {0x1FFF0000, 0x201EFFFF, MEMORY_AREA, MREAD_WRITE},
90 {0x40000000, 0x400FFFFF, PORT_AREA, MREAD_WRITE},
91#elif defined(TOPPERS_STM32F091_NUCLEO64) /* ARMV6m */
92 {0x08000000, 0x0803FFFF, MEMORY_AREA, MREAD_ONLY },
93 {0x20000000, 0x20007FFF, MEMORY_AREA, MREAD_WRITE},
94 {0x40000000, 0x50060FFF, PORT_AREA, MREAD_WRITE},
95 {0xA0000000, 0xBFFFFFFF, PORT_AREA, MREAD_WRITE},
96#elif defined(TOPPERS_STM32L073_NUCLEO64) || defined(TOPPERS_STM32LORA_DISCOVERY) /* ARMV6m */
97 {0x08000000, 0x0802FFFF, MEMORY_AREA, MREAD_ONLY },
98 {0x20000000, 0x20004FFF, MEMORY_AREA, MREAD_WRITE},
99 {0x40000000, 0x50060FFF, PORT_AREA, MREAD_WRITE},
100 {0xA0000000, 0xBFFFFFFF, PORT_AREA, MREAD_WRITE},
101#elif defined(TOPPERS_STM32G071_NUCLEO64) /* ARMV6m */
102 {0x08000000, 0x0801FFFF, MEMORY_AREA, MREAD_ONLY },
103 {0x20000000, 0x20008FFF, MEMORY_AREA, MREAD_WRITE},
104 {0x40000000, 0x50060FFF, PORT_AREA, MREAD_WRITE},
105 {0xA0000000, 0xBFFFFFFF, PORT_AREA, MREAD_WRITE},
106#elif defined(TOPPERS_STM32L476_NUCLEO64) || defined(TOPPERS_STM32L476_DISCOVERY)
107 {0x08000000, 0x080FFFFF, MEMORY_AREA, MREAD_ONLY },
108 {0x10000000, 0x10007FFF, MEMORY_AREA, MREAD_WRITE},
109 {0x20000000, 0x20017FFF, MEMORY_AREA, MREAD_WRITE},
110 {0x40000000, 0x50060FFF, PORT_AREA, MREAD_WRITE},
111 {0x90000000, 0xBFFFFFFF, PORT_AREA, MREAD_WRITE},
112#elif defined(TOPPERS_STM32L4R5_NUCLEO144)
113 {0x08000000, 0x080FFFFF, MEMORY_AREA, MREAD_ONLY },
114 {0x10000000, 0x10007FFF, MEMORY_AREA, MREAD_WRITE},
115 {0x20000000, 0x2009FFFF, MEMORY_AREA, MREAD_WRITE},
116 {0x40000000, 0x6FFFFFFF, PORT_AREA, MREAD_WRITE},
117 {0x80000000, 0xBFFFFFFF, PORT_AREA, MREAD_WRITE},
118#elif defined(TOPPERS_STM32WB55_NUCLEO)
119 {0x08000000, 0x080CBFFF, MEMORY_AREA, MREAD_ONLY },
120 {0x20000000, 0x2003FFFF, MEMORY_AREA, MREAD_WRITE},
121 {0x40000000, 0x6FFFFFFF, PORT_AREA, MREAD_WRITE},
122 {0x80000000, 0xBFFFFFFF, PORT_AREA, MREAD_WRITE},
123#elif defined(TOPPERS_STM32F4_DISCOVERY) || defined(TOPPERS_STM32_E407)
124 {0x08000000, 0x080FFFFF, MEMORY_AREA, MREAD_ONLY },
125 {0x20000000, 0x2001FFFF, MEMORY_AREA, MREAD_WRITE},
126 {0x40000000, 0x50060FFF, PORT_AREA, MREAD_WRITE},
127 {0xA0000000, 0xBFFFFFFF, PORT_AREA, MREAD_WRITE},
128#elif defined(TOPPERS_STM32F401_NUCLEO)
129 {0x08000000, 0x0807FFFF, MEMORY_AREA, MREAD_ONLY },
130 {0x20000000, 0x20017FFF, MEMORY_AREA, MREAD_WRITE},
131 {0x40000000, 0x50060FFF, PORT_AREA, MREAD_WRITE},
132 {0xA0000000, 0xBFFFFFFF, PORT_AREA, MREAD_WRITE},
133#elif defined(TOPPERS_STM32F446_NUCLEO64) || defined(TOPPERS_STM32F446_NUCLEO144)
134 {0x08000000, 0x0807FFFF, MEMORY_AREA, MREAD_ONLY },
135 {0x20000000, 0x2001FFFF, MEMORY_AREA, MREAD_WRITE},
136 {0x40000000, 0x50060FFF, PORT_AREA, MREAD_WRITE},
137 {0xA0000000, 0xBFFFFFFF, PORT_AREA, MREAD_WRITE},
138#elif defined(TOPPERS_STM32F429_BOARD)
139 {0x08000000, 0x080FFFFF, MEMORY_AREA, MREAD_ONLY },
140 {0x20000000, 0x2002FFFF, MEMORY_AREA, MREAD_WRITE},
141 {0x40000000, 0x50060FFF, PORT_AREA, MREAD_WRITE},
142 {0xA0000000, 0xBFFFFFFF, PORT_AREA, MREAD_WRITE},
143#elif defined(TOPPERS_STM32G474_NUCLEO64)
144 {0x08000000, 0x0807FFFF, MEMORY_AREA, MREAD_ONLY },
145 {0x10000000, 0x10007FFF, MEMORY_AREA, MREAD_WRITE},
146 {0x20000000, 0x20017FFF, MEMORY_AREA, MREAD_WRITE},
147 {0x40000000, 0xAFFFFFFF, PORT_AREA, MREAD_WRITE},
148#elif defined(TOPPERS_STM32G431_NUCLEO64)
149 {0x08000000, 0x0801FFFF, MEMORY_AREA, MREAD_ONLY },
150 {0x10000000, 0x10002FFF, MEMORY_AREA, MREAD_WRITE},
151 {0x20000000, 0x200057FF, MEMORY_AREA, MREAD_WRITE},
152 {0x40000000, 0xAFFFFFFF, PORT_AREA, MREAD_WRITE},
153#elif defined(TOPPERS_STM32F723_DISCOVERY)
154 {0x00000000, 0x0003FFFF, MEMORY_AREA, MREAD_WRITE},
155 {0x08000000, 0x0807FFFF, MEMORY_AREA, MREAD_ONLY },
156 {0x20000000, 0x2003FFFF, MEMORY_AREA, MREAD_WRITE},
157 {0x40000000, 0x50060FFF, PORT_AREA, MREAD_WRITE},
158 {0x90000000, 0xBFFFFFFF, PORT_AREA, MREAD_WRITE},
159 {0xC0000000, 0xC07FFFFF, MEMORY_AREA, MREAD_WRITE},
160#elif defined(TOPPERS_STM32F7_DISCOVERY) ||defined(TOPPERS_STM32F746_NUCLEO144)
161 {0x00000000, 0x0003FFFF, MEMORY_AREA, MREAD_WRITE},
162 {0x08000000, 0x080FFFFF, MEMORY_AREA, MREAD_ONLY },
163 {0x20000000, 0x2004FFFF, MEMORY_AREA, MREAD_WRITE},
164 {0x40000000, 0x50060FFF, PORT_AREA, MREAD_WRITE},
165 {0x90000000, 0xBFFFFFFF, PORT_AREA, MREAD_WRITE},
166 {0xC0000000, 0xC07FFFFF, MEMORY_AREA, MREAD_WRITE},
167#elif defined(TOPPERS_STM32F769_DISCOVERY) || defined(TOPPERS_STM32F767_NUCLEO144)
168 {0x00000000, 0x0003FFFF, MEMORY_AREA, MREAD_WRITE},
169 {0x08000000, 0x081FFFFF, MEMORY_AREA, MREAD_ONLY },
170 {0x20000000, 0x2007FFFF, MEMORY_AREA, MREAD_WRITE},
171 {0x40000000, 0x50060FFF, PORT_AREA, MREAD_WRITE},
172 {0x90000000, 0xBFFFFFFF, PORT_AREA, MREAD_WRITE},
173 {0xC0000000, 0xC07FFFFF, MEMORY_AREA, MREAD_WRITE},
174#elif defined(TOPPERS_STM32H743_NUCLEO144)
175 {0x08000000, 0x081FFFFF, MEMORY_AREA, MREAD_ONLY },
176 {0x20000000, 0x0001FFFF, MEMORY_AREA, MREAD_WRITE},
177 {0x24000000, 0x2407FFFF, MEMORY_AREA, MREAD_WRITE},
178 {0x30000000, 0x30047FFF, MEMORY_AREA, MREAD_WRITE},
179 {0x38000000, 0x3800FFFF, MEMORY_AREA, MREAD_WRITE},
180 {0x40000000, 0x5802FFFF, PORT_AREA, MREAD_WRITE},
181 {0x90000000, 0xBFFFFFFF, PORT_AREA, MREAD_WRITE},
182#elif defined(NRF52832)
183 {0x00000000, 0x0007FFFF, MEMORY_AREA, MREAD_ONLY },
184 {0x10000000, 0x1FFFFFFF, PORT_AREA, MREAD_WRITE},
185 {0x20000000, 0x2000FFFF, MEMORY_AREA, MREAD_WRITE},
186 {0x40000000, 0x5007FFFF, PORT_AREA, MREAD_WRITE},
187 {0xF0000000, 0xF1FFFFFF, PORT_AREA, MREAD_WRITE},
188#elif defined(NRF52810)
189 {0x00000000, 0x0002FFFF, MEMORY_AREA, MREAD_ONLY },
190 {0x10000000, 0x1FFFFFFF, PORT_AREA, MREAD_WRITE},
191 {0x20000000, 0x20005FFF, MEMORY_AREA, MREAD_WRITE},
192 {0x40000000, 0x5007FFFF, PORT_AREA, MREAD_WRITE},
193 {0xF0000000, 0xF1FFFFFF, PORT_AREA, MREAD_WRITE},
194#else
195#error "No support board type in ARMV7-M groups."
196#endif
197 {0xE0000000, 0xFFFFFFFF, PORT_AREA, MREAD_WRITE}
198};
199
200static T_REG sreg;
201
202/******************************************************************************
203 * ハードウェアポート属性参照関数
204 ******************************************************************************/
205/*
206 * アドレスからメモリ領域属性を取り出す
207 * mode=0:領域の型
208 * mode=1:読み取り書き込み属性
209 */
210
211char
212getMemoryType(ulong_t address, int_t mode)
213{
214 int_t count = sizeof(memdefine) / sizeof(T_MEMDEF);
215 int_t i;
216
217 for(i = 0 ; i < count ; i++){
218 if(address >= memdefine[i].mstart && address <= memdefine[i].mend){
219 if(mode == 0)
220 return memdefine[i].mtype;
221 else
222 return memdefine[i].mstate;
223 }
224 }
225 return NONE_AREA;
226}
227
228/*
229 * アドレスからアライン後のアドレスを取り出す
230 */
231
232ulong_t
233MonAlignAddress(ulong_t address)
234{
235 return address;
236}
237
238/******************************************************************************
239 * メモリアクセス用関数
240 ******************************************************************************/
241/*
242 * メモリ領域に対する読み出し関数
243 * 領域のチェックを行い、エラーならゼロを返す
244 */
245int_t
246MemoryRead(ulong_t address, intptr_t p, int_t type)
247{
248 int_t len;
249
250 switch(getMemoryType(address, 0)){
251 case PORT_AREA:
252 if(type == 2){
253 len = 2;
254 *((UH *)p) = sil_reh_mem((VP)address);
255 }
256 else if(type == 4){
257 len = 4;
258 *((UW *)p) = sil_rew_mem((VP)address);
259 }
260 else{
261 len = 1;
262 *((UB *)p) = sil_reb_mem((VP)address);
263 }
264 break;
265 case MEMORY_AREA:
266 if(type == 2){
267 len = 2;
268 *((UH *)p) = *((UH *)set_align(address, len));
269 }
270 else if(type == 4){
271 len = 4;
272 *((UW *)p) = *((UW *)set_align(address, len));
273 }
274 else{
275 len = 1;
276 *((UB *)p) = *((UB *)address);
277 }
278 break;
279 default:
280 len = 0;
281 break;
282 }
283 return len;
284}
285
286/*
287 * メモリ領域に対する書き込み関数
288 * 領域のチェックを行い、エラーならゼロを返す
289 */
290int_t
291MemoryWrite(ulong_t address, intptr_t p, int_t type)
292{
293 int_t len;
294
295 switch(getMemoryType(address, 0)){
296 case PORT_AREA:
297 if(type == 2){
298 len = 2;
299 address = set_align(address, len);
300 sil_wrh_mem((VP)address, *((UH *)p));
301 }
302 else if(type == 4){
303 len = 4;
304 address = set_align(address, len);
305 sil_wrw_mem((VP)address, *((UW *)p));
306 }
307 else{
308 len = 1;
309 sil_wrb_mem((VP)address, *((UB *)p));
310 }
311 break;
312 case MEMORY_AREA:
313 if(getMemoryType(address, 1) == MREAD_ONLY){
314 len = 0;
315 }
316 else if(type == 2){
317 len = 2;
318 *((UH *)address) = *((UH *)set_align(p, len));
319 }
320 else if(type == 4){
321 len = 4;
322 *((UW *)address) = *((UW *)set_align(p, len));
323 }
324 else{
325 len = 1;
326 *((UB *)address) = *((UB *)p);
327 }
328 break;
329 default:
330 len = 0;
331 break;
332 }
333 return len;
334}
335
336/******************************************************************************
337 * モニタ用関数
338 ******************************************************************************/
339/*
340 * レジスタ内容の表示
341 */
342void
343display_registers(ID tskid)
344{
345 ER ercd;
346 T_RTST rtst;
347
348 ercd = ref_tst(tskid, &rtst);
349 if(ercd == E_OK){
350 if(rtst.tskpc == (FP)dispatch_r){
351 sreg = *((T_REG *)rtst.tsksp);
352 printf(" PC =%08lx SP =%08x\n", (long)sreg.pc, (UW)((long)rtst.tsksp+sizeof(T_REG)));
353 printf(" R4 =%08x R5 =%08x R6 =%08x R7 =%08x\n", sreg.r4, sreg.r5, sreg.r6, sreg.r7);
354 printf(" R8 =%08x R9 =%08x R10 =%08x R11 =%08x\n", sreg.r8, sreg.r9, sreg.r10, sreg.r11);
355 printf(" %08lx %04x\n", (long)sreg.pc, *((UH*)(sreg.pc & ~1)));
356 return;
357 }
358 else if(rtst.tskstat == TTS_DMT){
359 printf(" wait in activate_r() !!\n");
360 return;
361 }
362 }
363 printf(" wait in dispatch() !!\n");
364}
365
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