[388] | 1 | /*
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| 2 | * TINET (TCP/IP Protocol Stack)
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| 3 | *
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| 4 | * Copyright (C) 2001-2009 by Dep. of Computer Science and Engineering
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| 5 | * Tomakomai National College of Technology, JAPAN
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| 6 | * Copyright (C) 2014-2015 Cores Co., Ltd. Japan
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| 7 | *
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| 8 | * ä¸è¨èä½æ¨©è
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| 9 | ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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| 10 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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| 11 | * å¤ã»åé
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| 12 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 13 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 14 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 15 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 16 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 17 | * ç¨ã§ããå½¢ã§åé
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| 18 | å¸ããå ´åã«ã¯ï¼åé
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| 19 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 20 | * è
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| 21 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 22 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 23 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 24 | * ç¨ã§ããªãå½¢ã§åé
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| 25 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 26 | * ã¨ï¼
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| 27 | * (a) åé
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| 28 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 29 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 30 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 31 | * (b) åé
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| 32 | å¸ã®å½¢æ
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| 33 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 34 | * å ±åãããã¨ï¼
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| 35 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 36 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 37 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 38 | 責ãããã¨ï¼
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| 39 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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| 40 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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| 41 | ããã³TOPPERSããã¸ã§ã¯ãã
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| 42 | * å
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| 43 | 責ãããã¨ï¼
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| 44 | *
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| 45 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 46 | ã
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| 47 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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| 48 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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| 49 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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| 50 | * ã®è²¬ä»»ãè² ããªãï¼
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| 51 | *
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| 52 | * @(#) $Id: if_rx62nreg.h 388 2019-05-22 11:25:18Z coas-nagasima $
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| 53 | */
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| 54 |
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| 55 | #ifndef RX62NRegH
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| 56 | #define RX62NRegH
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| 57 |
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| 58 | #include "t_stddef.h"
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| 59 |
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| 60 | #define EDMAC_EDMR ((uint32_t *)0x000C0000) /* EDMACã¢ã¼ãã¬ã¸ã¹ã¿ */
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| 61 | #define EDMAC_EDMR_SWR_BIT 0x00000001
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| 62 | #define EDMAC_EDMR_DE_BIT 0x00000040
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| 63 |
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| 64 | #define EDMAC_EDTRR ((uint32_t *)0x000C0008) /* EDMACéä¿¡è¦æ±ã¬ã¸ã¹ã¿ */
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| 65 | #define EDMAC_EDTRR_TR 0x00000001
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| 66 |
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| 67 | #define EDMAC_EDRRR ((uint32_t *)0x000C0010) /* EDMACåä¿¡è¦æ±ã¬ã¸ã¹ã¿ */
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| 68 | #define EDMAC_EDRRR_RR 0x00000001
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| 69 |
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| 70 | #define EDMAC_TDLAR ((uint32_t *)0x000C0018) /* éä¿¡ãã£ã¹ã¯ãªãã¿ãªã¹ãå
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| 71 | é ã¢ãã¬ã¹ã¬ã¸ã¹ã¿ */
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| 72 | #define EDMAC_RDLAR ((uint32_t *)0x000C0020) /* åä¿¡ãã£ã¹ã¯ãªãã¿ãªã¹ãå
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| 73 | é ã¢ãã¬ã¹ã¬ã¸ã¹ã¿ */
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| 74 |
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| 75 | #define EDMAC_EESR ((uint32_t *)0x000C0028) /* ETHERC/EDMACã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ */
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| 76 | #define EDMAC_EESR_FROF 0x00010000
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| 77 | #define EDMAC_EESR_RDE 0x00020000
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| 78 | #define EDMAC_EESR_FR 0x00040000
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| 79 | #define EDMAC_EESR_TC 0x00200000
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| 80 | #define EDMAC_EESR_TWB 0x40000000
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| 81 |
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| 82 | #define EDMAC_EESIPR ((uint32_t *)0x000C0030) /* ETHERC/EDMACã¹ãã¼ã¿ã¹å²ãè¾¼ã¿è¨±å¯ã¬ã¸ã¹ã¿ */
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| 83 | #define EDMAC_EESIPR_RMAFIP 0x00000080
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| 84 | #define EDMAC_EESIPR_FROFIP 0x00010000
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| 85 | #define EDMAC_EESIPR_RDEIP 0x00020000
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| 86 | #define EDMAC_EESIPR_FRIP 0x00040000
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| 87 | #define EDMAC_EESIPR_TCIP 0x00200000
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| 88 | #define EDMAC_EESIPR_TWBIP 0x40000000
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| 89 |
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| 90 | #define EDMAC_TRSCER ((uint32_t *)0x000C0038) /* éåä¿¡ã¹ãã¼ã¿ã¹ã³ãã¼æ示ã¬ã¸ã¹ã¿ */
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| 91 | #define EDMAC_RMFCR ((uint32_t *)0x000C0040) /* ãã¹ããã¬ã¼ã ã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ */
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| 92 | #define EDMAC_TFTR ((uint32_t *)0x000C0048) /* éä¿¡FIFOãããå¤æå®ã¬ã¸ã¹ã¿ */
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| 93 | #define EDMAC_FDR ((uint32_t *)0x000C0050) /* FIFO容éæå®ã¬ã¸ã¹ã¿ */
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| 94 | #define EDMAC_RMCR ((uint32_t *)0x000C0058) /* åä¿¡æ¹å¼å¶å¾¡ã¬ã¸ã¹ã¿ */
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| 95 | #define EDMAC_TFUCR ((uint32_t *)0x000C0064) /* éä¿¡FIFOã¢ã³ãã©ã³ã«ã¦ã³ã */
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| 96 | #define EDMAC_RFOCR ((uint32_t *)0x000C0068) /* åä¿¡FIFOãªã¼ãããã¼ã«ã¦ã³ã */
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| 97 | #define EDMAC_IOSR ((uint32_t *)0x000C006C) /* åå¥åºåä¿¡å·è¨å®ã¬ã¸ã¹ã¿ */
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| 98 | #define EDMAC_FCFTR ((uint32_t *)0x000C0070) /* ããã¼å¶å¾¡éå§FIFOãããå¤è¨å®ã¬ã¸ã¹ã¿ */
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| 99 | #define EDMAC_RPADIR ((uint32_t *)0x000C0078) /* åä¿¡ãã¼ã¿ããã£ã³ã°æ¿å
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| 100 | ¥è¨å®ã¬ã¸ã¹ã¿ */
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| 101 | #define EDMAC_TRIMD ((uint32_t *)0x000C007C) /* éä¿¡å²ãè¾¼ã¿è¨å®ã¬ã¸ã¹ã¿ */
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| 102 | #define EDMAC_RBWAR ((uint32_t *)0x000C00C8) /* åä¿¡ãããã¡ã©ã¤ãã¢ãã¬ã¹ã¬ã¸ã¹ã¿ */
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| 103 | #define EDMAC_RDFAR ((uint32_t *)0x000C00CC) /* åä¿¡ãã£ã¹ã¯ãªãã¿ãã§ããã¢ãã¬ã¹ã¬ã¸ã¹ã¿ */
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| 104 | #define EDMAC_TBRAR ((uint32_t *)0x000C00D4) /* éä¿¡ãããã¡ãªã¼ãã¢ãã¬ã¹ã¬ã¸ã¹ã¿ */
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| 105 | #define EDMAC_TDFAR ((uint32_t *)0x000C00D8) /* éä¿¡ãã£ã¹ã¯ãªãã¿ãã§ããã¢ãã¬ã¹ã¬ã¸ã¹ã¿ */
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| 106 |
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| 107 | #define ETHERC_ECMR ((uint32_t *)0x000C0100) /* ETHERCã¢ã¼ãã¬ã¸ã¹ã¿ */
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| 108 | #define ETHERC_ECMR_PRM 0x00000001
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| 109 | #define ETHERC_ECMR_DM 0x00000002
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| 110 | #define ETHERC_ECMR_RTM 0x00000004
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| 111 | #define ETHERC_ECMR_TE 0x00000020
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| 112 | #define ETHERC_ECMR_RE 0x00000040
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| 113 |
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| 114 | #define ETHERC_RFLR ((uint32_t *)0x000C0108) /* åä¿¡ãã¬ã¼ã é·ä¸éã¬ã¸ã¹ã¿ */
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| 115 | #define ETHERC_ECSR ((uint32_t *)0x000C0110) /* ETHERCã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ */
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| 116 | #define ETHERC_ECSR_LCHNG 0x00000004
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| 117 | #define ETHERC_ECSIPR ((uint32_t *)0x000C0118) /* ETHERCå²ãè¾¼ã¿è¨±å¯ã¬ã¸ã¹ã¿ */
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| 118 | #define ETHERC_ECSIPR_LCHNGIP 0x00000004
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| 119 | #define ETHERC_PIR ((uint32_t *)0x000C0120) /* PHYé¨ã¤ã³ã¿ãã§ã¼ã¹ã¬ã¸ã¹ã¿ */
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| 120 | #define ETHERC_PIR_MDC 0x00000001
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| 121 | #define ETHERC_PIR_MMD 0x00000002
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| 122 | #define ETHERC_PIR_MDO 0x00000004
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| 123 | #define ETHERC_PIR_MDI 0x00000008
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| 124 |
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| 125 | #define ETHERC_PSR ((uint32_t *)0x000C0128) /* PHYé¨ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ */
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| 126 | #define ETHERC_PSR_LMON 0x00000001
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| 127 |
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| 128 | #define ETHERC_RDMLR ((uint32_t *)0x000C0140) /* ä¹±æ°çæã«ã¦ã³ã¿ä¸éå¤è¨å®ã¬ã¸ã¹ã¿ */
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| 129 | #define ETHERC_IPGR ((uint32_t *)0x000C0150) /* IPGè¨å®ã¬ã¸ã¹ã¿ */
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| 130 | #define ETHERC_APR ((uint32_t *)0x000C0154) /* èªåPAUSEãã¬ã¼ã è¨å®ã¬ã¸ã¹ã¿ */
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| 131 | #define ETHERC_MPR ((uint32_t *)0x000C0158) /* æåPAUSEãã¬ã¼ã è¨å®ã¬ã¸ã¹ã¿ */
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| 132 | #define ETHERC_RFCF ((uint32_t *)0x000C0160) /* åä¿¡PAUSEãã¬ã¼ã ã«ã¦ã³ã¿ */
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| 133 | #define ETHERC_TPAUSER ((uint32_t *)0x000C0164) /* èªåPAUSEãã¬ã¼ã åéåæ°è¨å®ã¬ã¸ã¹ã¿ */
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| 134 | #define ETHERC_TPAUSECR ((uint32_t *)0x000C0168) /* PAUSEãã¬ã¼ã åéåæ°ã«ã¦ã³ã¿ */
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| 135 | #define ETHERC_BCFRR ((uint32_t *)0x000C016C) /* Broadcastãã¬ã¼ã åä¿¡åæ°è¨å®ã¬ã¸ã¹ã¿ */
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| 136 | #define ETHERC_MAHR ((uint32_t *)0x000C01C0) /* MACã¢ãã¬ã¹ä¸ä½è¨å®ã¬ã¸ã¹ã¿ */
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| 137 | #define ETHERC_MALR ((uint32_t *)0x000C01C8) /* MACã¢ãã¬ã¹ä¸ä½è¨å®ã¬ã¸ã¹ã¿ */
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| 138 | #define ETHERC_TROCR ((uint32_t *)0x000C01D0) /* éä¿¡ãªãã©ã¤ãªã¼ãã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ */
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| 139 | #define ETHERC_CDCR ((uint32_t *)0x000C01D4) /* é
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| 140 | 延è¡çªæ¤åºã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ */
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| 141 | #define ETHERC_LCCR ((uint32_t *)0x000C01D8) /* ãã£ãªã¢æ¶å¤±ã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ */
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| 142 | #define ETHERC_CNDCR ((uint32_t *)0x000C01DC) /* ãã£ãªã¢æªæ¤åºã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ */
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| 143 | #define ETHERC_CEFCR ((uint32_t *)0x000C01E4) /* CRCã¨ã©ã¼ãã¬ã¼ã åä¿¡ã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ */
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| 144 | #define ETHERC_FRECR ((uint32_t *)0x000C01E8) /* ãã¬ã¼ã åä¿¡ã¨ã©ã¼ã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ */
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| 145 | #define ETHERC_TSFRCR ((uint32_t *)0x000C01EC) /* 64ãã¤ãæªæºãã¬ã¼ã åä¿¡ã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ */
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| 146 | #define ETHERC_TLFRCR ((uint32_t *)0x000C01F0) /* æå®ãã¤ãè¶
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| 147 | ãã¬ã¼ã åä¿¡ã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ */
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| 148 | #define ETHERC_RFCR ((uint32_t *)0x000C01F4) /* 端æ°ããããã¬ã¼ã åä¿¡ã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ */
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| 149 | #define ETHERC_MAFCR ((uint32_t *)0x000C01F8) /* ãã«ããã£ã¹ãã¢ãã¬ã¹ãã¬ã¼ã åä¿¡ã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ */
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| 150 |
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| 151 | /* éä¿¡ãã£ã¹ã¯ãªãã¿ */
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| 152 | typedef struct t_rx62n_tx_desc {
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| 153 | uint32_t tfs : 26;
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| 154 | uint32_t twbi : 1;
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| 155 | uint32_t tfe : 1;
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| 156 | uint32_t tfp : 2;
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| 157 | uint32_t tdle : 1;
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| 158 | uint32_t tact : 1;
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| 159 | uint32_t : 16;
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| 160 | uint32_t tbl : 16;
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| 161 | uint32_t tba;
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| 162 | uint32_t binding;
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| 163 | } T_RX62N_TX_DESC;
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| 164 |
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| 165 | /* åä¿¡ãã£ã¹ã¯ãªãã¿ */
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| 166 | typedef struct t_rx62n_rx_desc {
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| 167 | uint32_t rfs : 27;
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| 168 | uint32_t rfe : 1;
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| 169 | uint32_t rfp : 2;
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| 170 | uint32_t rdle : 1;
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| 171 | uint32_t ract : 1;
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| 172 | uint32_t rfl : 16;
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| 173 | uint32_t rbl : 16;
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| 174 | uint32_t rba;
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| 175 | uint32_t binding;
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| 176 | } T_RX62N_RX_DESC;
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| 177 |
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| 178 | #endif /* RX62NRegH */
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