[388] | 1 | /*
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| 2 | * TOPPERS/ASP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Advanced Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | * Copyright (C) 2003-2004 by Naoki Saito
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| 9 | * Nagoya Municipal Industrial Research Institute, JAPAN
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| 10 | * Copyright (C) 2003-2004 by Platform Development Center
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| 11 | * RICOH COMPANY,LTD. JAPAN
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| 12 | * Copyright (C) 2008-2010 by Witz Corporation, JAPAN
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| 13 | * Copyright (C) 2013 by Mitsuhiro Matsuura
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| 14 | * Copyright (C) 2017 by Cores Co., Ltd. Japan
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| 15 | *
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| 16 | * ä¸è¨èä½æ¨©è
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| 17 | ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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| 18 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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| 19 | * å¤ã»åé
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| 20 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 21 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 22 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 23 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 24 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 25 | * ç¨ã§ããå½¢ã§åé
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| 26 | å¸ããå ´åã«ã¯ï¼åé
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| 27 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 28 | * è
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| 29 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 30 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 31 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 32 | * ç¨ã§ããªãå½¢ã§åé
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| 33 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 34 | * ã¨ï¼
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| 35 | * (a) åé
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| 36 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 37 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 38 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 39 | * (b) åé
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| 40 | å¸ã®å½¢æ
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| 41 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 42 | * å ±åãããã¨ï¼
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| 43 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 44 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 45 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 46 | 責ãããã¨ï¼
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| 47 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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| 48 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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| 49 | ããã³TOPPERSããã¸ã§ã¯ãã
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| 50 | * å
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| 51 | 責ãããã¨ï¼
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| 52 | *
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| 53 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 54 | ã
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| 55 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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| 56 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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| 57 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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| 58 | * ã®è²¬ä»»ãè² ããªãï¼
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| 59 | *
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| 60 | * @(#) $Id: target_timer.c 388 2019-05-22 11:25:18Z coas-nagasima $
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| 61 | */
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| 62 |
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| 63 | /*
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| 64 | * ã¿ã¤ããã©ã¤ãï¼GR-SAKURAç¨ï¼
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| 65 | */
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| 66 |
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| 67 | #include "kernel_impl.h"
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| 68 | #include "time_event.h"
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| 69 | #include <sil.h>
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| 70 | #include "target_timer.h"
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| 71 | #ifdef TOPPERS_SUPPORT_OVRHDR
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| 72 | #include "overrun.h"
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| 73 | #endif /* TOPPERS_SUPPORT_OVRHDR */
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| 74 |
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| 75 | /*
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| 76 | * ä¸ä½ã¿ã¤ãã½ããã«ã¦ã³ã¿
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| 77 | */
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| 78 | static uint16_t elapse_upper_timer = 0;
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| 79 |
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| 80 | /*
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| 81 | * ä¸ä¸ä½ã¿ã¤ãè¨å®ã«ã¦ã³ã¿
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| 82 | */
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| 83 | static uint16_t timer_upper_set_count = 0, timer_lower_set_count = 0;
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| 84 |
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| 85 | #ifdef TOPPERS_SUPPORT_OVRHDR
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| 86 |
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| 87 | /* ãªã¼ãã©ã³ä¸ä¸ä½ã¿ã¤ãè¨å®ã«ã¦ã³ã¿ */
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| 88 | static uint16_t timer_ovr_upper_set_count = 0, timer_ovr_lower_set_count = 0;
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| 89 |
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| 90 | /* ãªã¼ãã©ã³ã¿ã¤ãå®è¡ä¸ãã©ã° */
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| 91 | static bool_t timer_ovr_running_flg = false;
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| 92 |
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| 93 | /* ãªã¼ãã©ã³ã¿ã¤ãéå§æHRTã¿ã¤ãå¤ */
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| 94 | static HRTCNT timer_ovr_hrt_backup;
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| 95 |
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| 96 | /* ãªã¼ãã©ã³ã¿ã¤ãè¨å®æé */
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| 97 | static PRCTIM timer_ovr_ovrtim_backup;
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| 98 |
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| 99 | /*
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| 100 | * ãªã¼ãã©ã³ã¿ã¤ãå²è¾¼ã¿è¦æ±ã®ã¯ãªã¢
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| 101 | */
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| 102 | Inline void
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| 103 | target_ovrtimer_int_clear()
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| 104 | {
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| 105 | clear_int(INTNO_TIMER2);
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| 106 | }
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| 107 |
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| 108 | #endif /* TOPPERS_SUPPORT_OVRHDR */
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| 109 |
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| 110 | /*
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| 111 | * ã¿ã¤ãã®åæåå¦ç
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| 112 | */
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| 113 | void
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| 114 | target_timer_initialize(intptr_t exinf)
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| 115 | {
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| 116 | /*
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| 117 | * ã¢ã¸ã¥ã¼ã«ã¹ãããæ©è½ã®è¨å® CMTã¦ããã0 解é¤
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| 118 | */
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| 119 | sil_wrh_mem(SYSTEM_PRCR_ADDR, 0xA502); /* æ¸è¾¼ã¿è¨±å¯ */
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| 120 | sil_wrw_mem(SYSTEM_MSTPCRA_ADDR,
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| 121 | sil_rew_mem(SYSTEM_MSTPCRA_ADDR) & ~SYSTEM_MSTPCRA_MSTPA15_BIT);
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| 122 | sil_wrh_mem(SYSTEM_PRCR_ADDR, 0xA500); /* æ¸è¾¼ã¿ç¦æ¢ */
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| 123 |
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| 124 | /*
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| 125 | * ã¿ã¤ãåæ¢
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| 126 | */
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| 127 | sil_wrh_mem(CMT_CMSTR0_ADDR,
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| 128 | sil_reh_mem(CMT_CMSTR0_ADDR) & ~(CMT_CMSTR0_STR0_BIT | CMT_CMSTR0_STR1_BIT));
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| 129 |
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| 130 | /*
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| 131 | * ã«ã¦ã³ãã¢ããã«ç¨ããããã¯ããã¯è¨å®
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| 132 | * PCLK/8ãé¸æ
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| 133 | */
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| 134 | sil_wrh_mem(CMT0_CMCR_ADDR, CMT_PCLK_DIV_8);
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| 135 | sil_wrh_mem(CMT1_CMCR_ADDR, CMT_PCLK_DIV_8);
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| 136 |
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| 137 | /*
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| 138 | * ã³ã³ãã¢ãããã¿ã¤ãã«ã¦ã³ã¿è¨å®
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| 139 | */
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| 140 | sil_wrh_mem(CMT0_CMCNT_ADDR, 0U);
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| 141 | sil_wrh_mem(CMT1_CMCNT_ADDR, 0U);
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| 142 |
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| 143 | /*
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| 144 | * ã³ã³ãã¢ãããã¿ã¤ãå¨æè¨å®
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| 145 | */
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| 146 | sil_wrh_mem(CMT0_CMCOR_ADDR, 0); /* lower */
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| 147 | sil_wrh_mem(CMT1_CMCOR_ADDR, CMCOR_PERIOD - 1); /* upper */
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| 148 | elapse_upper_timer = 0;
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| 149 |
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| 150 | /*
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| 151 | * ã³ã³ãã¢ãããã¿ã¤ãå²ãè¾¼ã¿è¦æ±å
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| 152 | è¨å®ã¬ã¸ã¹ã¿ï¼28,29ï¼
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| 153 | */
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| 154 | sil_wrb_mem(ICU_ISELR028_ADDR, ICU_ISEL_CPU);
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| 155 | sil_wrb_mem(ICU_ISELR029_ADDR, ICU_ISEL_CPU);
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| 156 |
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| 157 | /*
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| 158 | * ã¿ã¤ãåä½éå§åã®å²è¾¼ã¿è¦æ±ãã¯ãªã¢
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| 159 | */
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| 160 | clear_int(INTNO_TIMER0);
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| 161 | clear_int(INTNO_TIMER1);
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| 162 |
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| 163 | /*
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| 164 | * ã³ã³ãã¢ãããã¿ã¤ãå²ãè¾¼ã¿ã許å¯
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| 165 | */
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| 166 | // sil_wrh_mem(CMT0_CMCR_ADDR,
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| 167 | // sil_reh_mem(CMT0_CMCR_ADDR) | CMT0_CMCR_CMIE_BIT); /* lower */
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| 168 | sil_wrh_mem(CMT1_CMCR_ADDR,
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| 169 | sil_reh_mem(CMT1_CMCR_ADDR) | CMT1_CMCR_CMIE_BIT); /* upper */
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| 170 |
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| 171 | /*
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| 172 | * ã¿ã¤ãåä½éå§
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| 173 | */
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| 174 | // sil_wrh_mem(CMT_CMSTR0_ADDR,
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| 175 | // sil_reh_mem(CMT_CMSTR0_ADDR) | CMT_CMSTR0_STR0_BIT); /* lower */
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| 176 | sil_wrh_mem(CMT_CMSTR0_ADDR,
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| 177 | sil_reh_mem(CMT_CMSTR0_ADDR) | CMT_CMSTR0_STR1_BIT); /* upper */
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| 178 | }
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| 179 |
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| 180 | /*
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| 181 | * ã¿ã¤ãã®åæ¢å¦ç
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| 182 | */
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| 183 | void
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| 184 | target_timer_terminate(intptr_t exinf)
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| 185 | {
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| 186 | /*
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| 187 | * ã¿ã¤ãåæ¢ lower, upper
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| 188 | */
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| 189 | sil_wrh_mem(CMT_CMSTR0_ADDR,
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| 190 | sil_reh_mem(CMT_CMSTR0_ADDR) & ~(CMT_CMSTR0_STR0_BIT | CMT_CMSTR0_STR1_BIT));
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| 191 |
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| 192 | /*
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| 193 | * ã¿ã¤ãå²ãè¾¼ã¿ç¦æ¢ãlower,upper
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| 194 | */
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| 195 | sil_wrh_mem(CMT0_CMCR_ADDR,
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| 196 | sil_reh_mem(CMT0_CMCR_ADDR) & ~CMT0_CMCR_CMIE_BIT);
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| 197 | sil_wrh_mem(CMT1_CMCR_ADDR,
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| 198 | sil_reh_mem(CMT1_CMCR_ADDR) & ~CMT1_CMCR_CMIE_BIT);
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| 199 |
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| 200 | /*
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| 201 | * ã¿ã¤ãå²è¾¼ã¿è¦æ±ãã¯ãªã¢
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| 202 | */
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| 203 | clear_int(INTNO_TIMER0);
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| 204 | clear_int(INTNO_TIMER1);
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| 205 |
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| 206 | /*
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| 207 | * ã¢ã¸ã¥ã¼ã«ã¹ãããæ©è½ã®è¨å® CMTã¦ããã0 åæ¢
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| 208 | */
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| 209 | sil_wrh_mem(SYSTEM_PRCR_ADDR, 0xA502); /* æ¸è¾¼ã¿è¨±å¯ */
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| 210 | sil_wrw_mem(SYSTEM_MSTPCRA_ADDR,
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| 211 | sil_rew_mem(SYSTEM_MSTPCRA_ADDR) | SYSTEM_MSTPCRA_MSTPA15_BIT);
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| 212 | sil_wrh_mem(SYSTEM_PRCR_ADDR, 0xA500); /* æ¸è¾¼ã¿ç¦æ¢ */
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| 213 | }
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| 214 |
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| 215 | /*
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| 216 | * ä¸ä½ã¿ã¤ãå²è¾¼ã¿ãã³ãã©(CMT0)
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| 217 | */
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| 218 | void target_lower_timer_handler(void)
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| 219 | {
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| 220 | /*
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| 221 | * ã¿ã¤ãåæ¢
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| 222 | */
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| 223 | sil_wrh_mem(CMT_CMSTR0_ADDR,
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| 224 | sil_reh_mem(CMT_CMSTR0_ADDR) & ~CMT_CMSTR0_STR0_BIT);
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| 225 |
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| 226 | /*
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| 227 | * ã¿ã¤ãå²ãè¾¼ã¿ç¦æ¢
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| 228 | */
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| 229 | sil_wrh_mem(CMT0_CMCR_ADDR,
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| 230 | sil_reh_mem(CMT0_CMCR_ADDR) & ~CMT0_CMCR_CMIE_BIT);
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| 231 |
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| 232 | /*
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| 233 | * å²ãè¾¼ã¿è¦å ã¯ãªã¢
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| 234 | */
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| 235 | clear_int(INTNO_TIMER0);
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| 236 |
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| 237 | /*
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| 238 | * ã«ã¦ã³ãè¨å®ã¯ãªã¢
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| 239 | */
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| 240 | timer_lower_set_count = 0;
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| 241 |
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| 242 | /*
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| 243 | * ã¿ã¤ãå²ãè¾¼ã¿å¦ç
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| 244 | */
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| 245 | signal_time();
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| 246 | }
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| 247 |
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| 248 | /*
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| 249 | * ä¸ä½ã¿ã¤ãå²è¾¼ã¿ãã³ãã©(CMT1)
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| 250 | */
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| 251 | void target_upper_timer_handler(void)
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| 252 | {
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| 253 | /*
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| 254 | * ä¸ä½ã¿ã¤ãã½ããã«ã¦ã³ã¿æ´æ°
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| 255 | */
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| 256 | elapse_upper_timer++;
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| 257 |
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| 258 | /*
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| 259 | * ä¸ä½ã¿ã¤ãè¨å®å¤æ´æ°
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| 260 | */
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| 261 | if(timer_upper_set_count > 0) {
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| 262 | timer_upper_set_count--;
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| 263 | }
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| 264 |
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| 265 | /*
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| 266 | * ä¸ä½ã¿ã¤ããããå¦ç
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| 267 | */
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| 268 | if(timer_upper_set_count == 0){
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| 269 | if(timer_lower_set_count > 0){
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| 270 | /*
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| 271 | * ä¸ä½ã¿ã¤ãè¨å®ãéå§
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| 272 | */
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| 273 | sil_wrh_mem(CMT0_CMCOR_ADDR, timer_lower_set_count);
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| 274 | clear_int(INTNO_TIMER0);
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| 275 | sil_wrh_mem(CMT0_CMCR_ADDR,
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| 276 | sil_reh_mem(CMT0_CMCR_ADDR) | CMT0_CMCR_CMIE_BIT);
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| 277 | sil_wrh_mem(CMT_CMSTR0_ADDR,
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| 278 | sil_reh_mem(CMT_CMSTR0_ADDR) | CMT_CMSTR0_STR0_BIT);
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| 279 | }
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| 280 | else{
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| 281 | /*
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| 282 | * ä¸ä½ã¿ã¤ãå²ãè¾¼ã¿å¼·å¶èµ·å
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| 283 | */
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| 284 | target_hrt_raise_event();
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| 285 | }
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| 286 | }
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| 287 |
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| 288 | #ifdef TOPPERS_SUPPORT_OVRHDR
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| 289 | if(timer_ovr_running_flg == true) {
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| 290 | /*
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| 291 | * ãªã¼ãã©ã³ä¸ä½ã¿ã¤ãè¨å®å¤æ´æ°
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| 292 | */
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| 293 | if(timer_ovr_upper_set_count > 0) {
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| 294 | timer_ovr_upper_set_count--;
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| 295 | }
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| 296 |
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| 297 | /*
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| 298 | * ãªã¼ãã©ã³ä¸ä½ã¿ã¤ããããå¦ç
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| 299 | */
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| 300 | if(timer_ovr_upper_set_count == 0) {
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| 301 | if(timer_ovr_lower_set_count > 0){
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| 302 | /*
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| 303 | * ãªã¼ãã©ã³ä¸ä½ã¿ã¤ãè¨å®ãéå§
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| 304 | */
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| 305 | sil_wrh_mem(CMT2_CMCNT_ADDR, 0U);
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| 306 | sil_wrh_mem(CMT2_CMCOR_ADDR, timer_ovr_lower_set_count);
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| 307 | target_ovrtimer_int_clear();
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| 308 | sil_wrh_mem(CMT2_CMCR_ADDR,
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| 309 | sil_reh_mem(CMT2_CMCR_ADDR) | CMT2_CMCR_CMIE_BIT);
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| 310 | sil_wrh_mem(CMT_CMSTR1_ADDR,
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| 311 | sil_reh_mem(CMT_CMSTR1_ADDR) | CMT_CMSTR1_STR2_BIT);
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| 312 | }
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| 313 | else {
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| 314 | /*
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| 315 | * ãªã¼ãã©ã³ä¸ä½ã¿ã¤ãå²ãè¾¼ã¿å¼·å¶èµ·å
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| 316 | */
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| 317 | target_ovrtimer_raise_event();
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| 318 | }
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| 319 | }
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| 320 | }
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| 321 | #endif /* TOPPERS_SUPPORT_OVRHDR */
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| 322 | }
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| 323 |
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| 324 | /*
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| 325 | * é«å解è½ã¿ã¤ãã¸ã®å²è¾¼ã¿ã¿ã¤ãã³ã°ã®è¨å®
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| 326 | */
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| 327 | void
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| 328 | target_hrt_set_event(HRTCNT hrtcnt)
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| 329 | {
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| 330 | uint32_t current_timer_count_work;
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| 331 | uint32_t total_timer_count;
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| 332 |
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| 333 | /*
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| 334 | * æé -> ã¿ã¤ãã«ã¦ã³ã¿ å¤æ
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| 335 | */
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| 336 | total_timer_count = hrtcnt * USEC_CONVERT_VALUE;
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| 337 | timer_upper_set_count = total_timer_count / CMCOR_PERIOD;
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| 338 | timer_lower_set_count = total_timer_count % CMCOR_PERIOD;
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| 339 |
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| 340 | /*
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| 341 | * ä¸ä½ã¿ã¤ãã«ã¦ã³ã¿ç¾å¨å¤ã§èª¿æ´
|
---|
| 342 | */
|
---|
| 343 | current_timer_count_work = timer_lower_set_count + sil_reh_mem(CMT1_CMCNT_ADDR);
|
---|
| 344 | if(current_timer_count_work >= CMCOR_PERIOD) {
|
---|
| 345 | timer_upper_set_count++;
|
---|
| 346 | timer_lower_set_count = current_timer_count_work - CMCOR_PERIOD;
|
---|
| 347 | }
|
---|
| 348 |
|
---|
| 349 | /*
|
---|
| 350 | * ä¸ä½ã¿ã¤ãè¨å®
|
---|
| 351 | */
|
---|
| 352 | if(timer_upper_set_count == 0 && timer_lower_set_count > 0) {
|
---|
| 353 | /*
|
---|
| 354 | * ã³ã³ãã¢ãããã¿ã¤ãã«ã¦ã³ã¿è¨å®
|
---|
| 355 | */
|
---|
| 356 | sil_wrh_mem(CMT0_CMCNT_ADDR, 0U);
|
---|
| 357 |
|
---|
| 358 | /*
|
---|
| 359 | * å²ãè¾¼ã¿è¦å ã¯ãªã¢
|
---|
| 360 | */
|
---|
| 361 | clear_int(INTNO_TIMER0);
|
---|
| 362 |
|
---|
| 363 | /*
|
---|
| 364 | * ã³ã³ãã¢ãããã¿ã¤ãå¨æè¨å®
|
---|
| 365 | */
|
---|
| 366 | sil_wrh_mem(CMT0_CMCOR_ADDR, timer_lower_set_count);
|
---|
| 367 |
|
---|
| 368 | /*
|
---|
| 369 | * ã¿ã¤ãå²ãè¾¼ã¿è¨±å¯
|
---|
| 370 | */
|
---|
| 371 | sil_wrh_mem(CMT0_CMCR_ADDR,
|
---|
| 372 | sil_reh_mem(CMT0_CMCR_ADDR) | CMT0_CMCR_CMIE_BIT);
|
---|
| 373 |
|
---|
| 374 | /*
|
---|
| 375 | * ã¿ã¤ãéå§
|
---|
| 376 | */
|
---|
| 377 | sil_wrh_mem(CMT_CMSTR0_ADDR,
|
---|
| 378 | sil_reh_mem(CMT_CMSTR0_ADDR) | CMT_CMSTR0_STR0_BIT);
|
---|
| 379 | }
|
---|
| 380 | }
|
---|
| 381 |
|
---|
| 382 | /*
|
---|
| 383 | * é«å解è½ã¿ã¤ãå²è¾¼ã¿ã®è¦æ±
|
---|
| 384 | */
|
---|
| 385 | void
|
---|
| 386 | target_hrt_raise_event(void)
|
---|
| 387 | {
|
---|
| 388 | /*
|
---|
| 389 | * ä¸ä½ã¿ã¤ãå¼·å¶å²ãè¾¼ã¿èµ·å
|
---|
| 390 | * 注æï¼åæ¢ããã¾ã§å²ãè¾¼ã¿ãç¹°ãè¿ãçºçãã
|
---|
| 391 | */
|
---|
| 392 | sil_wrh_mem(CMT0_CMCNT_ADDR, 0U); /* ã«ã¦ã³ã¿åæå */
|
---|
| 393 | clear_int(INTNO_TIMER0); /* è¦æ±ã¯ãªã¢ */
|
---|
| 394 | sil_wrh_mem(CMT0_CMCOR_ADDR, 0U); /* ãããå¨æè¨å® */
|
---|
| 395 | sil_wrh_mem(CMT0_CMCR_ADDR, /* å²ãè¾¼ã¿è¨±å¯ */
|
---|
| 396 | sil_reh_mem(CMT0_CMCR_ADDR) | CMT0_CMCR_CMIE_BIT);
|
---|
| 397 | sil_wrh_mem(CMT_CMSTR0_ADDR, /* ã¿ã¤ãèµ·å */
|
---|
| 398 | sil_reh_mem(CMT_CMSTR0_ADDR) | CMT_CMSTR0_STR0_BIT);
|
---|
| 399 | }
|
---|
| 400 |
|
---|
| 401 | /*
|
---|
| 402 | * é«å解è½ã¿ã¤ãã®ç¾å¨ã®ã«ã¦ã³ãå¤ã®èªåºããå
|
---|
| 403 | é¨å¦ç
|
---|
| 404 | */
|
---|
| 405 | HRTCNT target_hrt_get_current_convert(void)
|
---|
| 406 | {
|
---|
| 407 | uint16_t local_cnt, local_eut;
|
---|
| 408 | HRTCNT time;
|
---|
| 409 |
|
---|
| 410 | local_eut = elapse_upper_timer;
|
---|
| 411 | local_cnt = sil_reh_mem(CMT1_CMCNT_ADDR);
|
---|
| 412 |
|
---|
| 413 | /*
|
---|
| 414 | * ä¸ä½ã¿ã¤ã ã³ã³ãã¢ããããã§ãã¯
|
---|
| 415 | */
|
---|
| 416 | if (probe_int(INTNO_TIMER1)) {
|
---|
| 417 | if (local_cnt < 0x8000)
|
---|
| 418 | local_eut += 1;
|
---|
| 419 | }
|
---|
| 420 |
|
---|
| 421 | time = (((HRTCNT)local_eut * CMCOR_PERIOD) + (HRTCNT)local_cnt) / USEC_CONVERT_VALUE;
|
---|
| 422 | #ifdef _MSC_VER
|
---|
| 423 | // ã·ãã¥ã¬ã¼ã·ã§ã³ã§ã¯ã¿ã¤ãã¼ãæ»ããªããã調æ´
|
---|
| 424 | if (time < current_hrtcnt)
|
---|
| 425 | time = current_hrtcnt + ((HRTCNT)local_cnt / USEC_CONVERT_VALUE);
|
---|
| 426 | #endif
|
---|
| 427 | return time;
|
---|
| 428 | }
|
---|
| 429 |
|
---|
| 430 | /*
|
---|
| 431 | * ãªã¼ãã©ã³ã¿ã¤ããã©ã¤ã
|
---|
| 432 | */
|
---|
| 433 | #ifdef TOPPERS_SUPPORT_OVRHDR
|
---|
| 434 |
|
---|
| 435 | /*
|
---|
| 436 | * ãªã¼ãã©ã³ã¿ã¤ãã®åæåå¦ç
|
---|
| 437 | */
|
---|
| 438 | void
|
---|
| 439 | target_ovrtimer_initialize(intptr_t exinf)
|
---|
| 440 | {
|
---|
| 441 | /*
|
---|
| 442 | * ã¢ã¸ã¥ã¼ã«ã¹ãããæ©è½ã®è¨å® CMTã¦ããã1 解é¤
|
---|
| 443 | */
|
---|
| 444 | sil_wrh_mem(SYSTEM_PRCR_ADDR, 0xA502); /* æ¸è¾¼ã¿è¨±å¯ */
|
---|
| 445 | sil_wrw_mem(SYSTEM_MSTPCRA_ADDR,
|
---|
| 446 | sil_rew_mem(SYSTEM_MSTPCRA_ADDR) & ~SYSTEM_MSTPCRA_MSTPA14_BIT);
|
---|
| 447 | sil_wrh_mem(SYSTEM_PRCR_ADDR, 0xA500); /* æ¸è¾¼ã¿ç¦æ¢ */
|
---|
| 448 |
|
---|
| 449 | /*
|
---|
| 450 | * ã¿ã¤ãåæ¢ CMT2
|
---|
| 451 | */
|
---|
| 452 | sil_wrh_mem(CMT_CMSTR1_ADDR,
|
---|
| 453 | sil_reh_mem(CMT_CMSTR1_ADDR) & ~CMT_CMSTR1_STR2_BIT);
|
---|
| 454 |
|
---|
| 455 | /*
|
---|
| 456 | * ã«ã¦ã³ãã¢ããã«ç¨ããããã¯ããã¯è¨å® CMT2
|
---|
| 457 | * PCLK/8ãé¸æ
|
---|
| 458 | */
|
---|
| 459 | sil_wrh_mem(CMT2_CMCR_ADDR, CMT_PCLK_DIV_8);
|
---|
| 460 |
|
---|
| 461 | /*
|
---|
| 462 | * ã³ã³ãã¢ãããã¿ã¤ãã«ã¦ã³ã¿è¨å® CMT2
|
---|
| 463 | */
|
---|
| 464 | sil_wrh_mem(CMT2_CMCNT_ADDR, 0U);
|
---|
| 465 |
|
---|
| 466 | /*
|
---|
| 467 | * ã³ã³ãã¢ãããã¿ã¤ãå¨æè¨å® CMT2
|
---|
| 468 | */
|
---|
| 469 | sil_wrh_mem(CMT2_CMCOR_ADDR, 0U);
|
---|
| 470 |
|
---|
| 471 | /*
|
---|
| 472 | * ã³ã³ãã¢ãããã¿ã¤ãå²ãè¾¼ã¿è¦æ±å
|
---|
| 473 | è¨å®ã¬ã¸ã¹ã¿ï¼30ï¼
|
---|
| 474 | */
|
---|
| 475 | sil_wrb_mem(ICU_ISELR030_ADDR, ICU_ISEL_CPU);
|
---|
| 476 |
|
---|
| 477 | /*
|
---|
| 478 | * ã¿ã¤ãåä½éå§åã®å²è¾¼ã¿è¦æ±ãã¯ãªã¢
|
---|
| 479 | */
|
---|
| 480 | target_ovrtimer_int_clear();
|
---|
| 481 | }
|
---|
| 482 |
|
---|
| 483 | void
|
---|
| 484 | target_ovrtimer_start(PRCTIM ovrtim)
|
---|
| 485 | {
|
---|
| 486 | uint32_t current_timer_count_work;
|
---|
| 487 | uint32_t total_timer_count;
|
---|
| 488 |
|
---|
| 489 | /*
|
---|
| 490 | * æé -> ã¿ã¤ãã«ã¦ã³ã¿ å¤æ
|
---|
| 491 | */
|
---|
| 492 | total_timer_count = ovrtim * USEC_CONVERT_VALUE;
|
---|
| 493 | timer_ovr_upper_set_count = total_timer_count / CMCOR_PERIOD;
|
---|
| 494 | timer_ovr_lower_set_count = total_timer_count % CMCOR_PERIOD;
|
---|
| 495 |
|
---|
| 496 | /*
|
---|
| 497 | * é«å解è½ä¸ä½ã¿ã¤ãã«ã¦ã³ã¿ç¾å¨å¤ã§èª¿æ´
|
---|
| 498 | */
|
---|
| 499 | timer_ovr_ovrtim_backup = ovrtim;
|
---|
| 500 | timer_ovr_hrt_backup = target_hrt_get_current();
|
---|
| 501 | current_timer_count_work = timer_ovr_lower_set_count + sil_reh_mem(CMT1_CMCNT_ADDR);
|
---|
| 502 | if(current_timer_count_work >= CMCOR_PERIOD) {
|
---|
| 503 | timer_ovr_upper_set_count++;
|
---|
| 504 | timer_ovr_lower_set_count = current_timer_count_work - CMCOR_PERIOD;
|
---|
| 505 | }
|
---|
| 506 |
|
---|
| 507 | /*
|
---|
| 508 | * ãªã¼ãã©ã³ã¿ã¤ãåä½ä¸ãã©ã°
|
---|
| 509 | */
|
---|
| 510 | timer_ovr_running_flg = true;
|
---|
| 511 |
|
---|
| 512 | /*
|
---|
| 513 | * ä¸ä½ã¿ã¤ãè¨å®
|
---|
| 514 | */
|
---|
| 515 | if(timer_ovr_upper_set_count == 0) {
|
---|
| 516 | if(timer_ovr_lower_set_count == 0) {
|
---|
| 517 | target_ovrtimer_raise_event();
|
---|
| 518 | }
|
---|
| 519 | else {
|
---|
| 520 | /*
|
---|
| 521 | * ã³ã³ãã¢ãããã¿ã¤ãã«ã¦ã³ã¿ã¯ãªã¢ CMT2
|
---|
| 522 | */
|
---|
| 523 | sil_wrh_mem(CMT2_CMCNT_ADDR, 0U);
|
---|
| 524 |
|
---|
| 525 | /*
|
---|
| 526 | * ã³ã³ãã¢ãããã¿ã¤ãå¨æè¨å® CMT2
|
---|
| 527 | */
|
---|
| 528 | sil_wrh_mem(CMT2_CMCOR_ADDR, timer_ovr_lower_set_count);
|
---|
| 529 |
|
---|
| 530 | /*
|
---|
| 531 | * ã¿ã¤ãåä½éå§åã®å²è¾¼ã¿è¦æ±ãã¯ãªã¢
|
---|
| 532 | */
|
---|
| 533 | target_ovrtimer_int_clear();
|
---|
| 534 |
|
---|
| 535 | /*
|
---|
| 536 | * ã³ã³ãã¢ãããã¿ã¤ãå²ãè¾¼ã¿ãè¨±å¯ CMT2
|
---|
| 537 | */
|
---|
| 538 | sil_wrh_mem(CMT2_CMCR_ADDR,
|
---|
| 539 | sil_reh_mem(CMT2_CMCR_ADDR) | CMT2_CMCR_CMIE_BIT);
|
---|
| 540 |
|
---|
| 541 | /*
|
---|
| 542 | * ã¿ã¤ãåä½éå§ CMT2
|
---|
| 543 | */
|
---|
| 544 | sil_wrh_mem(CMT_CMSTR1_ADDR,
|
---|
| 545 | sil_reh_mem(CMT_CMSTR1_ADDR) | CMT_CMSTR1_STR2_BIT);
|
---|
| 546 | }
|
---|
| 547 | }
|
---|
| 548 | }
|
---|
| 549 |
|
---|
| 550 | /*
|
---|
| 551 | * ãªã¼ãã©ã³ã¿ã¤ãã®åæ¢å¦ç
|
---|
| 552 | */
|
---|
| 553 | void
|
---|
| 554 | target_ovrtimer_terminate(intptr_t exinf)
|
---|
| 555 | {
|
---|
| 556 | /*
|
---|
| 557 | * ã¿ã¤ãåæ¢
|
---|
| 558 | */
|
---|
| 559 | sil_wrh_mem(CMT_CMSTR1_ADDR,
|
---|
| 560 | sil_reh_mem(CMT_CMSTR1_ADDR) & ~CMT_CMSTR1_STR2_BIT);
|
---|
| 561 |
|
---|
| 562 | /*
|
---|
| 563 | * ã¿ã¤ãå²ãè¾¼ã¿ç¦æ¢
|
---|
| 564 | */
|
---|
| 565 | sil_wrh_mem(CMT2_CMCR_ADDR,
|
---|
| 566 | sil_reh_mem(CMT2_CMCR_ADDR) & ~CMT2_CMCR_CMIE_BIT);
|
---|
| 567 |
|
---|
| 568 | /*
|
---|
| 569 | * ã¿ã¤ãå²è¾¼ã¿è¦æ±ãã¯ãªã¢
|
---|
| 570 | */
|
---|
| 571 | target_ovrtimer_int_clear();
|
---|
| 572 |
|
---|
| 573 | /*
|
---|
| 574 | * ãªã¼ãã©ã³ã¿ã¤ãåä½ä¸ãã©ã°
|
---|
| 575 | */
|
---|
| 576 | timer_ovr_running_flg = false;
|
---|
| 577 |
|
---|
| 578 | /*
|
---|
| 579 | * ã¢ã¸ã¥ã¼ã«ã¹ãããæ©è½ã®è¨å® CMTã¦ããã0 åæ¢
|
---|
| 580 | */
|
---|
| 581 | sil_wrh_mem(SYSTEM_PRCR_ADDR, 0xA502); /* æ¸è¾¼ã¿è¨±å¯ */
|
---|
| 582 | sil_wrw_mem(SYSTEM_MSTPCRA_ADDR,
|
---|
| 583 | sil_rew_mem(SYSTEM_MSTPCRA_ADDR) | SYSTEM_MSTPCRA_MSTPA14_BIT);
|
---|
| 584 | sil_wrh_mem(SYSTEM_PRCR_ADDR, 0xA500); /* æ¸è¾¼ã¿ç¦æ¢ */
|
---|
| 585 | }
|
---|
| 586 |
|
---|
| 587 | /*
|
---|
| 588 | * ãªã¼ãã©ã³ã¿ã¤ãã®åæ¢
|
---|
| 589 | */
|
---|
| 590 | PRCTIM
|
---|
| 591 | target_ovrtimer_stop(uint_t int_num)
|
---|
| 592 | {
|
---|
| 593 | uint32_t cnt;
|
---|
| 594 |
|
---|
| 595 | /*
|
---|
| 596 | * ã¿ã¤ãåæ¢
|
---|
| 597 | */
|
---|
| 598 | sil_wrh_mem(CMT_CMSTR1_ADDR,
|
---|
| 599 | sil_reh_mem(CMT_CMSTR1_ADDR) & ~CMT_CMSTR1_STR2_BIT);
|
---|
| 600 |
|
---|
| 601 | /*
|
---|
| 602 | * ãªã¼ãã©ã³ã¿ã¤ãåä½ä¸ãã©ã°
|
---|
| 603 | */
|
---|
| 604 | timer_ovr_running_flg = false;
|
---|
| 605 |
|
---|
| 606 | if(int_num == INTNO_TIMER2) {
|
---|
| 607 | /*
|
---|
| 608 | * ãªã¼ãã©ã³å²è¾¼ã¿ã®å ´å
|
---|
| 609 | */
|
---|
| 610 | target_ovrtimer_int_clear();
|
---|
| 611 | return(0U);
|
---|
| 612 | }
|
---|
| 613 | else {
|
---|
| 614 | HRTCNT timer_ovr_hrt_current = target_hrt_get_current();
|
---|
| 615 | if((timer_ovr_hrt_current < timer_ovr_hrt_backup) && (int_num == INTNO_OVR_BASE_TIMER)) {
|
---|
| 616 | timer_ovr_hrt_current += (CMCOR_PERIOD / USEC_CONVERT_VALUE);
|
---|
| 617 | }
|
---|
| 618 |
|
---|
| 619 | cnt = timer_ovr_ovrtim_backup - (timer_ovr_hrt_current - timer_ovr_hrt_backup);
|
---|
| 620 | if(timer_ovr_hrt_current < timer_ovr_hrt_backup) {
|
---|
| 621 | cnt += TCYC_HRTCNT;
|
---|
| 622 | }
|
---|
| 623 |
|
---|
| 624 | if(cnt > timer_ovr_ovrtim_backup) { /* è¨å®æéãéãã */
|
---|
| 625 | cnt = 0;
|
---|
| 626 | }
|
---|
| 627 | return (PRCTIM)cnt;
|
---|
| 628 | }
|
---|
| 629 | }
|
---|
| 630 |
|
---|
| 631 | /*
|
---|
| 632 | * ãªã¼ãã©ã³ã¿ã¤ãã®ç¾å¨å¤ã®èªåºã
|
---|
| 633 | */
|
---|
| 634 | PRCTIM
|
---|
| 635 | target_ovrtimer_get_current(void)
|
---|
| 636 | {
|
---|
| 637 | uint32_t cnt;
|
---|
| 638 |
|
---|
| 639 | if (probe_int(INTNO_TIMER2)) {
|
---|
| 640 | /*
|
---|
| 641 | * å²è¾¼ã¿è¦æ±ãçºçãã¦ããå ´å
|
---|
| 642 | */
|
---|
| 643 | return(0U);
|
---|
| 644 | }
|
---|
| 645 | else {
|
---|
| 646 | HRTCNT timer_ovr_hrt_current = target_hrt_get_current();
|
---|
| 647 | cnt = timer_ovr_ovrtim_backup - (timer_ovr_hrt_current - timer_ovr_hrt_backup);
|
---|
| 648 | if(timer_ovr_hrt_current < timer_ovr_hrt_backup) {
|
---|
| 649 | cnt += TCYC_HRTCNT;
|
---|
| 650 | }
|
---|
| 651 |
|
---|
| 652 | if(cnt > timer_ovr_ovrtim_backup) { /* è¨å®æéãéãã */
|
---|
| 653 | cnt = 0;
|
---|
| 654 | }
|
---|
| 655 | return (PRCTIM)cnt;
|
---|
| 656 | }
|
---|
| 657 | }
|
---|
| 658 |
|
---|
| 659 | /*
|
---|
| 660 | * é«å解è½ã¿ã¤ãå²è¾¼ã¿ã®è¦æ±
|
---|
| 661 | */
|
---|
| 662 | void
|
---|
| 663 | target_ovrtimer_raise_event(void)
|
---|
| 664 | {
|
---|
| 665 | /*
|
---|
| 666 | * ãªã¼ãã©ã³ä¸ä½ã¿ã¤ãå¼·å¶å²ãè¾¼ã¿èµ·å
|
---|
| 667 | * 注æï¼åæ¢ããã¾ã§å²ãè¾¼ã¿ãç¹°ãè¿ãçºçãã
|
---|
| 668 | */
|
---|
| 669 | sil_wrh_mem(CMT2_CMCNT_ADDR, 0U); /* ã«ã¦ã³ã¿åæå */
|
---|
| 670 | clear_int(INTNO_TIMER2); /* è¦æ±ã¯ãªã¢ */
|
---|
| 671 | sil_wrh_mem(CMT2_CMCOR_ADDR, 0U); /* ãããå¨æè¨å® */
|
---|
| 672 | sil_wrh_mem(CMT2_CMCR_ADDR, /* å²ãè¾¼ã¿è¨±å¯ */
|
---|
| 673 | sil_reh_mem(CMT2_CMCR_ADDR) | CMT2_CMCR_CMIE_BIT);
|
---|
| 674 | sil_wrh_mem(CMT_CMSTR1_ADDR, /* ã¿ã¤ãèµ·å */
|
---|
| 675 | sil_reh_mem(CMT_CMSTR1_ADDR) | CMT_CMSTR1_STR2_BIT);
|
---|
| 676 | }
|
---|
| 677 |
|
---|
| 678 | /*
|
---|
| 679 | * ãªã¼ãã©ã³ã¿ã¤ãå²è¾¼ã¿ãã³ãã©
|
---|
| 680 | *
|
---|
| 681 | * ãã®ã«ã¼ãã³ã«æ¥ãã¾ã§ã«ï¼target_ovrtimer_stopãå¼ã°ãã¦ããããï¼
|
---|
| 682 | * OSã¿ã¤ããåæ¢ããå¿
|
---|
| 683 | è¦ã¯ãªãï¼
|
---|
| 684 | */
|
---|
| 685 | void
|
---|
| 686 | target_ovrtimer_handler(void)
|
---|
| 687 | {
|
---|
| 688 | /*
|
---|
| 689 | * ã¿ã¤ãå²ãè¾¼ã¿ç¦æ¢
|
---|
| 690 | */
|
---|
| 691 | sil_wrh_mem(CMT2_CMCR_ADDR,
|
---|
| 692 | sil_reh_mem(CMT2_CMCR_ADDR) & ~CMT2_CMCR_CMIE_BIT);
|
---|
| 693 |
|
---|
| 694 | /*
|
---|
| 695 | * ä¸ä¸ä½ã¿ã¤ãã«ã¦ã³ã¿ã¯ãªã¢
|
---|
| 696 | */
|
---|
| 697 | timer_ovr_upper_set_count = 0;
|
---|
| 698 | timer_ovr_lower_set_count = 0;
|
---|
| 699 |
|
---|
| 700 | call_ovrhdr(); /* ãªã¼ãã©ã³ãã³ãã©ã®èµ·åå¦ç */
|
---|
| 701 | }
|
---|
| 702 |
|
---|
| 703 | #endif /* TOPPERS_SUPPORT_OVRHDR */
|
---|