[388] | 1 | /*
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| 2 | * TOPPERS ECHONET Lite Communication Middleware
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| 3 | *
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| 4 | * Copyright (C) 2014-2018 Cores Co., Ltd. Japan
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| 5 | *
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| 6 | * ä¸è¨èä½æ¨©è
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| 7 | ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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| 8 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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| 9 | * å¤ã»åé
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| 10 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 11 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 12 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 13 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 14 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 15 | * ç¨ã§ããå½¢ã§åé
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| 16 | å¸ããå ´åã«ã¯ï¼åé
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| 17 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 18 | * è
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| 19 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 20 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 21 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 22 | * ç¨ã§ããªãå½¢ã§åé
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| 23 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 24 | * ã¨ï¼
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| 25 | * (a) åé
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| 26 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 27 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 28 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 29 | * (b) åé
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| 30 | å¸ã®å½¢æ
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| 31 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 32 | * å ±åãããã¨ï¼
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| 33 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 34 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 35 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 36 | 責ãããã¨ï¼
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| 37 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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| 38 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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| 39 | ããã³TOPPERSããã¸ã§ã¯ãã
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| 40 | * å
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| 41 | 責ãããã¨ï¼
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| 42 | *
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| 43 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 44 | ã
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| 45 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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| 46 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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| 47 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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| 48 | * ã®è²¬ä»»ãè² ããªãï¼
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| 49 | *
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| 50 | * @(#) $Id: mbed_api.c 388 2019-05-22 11:25:18Z coas-nagasima $
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| 51 | */
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| 52 |
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| 53 | #include <stdint.h>
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| 54 | #include <time.h>
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| 55 | #include <gpio_api.h>
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| 56 | #include <ticker_api.h>
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| 57 | #include <serial_api.h>
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| 58 | #include <kernel.h>
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| 59 | #include <sil.h>
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| 60 | #include <t_syslog.h>
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| 61 | #include "rx630.h"
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| 62 | #include "target_stddef.h"
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| 63 | #include "target_kernel_impl.h"
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| 64 | #include "scif.h"
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| 65 |
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| 66 | /* PWMåºå(490Hz) */
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| 67 | #define TPU_BASE_COUNTER (48000000 / 4 / 490)
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| 68 |
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| 69 | void mbed_api_init()
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| 70 | {
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| 71 | }
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| 72 |
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| 73 | void error(const char *text)
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| 74 | {
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| 75 | syslog(LOG_ERROR, text);
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| 76 | }
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| 77 |
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| 78 | void core_util_critical_section_enter(void)
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| 79 | {
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| 80 |
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| 81 | }
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| 82 |
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| 83 | void core_util_critical_section_exit(void)
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| 84 | {
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| 85 |
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| 86 | }
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| 87 |
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| 88 | void wait_ms(int ms)
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| 89 | {
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| 90 | dly_tsk(ms * 1000);
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| 91 | }
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| 92 |
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| 93 | void us_ticker_init(void)
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| 94 | {
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| 95 | }
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| 96 |
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| 97 | void us_ticker_set_interrupt(timestamp_t timestamp)
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| 98 | {
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| 99 | }
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| 100 |
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| 101 | void us_ticker_disable_interrupt(void)
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| 102 | {
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| 103 | }
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| 104 |
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| 105 | void us_ticker_clear_interrupt(void)
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| 106 | {
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| 107 | }
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| 108 |
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| 109 | uint32_t us_ticker_read(void)
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| 110 | {
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| 111 | SYSTIM result;
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| 112 | get_tim(&result);
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| 113 | return result;
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| 114 | }
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| 115 |
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| 116 | void gpio_init(gpio_t *obj, PinName pin)
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| 117 | {
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| 118 | obj->pin = pin;
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| 119 | obj->dir = PIN_INPUT;
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| 120 | obj->mode = PullDefault;
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| 121 | }
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| 122 |
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| 123 |
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| 124 | static bool_t pin_function_table[8] = {
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| 125 | true, true, true, true, true, true, true, true
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| 126 | };
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| 127 |
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| 128 | static ER change_pin_function(int pin, bool_t gpio)
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| 129 | {
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| 130 | ER result = E_PAR;
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| 131 |
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| 132 | if ((pin < 0) || (pin >= 8))
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| 133 | return E_PAR;
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| 134 |
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| 135 | if (pin_function_table[pin] == gpio)
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| 136 | return E_OK;
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| 137 |
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| 138 | /* æ±ç¨å
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| 139 | ¥åºåãã¼ãã«è¨å® */
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| 140 | switch (pin) {
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| 141 | case D0:
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| 142 | /* P21 */
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| 143 | sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) & ~PORT_PMR_B1_BIT);
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| 144 | break;
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| 145 | case D1:
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| 146 | /* P20 */
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| 147 | sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) & ~PORT_PMR_B0_BIT);
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| 148 | break;
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| 149 | case D2:
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| 150 | /* P22 */
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| 151 | sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) & ~PORT_PMR_B2_BIT);
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| 152 | break;
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| 153 | case D3:
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| 154 | /* P23 */
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| 155 | sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) & ~PORT_PMR_B3_BIT);
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| 156 | break;
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| 157 | case D4:
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| 158 | /* P24 */
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| 159 | sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) & ~PORT_PMR_B4_BIT);
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| 160 | break;
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| 161 | case D5:
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| 162 | /* P25 */
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| 163 | sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) & ~PORT_PMR_B5_BIT);
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| 164 | break;
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| 165 | case D6:
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| 166 | /* P32 */
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| 167 | sil_wrb_mem(PORT3_PMR_ADDR, sil_reb_mem(PORT3_PMR_ADDR) & ~PORT_PMR_B2_BIT);
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| 168 | break;
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| 169 | case D7:
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| 170 | /* P33 */
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| 171 | sil_wrb_mem(PORT3_PMR_ADDR, sil_reb_mem(PORT3_PMR_ADDR) & ~PORT_PMR_B3_BIT);
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| 172 | break;
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| 173 | default:
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| 174 | break;
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| 175 | }
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| 176 |
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| 177 | /* æ¸ãè¾¼ã¿ãããã¯ãã¬ã¸ã¹ã¿ã®è¨å® PFSWEãããã¸ã®æ¸ãè¾¼ã¿ãè¨±å¯ */
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| 178 | sil_wrb_mem(MPC_PWPR_ADDR, 0x00);
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| 179 | /* æ¸ãè¾¼ã¿ãããã¯ãã¬ã¸ã¹ã¿ã®è¨å® PxxFSã¬ã¸ã¹ã¿ã¸ã®æ¸ãè¾¼ã¿ãè¨±å¯ */
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| 180 | sil_wrb_mem(MPC_PWPR_ADDR, 0x40);
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| 181 |
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| 182 | switch (pin) {
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| 183 | /* P21/TIOCA3 */
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| 184 | case D0:
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| 185 | if (gpio) {
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| 186 | /* P21端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ P21ã¨ãã */
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| 187 | sil_wrb_mem(MPC_P21PFS_ADDR, 0x00);
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| 188 | }
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| 189 | else {
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| 190 | /* P21端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ TIOCA3ã¨ãã */
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| 191 | sil_wrb_mem(MPC_P21PFS_ADDR, 0x03);
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| 192 | }
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| 193 | result = E_OK;
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| 194 | break;
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| 195 | /* P20/TIOCB3 */
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| 196 | case D1:
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| 197 | if (gpio) {
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| 198 | /* P20端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ P20ã¨ãã */
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| 199 | sil_wrb_mem(MPC_P20PFS_ADDR, 0x00);
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| 200 | }
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| 201 | else {
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| 202 | /* P20端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ TIOCB3ã¨ãã */
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| 203 | sil_wrb_mem(MPC_P20PFS_ADDR, 0x03);
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| 204 | }
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| 205 | result = E_OK;
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| 206 | break;
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| 207 | /* P22/TIOCC3 */
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| 208 | case D2:
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| 209 | if (gpio) {
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| 210 | /* P22端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ P22ã¨ãã */
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| 211 | sil_wrb_mem(MPC_P22PFS_ADDR, 0x00);
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| 212 | }
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| 213 | else {
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| 214 | /* P22端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ TIOCC3ã¨ãã */
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| 215 | sil_wrb_mem(MPC_P22PFS_ADDR, 0x03);
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| 216 | }
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| 217 | result = E_OK;
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| 218 | break;
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| 219 | /* P23/TIOCD3 */
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| 220 | case D3:
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| 221 | if (gpio) {
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| 222 | /* P23端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ P23ã¨ãã */
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| 223 | sil_wrb_mem(MPC_P23PFS_ADDR, 0x00);
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| 224 | }
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| 225 | else {
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| 226 | /* P23端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ TIOCD3ã¨ãã */
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| 227 | sil_wrb_mem(MPC_P23PFS_ADDR, 0x03);
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| 228 | }
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| 229 | result = E_OK;
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| 230 | break;
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| 231 | /* P24/TIOCB4 */
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| 232 | case D4:
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| 233 | if (gpio) {
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| 234 | /* P24端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ P24ã¨ãã */
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| 235 | sil_wrb_mem(MPC_P24PFS_ADDR, 0x00);
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| 236 | }
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| 237 | else {
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| 238 | /* P24端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ TIOCB4ã¨ãã */
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| 239 | sil_wrb_mem(MPC_P24PFS_ADDR, 0x03);
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| 240 | }
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| 241 | result = E_OK;
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| 242 | break;
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| 243 | /* P25/TIOCA4 */
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| 244 | case D5:
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| 245 | if (gpio) {
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| 246 | /* P25端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ P25ã¨ãã */
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| 247 | sil_wrb_mem(MPC_P25PFS_ADDR, 0x00);
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| 248 | }
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| 249 | else {
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| 250 | /* P25端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ TIOCA4ã¨ãã */
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| 251 | sil_wrb_mem(MPC_P25PFS_ADDR, 0x03);
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| 252 | }
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| 253 | result = E_OK;
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| 254 | break;
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| 255 | /* P32/TIOCC0 */
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| 256 | case D6:
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| 257 | if (gpio) {
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| 258 | /* P32端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ P32ã¨ãã */
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| 259 | sil_wrb_mem(MPC_P32PFS_ADDR, 0x00);
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| 260 | }
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| 261 | else {
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| 262 | /* P32端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ TIOCC0ã¨ãã */
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| 263 | sil_wrb_mem(MPC_P32PFS_ADDR, 0x03);
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| 264 | }
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| 265 | result = E_OK;
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| 266 | break;
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| 267 | /* P33/TIOCD0 */
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| 268 | case D7:
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| 269 | if (gpio) {
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| 270 | /* P33端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ P33ã¨ãã */
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| 271 | sil_wrb_mem(MPC_P33PFS_ADDR, 0x00);
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| 272 | }
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| 273 | else {
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| 274 | /* P33端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ TIOCD0ã¨ãã */
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| 275 | sil_wrb_mem(MPC_P33PFS_ADDR, 0x03);
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| 276 | }
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| 277 | result = E_OK;
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| 278 | break;
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| 279 | default:
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| 280 | break;
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| 281 | }
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| 282 |
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| 283 | /* æ¸ãè¾¼ã¿ãããã¯ãã¬ã¸ã¹ã¿ã®è¨å® æ¸ãè¾¼ã¿ãç¦æ¢ */
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| 284 | sil_wrb_mem(MPC_PWPR_ADDR, 0x80);
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| 285 |
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| 286 | /* æ©è½ãã¼ãã«è¨å® */
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| 287 | if (!gpio) {
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| 288 | switch (pin) {
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| 289 | /* P21/TIOCA3 */
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| 290 | case D0:
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| 291 | sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B1_BIT);
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| 292 | sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B1_BIT);
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| 293 | break;
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| 294 | /* P20/TIOCB3 */
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| 295 | case D1:
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| 296 | sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B0_BIT);
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| 297 | sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B0_BIT);
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| 298 | break;
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| 299 | /* P22/TIOCC3 */
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| 300 | case D2:
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| 301 | sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B2_BIT);
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| 302 | sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B2_BIT);
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| 303 | break;
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| 304 | /* P23/TIOCD3 */
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| 305 | case D3:
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| 306 | sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B3_BIT);
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| 307 | sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B3_BIT);
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| 308 | break;
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| 309 | /* P24/TIOCB4 */
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| 310 | case D4:
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| 311 | sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B4_BIT);
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| 312 | sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B4_BIT);
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| 313 | break;
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| 314 | /* P25/TIOCA4 */
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| 315 | case D5:
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| 316 | sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B5_BIT);
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| 317 | sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B5_BIT);
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| 318 | break;
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| 319 | /* P32/TIOCC0 */
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| 320 | case D6:
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| 321 | sil_wrb_mem(PORT3_PDR_ADDR, sil_reb_mem(PORT3_PDR_ADDR) | PORT_PDR_B2_BIT);
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| 322 | sil_wrb_mem(PORT3_PMR_ADDR, sil_reb_mem(PORT3_PMR_ADDR) | PORT_PMR_B2_BIT);
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| 323 | break;
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| 324 | /* P33/TIOCD0 */
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| 325 | case D7:
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| 326 | sil_wrb_mem(PORT3_PDR_ADDR, sil_reb_mem(PORT3_PDR_ADDR) | PORT_PDR_B3_BIT);
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| 327 | sil_wrb_mem(PORT3_PMR_ADDR, sil_reb_mem(PORT3_PMR_ADDR) | PORT_PMR_B3_BIT);
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| 328 | break;
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| 329 | default:
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| 330 | break;
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| 331 | }
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| 332 | }
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| 333 |
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| 334 | pin_function_table[pin] = gpio;
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| 335 |
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| 336 | return result;
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| 337 | }
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| 338 |
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| 339 | static void change_pin_mode(gpio_t *obj)
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| 340 | {
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| 341 | volatile __evenaccess uint8_t *pdr; int bit;
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| 342 |
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| 343 | switch (obj->pin) {
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| 344 | case D0:
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| 345 | /* P21 */
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| 346 | pdr = PORT2_PDR_ADDR; bit = PORT_PDR_B1_BIT;
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| 347 | break;
|
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| 348 | case D1:
|
---|
| 349 | /* P20 */
|
---|
| 350 | pdr = PORT2_PDR_ADDR; bit = PORT_PDR_B0_BIT;
|
---|
| 351 | break;
|
---|
| 352 | case D2:
|
---|
| 353 | /* P22 */
|
---|
| 354 | pdr = PORT2_PDR_ADDR; bit = PORT_PDR_B2_BIT;
|
---|
| 355 | break;
|
---|
| 356 | case D3:
|
---|
| 357 | /* P23 */
|
---|
| 358 | pdr = PORT2_PDR_ADDR; bit = PORT_PDR_B3_BIT;
|
---|
| 359 | break;
|
---|
| 360 | case D4:
|
---|
| 361 | /* P24 */
|
---|
| 362 | pdr = PORT2_PDR_ADDR; bit = PORT_PDR_B4_BIT;
|
---|
| 363 | break;
|
---|
| 364 | case D5:
|
---|
| 365 | /* P25 */
|
---|
| 366 | pdr = PORT2_PDR_ADDR; bit = PORT_PDR_B5_BIT;
|
---|
| 367 | break;
|
---|
| 368 | case D6:
|
---|
| 369 | /* P32 */
|
---|
| 370 | pdr = PORT3_PDR_ADDR; bit = PORT_PDR_B2_BIT;
|
---|
| 371 | break;
|
---|
| 372 | case D7:
|
---|
| 373 | /* P33 */
|
---|
| 374 | pdr = PORT3_PDR_ADDR; bit = PORT_PDR_B3_BIT;
|
---|
| 375 | break;
|
---|
| 376 | case D8:
|
---|
| 377 | /* PC2 */
|
---|
| 378 | pdr = PORTC_PDR_ADDR; bit = PORT_PDR_B2_BIT;
|
---|
| 379 | break;
|
---|
| 380 | case D9:
|
---|
| 381 | /* PC3 */
|
---|
| 382 | pdr = PORTC_PDR_ADDR; bit = PORT_PDR_B3_BIT;
|
---|
| 383 | break;
|
---|
| 384 | case D10:
|
---|
| 385 | /* PC4 */
|
---|
| 386 | pdr = PORTC_PDR_ADDR; bit = PORT_PDR_B4_BIT;
|
---|
| 387 | break;
|
---|
| 388 | case D11:
|
---|
| 389 | /* PC6 */
|
---|
| 390 | pdr = PORTC_PDR_ADDR; bit = PORT_PDR_B6_BIT;
|
---|
| 391 | break;
|
---|
| 392 | case D12:
|
---|
| 393 | /* PC7 */
|
---|
| 394 | pdr = PORTC_PDR_ADDR; bit = PORT_PDR_B7_BIT;
|
---|
| 395 | break;
|
---|
| 396 | case D13:
|
---|
| 397 | /* PC5 */
|
---|
| 398 | pdr = PORTC_PDR_ADDR; bit = PORT_PDR_B5_BIT;
|
---|
| 399 | break;
|
---|
| 400 | default:
|
---|
| 401 | return;
|
---|
| 402 | }
|
---|
| 403 |
|
---|
| 404 | volatile __evenaccess uint8_t *pcr = pdr + (PORT0_PCR_ADDR - PORT0_PDR_ADDR);
|
---|
| 405 |
|
---|
| 406 | switch (obj->dir) {
|
---|
| 407 | case PIN_INPUT:
|
---|
| 408 | sil_wrb_mem(pdr, sil_reb_mem(pdr) & ~bit);
|
---|
| 409 | break;
|
---|
| 410 | case PIN_OUTPUT:
|
---|
| 411 | sil_wrb_mem(pdr, sil_reb_mem(pdr) | bit);
|
---|
| 412 | break;
|
---|
| 413 | default:
|
---|
| 414 | break;
|
---|
| 415 | }
|
---|
| 416 |
|
---|
| 417 | switch (obj->mode) {
|
---|
| 418 | case PullUp:
|
---|
| 419 | sil_wrb_mem(pcr, sil_reb_mem(pcr) | bit);
|
---|
| 420 | break;
|
---|
| 421 | default:
|
---|
| 422 | sil_wrb_mem(pcr, sil_reb_mem(pcr) & ~bit);
|
---|
| 423 | break;
|
---|
| 424 | }
|
---|
| 425 | }
|
---|
| 426 |
|
---|
| 427 | void gpio_mode(gpio_t *obj, PinMode mode)
|
---|
| 428 | {
|
---|
| 429 | /* æ±ç¨å
|
---|
| 430 | ¥åºåãã¼ãã«è¨å® */
|
---|
| 431 | change_pin_function(obj->pin, true);
|
---|
| 432 |
|
---|
| 433 | obj->mode = mode;
|
---|
| 434 |
|
---|
| 435 | change_pin_mode(obj);
|
---|
| 436 | }
|
---|
| 437 |
|
---|
| 438 | void gpio_dir(gpio_t *obj, PinDirection direction)
|
---|
| 439 | {
|
---|
| 440 | /* æ±ç¨å
|
---|
| 441 | ¥åºåãã¼ãã«è¨å® */
|
---|
| 442 | change_pin_function(obj->pin, true);
|
---|
| 443 |
|
---|
| 444 | obj->dir = direction;
|
---|
| 445 |
|
---|
| 446 | change_pin_mode(obj);
|
---|
| 447 | }
|
---|
| 448 |
|
---|
| 449 | void gpio_write(gpio_t *obj, int value)
|
---|
| 450 | {
|
---|
| 451 | volatile __evenaccess uint8_t *podr;
|
---|
| 452 | int bit;
|
---|
| 453 |
|
---|
| 454 | switch (obj->pin) {
|
---|
| 455 | case D0:
|
---|
| 456 | /* P21 */
|
---|
| 457 | podr = PORT2_PODR_ADDR; bit = PORT_PODR_B1_BIT;
|
---|
| 458 | break;
|
---|
| 459 | case D1:
|
---|
| 460 | /* P20 */
|
---|
| 461 | podr = PORT2_PODR_ADDR; bit = PORT_PODR_B0_BIT;
|
---|
| 462 | break;
|
---|
| 463 | case D2:
|
---|
| 464 | /* P22 */
|
---|
| 465 | podr = PORT2_PODR_ADDR; bit = PORT_PODR_B2_BIT;
|
---|
| 466 | break;
|
---|
| 467 | case D3:
|
---|
| 468 | /* P23 */
|
---|
| 469 | podr = PORT2_PODR_ADDR; bit = PORT_PODR_B3_BIT;
|
---|
| 470 | break;
|
---|
| 471 | case D4:
|
---|
| 472 | /* P24 */
|
---|
| 473 | podr = PORT2_PODR_ADDR; bit = PORT_PODR_B4_BIT;
|
---|
| 474 | break;
|
---|
| 475 | case D5:
|
---|
| 476 | /* P25 */
|
---|
| 477 | podr = PORT2_PODR_ADDR; bit = PORT_PODR_B5_BIT;
|
---|
| 478 | break;
|
---|
| 479 | case D6:
|
---|
| 480 | /* P32 */
|
---|
| 481 | podr = PORT3_PODR_ADDR; bit = PORT_PODR_B2_BIT;
|
---|
| 482 | break;
|
---|
| 483 | case D7:
|
---|
| 484 | /* P33 */
|
---|
| 485 | podr = PORT3_PODR_ADDR; bit = PORT_PODR_B3_BIT;
|
---|
| 486 | break;
|
---|
| 487 | case D8:
|
---|
| 488 | /* PC2 */
|
---|
| 489 | podr = PORTC_PODR_ADDR; bit = PORT_PODR_B2_BIT;
|
---|
| 490 | break;
|
---|
| 491 | case D9:
|
---|
| 492 | /* PC3 */
|
---|
| 493 | podr = PORTC_PODR_ADDR; bit = PORT_PODR_B3_BIT;
|
---|
| 494 | break;
|
---|
| 495 | case D10:
|
---|
| 496 | /* PC4 */
|
---|
| 497 | podr = PORTC_PODR_ADDR; bit = PORT_PODR_B4_BIT;
|
---|
| 498 | break;
|
---|
| 499 | case D11:
|
---|
| 500 | /* PC6 */
|
---|
| 501 | podr = PORTC_PODR_ADDR; bit = PORT_PODR_B6_BIT;
|
---|
| 502 | break;
|
---|
| 503 | case D12:
|
---|
| 504 | /* PC7 */
|
---|
| 505 | podr = PORTC_PODR_ADDR; bit = PORT_PODR_B7_BIT;
|
---|
| 506 | break;
|
---|
| 507 | case D13:
|
---|
| 508 | /* PC5 */
|
---|
| 509 | podr = PORTC_PODR_ADDR; bit = PORT_PODR_B5_BIT;
|
---|
| 510 | break;
|
---|
| 511 | default:
|
---|
| 512 | return;
|
---|
| 513 | }
|
---|
| 514 |
|
---|
| 515 | switch (value) {
|
---|
| 516 | case 0:
|
---|
| 517 | sil_wrb_mem(podr, sil_reb_mem(podr) & ~bit);
|
---|
| 518 | break;
|
---|
| 519 | case 1:
|
---|
| 520 | sil_wrb_mem(podr, sil_reb_mem(podr) | bit);
|
---|
| 521 | break;
|
---|
| 522 | }
|
---|
| 523 | }
|
---|
| 524 |
|
---|
| 525 | int gpio_read(gpio_t *obj)
|
---|
| 526 | {
|
---|
| 527 | volatile __evenaccess uint8_t *pidr;
|
---|
| 528 | int bit;
|
---|
| 529 |
|
---|
| 530 | switch (obj->pin) {
|
---|
| 531 | case D0:
|
---|
| 532 | /* P21 */
|
---|
| 533 | pidr = PORT2_PIDR_ADDR; bit = PORT_PIDR_B1_BIT;
|
---|
| 534 | break;
|
---|
| 535 | case D1:
|
---|
| 536 | /* P20 */
|
---|
| 537 | pidr = PORT2_PIDR_ADDR; bit = PORT_PIDR_B0_BIT;
|
---|
| 538 | break;
|
---|
| 539 | case D2:
|
---|
| 540 | /* P22 */
|
---|
| 541 | pidr = PORT2_PIDR_ADDR; bit = PORT_PIDR_B2_BIT;
|
---|
| 542 | break;
|
---|
| 543 | case D3:
|
---|
| 544 | /* P23 */
|
---|
| 545 | pidr = PORT2_PIDR_ADDR; bit = PORT_PIDR_B3_BIT;
|
---|
| 546 | break;
|
---|
| 547 | case D4:
|
---|
| 548 | /* P24 */
|
---|
| 549 | pidr = PORT2_PIDR_ADDR; bit = PORT_PIDR_B4_BIT;
|
---|
| 550 | break;
|
---|
| 551 | case D5:
|
---|
| 552 | /* P25 */
|
---|
| 553 | pidr = PORT2_PIDR_ADDR; bit = PORT_PIDR_B5_BIT;
|
---|
| 554 | break;
|
---|
| 555 | case D6:
|
---|
| 556 | /* P32 */
|
---|
| 557 | pidr = PORT3_PIDR_ADDR; bit = PORT_PIDR_B2_BIT;
|
---|
| 558 | break;
|
---|
| 559 | case D7:
|
---|
| 560 | /* P33 */
|
---|
| 561 | pidr = PORT3_PIDR_ADDR; bit = PORT_PIDR_B3_BIT;
|
---|
| 562 | break;
|
---|
| 563 | case D8:
|
---|
| 564 | /* PC2 */
|
---|
| 565 | pidr = PORTC_PIDR_ADDR; bit = PORT_PIDR_B2_BIT;
|
---|
| 566 | break;
|
---|
| 567 | case D9:
|
---|
| 568 | /* PC3 */
|
---|
| 569 | pidr = PORTC_PIDR_ADDR; bit = PORT_PIDR_B3_BIT;
|
---|
| 570 | break;
|
---|
| 571 | case D10:
|
---|
| 572 | /* PC4 */
|
---|
| 573 | pidr = PORTC_PIDR_ADDR; bit = PORT_PIDR_B4_BIT;
|
---|
| 574 | break;
|
---|
| 575 | case D11:
|
---|
| 576 | /* PC6 */
|
---|
| 577 | pidr = PORTC_PIDR_ADDR; bit = PORT_PIDR_B6_BIT;
|
---|
| 578 | break;
|
---|
| 579 | case D12:
|
---|
| 580 | /* PC7 */
|
---|
| 581 | pidr = PORTC_PIDR_ADDR; bit = PORT_PIDR_B7_BIT;
|
---|
| 582 | break;
|
---|
| 583 | case D13:
|
---|
| 584 | /* PC5 */
|
---|
| 585 | pidr = PORTC_PIDR_ADDR; bit = PORT_PIDR_B5_BIT;
|
---|
| 586 | break;
|
---|
| 587 | default:
|
---|
| 588 | return 0;
|
---|
| 589 | }
|
---|
| 590 |
|
---|
| 591 | if ((sil_reb_mem(pidr) & bit) != 0) {
|
---|
| 592 | return 1;
|
---|
| 593 | }
|
---|
| 594 | else {
|
---|
| 595 | return 0;
|
---|
| 596 | }
|
---|
| 597 | }
|
---|
| 598 |
|
---|
| 599 | void pin_function(PinName pin, int function)
|
---|
| 600 | {
|
---|
| 601 | }
|
---|
| 602 |
|
---|
| 603 | void pin_mode(PinName pin, PinMode mode)
|
---|
| 604 | {
|
---|
| 605 |
|
---|
| 606 | }
|
---|
| 607 |
|
---|
| 608 | #define arduino_ad_table_count 64
|
---|
| 609 | static uint16_t arduino_ad_table[8][arduino_ad_table_count];
|
---|
| 610 | static int arduino_ad_pos = 0;
|
---|
| 611 | static uint32_t arduino_ad_avelage[8];
|
---|
| 612 |
|
---|
| 613 | void analogin_init(analogin_t *obj, PinName pin)
|
---|
| 614 | {
|
---|
| 615 | /*
|
---|
| 616 | * ã¢ã¸ã¥ã¼ã«ã¹ãããæ©è½ã®è¨å®(S12AD)
|
---|
| 617 | */
|
---|
| 618 | sil_wrh_mem(SYSTEM_PRCR_ADDR, (uint16_t)0xA502); /* æ¸è¾¼ã¿è¨±å¯ */
|
---|
| 619 | sil_wrw_mem(SYSTEM_MSTPCRA_ADDR,
|
---|
| 620 | sil_rew_mem(SYSTEM_MSTPCRA_ADDR) & ~SYSTEM_MSTPCRA_MSTPA17_BIT);
|
---|
| 621 | sil_wrh_mem(SYSTEM_PRCR_ADDR, (uint16_t)0xA500); /* æ¸è¾¼ã¿ç¦æ¢ */
|
---|
| 622 |
|
---|
| 623 | /* 12bitADCåæå */
|
---|
| 624 | sil_wrh_mem(S12AD_ADEXICR_ADDR, 0x0000); /* 温度ã»ã³ãµåºåãå
|
---|
| 625 | é¨åºæºé»å§éé¸æ */
|
---|
| 626 | sil_wrh_mem(S12AD_ADANS0_ADDR, 0x00FF); /* å¤æãã¼ãAN000ï½AN007é¸æãAN008ï½AN015éé¸æ */
|
---|
| 627 | sil_wrh_mem(S12AD_ADANS1_ADDR, 0x0000); /* å¤æãã¼ãAN016ï½AN020éé¸æ */
|
---|
| 628 | }
|
---|
| 629 |
|
---|
| 630 | uint16_t analogin_read_u16(analogin_t *obj)
|
---|
| 631 | {
|
---|
| 632 | uint16_t result = 0;
|
---|
| 633 |
|
---|
| 634 | switch (obj->pin) {
|
---|
| 635 | case A0:
|
---|
| 636 | /* *value = sil_reh_mem(S12AD_ADDR0_ADDR); */
|
---|
| 637 | result = (arduino_ad_avelage[0] / (arduino_ad_table_count));
|
---|
| 638 | break;
|
---|
| 639 | case A1:
|
---|
| 640 | /* *value = sil_reh_mem(S12AD_ADDR1_ADDR); */
|
---|
| 641 | result = (arduino_ad_avelage[1] / (arduino_ad_table_count));
|
---|
| 642 | break;
|
---|
| 643 | case A2:
|
---|
| 644 | /* *value = sil_reh_mem(S12AD_ADDR2_ADDR); */
|
---|
| 645 | result = (arduino_ad_avelage[2] / (arduino_ad_table_count));
|
---|
| 646 | break;
|
---|
| 647 | case A3:
|
---|
| 648 | /* *value = sil_reh_mem(S12AD_ADDR3_ADDR); */
|
---|
| 649 | result = (arduino_ad_avelage[3] / (arduino_ad_table_count));
|
---|
| 650 | break;
|
---|
| 651 | case A4:
|
---|
| 652 | /* *value = sil_reh_mem(S12AD_ADDR4_ADDR); */
|
---|
| 653 | result = (arduino_ad_avelage[4] / (arduino_ad_table_count));
|
---|
| 654 | break;
|
---|
| 655 | case A5:
|
---|
| 656 | /* *value = sil_reh_mem(S12AD_ADDR5_ADDR); */
|
---|
| 657 | result = (arduino_ad_avelage[5] / (arduino_ad_table_count));
|
---|
| 658 | break;
|
---|
| 659 | case A6:
|
---|
| 660 | /* *value = sil_reh_mem(S12AD_ADDR6_ADDR); */
|
---|
| 661 | result = (arduino_ad_avelage[6] / (arduino_ad_table_count));
|
---|
| 662 | break;
|
---|
| 663 | case A7:
|
---|
| 664 | /* *value = sil_reh_mem(S12AD_ADDR7_ADDR); */
|
---|
| 665 | result = (arduino_ad_avelage[7] / (arduino_ad_table_count));
|
---|
| 666 | break;
|
---|
| 667 | default:
|
---|
| 668 | return 0;
|
---|
| 669 | }
|
---|
| 670 |
|
---|
| 671 | return 65535 - ((result << 4) | (result >> 8));
|
---|
| 672 | }
|
---|
| 673 |
|
---|
| 674 | void arduino_tick()
|
---|
| 675 | {
|
---|
| 676 | static volatile __evenaccess uint16_t *const regs[8] = {
|
---|
| 677 | S12AD_ADDR0_ADDR,
|
---|
| 678 | S12AD_ADDR1_ADDR,
|
---|
| 679 | S12AD_ADDR2_ADDR,
|
---|
| 680 | S12AD_ADDR3_ADDR,
|
---|
| 681 | S12AD_ADDR4_ADDR,
|
---|
| 682 | S12AD_ADDR5_ADDR,
|
---|
| 683 | S12AD_ADDR6_ADDR,
|
---|
| 684 | S12AD_ADDR7_ADDR
|
---|
| 685 | };
|
---|
| 686 | uint16_t ad_value;
|
---|
| 687 | int i;
|
---|
| 688 |
|
---|
| 689 | /* ADCã®å¤æçµæåå¾ */
|
---|
| 690 | if ((sil_reb_mem(S12AD_ADCSR_ADDR) & S12AD_ADCSR_ADST_BIT) == 0) {
|
---|
| 691 | for (i = 0; i < 8; i++) {
|
---|
| 692 | arduino_ad_avelage[i] -= arduino_ad_table[i][arduino_ad_pos];
|
---|
| 693 | ad_value = sil_reh_mem(regs[i]);
|
---|
| 694 | arduino_ad_table[i][arduino_ad_pos] = ad_value;
|
---|
| 695 | arduino_ad_avelage[i] += ad_value;
|
---|
| 696 | }
|
---|
| 697 |
|
---|
| 698 | arduino_ad_pos++;
|
---|
| 699 | if (arduino_ad_pos >= arduino_ad_table_count) {
|
---|
| 700 | arduino_ad_pos = 0;
|
---|
| 701 | }
|
---|
| 702 |
|
---|
| 703 | /* å¤æéå§ï¼ã·ã³ã°ã«ã¹ãã£ã³ã¢ã¼ãï¼ */
|
---|
| 704 | sil_wrb_mem(S12AD_ADCSR_ADDR, S12AD_ADCSR_ADST_BIT);
|
---|
| 705 | }
|
---|
| 706 | }
|
---|
| 707 |
|
---|
| 708 | void analogout_init(dac_t *obj, PinName pin)
|
---|
| 709 | {
|
---|
| 710 | }
|
---|
| 711 |
|
---|
| 712 | void analogout_write_u16(dac_t *obj, uint16_t value)
|
---|
| 713 | {
|
---|
| 714 | }
|
---|
| 715 |
|
---|
| 716 | void pwmout_init(pwmout_t* obj, PinName pin)
|
---|
| 717 | {
|
---|
| 718 | /* PWMåºå(490Hz) */
|
---|
| 719 | sil_wrh_mem(SYSTEM_PRCR_ADDR, (uint16_t)0xA502); /* æ¸è¾¼ã¿è¨±å¯ */
|
---|
| 720 | sil_wrw_mem(SYSTEM_MSTPCRA_ADDR,
|
---|
| 721 | sil_rew_mem(SYSTEM_MSTPCRA_ADDR) & ~SYSTEM_MSTPCRA_MSTPA13_BIT); /* TPU0ï½TPU5 */
|
---|
| 722 | sil_wrh_mem(SYSTEM_PRCR_ADDR, (uint16_t)0xA500); /* æ¸è¾¼ã¿ç¦æ¢ */
|
---|
| 723 |
|
---|
| 724 | /* ã«ã¦ã³ã¿ã¯ããã¯ã®é¸æãã«ã¦ã³ã¿ã¯ãªã¢è¦å ã®é¸æ */
|
---|
| 725 | sil_wrb_mem(TPU0_TCR_ADDR, (1 << TPU_TCR_TPSC_OFFSET) | (1 << TPU_TCR_CKEG_OFFSET)
|
---|
| 726 | | (1 << TPU_TCR_CCLR_OFFSET));
|
---|
| 727 | sil_wrb_mem(TPU3_TCR_ADDR, (1 << TPU_TCR_TPSC_OFFSET) | (1 << TPU_TCR_CKEG_OFFSET)
|
---|
| 728 | | (3 << TPU_TCR_CCLR_OFFSET));
|
---|
| 729 | sil_wrb_mem(TPU4_TCR_ADDR, (1 << TPU_TCR_TPSC_OFFSET) | (1 << TPU_TCR_CKEG_OFFSET)
|
---|
| 730 | | (3 << TPU_TCR_CCLR_OFFSET));
|
---|
| 731 | /* 波形åºåã¬ãã«ã®é¸æ */
|
---|
| 732 | sil_wrb_mem(TPU0_TIORL_ADDR, (5 << TPU_TIORL_IOC_OFFSET) | (5 << TPU_TIORL_IOD_OFFSET));
|
---|
| 733 | sil_wrb_mem(TPU3_TIORH_ADDR, (5 << TPU_TIORH_IOA_OFFSET) | (5 << TPU_TIORH_IOB_OFFSET));
|
---|
| 734 | sil_wrb_mem(TPU3_TIORL_ADDR, (5 << TPU_TIORL_IOC_OFFSET) | (5 << TPU_TIORL_IOD_OFFSET));
|
---|
| 735 | sil_wrb_mem(TPU4_TIOR_ADDR, (5 << TPU_TIOR_IOA_OFFSET) | (5 << TPU_TIOR_IOB_OFFSET));
|
---|
| 736 | /* TGRyã®è¨å® */
|
---|
| 737 | sil_wrh_mem(TPU0_TGRA_ADDR, TPU_BASE_COUNTER);
|
---|
| 738 | sil_wrh_mem(TPU0_TGRC_ADDR, 0);
|
---|
| 739 | sil_wrh_mem(TPU0_TGRD_ADDR, 0);
|
---|
| 740 | sil_wrh_mem(TPU3_TGRA_ADDR, 0);
|
---|
| 741 | sil_wrh_mem(TPU3_TGRB_ADDR, 0);
|
---|
| 742 | sil_wrh_mem(TPU3_TGRC_ADDR, 0);
|
---|
| 743 | sil_wrh_mem(TPU3_TGRD_ADDR, 0);
|
---|
| 744 | sil_wrh_mem(TPU4_TGRA_ADDR, 0);
|
---|
| 745 | sil_wrh_mem(TPU4_TGRB_ADDR, 0);
|
---|
| 746 | /* PWMã¢ã¼ã2ã®è¨å® */
|
---|
| 747 | sil_wrb_mem(TPU0_TMDR_ADDR, 3);
|
---|
| 748 | sil_wrb_mem(TPU3_TMDR_ADDR, 3);
|
---|
| 749 | sil_wrb_mem(TPU4_TMDR_ADDR, 3);
|
---|
| 750 | /* åæåä½è¨å® */
|
---|
| 751 | sil_wrb_mem(TPUA_TSYR_ADDR, TPU_TSYR_SYNC0_BIT | TPU_TSYR_SYNC3_BIT | TPU_TSYR_SYNC4_BIT);
|
---|
| 752 | /* ã«ã¦ã³ãåä½éå§ */
|
---|
| 753 | sil_wrb_mem(TPUA_TSTR_ADDR, TPU_TSTR_CST0_BIT | TPU_TSTR_CST3_BIT | TPU_TSTR_CST4_BIT);
|
---|
| 754 | }
|
---|
| 755 |
|
---|
| 756 | void pwmout_free(pwmout_t* obj)
|
---|
| 757 | {
|
---|
| 758 | /* ã«ã¦ã³ãåä½çµäº */
|
---|
| 759 | sil_wrb_mem(TPUA_TSTR_ADDR, 0);
|
---|
| 760 | }
|
---|
| 761 |
|
---|
| 762 | void pwmout_period_us(pwmout_t* obj, int us)
|
---|
| 763 | {
|
---|
| 764 | }
|
---|
| 765 |
|
---|
| 766 | void pwmout_pulsewidth_us(pwmout_t* obj, int us)
|
---|
| 767 | {
|
---|
| 768 | }
|
---|
| 769 |
|
---|
| 770 | typedef enum {
|
---|
| 771 | sciSerial,
|
---|
| 772 | sciI2C,
|
---|
| 773 | sciSPIM,
|
---|
| 774 | sciSPIS,
|
---|
| 775 | } sci_mode_t;
|
---|
| 776 |
|
---|
| 777 | void sci_enable(void *base_address, sci_mode_t mode)
|
---|
| 778 | {
|
---|
| 779 | /*
|
---|
| 780 | * ã¢ã¸ã¥ã¼ã«ã¹ãããæ©è½ã®è¨å®
|
---|
| 781 | */
|
---|
| 782 | sil_wrh_mem(SYSTEM_PRCR_ADDR, (uint16_t)0xA502); /* æ¸è¾¼ã¿è¨±å¯ */
|
---|
| 783 | sil_wrw_mem(SYSTEM_MSTPCRB_ADDR,
|
---|
| 784 | sil_rew_mem(SYSTEM_MSTPCRB_ADDR) & ~SCI_MSTPCRB_BIT(base_address));
|
---|
| 785 | sil_wrh_mem(SYSTEM_PRCR_ADDR, (uint16_t)0xA500); /* æ¸è¾¼ã¿ç¦æ¢ */
|
---|
| 786 |
|
---|
| 787 | /* éåä¿¡ç¦æ¢, SCKn端åã¯å
|
---|
| 788 | ¥åºåãã¼ãã¨ãã¦ä½¿ç¨ */
|
---|
| 789 | sil_wrb_mem(SCI_SCR(base_address), 0x00U);
|
---|
| 790 |
|
---|
| 791 | switch ((uint32_t)base_address) {
|
---|
| 792 | /* TXD/SDA/MOSI:P20, RXD/SCL/MISO:P21, SCK:P22 */
|
---|
| 793 | case SCI0_BASE:
|
---|
| 794 | switch (mode) {
|
---|
| 795 | case sciSerial:
|
---|
| 796 | /* HIGHç¶æ
|
---|
| 797 | ã«è¨å® */
|
---|
| 798 | sil_wrb_mem(PORT2_PODR_ADDR,
|
---|
| 799 | sil_reb_mem(PORT2_PODR_ADDR) | PORT_PODR_B0_BIT | PORT_PODR_B1_BIT);
|
---|
| 800 | /* TXåºå/RXå
|
---|
| 801 | ¥åãã¼ãè¨å® */
|
---|
| 802 | sil_wrb_mem(PORT2_PDR_ADDR, (sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B0_BIT) & ~PORT_PDR_B1_BIT);
|
---|
| 803 | /* ãã«ã¢ããç¡å¹ */
|
---|
| 804 | sil_wrb_mem(PORT2_PCR_ADDR, sil_reb_mem(PORT2_PCR_ADDR) & ~(PORT_PCR_B0_BIT | PORT_PCR_B1_BIT));
|
---|
| 805 | /* RX CMOS */
|
---|
| 806 | sil_wrb_mem(PORT2_ODR0_ADDR,
|
---|
| 807 | (sil_reb_mem(PORT2_ODR0_ADDR) & ~(PORT_ODR_Pm0_MASK | PORT_ODR_Pm1_MASK))
|
---|
| 808 | | (PORT_ODR_CMOS << PORT_ODR_Pm0_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm1_OFFSET));
|
---|
| 809 | /* å¨è¾ºæ©è½ã¨ãã¦ä½¿ç¨ */
|
---|
| 810 | sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B0_BIT | PORT_PMR_B1_BIT);
|
---|
| 811 | break;
|
---|
| 812 | case sciI2C:
|
---|
| 813 | /* HIGHç¶æ
|
---|
| 814 | ã«è¨å® */
|
---|
| 815 | sil_wrb_mem(PORT2_PODR_ADDR,
|
---|
| 816 | sil_reb_mem(PORT2_PODR_ADDR) | PORT_PODR_B0_BIT | PORT_PODR_B1_BIT);
|
---|
| 817 | /* SCL,SDA åºåãã¼ãè¨å® */
|
---|
| 818 | sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B0_BIT | PORT_PDR_B1_BIT);
|
---|
| 819 | /* ãã«ã¢ããæå¹ */
|
---|
| 820 | sil_wrb_mem(PORT2_PCR_ADDR, sil_reb_mem(PORT2_PCR_ADDR) | PORT_PCR_B0_BIT | PORT_PCR_B1_BIT);
|
---|
| 821 | /* Nãã£ãã«ãªã¼ãã³ãã¬ã¤ã³ */
|
---|
| 822 | sil_wrb_mem(PORT2_ODR0_ADDR,
|
---|
| 823 | (sil_reb_mem(PORT2_ODR0_ADDR) & ~(PORT_ODR_Pm0_MASK | PORT_ODR_Pm1_MASK))
|
---|
| 824 | | (PORT_ODR_NCH_OPEN_DRAIN << PORT_ODR_Pm0_OFFSET) | (PORT_ODR_NCH_OPEN_DRAIN << PORT_ODR_Pm1_OFFSET));
|
---|
| 825 | /* å¨è¾ºæ©è½ã¨ãã¦ä½¿ç¨ */
|
---|
| 826 | sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B0_BIT | PORT_PMR_B1_BIT);
|
---|
| 827 | break;
|
---|
| 828 | case sciSPIM:
|
---|
| 829 | /* HIGHç¶æ
|
---|
| 830 | ã«è¨å® */
|
---|
| 831 | sil_wrb_mem(PORT2_PODR_ADDR,
|
---|
| 832 | sil_reb_mem(PORT2_PODR_ADDR) | PORT_PODR_B0_BIT | PORT_PODR_B1_BIT | PORT_PODR_B2_BIT);
|
---|
| 833 | /* MOSIåºå/MISOå
|
---|
| 834 | ¥å/SCKå
|
---|
| 835 | ¥åºåãã¼ãè¨å® */
|
---|
| 836 | sil_wrb_mem(PORT2_PDR_ADDR, (sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B0_BIT | PORT_PDR_B2_BIT) & ~PORT_PDR_B1_BIT);
|
---|
| 837 | /* ãã«ã¢ããç¡å¹ */
|
---|
| 838 | sil_wrb_mem(PORT2_PCR_ADDR, sil_reb_mem(PORT2_PCR_ADDR) & ~(PORT_PCR_B0_BIT | PORT_PCR_B1_BIT | PORT_PCR_B2_BIT));
|
---|
| 839 | /* MISO CMOS */
|
---|
| 840 | sil_wrb_mem(PORT2_ODR0_ADDR,
|
---|
| 841 | (sil_reb_mem(PORT2_ODR0_ADDR) & ~(PORT_ODR_Pm0_MASK | PORT_ODR_Pm1_MASK | PORT_ODR_Pm2_MASK))
|
---|
| 842 | | (PORT_ODR_CMOS << PORT_ODR_Pm0_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm1_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm2_OFFSET));
|
---|
| 843 | /* å¨è¾ºæ©è½ã¨ãã¦ä½¿ç¨ */
|
---|
| 844 | sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B0_BIT | PORT_PMR_B1_BIT | PORT_PMR_B2_BIT);
|
---|
| 845 | break;
|
---|
| 846 | }
|
---|
| 847 | /* æ¸ãè¾¼ã¿ãããã¯ãã¬ã¸ã¹ã¿ã®è¨å® PFSWEãããã¸ã®æ¸ãè¾¼ã¿ãè¨±å¯ */
|
---|
| 848 | sil_wrb_mem(MPC_PWPR_ADDR, 0x00);
|
---|
| 849 | /* æ¸ãè¾¼ã¿ãããã¯ãã¬ã¸ã¹ã¿ã®è¨å® PxxFSã¬ã¸ã¹ã¿ã¸ã®æ¸ãè¾¼ã¿ãè¨±å¯ */
|
---|
| 850 | sil_wrb_mem(MPC_PWPR_ADDR, 0x40);
|
---|
| 851 |
|
---|
| 852 | /* P20端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ TXD0/SMOSI0/SSDA0ã¨ãã */
|
---|
| 853 | sil_wrb_mem(MPC_P20PFS_ADDR, 0x0A);
|
---|
| 854 | /* P21端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ RXD0/SMISO0/SSCL0ã¨ãã */
|
---|
| 855 | sil_wrb_mem(MPC_P21PFS_ADDR, 0x0A);
|
---|
| 856 | if (mode == sciSPIM) {
|
---|
| 857 | /* P22端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ SCK0ã¨ãã */
|
---|
| 858 | sil_wrb_mem(MPC_P22PFS_ADDR, 0x0A);
|
---|
| 859 | }
|
---|
| 860 |
|
---|
| 861 | /* æ¸ãè¾¼ã¿ãããã¯ãã¬ã¸ã¹ã¿ã®è¨å® æ¸ãè¾¼ã¿ãç¦æ¢ */
|
---|
| 862 | sil_wrb_mem(MPC_PWPR_ADDR, 0x80);
|
---|
| 863 | break;
|
---|
| 864 | /* TXD/SDA/MOSI:P50, RXD/SCL/MISO:P52, SCK:P51 */
|
---|
| 865 | case SCI2_BASE:
|
---|
| 866 | switch (mode) {
|
---|
| 867 | case sciSerial:
|
---|
| 868 | /* HIGHç¶æ
|
---|
| 869 | ã«è¨å® */
|
---|
| 870 | sil_wrb_mem(PORT5_PODR_ADDR,
|
---|
| 871 | sil_reb_mem(PORT5_PODR_ADDR) | PORT_PODR_B0_BIT | PORT_PODR_B2_BIT);
|
---|
| 872 | /* TXåºå/RXå
|
---|
| 873 | ¥åãã¼ãè¨å® */
|
---|
| 874 | sil_wrb_mem(PORT5_PDR_ADDR, (sil_reb_mem(PORT5_PDR_ADDR) | PORT_PDR_B0_BIT) & ~PORT_PDR_B2_BIT);
|
---|
| 875 | /* ãã«ã¢ããç¡å¹ */
|
---|
| 876 | sil_wrb_mem(PORT5_PCR_ADDR, sil_reb_mem(PORT5_PCR_ADDR) & ~(PORT_PCR_B0_BIT | PORT_PCR_B2_BIT));
|
---|
| 877 | /* RX CMOS */
|
---|
| 878 | sil_wrb_mem(PORT5_ODR0_ADDR,
|
---|
| 879 | (sil_reb_mem(PORT5_ODR0_ADDR) & ~(PORT_ODR_Pm0_MASK | PORT_ODR_Pm2_MASK))
|
---|
| 880 | | (PORT_ODR_CMOS << PORT_ODR_Pm0_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm2_OFFSET));
|
---|
| 881 | /* å¨è¾ºæ©è½ã¨ãã¦ä½¿ç¨ */
|
---|
| 882 | sil_wrb_mem(PORT5_PMR_ADDR, sil_reb_mem(PORT5_PMR_ADDR) | PORT_PMR_B0_BIT | PORT_PMR_B2_BIT);
|
---|
| 883 | break;
|
---|
| 884 | case sciI2C:
|
---|
| 885 | /* HIGHç¶æ
|
---|
| 886 | ã«è¨å® */
|
---|
| 887 | sil_wrb_mem(PORT5_PODR_ADDR,
|
---|
| 888 | sil_reb_mem(PORT5_PODR_ADDR) | PORT_PODR_B0_BIT | PORT_PODR_B2_BIT);
|
---|
| 889 | /* SCL,SDA åºåãã¼ãè¨å® */
|
---|
| 890 | sil_wrb_mem(PORT5_PDR_ADDR, sil_reb_mem(PORT5_PDR_ADDR) | PORT_PDR_B0_BIT | PORT_PDR_B2_BIT);
|
---|
| 891 | /* ãã«ã¢ããæå¹ */
|
---|
| 892 | sil_wrb_mem(PORT5_PCR_ADDR, sil_reb_mem(PORT5_PCR_ADDR) | PORT_PCR_B0_BIT | PORT_PCR_B2_BIT);
|
---|
| 893 | /* Nãã£ãã«ãªã¼ãã³ãã¬ã¤ã³ */
|
---|
| 894 | sil_wrb_mem(PORT5_ODR0_ADDR,
|
---|
| 895 | (sil_reb_mem(PORT5_ODR0_ADDR) & ~(PORT_ODR_Pm0_MASK | PORT_ODR_Pm2_MASK))
|
---|
| 896 | | (PORT_ODR_NCH_OPEN_DRAIN << PORT_ODR_Pm0_OFFSET) | (PORT_ODR_NCH_OPEN_DRAIN << PORT_ODR_Pm2_OFFSET));
|
---|
| 897 | /* å¨è¾ºæ©è½ã¨ãã¦ä½¿ç¨ */
|
---|
| 898 | sil_wrb_mem(PORT5_PMR_ADDR, sil_reb_mem(PORT5_PMR_ADDR) | PORT_PMR_B0_BIT | PORT_PMR_B2_BIT);
|
---|
| 899 | break;
|
---|
| 900 | case sciSPIM:
|
---|
| 901 | /* HIGHç¶æ
|
---|
| 902 | ã«è¨å® */
|
---|
| 903 | sil_wrb_mem(PORT5_PODR_ADDR,
|
---|
| 904 | sil_reb_mem(PORT5_PODR_ADDR) | PORT_PODR_B0_BIT | PORT_PODR_B1_BIT | PORT_PODR_B2_BIT);
|
---|
| 905 | /* MOSIåºå/MISOå
|
---|
| 906 | ¥å/SCKå
|
---|
| 907 | ¥åºåãã¼ãè¨å® */
|
---|
| 908 | sil_wrb_mem(PORT5_PDR_ADDR, (sil_reb_mem(PORT5_PDR_ADDR) | PORT_PDR_B0_BIT | PORT_PDR_B1_BIT) & ~PORT_PDR_B2_BIT);
|
---|
| 909 | /* ãã«ã¢ããç¡å¹ */
|
---|
| 910 | sil_wrb_mem(PORT5_PCR_ADDR, sil_reb_mem(PORT5_PCR_ADDR) & ~(PORT_PCR_B0_BIT | PORT_PCR_B1_BIT | PORT_PCR_B2_BIT));
|
---|
| 911 | /* MISO CMOS */
|
---|
| 912 | sil_wrb_mem(PORT5_ODR0_ADDR,
|
---|
| 913 | (sil_reb_mem(PORT5_ODR0_ADDR) & ~(PORT_ODR_Pm0_MASK | PORT_ODR_Pm1_MASK | PORT_ODR_Pm2_MASK))
|
---|
| 914 | | (PORT_ODR_CMOS << PORT_ODR_Pm0_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm1_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm2_OFFSET));
|
---|
| 915 | /* å¨è¾ºæ©è½ã¨ãã¦ä½¿ç¨ */
|
---|
| 916 | sil_wrb_mem(PORT5_PMR_ADDR, sil_reb_mem(PORT5_PMR_ADDR) | PORT_PMR_B0_BIT | PORT_PMR_B1_BIT | PORT_PMR_B1_BIT | PORT_PMR_B2_BIT);
|
---|
| 917 | break;
|
---|
| 918 | }
|
---|
| 919 | /* æ¸ãè¾¼ã¿ãããã¯ãã¬ã¸ã¹ã¿ã®è¨å® PFSWEãããã¸ã®æ¸ãè¾¼ã¿ãè¨±å¯ */
|
---|
| 920 | sil_wrb_mem(MPC_PWPR_ADDR, 0x00);
|
---|
| 921 | /* æ¸ãè¾¼ã¿ãããã¯ãã¬ã¸ã¹ã¿ã®è¨å® PxxFSã¬ã¸ã¹ã¿ã¸ã®æ¸ãè¾¼ã¿ãè¨±å¯ */
|
---|
| 922 | sil_wrb_mem(MPC_PWPR_ADDR, 0x40);
|
---|
| 923 |
|
---|
| 924 | /* P50端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ SSDA2ã¨ãã */
|
---|
| 925 | sil_wrb_mem(MPC_P50PFS_ADDR, 0x0A);
|
---|
| 926 | /* P52端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ SSCL2ã¨ãã */
|
---|
| 927 | sil_wrb_mem(MPC_P52PFS_ADDR, 0x0A);
|
---|
| 928 | if (mode == sciSPIM) {
|
---|
| 929 | /* P51端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ SCK2ã¨ãã */
|
---|
| 930 | sil_wrb_mem(MPC_P51PFS_ADDR, 0x0A);
|
---|
| 931 | }
|
---|
| 932 |
|
---|
| 933 | /* æ¸ãè¾¼ã¿ãããã¯ãã¬ã¸ã¹ã¿ã®è¨å® æ¸ãè¾¼ã¿ãç¦æ¢ */
|
---|
| 934 | sil_wrb_mem(MPC_PWPR_ADDR, 0x80);
|
---|
| 935 | break;
|
---|
| 936 | /* TXD/SDA/MOSI:P23, RXD/SCL/MISO:P25, SCK:P24 */
|
---|
| 937 | case SCI3_BASE:
|
---|
| 938 | switch (mode) {
|
---|
| 939 | case sciSerial:
|
---|
| 940 | /* HIGHç¶æ
|
---|
| 941 | ã«è¨å® */
|
---|
| 942 | sil_wrb_mem(PORT2_PODR_ADDR,
|
---|
| 943 | sil_reb_mem(PORT2_PODR_ADDR) | PORT_PODR_B3_BIT | PORT_PODR_B5_BIT);
|
---|
| 944 | /* TXåºå/RXå
|
---|
| 945 | ¥åãã¼ãè¨å® */
|
---|
| 946 | sil_wrb_mem(PORT2_PDR_ADDR, (sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B3_BIT) & ~PORT_PDR_B5_BIT);
|
---|
| 947 | /* ãã«ã¢ããç¡å¹ */
|
---|
| 948 | sil_wrb_mem(PORT2_PCR_ADDR, sil_reb_mem(PORT2_PCR_ADDR) & ~(PORT_PCR_B3_BIT | PORT_PCR_B5_BIT));
|
---|
| 949 | /* RX CMOS */
|
---|
| 950 | sil_wrb_mem(PORT2_ODR0_ADDR,
|
---|
| 951 | (sil_reb_mem(PORT2_ODR0_ADDR) & ~(PORT_ODR_Pm3_MASK | PORT_ODR_Pm5_MASK))
|
---|
| 952 | | (PORT_ODR_CMOS << PORT_ODR_Pm3_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm5_OFFSET));
|
---|
| 953 | /* å¨è¾ºæ©è½ã¨ãã¦ä½¿ç¨ */
|
---|
| 954 | sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B3_BIT | PORT_PMR_B5_BIT);
|
---|
| 955 | break;
|
---|
| 956 | case sciI2C:
|
---|
| 957 | /* HIGHç¶æ
|
---|
| 958 | ã«è¨å® */
|
---|
| 959 | sil_wrb_mem(PORT2_PODR_ADDR,
|
---|
| 960 | sil_reb_mem(PORT2_PODR_ADDR) | PORT_PODR_B3_BIT | PORT_PODR_B5_BIT);
|
---|
| 961 | /* SCL,SDA åºåãã¼ãè¨å® */
|
---|
| 962 | sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B3_BIT | PORT_PDR_B5_BIT);
|
---|
| 963 | /* ãã«ã¢ããæå¹ */
|
---|
| 964 | sil_wrb_mem(PORT2_PCR_ADDR, sil_reb_mem(PORT2_PCR_ADDR) | PORT_PCR_B3_BIT | PORT_PCR_B5_BIT);
|
---|
| 965 | /* Nãã£ãã«ãªã¼ãã³ãã¬ã¤ã³ */
|
---|
| 966 | sil_wrb_mem(PORT2_ODR0_ADDR,
|
---|
| 967 | (sil_reb_mem(PORT2_ODR0_ADDR) & ~(PORT_ODR_Pm3_MASK | PORT_ODR_Pm5_MASK))
|
---|
| 968 | | (PORT_ODR_NCH_OPEN_DRAIN << PORT_ODR_Pm3_OFFSET) | (PORT_ODR_NCH_OPEN_DRAIN << PORT_ODR_Pm5_OFFSET));
|
---|
| 969 | /* å¨è¾ºæ©è½ã¨ãã¦ä½¿ç¨ */
|
---|
| 970 | sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B3_BIT | PORT_PMR_B5_BIT);
|
---|
| 971 | break;
|
---|
| 972 | case sciSPIM:
|
---|
| 973 | /* HIGHç¶æ
|
---|
| 974 | ã«è¨å® */
|
---|
| 975 | sil_wrb_mem(PORT2_PODR_ADDR,
|
---|
| 976 | sil_reb_mem(PORT2_PODR_ADDR) | PORT_PODR_B3_BIT | PORT_PODR_B4_BIT | PORT_PODR_B5_BIT);
|
---|
| 977 | /* MOSIåºå/MISOå
|
---|
| 978 | ¥å/SCKå
|
---|
| 979 | ¥åºåãã¼ãè¨å® */
|
---|
| 980 | sil_wrb_mem(PORT2_PDR_ADDR, (sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B3_BIT | PORT_PDR_B4_BIT) & ~PORT_PDR_B5_BIT);
|
---|
| 981 | /* ãã«ã¢ããç¡å¹ */
|
---|
| 982 | sil_wrb_mem(PORT2_PCR_ADDR, sil_reb_mem(PORT2_PCR_ADDR) & ~(PORT_PCR_B3_BIT | PORT_PCR_B4_BIT | PORT_PCR_B5_BIT));
|
---|
| 983 | /* MISO CMOS */
|
---|
| 984 | sil_wrb_mem(PORT2_ODR0_ADDR,
|
---|
| 985 | (sil_reb_mem(PORT2_ODR0_ADDR) & ~(PORT_ODR_Pm3_MASK | PORT_ODR_Pm4_MASK | PORT_ODR_Pm5_MASK))
|
---|
| 986 | | (PORT_ODR_CMOS << PORT_ODR_Pm3_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm4_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm5_OFFSET));
|
---|
| 987 | /* å¨è¾ºæ©è½ã¨ãã¦ä½¿ç¨ */
|
---|
| 988 | sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B3_BIT | PORT_PMR_B4_BIT | PORT_PMR_B4_BIT | PORT_PMR_B5_BIT);
|
---|
| 989 | break;
|
---|
| 990 | }
|
---|
| 991 | /* æ¸ãè¾¼ã¿ãããã¯ãã¬ã¸ã¹ã¿ã®è¨å® PFSWEãããã¸ã®æ¸ãè¾¼ã¿ãè¨±å¯ */
|
---|
| 992 | sil_wrb_mem(MPC_PWPR_ADDR, 0x00);
|
---|
| 993 | /* æ¸ãè¾¼ã¿ãããã¯ãã¬ã¸ã¹ã¿ã®è¨å® PxxFSã¬ã¸ã¹ã¿ã¸ã®æ¸ãè¾¼ã¿ãè¨±å¯ */
|
---|
| 994 | sil_wrb_mem(MPC_PWPR_ADDR, 0x40);
|
---|
| 995 |
|
---|
| 996 | /* P23端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ SSDA2ã¨ãã */
|
---|
| 997 | sil_wrb_mem(MPC_P23PFS_ADDR, 0x0A);
|
---|
| 998 | /* P25端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ SSCL2ã¨ãã */
|
---|
| 999 | sil_wrb_mem(MPC_P25PFS_ADDR, 0x0A);
|
---|
| 1000 | if (mode == sciSPIM) {
|
---|
| 1001 | /* P24端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ SCK2ã¨ãã */
|
---|
| 1002 | sil_wrb_mem(MPC_P24PFS_ADDR, 0x0A);
|
---|
| 1003 | }
|
---|
| 1004 |
|
---|
| 1005 | /* æ¸ãè¾¼ã¿ãããã¯ãã¬ã¸ã¹ã¿ã®è¨å® æ¸ãè¾¼ã¿ãç¦æ¢ */
|
---|
| 1006 | sil_wrb_mem(MPC_PWPR_ADDR, 0x80);
|
---|
| 1007 | break;
|
---|
| 1008 | /* TXD/SDA/MOSI:P32, RXD/SCL/MISO:P33, SCK:P34 */
|
---|
| 1009 | case SCI6_BASE:
|
---|
| 1010 | switch (mode) {
|
---|
| 1011 | case sciSerial:
|
---|
| 1012 | /* HIGHç¶æ
|
---|
| 1013 | ã«è¨å® */
|
---|
| 1014 | sil_wrb_mem(PORT3_PODR_ADDR,
|
---|
| 1015 | sil_reb_mem(PORT3_PODR_ADDR) | PORT_PODR_B2_BIT | PORT_PODR_B3_BIT);
|
---|
| 1016 | /* TXåºå/RXå
|
---|
| 1017 | ¥åãã¼ãè¨å® */
|
---|
| 1018 | sil_wrb_mem(PORT3_PDR_ADDR, (sil_reb_mem(PORT3_PDR_ADDR) | PORT_PDR_B2_BIT) & ~PORT_PDR_B3_BIT);
|
---|
| 1019 | /* ãã«ã¢ããç¡å¹ */
|
---|
| 1020 | sil_wrb_mem(PORT3_PCR_ADDR, sil_reb_mem(PORT3_PCR_ADDR) & ~(PORT_PCR_B2_BIT | PORT_PCR_B3_BIT));
|
---|
| 1021 | /* RX CMOS */
|
---|
| 1022 | sil_wrb_mem(PORT3_ODR0_ADDR,
|
---|
| 1023 | (sil_reb_mem(PORT3_ODR0_ADDR) & ~(PORT_ODR_Pm2_MASK | PORT_ODR_Pm3_MASK))
|
---|
| 1024 | | (PORT_ODR_CMOS << PORT_ODR_Pm2_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm3_OFFSET));
|
---|
| 1025 | /* å¨è¾ºæ©è½ã¨ãã¦ä½¿ç¨ */
|
---|
| 1026 | sil_wrb_mem(PORT3_PMR_ADDR, sil_reb_mem(PORT3_PMR_ADDR) | PORT_PMR_B2_BIT | PORT_PMR_B3_BIT);
|
---|
| 1027 | break;
|
---|
| 1028 | case sciI2C:
|
---|
| 1029 | /* HIGHç¶æ
|
---|
| 1030 | ã«è¨å® */
|
---|
| 1031 | sil_wrb_mem(PORT3_PODR_ADDR,
|
---|
| 1032 | sil_reb_mem(PORT3_PODR_ADDR) | PORT_PODR_B2_BIT | PORT_PODR_B3_BIT);
|
---|
| 1033 | /* SCL,SDA åºåãã¼ãè¨å® */
|
---|
| 1034 | sil_wrb_mem(PORT3_PDR_ADDR, sil_reb_mem(PORT3_PDR_ADDR) | PORT_PDR_B2_BIT | PORT_PDR_B3_BIT);
|
---|
| 1035 | /* ãã«ã¢ããæå¹ */
|
---|
| 1036 | sil_wrb_mem(PORT3_PCR_ADDR, sil_reb_mem(PORT3_PCR_ADDR) | PORT_PCR_B2_BIT | PORT_PCR_B3_BIT);
|
---|
| 1037 | /* Nãã£ãã«ãªã¼ãã³ãã¬ã¤ã³ */
|
---|
| 1038 | sil_wrb_mem(PORT3_ODR0_ADDR,
|
---|
| 1039 | (sil_reb_mem(PORT3_ODR0_ADDR) & ~(PORT_ODR_Pm2_MASK | PORT_ODR_Pm3_MASK))
|
---|
| 1040 | | (PORT_ODR_NCH_OPEN_DRAIN << PORT_ODR_Pm2_OFFSET) | (PORT_ODR_NCH_OPEN_DRAIN << PORT_ODR_Pm3_OFFSET));
|
---|
| 1041 | /* å¨è¾ºæ©è½ã¨ãã¦ä½¿ç¨ */
|
---|
| 1042 | sil_wrb_mem(PORT3_PMR_ADDR, sil_reb_mem(PORT3_PMR_ADDR) | PORT_PMR_B2_BIT | PORT_PMR_B3_BIT);
|
---|
| 1043 | break;
|
---|
| 1044 | case sciSPIM:
|
---|
| 1045 | /* HIGHç¶æ
|
---|
| 1046 | ã«è¨å® */
|
---|
| 1047 | sil_wrb_mem(PORT3_PODR_ADDR,
|
---|
| 1048 | sil_reb_mem(PORT3_PODR_ADDR) | PORT_PODR_B2_BIT | PORT_PODR_B3_BIT | PORT_PODR_B4_BIT);
|
---|
| 1049 | /* MOSIåºå/MISOå
|
---|
| 1050 | ¥å/SCKå
|
---|
| 1051 | ¥åºåãã¼ãè¨å® */
|
---|
| 1052 | sil_wrb_mem(PORT3_PDR_ADDR, (sil_reb_mem(PORT3_PDR_ADDR) | PORT_PDR_B2_BIT | PORT_PDR_B4_BIT) & ~PORT_PDR_B3_BIT);
|
---|
| 1053 | /* ãã«ã¢ããç¡å¹ */
|
---|
| 1054 | sil_wrb_mem(PORT3_PCR_ADDR, sil_reb_mem(PORT3_PCR_ADDR) & ~(PORT_PCR_B2_BIT | PORT_PCR_B3_BIT | PORT_PCR_B4_BIT));
|
---|
| 1055 | /* MISO CMOS */
|
---|
| 1056 | sil_wrb_mem(PORT3_ODR0_ADDR,
|
---|
| 1057 | (sil_reb_mem(PORT3_ODR0_ADDR) & ~(PORT_ODR_Pm2_MASK | PORT_ODR_Pm3_MASK | PORT_ODR_Pm4_MASK))
|
---|
| 1058 | | (PORT_ODR_CMOS << PORT_ODR_Pm2_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm3_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm4_OFFSET));
|
---|
| 1059 | /* å¨è¾ºæ©è½ã¨ãã¦ä½¿ç¨ */
|
---|
| 1060 | sil_wrb_mem(PORT3_PMR_ADDR, sil_reb_mem(PORT3_PMR_ADDR) | PORT_PMR_B2_BIT | PORT_PMR_B3_BIT | PORT_PMR_B4_BIT);
|
---|
| 1061 | break;
|
---|
| 1062 | }
|
---|
| 1063 |
|
---|
| 1064 | /* æ¸ãè¾¼ã¿ãããã¯ãã¬ã¸ã¹ã¿ã®è¨å® PFSWEãããã¸ã®æ¸ãè¾¼ã¿ãè¨±å¯ */
|
---|
| 1065 | sil_wrb_mem(MPC_PWPR_ADDR, 0x00);
|
---|
| 1066 | /* æ¸ãè¾¼ã¿ãããã¯ãã¬ã¸ã¹ã¿ã®è¨å® PxxFSã¬ã¸ã¹ã¿ã¸ã®æ¸ãè¾¼ã¿ãè¨±å¯ */
|
---|
| 1067 | sil_wrb_mem(MPC_PWPR_ADDR, 0x40);
|
---|
| 1068 |
|
---|
| 1069 | /* P32端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ TXD6/SMOSI6/SSDA6ã¨ãã */
|
---|
| 1070 | sil_wrb_mem(MPC_P32PFS_ADDR, 0x0A);
|
---|
| 1071 | /* P33端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ RXD6/SMISO6/SSCL6ã¨ãã */
|
---|
| 1072 | sil_wrb_mem(MPC_P33PFS_ADDR, 0x0A);
|
---|
| 1073 | if (mode == sciSPIM) {
|
---|
| 1074 | /* P34端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ SCK6ã¨ãã */
|
---|
| 1075 | sil_wrb_mem(MPC_P34PFS_ADDR, 0x0A);
|
---|
| 1076 | }
|
---|
| 1077 |
|
---|
| 1078 | /* æ¸ãè¾¼ã¿ãããã¯ãã¬ã¸ã¹ã¿ã®è¨å® æ¸ãè¾¼ã¿ãç¦æ¢ */
|
---|
| 1079 | sil_wrb_mem(MPC_PWPR_ADDR, 0x80);
|
---|
| 1080 | break;
|
---|
| 1081 | /* TXD/SDA/MOSI:PC7, RXD/SCL/MISO:PC6, SCK:PC5 */
|
---|
| 1082 | case SCI8_BASE:
|
---|
| 1083 | switch (mode) {
|
---|
| 1084 | case sciSerial:
|
---|
| 1085 | /* HIGHç¶æ
|
---|
| 1086 | ã«è¨å® */
|
---|
| 1087 | sil_wrb_mem(PORTC_PODR_ADDR,
|
---|
| 1088 | sil_reb_mem(PORTC_PODR_ADDR) | PORT_PODR_B6_BIT | PORT_PODR_B7_BIT);
|
---|
| 1089 | /* TXåºå/RXå
|
---|
| 1090 | ¥åãã¼ãè¨å® */
|
---|
| 1091 | sil_wrb_mem(PORTC_PDR_ADDR, (sil_reb_mem(PORTC_PDR_ADDR) | PORT_PDR_B6_BIT) & ~PORT_PDR_B7_BIT);
|
---|
| 1092 | /* ãã«ã¢ããç¡å¹ */
|
---|
| 1093 | sil_wrb_mem(PORTC_PCR_ADDR, sil_reb_mem(PORTC_PCR_ADDR) & ~(PORT_PCR_B6_BIT | PORT_PCR_B7_BIT));
|
---|
| 1094 | /* RX CMOS */
|
---|
| 1095 | sil_wrb_mem(PORTC_ODR0_ADDR,
|
---|
| 1096 | (sil_reb_mem(PORTC_ODR0_ADDR) & ~(PORT_ODR_Pm6_MASK | PORT_ODR_Pm7_MASK))
|
---|
| 1097 | | (PORT_ODR_CMOS << PORT_ODR_Pm6_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm7_OFFSET));
|
---|
| 1098 | /* å¨è¾ºæ©è½ã¨ãã¦ä½¿ç¨ */
|
---|
| 1099 | sil_wrb_mem(PORTC_PMR_ADDR, sil_reb_mem(PORTC_PMR_ADDR) | PORT_PMR_B6_BIT | PORT_PMR_B7_BIT);
|
---|
| 1100 | break;
|
---|
| 1101 | case sciI2C:
|
---|
| 1102 | /* HIGHç¶æ
|
---|
| 1103 | ã«è¨å® */
|
---|
| 1104 | sil_wrb_mem(PORTC_PODR_ADDR,
|
---|
| 1105 | sil_reb_mem(PORTC_PODR_ADDR) | PORT_PODR_B6_BIT | PORT_PODR_B7_BIT);
|
---|
| 1106 | /* SCL,SDA åºåãã¼ãè¨å® */
|
---|
| 1107 | sil_wrb_mem(PORTC_PDR_ADDR, sil_reb_mem(PORTC_PDR_ADDR) | PORT_PDR_B6_BIT | PORT_PDR_B7_BIT);
|
---|
| 1108 | /* ãã«ã¢ããæå¹ */
|
---|
| 1109 | sil_wrb_mem(PORTC_PCR_ADDR, sil_reb_mem(PORTC_PCR_ADDR) | PORT_PCR_B6_BIT | PORT_PCR_B7_BIT);
|
---|
| 1110 | /* Nãã£ãã«ãªã¼ãã³ãã¬ã¤ã³ */
|
---|
| 1111 | sil_wrb_mem(PORTC_ODR0_ADDR,
|
---|
| 1112 | (sil_reb_mem(PORTC_ODR0_ADDR) & ~(PORT_ODR_Pm6_MASK | PORT_ODR_Pm7_MASK))
|
---|
| 1113 | | (PORT_ODR_NCH_OPEN_DRAIN << PORT_ODR_Pm6_OFFSET) | (PORT_ODR_NCH_OPEN_DRAIN << PORT_ODR_Pm7_OFFSET));
|
---|
| 1114 | /* å¨è¾ºæ©è½ã¨ãã¦ä½¿ç¨ */
|
---|
| 1115 | sil_wrb_mem(PORTC_PMR_ADDR, sil_reb_mem(PORTC_PMR_ADDR) | PORT_PMR_B6_BIT | PORT_PMR_B7_BIT);
|
---|
| 1116 | break;
|
---|
| 1117 | case sciSPIM:
|
---|
| 1118 | /* HIGHç¶æ
|
---|
| 1119 | ã«è¨å® */
|
---|
| 1120 | sil_wrb_mem(PORTC_PODR_ADDR,
|
---|
| 1121 | sil_reb_mem(PORTC_PODR_ADDR) | PORT_PODR_B7_BIT | PORT_PODR_B6_BIT | PORT_PODR_B5_BIT);
|
---|
| 1122 | /* MOSIåºå/MISOå
|
---|
| 1123 | ¥å/SCKå
|
---|
| 1124 | ¥åºåãã¼ãè¨å® */
|
---|
| 1125 | sil_wrb_mem(PORTC_PDR_ADDR, (sil_reb_mem(PORTC_PDR_ADDR) | PORT_PDR_B5_BIT | PORT_PDR_B7_BIT) & ~PORT_PDR_B6_BIT);
|
---|
| 1126 | /* ãã«ã¢ããç¡å¹ */
|
---|
| 1127 | sil_wrb_mem(PORTC_PCR_ADDR, sil_reb_mem(PORTC_PCR_ADDR) & ~(PORT_PCR_B5_BIT | PORT_PCR_B7_BIT | PORT_PCR_B6_BIT));
|
---|
| 1128 | /* MISO CMOS */
|
---|
| 1129 | sil_wrb_mem(PORTC_ODR0_ADDR,
|
---|
| 1130 | (sil_reb_mem(PORTC_ODR0_ADDR) & ~(PORT_ODR_Pm5_MASK | PORT_ODR_Pm6_MASK | PORT_ODR_Pm7_MASK))
|
---|
| 1131 | | (PORT_ODR_CMOS << PORT_ODR_Pm5_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm6_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm7_OFFSET));
|
---|
| 1132 | /* å¨è¾ºæ©è½ã¨ãã¦ä½¿ç¨ */
|
---|
| 1133 | sil_wrb_mem(PORTC_PMR_ADDR, sil_reb_mem(PORTC_PMR_ADDR) | PORT_PMR_B5_BIT | PORT_PMR_B6_BIT | PORT_PMR_B7_BIT);
|
---|
| 1134 | break;
|
---|
| 1135 | }
|
---|
| 1136 |
|
---|
| 1137 | /* æ¸ãè¾¼ã¿ãããã¯ãã¬ã¸ã¹ã¿ã®è¨å® PFSWEãããã¸ã®æ¸ãè¾¼ã¿ãè¨±å¯ */
|
---|
| 1138 | sil_wrb_mem(MPC_PWPR_ADDR, 0x00);
|
---|
| 1139 | /* æ¸ãè¾¼ã¿ãããã¯ãã¬ã¸ã¹ã¿ã®è¨å® PxxFSã¬ã¸ã¹ã¿ã¸ã®æ¸ãè¾¼ã¿ãè¨±å¯ */
|
---|
| 1140 | sil_wrb_mem(MPC_PWPR_ADDR, 0x40);
|
---|
| 1141 |
|
---|
| 1142 | /* PC7端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ TXD8/SMOSI8/SSDA8ã¨ãã */
|
---|
| 1143 | sil_wrb_mem(MPC_PC7PFS_ADDR, 0x0A);
|
---|
| 1144 | /* PC6端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ RXD8/SMISO8/SSCL8ã¨ãã */
|
---|
| 1145 | sil_wrb_mem(MPC_PC6PFS_ADDR, 0x0A);
|
---|
| 1146 | if (mode == sciSPIM) {
|
---|
| 1147 | /* PC5端åæ©è½å¶å¾¡ã¬ã¸ã¹ã¿ SCK8ã¨ãã */
|
---|
| 1148 | sil_wrb_mem(MPC_PC5PFS_ADDR, 0x0A);
|
---|
| 1149 | }
|
---|
| 1150 |
|
---|
| 1151 | /* æ¸ãè¾¼ã¿ãããã¯ãã¬ã¸ã¹ã¿ã®è¨å® æ¸ãè¾¼ã¿ãç¦æ¢ */
|
---|
| 1152 | sil_wrb_mem(MPC_PWPR_ADDR, 0x80);
|
---|
| 1153 | break;
|
---|
| 1154 | }
|
---|
| 1155 | }
|
---|
| 1156 |
|
---|
| 1157 | void sci_disable(void *base_address)
|
---|
| 1158 | {
|
---|
| 1159 | /* éåä¿¡ç¦æ¢, SCKn端åã¯å
|
---|
| 1160 | ¥åºåãã¼ãã¨ãã¦ä½¿ç¨ */
|
---|
| 1161 | sil_wrb_mem(SCI_SCR(base_address), 0x00U);
|
---|
| 1162 |
|
---|
| 1163 | /*
|
---|
| 1164 | * ã¢ã¸ã¥ã¼ã«ã¹ãããæ©è½ã®è¨å®
|
---|
| 1165 | */
|
---|
| 1166 | sil_wrh_mem(SYSTEM_PRCR_ADDR, (uint16_t)0xA502); /* æ¸è¾¼ã¿è¨±å¯ */
|
---|
| 1167 | sil_wrw_mem(SYSTEM_MSTPCRB_ADDR,
|
---|
| 1168 | sil_rew_mem(SYSTEM_MSTPCRB_ADDR) | SCI_MSTPCRB_BIT(base_address));
|
---|
| 1169 | sil_wrh_mem(SYSTEM_PRCR_ADDR, (uint16_t)0xA500); /* æ¸è¾¼ã¿ç¦æ¢ */
|
---|
| 1170 | }
|
---|
| 1171 |
|
---|
| 1172 | void sci_set_frequency(void *base_address, int hz)
|
---|
| 1173 | {
|
---|
| 1174 | uint_t cnt, brr, clk;
|
---|
| 1175 |
|
---|
| 1176 | cnt = (FREQ_PCLK * 1000) / (16 * hz);
|
---|
| 1177 | if (cnt < 512)
|
---|
| 1178 | clk = 0;
|
---|
| 1179 | else if (cnt < 4 * 512)
|
---|
| 1180 | clk = 1;
|
---|
| 1181 | else if (cnt < 16 * 512)
|
---|
| 1182 | clk = 2;
|
---|
| 1183 | else if (cnt < 64 * 512)
|
---|
| 1184 | clk = 3;
|
---|
| 1185 | else
|
---|
| 1186 | return;
|
---|
| 1187 |
|
---|
| 1188 | brr = cnt / (1 << (2 * clk));
|
---|
| 1189 | brr = (brr / 2) + (brr % 2) - 1;
|
---|
| 1190 |
|
---|
| 1191 | /* SMRã«éä¿¡ï¼ åä¿¡ãã©ã¼ããããè¨å® */
|
---|
| 1192 | /* ã¯ããã¯é¸æããã(SMR.CKS[1:0]ããããè¨å®)ããã以å¤ã®ããããâ0âã«è¨å® */
|
---|
| 1193 | sil_wrb_mem(SCI_SMR(base_address), clk);
|
---|
| 1194 |
|
---|
| 1195 | /* ãããã¬ã¼ããè¨å® */
|
---|
| 1196 | sil_wrb_mem(SCI_BRR(base_address), brr);
|
---|
| 1197 | }
|
---|
| 1198 |
|
---|
| 1199 | void serial_init(serial_t *obj, PinName tx, PinName rx)
|
---|
| 1200 | {
|
---|
| 1201 | #ifdef TOPPERS_GRCITRUS
|
---|
| 1202 | if ((rx == D1) && (tx == D0)) {
|
---|
| 1203 | obj->base_address = (void *)SCI0_BASE;
|
---|
| 1204 | obj->rxi_intno = INT_SCI0_RXI;
|
---|
| 1205 | obj->tei_intno = INT_SCI0_TEI;
|
---|
| 1206 | }
|
---|
| 1207 | else if ((rx == D6) && (tx == D5)) {
|
---|
| 1208 | obj->base_address = (void *)SCI2_BASE;
|
---|
| 1209 | obj->rxi_intno = INT_SCI2_RXI;
|
---|
| 1210 | obj->tei_intno = INT_SCI2_TEI;
|
---|
| 1211 | }
|
---|
| 1212 | else if ((rx == D8) && (tx == D7)) {
|
---|
| 1213 | obj->base_address = (void *)SCI6_BASE;
|
---|
| 1214 | obj->rxi_intno = INT_SCI6_RXI;
|
---|
| 1215 | obj->tei_intno = INT_SCI6_TEI;
|
---|
| 1216 | }
|
---|
| 1217 | else if ((rx == D11) && (tx == D12)) {
|
---|
| 1218 | obj->base_address = (void *)SCI8_BASE;
|
---|
| 1219 | obj->rxi_intno = INT_SCI8_RXI;
|
---|
| 1220 | obj->tei_intno = INT_SCI8_TEI;
|
---|
| 1221 | }
|
---|
| 1222 | else {
|
---|
| 1223 | obj->base_address = NULL;
|
---|
| 1224 | return;
|
---|
| 1225 | }
|
---|
| 1226 | #else
|
---|
| 1227 | if ((rx == D0) && (tx == D1)) {
|
---|
| 1228 | obj->base_address = (void *)SCI0_BASE;
|
---|
| 1229 | obj->rxi_intno = INT_SCI0_RXI;
|
---|
| 1230 | obj->tei_intno = INT_SCI0_TEI;
|
---|
| 1231 | }
|
---|
| 1232 | else if ((rx == D6) && (tx == D7)) {
|
---|
| 1233 | obj->base_address = (void *)SCI6_BASE;
|
---|
| 1234 | obj->rxi_intno = INT_SCI6_RXI;
|
---|
| 1235 | obj->tei_intno = INT_SCI6_TEI;
|
---|
| 1236 | }
|
---|
| 1237 | else if ((rx == D11) && (tx == D12)) {
|
---|
| 1238 | obj->base_address = (void *)SCI8_BASE;
|
---|
| 1239 | obj->rxi_intno = INT_SCI8_RXI;
|
---|
| 1240 | obj->tei_intno = INT_SCI8_TEI;
|
---|
| 1241 | }
|
---|
| 1242 | else {
|
---|
| 1243 | obj->base_address = NULL;
|
---|
| 1244 | return;
|
---|
| 1245 | }
|
---|
| 1246 | #endif // TOPPERS_GRCITRUS
|
---|
| 1247 | dis_int(obj->rxi_intno);
|
---|
| 1248 | dis_int(obj->tei_intno);
|
---|
| 1249 |
|
---|
| 1250 | /* SCIæå¹ */
|
---|
| 1251 | sci_enable(obj->base_address, sciSerial);
|
---|
| 1252 |
|
---|
| 1253 | /* SIMR1.IICMããããâ0âã«è¨å® */
|
---|
| 1254 | sil_wrb_mem(SCI_SIMR1(obj->base_address),
|
---|
| 1255 | sil_reb_mem(SCI_SIMR1(obj->base_address)) & ~IICM);
|
---|
| 1256 |
|
---|
| 1257 | /* SPMR.CKPH, CKPOLããããâ0âã«è¨å® */
|
---|
| 1258 | sil_wrb_mem(SCI_SPMR(obj->base_address),
|
---|
| 1259 | sil_reb_mem(SCI_SPMR(obj->base_address)) & ~(CKPH | CKPOL));
|
---|
| 1260 |
|
---|
| 1261 | sci_set_frequency(obj->base_address, /*9600*/115200);
|
---|
| 1262 |
|
---|
| 1263 | /* SCMRã¬ã¸ã¹ã¿ã¯SDIRããããâ0âãSINVããããâ0âãSMIFããããâ0âã«è¨å® */
|
---|
| 1264 | sil_wrb_mem(SCI_SCMR(obj->base_address),
|
---|
| 1265 | (sil_reb_mem(SCI_SCMR(obj->base_address)) & ~(SINV | SMIF | SDIR)));
|
---|
| 1266 |
|
---|
| 1267 | /* SMRã«éä¿¡ï¼ åä¿¡ãã©ã¼ããããè¨å® */
|
---|
| 1268 | serial_format(obj, 8, ParityNone, 1);
|
---|
| 1269 |
|
---|
| 1270 | /* éåä¿¡è¨±å¯ */
|
---|
| 1271 | sil_wrb_mem(SCI_SCR(obj->base_address),
|
---|
| 1272 | (sil_reb_mem(SCI_SCR(obj->base_address)) | RE | TE));
|
---|
| 1273 |
|
---|
| 1274 | ena_int(obj->rxi_intno);
|
---|
| 1275 | ena_int(obj->tei_intno);
|
---|
| 1276 | }
|
---|
| 1277 |
|
---|
| 1278 | void serial_free(serial_t *obj)
|
---|
| 1279 | {
|
---|
| 1280 | dis_int(obj->rxi_intno);
|
---|
| 1281 | dis_int(obj->tei_intno);
|
---|
| 1282 |
|
---|
| 1283 | /* SCIç¡å¹ */
|
---|
| 1284 | sci_disable(obj->base_address);
|
---|
| 1285 |
|
---|
| 1286 | obj->base_address = NULL;
|
---|
| 1287 | }
|
---|
| 1288 |
|
---|
| 1289 | void serial_baud(serial_t *obj, int baudrate)
|
---|
| 1290 | {
|
---|
| 1291 | uint8_t scr = sil_reb_mem(SCI_SCR(obj->base_address));
|
---|
| 1292 |
|
---|
| 1293 | /* éåä¿¡ç¦æ¢, SCKn端åã¯å
|
---|
| 1294 | ¥åºåãã¼ãã¨ãã¦ä½¿ç¨ */
|
---|
| 1295 | sil_wrb_mem(SCI_SCR(obj->base_address), 0x00U);
|
---|
| 1296 |
|
---|
| 1297 | sci_set_frequency(obj->base_address, baudrate);
|
---|
| 1298 |
|
---|
| 1299 | /* éåä¿¡è¨±å¯ */
|
---|
| 1300 | sil_wrb_mem(SCI_SCR(obj->base_address), scr);
|
---|
| 1301 | }
|
---|
| 1302 |
|
---|
| 1303 | void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
|
---|
| 1304 | {
|
---|
| 1305 | uint8_t smr = sil_reb_mem(SCI_SMR(obj->base_address));
|
---|
| 1306 |
|
---|
| 1307 | smr &= ~(PE | PM | CHR | STOP);
|
---|
| 1308 |
|
---|
| 1309 | switch (parity) {
|
---|
| 1310 | case ParityNone:
|
---|
| 1311 | break;
|
---|
| 1312 | case ParityOdd:
|
---|
| 1313 | smr |= PE | PM;
|
---|
| 1314 | break;
|
---|
| 1315 | case ParityEven:
|
---|
| 1316 | smr |= PE;
|
---|
| 1317 | break;
|
---|
| 1318 | default:
|
---|
| 1319 | break;
|
---|
| 1320 | }
|
---|
| 1321 |
|
---|
| 1322 | switch (data_bits) {
|
---|
| 1323 | case 7:
|
---|
| 1324 | smr |= CHR;
|
---|
| 1325 | break;
|
---|
| 1326 | case 8:
|
---|
| 1327 | break;
|
---|
| 1328 | default:
|
---|
| 1329 | break;
|
---|
| 1330 | }
|
---|
| 1331 |
|
---|
| 1332 | switch (stop_bits) {
|
---|
| 1333 | case 1:
|
---|
| 1334 | break;
|
---|
| 1335 | case 2:
|
---|
| 1336 | smr |= STOP;
|
---|
| 1337 | break;
|
---|
| 1338 | default:
|
---|
| 1339 | break;
|
---|
| 1340 | }
|
---|
| 1341 |
|
---|
| 1342 | sil_wrb_mem(SCI_SMR(obj->base_address), smr);
|
---|
| 1343 | }
|
---|
| 1344 |
|
---|
| 1345 | int serial_getc(serial_t *obj)
|
---|
| 1346 | {
|
---|
| 1347 | uint8_t ssr;
|
---|
| 1348 | int c;
|
---|
| 1349 |
|
---|
| 1350 | for (;;) {
|
---|
| 1351 | /* SSR.ORER, PER, FERãã©ã°ããªã¼ã */
|
---|
| 1352 | ssr = sil_reb_mem(SCI_SSR(obj->base_address));
|
---|
| 1353 |
|
---|
| 1354 | /* åä¿¡ã¨ã©ã¼ãçºçããã¨ã */
|
---|
| 1355 | if ((ssr & (ORER | PER | FER)) != 0) {
|
---|
| 1356 | /* ãªã¼ãã©ã³ã¨ã©ã¼ */
|
---|
| 1357 | if ((ssr & ORER) != 0) {
|
---|
| 1358 | /* RDRã¬ã¸ã¹ã¿ããªã¼ã */
|
---|
| 1359 | c = (int)sil_reb_mem(SCI_RDR(obj->base_address));
|
---|
| 1360 | }
|
---|
| 1361 | /* ãã¬ã¼ãã³ã°ã¨ã©ã¼ */
|
---|
| 1362 | if ((ssr & FER) != 0) {
|
---|
| 1363 | }
|
---|
| 1364 | /* ããªãã£ã¨ã©ã¼ */
|
---|
| 1365 | if ((ssr & PER) != 0) {
|
---|
| 1366 | }
|
---|
| 1367 | }
|
---|
| 1368 |
|
---|
| 1369 | /* SSR.ORER, PER, FERãã©ã°ãâ0âã«è¨å® */
|
---|
| 1370 | sil_wrb_mem(SCI_SSR(obj->base_address), ssr & ~(ORER | PER | FER));
|
---|
| 1371 |
|
---|
| 1372 | /* SSR.ORER, PER, FERãã©ã°ããªã¼ã */
|
---|
| 1373 | ssr = sil_reb_mem(SCI_SSR(obj->base_address));
|
---|
| 1374 |
|
---|
| 1375 | /* RXIå²ã込㿠*/
|
---|
| 1376 | if (serial_readable(obj)) {
|
---|
| 1377 | clear_int(obj->rxi_intno);
|
---|
| 1378 | break;
|
---|
| 1379 | }
|
---|
| 1380 |
|
---|
| 1381 | dly_tsk(10);
|
---|
| 1382 | }
|
---|
| 1383 |
|
---|
| 1384 | /* RDRã¬ã¸ã¹ã¿ããªã¼ã */
|
---|
| 1385 | c = (int)sil_reb_mem(SCI_RDR(obj->base_address));
|
---|
| 1386 |
|
---|
| 1387 | return c;
|
---|
| 1388 | }
|
---|
| 1389 |
|
---|
| 1390 | void serial_putc(serial_t *obj, int c)
|
---|
| 1391 | {
|
---|
| 1392 | while (!serial_writable(obj))
|
---|
| 1393 | dly_tsk(10);
|
---|
| 1394 |
|
---|
| 1395 | sil_wrb_mem(SCI_TDR(obj->base_address), (char)c);
|
---|
| 1396 |
|
---|
| 1397 | clear_int(obj->tei_intno);
|
---|
| 1398 | }
|
---|
| 1399 |
|
---|
| 1400 | int serial_readable(serial_t *obj)
|
---|
| 1401 | {
|
---|
| 1402 | //return probe_int(obj->rxi_intno);
|
---|
| 1403 | return true;
|
---|
| 1404 | }
|
---|
| 1405 |
|
---|
| 1406 | int serial_writable(serial_t *obj)
|
---|
| 1407 | {
|
---|
| 1408 | //return probe_int(obj->tei_intno);
|
---|
| 1409 | return (sil_reb_mem(SCI_SSR(obj->base_address)) & TEND) != 0U;
|
---|
| 1410 | }
|
---|
| 1411 |
|
---|
| 1412 | void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
|
---|
| 1413 | {
|
---|
| 1414 | switch (irq) {
|
---|
| 1415 | case RxIrq:
|
---|
| 1416 | if (enable) {
|
---|
| 1417 | sil_wrb_mem(SCI_SCR(obj->base_address),
|
---|
| 1418 | (sil_reb_mem(SCI_SCR(obj->base_address)) | RIE));
|
---|
| 1419 | }
|
---|
| 1420 | else {
|
---|
| 1421 | sil_wrb_mem(SCI_SCR(obj->base_address),
|
---|
| 1422 | (sil_reb_mem(SCI_SCR(obj->base_address)) & (~RIE)));
|
---|
| 1423 | }
|
---|
| 1424 | break;
|
---|
| 1425 | case TxIrq:
|
---|
| 1426 | if (enable) {
|
---|
| 1427 | sil_wrb_mem(SCI_SCR(obj->base_address),
|
---|
| 1428 | (sil_reb_mem(SCI_SCR(obj->base_address)) | TEIE));
|
---|
| 1429 | }
|
---|
| 1430 | else {
|
---|
| 1431 | sil_wrb_mem(SCI_SCR(obj->base_address),
|
---|
| 1432 | (sil_reb_mem(SCI_SCR(obj->base_address)) & (~TEIE)));
|
---|
| 1433 | }
|
---|
| 1434 | break;
|
---|
| 1435 | }
|
---|
| 1436 | }
|
---|
| 1437 |
|
---|
| 1438 | struct uart_irq_info_t {
|
---|
| 1439 | uart_irq_handler handler;
|
---|
| 1440 | uint32_t id;
|
---|
| 1441 | };
|
---|
| 1442 |
|
---|
| 1443 | struct uart_irq_info_t sci_irq_info[7];
|
---|
| 1444 |
|
---|
| 1445 | void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
|
---|
| 1446 | {
|
---|
| 1447 | int no = SCI_NUM(obj->base_address);
|
---|
| 1448 | bool_t lock = sense_lock();
|
---|
| 1449 |
|
---|
| 1450 | if (!lock)
|
---|
| 1451 | loc_cpu();
|
---|
| 1452 |
|
---|
| 1453 | sci_irq_info[no].handler = handler;
|
---|
| 1454 | sci_irq_info[no].id = id;
|
---|
| 1455 |
|
---|
| 1456 | if (!lock)
|
---|
| 1457 | unl_cpu();
|
---|
| 1458 | }
|
---|
| 1459 |
|
---|
| 1460 | void i2c_init(i2c_t *obj, PinName sda, PinName scl)
|
---|
| 1461 | {
|
---|
| 1462 | if ((sda == I2C_SDA) && (scl == I2C_SCL)) {
|
---|
| 1463 | #ifdef TOPPERS_GRCITRUS
|
---|
| 1464 | obj->base_address = (void *)SCI6_BASE;
|
---|
| 1465 | obj->rxi_intno = INT_SCI6_RXI;
|
---|
| 1466 | obj->txi_intno = INT_SCI6_TXI;
|
---|
| 1467 | obj->tei_intno = INT_SCI6_TEI;
|
---|
| 1468 | #else
|
---|
| 1469 | obj->base_address = (void *)SCI2_BASE;
|
---|
| 1470 | obj->rxi_intno = INT_SCI2_RXI;
|
---|
| 1471 | obj->txi_intno = INT_SCI2_TXI;
|
---|
| 1472 | obj->tei_intno = INT_SCI2_TEI;
|
---|
| 1473 | #endif
|
---|
| 1474 | }
|
---|
| 1475 | else {
|
---|
| 1476 | obj->base_address = NULL;
|
---|
| 1477 | return;
|
---|
| 1478 | }
|
---|
| 1479 |
|
---|
| 1480 | /* SCIæå¹ */
|
---|
| 1481 | sci_enable(obj->base_address, sciI2C);
|
---|
| 1482 |
|
---|
| 1483 | /* SIMR3.IICSDAS[1:0](b5-b4), IICSCLS[1:0](b7-b6)ããããâ11bâã«è¨å® */
|
---|
| 1484 | sil_wrb_mem(SCI_SIMR3(obj->base_address), 0xF0U);
|
---|
| 1485 |
|
---|
| 1486 | sci_set_frequency(obj->base_address, 100000);
|
---|
| 1487 |
|
---|
| 1488 | /* SCMRã¬ã¸ã¹ã¿ã¯SDIRããããâ1âãSINVããããâ0âãSMIFããããâ0âã«è¨å® */
|
---|
| 1489 | sil_wrb_mem(SCI_SCMR(obj->base_address),
|
---|
| 1490 | (sil_reb_mem(SCI_SCMR(obj->base_address)) & ~(SINV | SMIF)) | SDIR);
|
---|
| 1491 |
|
---|
| 1492 | /* SEMRãSNFRãSIMR1ãSIMR2ãSPMRã¬ã¸ã¹ã¿ã«å¤ãè¨å® */
|
---|
| 1493 | /* SEMRã¬ã¸ã¹ã¿ã¯ãNFENããããè¨å® */
|
---|
| 1494 | sil_wrb_mem(SCI_SEMR(obj->base_address), NFEN);
|
---|
| 1495 |
|
---|
| 1496 | /* SNFRã¬ã¸ã¹ã¿ã¯ãNFCS[2:0]ããããè¨å®*/
|
---|
| 1497 | sil_wrb_mem(SCI_SNFR(obj->base_address), 1);
|
---|
| 1498 |
|
---|
| 1499 | /* SIMR1ã¬ã¸ã¹ã¿ã¯ãIICMããããâ1âã«è¨å®ããIICDL[4:0]ã ãããè¨å® */
|
---|
| 1500 | sil_wrb_mem(SCI_SIMR1(obj->base_address), IICM | (3 << 3));
|
---|
| 1501 |
|
---|
| 1502 | /* SIMR2ã¬ã¸ã¹ã¿ã¯ãIICACKTãIICCSCããããâ1âã«è¨å®ããIICINTMããããè¨å® */
|
---|
| 1503 | sil_wrb_mem(SCI_SIMR2(obj->base_address), IICACKT | IICCSC | IICINTM);
|
---|
| 1504 |
|
---|
| 1505 | /* SPMRã¬ã¸ã¹ã¿ã¯ãå
|
---|
| 1506 | ¨ãããâ0âã«è¨å® */
|
---|
| 1507 | sil_wrb_mem(SCI_SPMR(obj->base_address), 0);
|
---|
| 1508 |
|
---|
| 1509 | /* éåä¿¡è¨±å¯ */
|
---|
| 1510 | sil_wrb_mem(SCI_SCR(obj->base_address),
|
---|
| 1511 | (sil_reb_mem(SCI_SCR(obj->base_address)) | RE | TE));
|
---|
| 1512 | }
|
---|
| 1513 |
|
---|
| 1514 | void i2c_frequency(i2c_t *obj, int hz)
|
---|
| 1515 | {
|
---|
| 1516 | uint8_t scr = sil_reb_mem(SCI_SCR(obj->base_address));
|
---|
| 1517 |
|
---|
| 1518 | /* éåä¿¡ç¦æ¢, SCKn端åã¯å
|
---|
| 1519 | ¥åºåãã¼ãã¨ãã¦ä½¿ç¨ */
|
---|
| 1520 | sil_wrb_mem(SCI_SCR(obj->base_address), 0x00U);
|
---|
| 1521 |
|
---|
| 1522 | sci_set_frequency(obj->base_address, hz);
|
---|
| 1523 |
|
---|
| 1524 | /* éåä¿¡è¨±å¯ */
|
---|
| 1525 | sil_wrb_mem(SCI_SCR(obj->base_address), scr);
|
---|
| 1526 | }
|
---|
| 1527 |
|
---|
| 1528 | int i2c_start(i2c_t *obj)
|
---|
| 1529 | {
|
---|
| 1530 | if (obj->base_address == NULL)
|
---|
| 1531 | return 0;
|
---|
| 1532 |
|
---|
| 1533 | /* SIMR3.IICSTAREQããããâ1âã«è¨å®ããã¨åæã«ã
|
---|
| 1534 | * SIMR3.IICSCLS[1:0],IICSDAS[1:0]ããããâ01bâã«è¨å® */
|
---|
| 1535 | sil_wrb_mem(SCI_SIMR3(obj->base_address), IICSTAREQ | (1 << 4) | (1 << 6));
|
---|
| 1536 |
|
---|
| 1537 | return 0;
|
---|
| 1538 | }
|
---|
| 1539 |
|
---|
| 1540 | int i2c_restart(i2c_t *obj)
|
---|
| 1541 | {
|
---|
| 1542 | if (obj->base_address == NULL)
|
---|
| 1543 | return 0;
|
---|
| 1544 |
|
---|
| 1545 | sil_wrb_mem(SCI_SIMR3(obj->base_address), IICRSTAREQ | (1 << 4) | (1 << 6));
|
---|
| 1546 |
|
---|
| 1547 | return 0;
|
---|
| 1548 | }
|
---|
| 1549 |
|
---|
| 1550 | int i2c_stop(i2c_t *obj)
|
---|
| 1551 | {
|
---|
| 1552 | if (obj->base_address == NULL)
|
---|
| 1553 | return 0;
|
---|
| 1554 |
|
---|
| 1555 | /* SIMR3.IICSTPREQããããâ1âã«è¨å®ããã¨åæã«ã
|
---|
| 1556 | * SIMR3.IICSCLS[1:0],IICSDAS[1:0]ããããâ01bâã«è¨å® */
|
---|
| 1557 | sil_wrb_mem(SCI_SIMR3(obj->base_address), IICSTPREQ | (1 << 4) | (1 << 6));
|
---|
| 1558 |
|
---|
| 1559 | return 0;
|
---|
| 1560 | }
|
---|
| 1561 |
|
---|
| 1562 | int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
|
---|
| 1563 | {
|
---|
| 1564 | if (obj->base_address == NULL)
|
---|
| 1565 | return 0;
|
---|
| 1566 |
|
---|
| 1567 | /* éä¿¡å²ãè¾¼ã¿è¦æ±ãç¦æ¢ */
|
---|
| 1568 | sil_wrb_mem(SCI_SCR(obj->base_address),
|
---|
| 1569 | (sil_reb_mem(SCI_SCR(obj->base_address)) & ~(RIE)) | TEIE | TIE);
|
---|
| 1570 |
|
---|
| 1571 | /* éå§æ¡ä»¶ã®çæ */
|
---|
| 1572 | i2c_start(obj);
|
---|
| 1573 |
|
---|
| 1574 | /* STI(TEI)å²ãè¾¼ã¿çºçç¢ºèª */
|
---|
| 1575 | while (!probe_int(obj->tei_intno))
|
---|
| 1576 | dly_tsk(2);
|
---|
| 1577 | clear_int(obj->tei_intno);
|
---|
| 1578 |
|
---|
| 1579 | /* SIMR3.IICSTIFãã©ã°ãâ0âã«è¨å®ãã */
|
---|
| 1580 | sil_wrb_mem(SCI_SIMR3(obj->base_address),
|
---|
| 1581 | sil_reb_mem(SCI_SIMR3(obj->base_address)) & ~IICSTIF);
|
---|
| 1582 | /* SIMR3.IICSCLS[1:0], IICSDAS[1:0]ããããâ00bâã«è¨å® */
|
---|
| 1583 | sil_wrb_mem(SCI_SIMR3(obj->base_address),
|
---|
| 1584 | sil_reb_mem(SCI_SIMR3(obj->base_address)) & ~((3 << 4) | (3 << 6)));
|
---|
| 1585 |
|
---|
| 1586 | /* TDRã¬ã¸ã¹ã¿ã«ã¹ã¬ã¼ãã¢ãã¬ã¹ãR/Wããããã©ã¤ã */
|
---|
| 1587 | sil_wrb_mem(SCI_TDR(obj->base_address), address | 1);
|
---|
| 1588 |
|
---|
| 1589 | /* TXIå²ãè¾¼ã¿çºçç¢ºèª */
|
---|
| 1590 | while (!probe_int(obj->txi_intno))
|
---|
| 1591 | dly_tsk(10);
|
---|
| 1592 | clear_int(obj->txi_intno);
|
---|
| 1593 |
|
---|
| 1594 | /* ã¹ã¬ã¼ãããã¤ã¹ããã®ACKãç¢ºèª */
|
---|
| 1595 | if ((sil_reb_mem(SCI_SISR(obj->base_address)) & IICACKR) == 0) {
|
---|
| 1596 | /* SIMR2.IICACKTããããâ0âã«è¨å® */
|
---|
| 1597 | sil_wrb_mem(SCI_SIMR2(obj->base_address), sil_reb_mem(SCI_SIMR2(obj->base_address)) & ~IICACKT);
|
---|
| 1598 | /* SCR.RIEããããâ1âã«è¨å® */
|
---|
| 1599 | sil_wrb_mem(SCI_SCR(obj->base_address), sil_reb_mem(SCI_SCR(obj->base_address)) | RIE);
|
---|
| 1600 |
|
---|
| 1601 | for (int i = 0; i < length; i++) {
|
---|
| 1602 | /* 次ãã¼ã¿ãæçµ */
|
---|
| 1603 | if (i == length - 1) {
|
---|
| 1604 | /* SIMR2.IICACKTããããâ1âã«è¨å® */
|
---|
| 1605 | sil_wrb_mem(SCI_SIMR2(obj->base_address), sil_reb_mem(SCI_SIMR2(obj->base_address)) | IICACKT);
|
---|
| 1606 | }
|
---|
| 1607 |
|
---|
| 1608 | /* TDRã¬ã¸ã¹ã¿ã«ããã¼ãã¼ã¿âFFhâãã©ã¤ã */
|
---|
| 1609 | sil_wrb_mem(SCI_TDR(obj->base_address), 0xFF);
|
---|
| 1610 |
|
---|
| 1611 | /* RXIå²ãè¾¼ã¿çºçç¢ºèª */
|
---|
| 1612 | while (!probe_int(obj->rxi_intno))
|
---|
| 1613 | dly_tsk(10);
|
---|
| 1614 | clear_int(obj->rxi_intno);
|
---|
| 1615 |
|
---|
| 1616 | /* RDRã¬ã¸ã¹ã¿ã®åä¿¡ãã¼ã¿ããªã¼ã */
|
---|
| 1617 | *data = sil_reb_mem(SCI_RDR(obj->base_address));
|
---|
| 1618 | data++;
|
---|
| 1619 |
|
---|
| 1620 | /* TXIå²ãè¾¼ã¿çºçç¢ºèª */
|
---|
| 1621 | while (!probe_int(obj->txi_intno))
|
---|
| 1622 | dly_tsk(10);
|
---|
| 1623 | clear_int(obj->txi_intno);
|
---|
| 1624 | }
|
---|
| 1625 | }
|
---|
| 1626 |
|
---|
| 1627 | if (stop) {
|
---|
| 1628 | /* åæ¢æ¡ä»¶ã®çæ */
|
---|
| 1629 | i2c_stop(obj);
|
---|
| 1630 |
|
---|
| 1631 | /* STI(TEI)å²ãè¾¼ã¿çºçç¢ºèª */
|
---|
| 1632 | while (!probe_int(obj->tei_intno))
|
---|
| 1633 | dly_tsk(2);
|
---|
| 1634 | clear_int(obj->tei_intno);
|
---|
| 1635 |
|
---|
| 1636 | /* SIMR3.IICSTIFãã©ã°ãâ0âã«è¨å®ãã*/
|
---|
| 1637 | sil_wrb_mem(SCI_SIMR3(obj->base_address),
|
---|
| 1638 | sil_reb_mem(SCI_SIMR3(obj->base_address)) & ~IICSTIF);
|
---|
| 1639 | /* SIMR3.IICSCLS[1:0], IICSDAS[1:0]ããããâ11bâã«è¨å® */
|
---|
| 1640 | sil_wrb_mem(SCI_SIMR3(obj->base_address),
|
---|
| 1641 | sil_reb_mem(SCI_SIMR3(obj->base_address)) | ((3 << 4) | (3 << 6)));
|
---|
| 1642 | }
|
---|
| 1643 |
|
---|
| 1644 | return length;
|
---|
| 1645 | }
|
---|
| 1646 |
|
---|
| 1647 | int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
|
---|
| 1648 | {
|
---|
| 1649 | if (obj->base_address == NULL)
|
---|
| 1650 | return 0;
|
---|
| 1651 |
|
---|
| 1652 | /* åä¿¡å²ãè¾¼ã¿è¦æ±ãç¦æ¢ */
|
---|
| 1653 | sil_wrb_mem(SCI_SCR(obj->base_address),
|
---|
| 1654 | (sil_reb_mem(SCI_SCR(obj->base_address)) & ~(RIE)) | TEIE | TIE);
|
---|
| 1655 |
|
---|
| 1656 | /* éå§æ¡ä»¶ã®çæ */
|
---|
| 1657 | i2c_start(obj);
|
---|
| 1658 |
|
---|
| 1659 | /* STI(TEI)å²ãè¾¼ã¿çºçç¢ºèª */
|
---|
| 1660 | while (!probe_int(obj->tei_intno))
|
---|
| 1661 | dly_tsk(2);
|
---|
| 1662 | clear_int(obj->tei_intno);
|
---|
| 1663 |
|
---|
| 1664 | /* SIMR3.IICSTIFãã©ã°ãâ0âã«è¨å®ãã */
|
---|
| 1665 | sil_wrb_mem(SCI_SIMR3(obj->base_address),
|
---|
| 1666 | sil_reb_mem(SCI_SIMR3(obj->base_address)) & ~IICSTIF);
|
---|
| 1667 | /* SIMR3.IICSCLS[1:0], IICSDAS[1:0]ããããâ00bâã«è¨å® */
|
---|
| 1668 | sil_wrb_mem(SCI_SIMR3(obj->base_address),
|
---|
| 1669 | sil_reb_mem(SCI_SIMR3(obj->base_address)) & ~((3 << 4) | (3 << 6)));
|
---|
| 1670 |
|
---|
| 1671 | /* TDRã¬ã¸ã¹ã¿ã«ã¹ã¬ã¼ãã¢ãã¬ã¹ãR/Wããããã©ã¤ã */
|
---|
| 1672 | sil_wrb_mem(SCI_TDR(obj->base_address), address);
|
---|
| 1673 |
|
---|
| 1674 | /* TXIå²ãè¾¼ã¿çºçç¢ºèª */
|
---|
| 1675 | while (!probe_int(obj->txi_intno))
|
---|
| 1676 | dly_tsk(10);
|
---|
| 1677 | clear_int(obj->txi_intno);
|
---|
| 1678 |
|
---|
| 1679 | /* ã¹ã¬ã¼ãããã¤ã¹ããã®ACKãç¢ºèª */
|
---|
| 1680 | if ((sil_reb_mem(SCI_SISR(obj->base_address)) & IICACKR) == 0) {
|
---|
| 1681 |
|
---|
| 1682 | for (int i = 0; i < length; i++) {
|
---|
| 1683 | /* TDRã¬ã¸ã¹ã¿ã«ã¹ã¬ã¼ãã¢ãã¬ã¹ãR/Wããããã©ã¤ã */
|
---|
| 1684 | sil_wrb_mem(SCI_TDR(obj->base_address), *data);
|
---|
| 1685 | data++;
|
---|
| 1686 |
|
---|
| 1687 | /* TXIå²ãè¾¼ã¿çºçç¢ºèª */
|
---|
| 1688 | while (!probe_int(obj->txi_intno))
|
---|
| 1689 | dly_tsk(10);
|
---|
| 1690 | clear_int(obj->txi_intno);
|
---|
| 1691 | }
|
---|
| 1692 | }
|
---|
| 1693 |
|
---|
| 1694 | if (stop) {
|
---|
| 1695 | /* åæ¢æ¡ä»¶ã®çæ */
|
---|
| 1696 | i2c_stop(obj);
|
---|
| 1697 |
|
---|
| 1698 | /* STI(TEI)å²ãè¾¼ã¿çºçç¢ºèª */
|
---|
| 1699 | while (!probe_int(obj->tei_intno))
|
---|
| 1700 | dly_tsk(2);
|
---|
| 1701 | clear_int(obj->tei_intno);
|
---|
| 1702 |
|
---|
| 1703 | /* SIMR3.IICSTIFãã©ã°ãâ0âã«è¨å®ãã*/
|
---|
| 1704 | sil_wrb_mem(SCI_SIMR3(obj->base_address),
|
---|
| 1705 | sil_reb_mem(SCI_SIMR3(obj->base_address)) & ~IICSTIF);
|
---|
| 1706 | /* SIMR3.IICSCLS[1:0], IICSDAS[1:0]ããããâ11bâã«è¨å® */
|
---|
| 1707 | sil_wrb_mem(SCI_SIMR3(obj->base_address),
|
---|
| 1708 | sil_reb_mem(SCI_SIMR3(obj->base_address)) | ((3 << 4) | (3 << 6)));
|
---|
| 1709 | }
|
---|
| 1710 |
|
---|
| 1711 | return length;
|
---|
| 1712 | }
|
---|
| 1713 |
|
---|
| 1714 | int i2c_byte_read(i2c_t *obj, int last)
|
---|
| 1715 | {
|
---|
| 1716 | if (obj->base_address == NULL)
|
---|
| 1717 | return 0;
|
---|
| 1718 |
|
---|
| 1719 | return 0;
|
---|
| 1720 | }
|
---|
| 1721 |
|
---|
| 1722 | int i2c_byte_write(i2c_t *obj, int data)
|
---|
| 1723 | {
|
---|
| 1724 | if (obj->base_address == NULL)
|
---|
| 1725 | return 0;
|
---|
| 1726 |
|
---|
| 1727 | return 0;
|
---|
| 1728 | }
|
---|
| 1729 |
|
---|
| 1730 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
|
---|
| 1731 | {
|
---|
| 1732 | if ((mosi == D11) && (miso == D12) && (sclk == D13) && ((ssel == D10) || (ssel == NC))) {
|
---|
| 1733 | obj->base_address = (void *)SCI8_BASE;
|
---|
| 1734 | obj->txi_intno = INT_SCI8_TXI;
|
---|
| 1735 | obj->rxi_intno = INT_SCI8_RXI;
|
---|
| 1736 | obj->tei_intno = INT_SCI8_TEI;
|
---|
| 1737 | }
|
---|
| 1738 | else if ((mosi == D3) && (miso == D6) && (sclk == D4) && (ssel == NC)) {
|
---|
| 1739 | obj->base_address = (void *)SCI3_BASE;
|
---|
| 1740 | obj->txi_intno = INT_SCI3_TXI;
|
---|
| 1741 | obj->rxi_intno = INT_SCI3_RXI;
|
---|
| 1742 | obj->tei_intno = INT_SCI3_TEI;
|
---|
| 1743 | }
|
---|
| 1744 | else {
|
---|
| 1745 | obj->base_address = NULL;
|
---|
| 1746 | return;
|
---|
| 1747 | }
|
---|
| 1748 |
|
---|
| 1749 | /* SCIæå¹ */
|
---|
| 1750 | sci_enable(obj->base_address, (ssel != NC) ? sciSPIS : sciSPIM);
|
---|
| 1751 |
|
---|
| 1752 | /* SIMR1.IICMããããâ0âã«è¨å® */
|
---|
| 1753 | sil_wrb_mem(SCI_SIMR1(obj->base_address),
|
---|
| 1754 | sil_reb_mem(SCI_SIMR1(obj->base_address)) & ~IICM);
|
---|
| 1755 |
|
---|
| 1756 | if (ssel == NC) {
|
---|
| 1757 | /* SPMR.SSE, CTSE, MSS, MFF, CKPH, CKPOLããããâ0âã«è¨å® */
|
---|
| 1758 | sil_wrb_mem(SCI_SPMR(obj->base_address), 0);
|
---|
| 1759 | }
|
---|
| 1760 | else {
|
---|
| 1761 | /* SPMR, CTSE, MSS, MFF, CKPH, CKPOLããããâ0âã«è¨å® */
|
---|
| 1762 | /* SPMR.SSEããããâ1âã«è¨å® */
|
---|
| 1763 | sil_wrb_mem(SCI_SPMR(obj->base_address), SSE);
|
---|
| 1764 | }
|
---|
| 1765 |
|
---|
| 1766 | /* SCMRã¬ã¸ã¹ã¿ã¯SDIRããããâ0âãSINVããããâ0âãSMIFããããâ0âã«è¨å® */
|
---|
| 1767 | sil_wrb_mem(SCI_SCMR(obj->base_address),
|
---|
| 1768 | (sil_reb_mem(SCI_SCMR(obj->base_address)) & ~(SMIF | SDIR)) | SINV);
|
---|
| 1769 |
|
---|
| 1770 | /* SMRã«éä¿¡ï¼ åä¿¡ãã©ã¼ããããã¯ããã¯åæå¼ã¢ã¼ãã§åä½ã§è¨å® */
|
---|
| 1771 | sil_wrb_mem(SCI_SMR(obj->base_address), CM);
|
---|
| 1772 |
|
---|
| 1773 | sci_set_frequency(obj->base_address, 1000000);
|
---|
| 1774 |
|
---|
| 1775 | /* éåä¿¡è¨±å¯ */
|
---|
| 1776 | sil_wrb_mem(SCI_SCR(obj->base_address),
|
---|
| 1777 | (sil_reb_mem(SCI_SCR(obj->base_address)) | RE | TE));
|
---|
| 1778 | }
|
---|
| 1779 |
|
---|
| 1780 | void spi_free(spi_t *obj)
|
---|
| 1781 | {
|
---|
| 1782 | /* SCIç¡å¹ */
|
---|
| 1783 | sci_disable(obj->base_address);
|
---|
| 1784 |
|
---|
| 1785 | obj->base_address = NULL;
|
---|
| 1786 | }
|
---|
| 1787 |
|
---|
| 1788 | void spi_format(spi_t *obj, int bits, int mode, int slave)
|
---|
| 1789 | {
|
---|
| 1790 | int polarity = (mode & 0x2) ? 1 : 0;
|
---|
| 1791 | int phase = (mode & 0x1) ? 1 : 0;
|
---|
| 1792 | uint8_t spmr;
|
---|
| 1793 |
|
---|
| 1794 | if ((bits != 8) || (mode < 0) || (mode > 3)) {
|
---|
| 1795 | return;
|
---|
| 1796 | }
|
---|
| 1797 |
|
---|
| 1798 | /* éåä¿¡ç¦æ¢, SCKn端åã¯å
|
---|
| 1799 | ¥åºåãã¼ãã¨ãã¦ä½¿ç¨ */
|
---|
| 1800 | sil_wrb_mem(SCI_SCR(obj->base_address), 0x00U);
|
---|
| 1801 |
|
---|
| 1802 | spmr = sil_reb_mem(SCI_SPMR(obj->base_address));
|
---|
| 1803 |
|
---|
| 1804 | /* ã¯ããã¯æ¥µæ§å転ãã/ãªã */
|
---|
| 1805 | if (polarity)
|
---|
| 1806 | spmr |= CKPOL;
|
---|
| 1807 | else
|
---|
| 1808 | spmr &= ~CKPOL;
|
---|
| 1809 |
|
---|
| 1810 | /* ã¯ããã¯ä½ç¸å転ãã/ãªã */
|
---|
| 1811 | if (phase)
|
---|
| 1812 | spmr |= CKPH;
|
---|
| 1813 | else
|
---|
| 1814 | spmr &= ~CKPH;
|
---|
| 1815 |
|
---|
| 1816 | if (slave) {
|
---|
| 1817 | /* SCKn端åã¯ã¯ããã¯å
|
---|
| 1818 | ¥åã¨ãã¦ä½¿ç¨ */
|
---|
| 1819 | sil_wrb_mem(SCI_SCR(obj->base_address),
|
---|
| 1820 | (sil_reb_mem(SCI_SCR(obj->base_address)) & ~CKE) | 2);
|
---|
| 1821 |
|
---|
| 1822 | /* SPMR.MSSããããâ1âã«è¨å® */
|
---|
| 1823 | sil_wrb_mem(SCI_SPMR(obj->base_address), spmr | MSS);
|
---|
| 1824 | }
|
---|
| 1825 | else {
|
---|
| 1826 | /* SCKn端åã¯ã¯ããã¯åºåã¨ãã¦ä½¿ç¨ */
|
---|
| 1827 | sil_wrb_mem(SCI_SCR(obj->base_address),
|
---|
| 1828 | sil_reb_mem(SCI_SCR(obj->base_address)) & ~CKE);
|
---|
| 1829 |
|
---|
| 1830 | /* SPMR.MSSããããâ0âã«è¨å® */
|
---|
| 1831 | sil_wrb_mem(SCI_SPMR(obj->base_address), spmr & ~MSS);
|
---|
| 1832 | }
|
---|
| 1833 |
|
---|
| 1834 | /* éåä¿¡è¨±å¯ */
|
---|
| 1835 | sil_wrb_mem(SCI_SCR(obj->base_address),
|
---|
| 1836 | (sil_reb_mem(SCI_SCR(obj->base_address)) | RE | TE));
|
---|
| 1837 | }
|
---|
| 1838 |
|
---|
| 1839 | void spi_frequency(spi_t *obj, int hz)
|
---|
| 1840 | {
|
---|
| 1841 | uint8_t scr = sil_reb_mem(SCI_SCR(obj->base_address));
|
---|
| 1842 |
|
---|
| 1843 | /* éåä¿¡ç¦æ¢, SCKn端åã¯å
|
---|
| 1844 | ¥åºåãã¼ãã¨ãã¦ä½¿ç¨ */
|
---|
| 1845 | sil_wrb_mem(SCI_SCR(obj->base_address), 0x00U);
|
---|
| 1846 |
|
---|
| 1847 | sci_set_frequency(obj->base_address, hz);
|
---|
| 1848 |
|
---|
| 1849 | /* éåä¿¡è¨±å¯ */
|
---|
| 1850 | sil_wrb_mem(SCI_SCR(obj->base_address), scr);
|
---|
| 1851 | }
|
---|
| 1852 |
|
---|
| 1853 | int spi_master_write(spi_t *obj, int value)
|
---|
| 1854 | {
|
---|
| 1855 | /* TXIå²ãè¾¼ã¿çºçç¢ºèª */
|
---|
| 1856 | while (!probe_int(obj->txi_intno))
|
---|
| 1857 | ;
|
---|
| 1858 |
|
---|
| 1859 | /* éä¿¡ãã¼ã¿ãã©ã¤ã */
|
---|
| 1860 | sil_wrb_mem(SCI_TDR(obj->base_address), (char)value);
|
---|
| 1861 |
|
---|
| 1862 | do {
|
---|
| 1863 | uint8_t ssr = sil_reb_mem(SCI_SSR(obj->base_address));
|
---|
| 1864 | if ((ssr & ORER) != 0) {
|
---|
| 1865 | ssr &= ~ORER;
|
---|
| 1866 | sil_wrb_mem(SCI_SSR(obj->base_address), ssr);
|
---|
| 1867 | return -1;
|
---|
| 1868 | }
|
---|
| 1869 | }
|
---|
| 1870 | /* RXIå²ãè¾¼ã¿çºçç¢ºèª */
|
---|
| 1871 | while (!probe_int(obj->rxi_intno));
|
---|
| 1872 |
|
---|
| 1873 | /* åä¿¡ãã¼ã¿ããªã¼ã */
|
---|
| 1874 | return sil_reb_mem(SCI_RDR(obj->base_address));
|
---|
| 1875 | }
|
---|
| 1876 |
|
---|
| 1877 | int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
|
---|
| 1878 | char *rx_buffer, int rx_length, char write_fill)
|
---|
| 1879 | {
|
---|
| 1880 | int total = (tx_length > rx_length) ? tx_length : rx_length;
|
---|
| 1881 |
|
---|
| 1882 | for (int i = 0; i < total; i++) {
|
---|
| 1883 | char out = (i < tx_length) ? tx_buffer[i] : write_fill;
|
---|
| 1884 | char in = spi_master_write(obj, out);
|
---|
| 1885 | if (i < rx_length) {
|
---|
| 1886 | rx_buffer[i] = in;
|
---|
| 1887 | }
|
---|
| 1888 | }
|
---|
| 1889 |
|
---|
| 1890 | return total;
|
---|
| 1891 | }
|
---|
| 1892 |
|
---|
| 1893 | uint8_t DecToBcd(uint8_t value)
|
---|
| 1894 | {
|
---|
| 1895 | return ((value / 10) << 4) | (value % 10);
|
---|
| 1896 | }
|
---|
| 1897 |
|
---|
| 1898 | uint8_t BcdToDec(uint8_t value)
|
---|
| 1899 | {
|
---|
| 1900 | return (10 * (value >> 4)) | (value & 0x0F);
|
---|
| 1901 | }
|
---|
| 1902 |
|
---|
| 1903 | void rtc_init(void)
|
---|
| 1904 | {
|
---|
| 1905 | }
|
---|
| 1906 |
|
---|
| 1907 | void rtc_free(void)
|
---|
| 1908 | {
|
---|
| 1909 | }
|
---|
| 1910 |
|
---|
| 1911 | int rtc_isenabled(void)
|
---|
| 1912 | {
|
---|
| 1913 | return 1;
|
---|
| 1914 | }
|
---|
| 1915 |
|
---|
| 1916 | long long __tm_to_secs(const struct tm *tm);
|
---|
| 1917 | int __secs_to_tm(long long t, struct tm *tm);
|
---|
| 1918 |
|
---|
| 1919 | time_t rtc_read(void)
|
---|
| 1920 | {
|
---|
| 1921 | struct tm tm = { 0 };
|
---|
| 1922 | tm.tm_year = 2000 - 1900 + BcdToDec(sil_reb_mem((uint8_t *)RTC_RYRCNT_ADDR));
|
---|
| 1923 | tm.tm_mon = BcdToDec(sil_reb_mem((uint8_t *)RTC_RMONCNT_ADDR)) - 1;
|
---|
| 1924 | tm.tm_mday = BcdToDec(sil_reb_mem((uint8_t *)RTC_RDAYCNT_ADDR));
|
---|
| 1925 | tm.tm_hour = BcdToDec(sil_reb_mem((uint8_t *)RTC_RHRCNT_ADDR));
|
---|
| 1926 | tm.tm_min = BcdToDec(sil_reb_mem((uint8_t *)RTC_RMINCNT_ADDR));
|
---|
| 1927 | tm.tm_sec = BcdToDec(sil_reb_mem((uint8_t *)RTC_RSECCNT_ADDR));
|
---|
| 1928 | return __tm_to_secs(&tm);
|
---|
| 1929 | }
|
---|
| 1930 |
|
---|
| 1931 | void rtc_write(time_t t)
|
---|
| 1932 | {
|
---|
| 1933 | struct tm tm;
|
---|
| 1934 |
|
---|
| 1935 | __secs_to_tm(t, &tm);
|
---|
| 1936 | sil_wrb_mem((uint8_t *)RTC_RYRCNT_ADDR, DecToBcd(tm.tm_year + 1900 - 2000));
|
---|
| 1937 | sil_wrb_mem((uint8_t *)RTC_RMONCNT_ADDR, DecToBcd(tm.tm_mon + 1));
|
---|
| 1938 | sil_wrb_mem((uint8_t *)RTC_RDAYCNT_ADDR, DecToBcd(tm.tm_mday));
|
---|
| 1939 | sil_wrb_mem((uint8_t *)RTC_RHRCNT_ADDR, DecToBcd(tm.tm_hour));
|
---|
| 1940 | sil_wrb_mem((uint8_t *)RTC_RMINCNT_ADDR, DecToBcd(tm.tm_min));
|
---|
| 1941 | sil_wrb_mem((uint8_t *)RTC_RSECCNT_ADDR, DecToBcd(tm.tm_sec));
|
---|
| 1942 | }
|
---|
| 1943 |
|
---|
| 1944 | void sci_rxi_handler(uint32_t no)
|
---|
| 1945 | {
|
---|
| 1946 | struct uart_irq_info_t *info = &sci_irq_info[no];
|
---|
| 1947 | if (info->handler == NULL)
|
---|
| 1948 | return;
|
---|
| 1949 |
|
---|
| 1950 | info->handler(info->id, RxIrq);
|
---|
| 1951 | }
|
---|
| 1952 |
|
---|
| 1953 | void sci_txi_handler(uint32_t no)
|
---|
| 1954 | {
|
---|
| 1955 | /* struct uart_irq_info_t *info = &sci_irq_info[no];
|
---|
| 1956 | if (info->handler == NULL)
|
---|
| 1957 | return;
|
---|
| 1958 |
|
---|
| 1959 | info->handler(info->id, TxIrq);*/
|
---|
| 1960 | }
|
---|
| 1961 |
|
---|
| 1962 | void sci_tei_handler(int no)
|
---|
| 1963 | {
|
---|
| 1964 | struct uart_irq_info_t *info = &sci_irq_info[no];
|
---|
| 1965 | if (info->handler == NULL)
|
---|
| 1966 | return;
|
---|
| 1967 |
|
---|
| 1968 | info->handler(info->id, TxIrq);
|
---|
| 1969 | }
|
---|
| 1970 |
|
---|
| 1971 | void sci0_rxi_handler(void)
|
---|
| 1972 | {
|
---|
| 1973 | sci_rxi_handler(0);
|
---|
| 1974 | }
|
---|
| 1975 |
|
---|
| 1976 | void sci0_txi_handler(void)
|
---|
| 1977 | {
|
---|
| 1978 | sci_txi_handler(0);
|
---|
| 1979 | }
|
---|
| 1980 |
|
---|
| 1981 | void sci0_tei_handler(void)
|
---|
| 1982 | {
|
---|
| 1983 | sci_tei_handler(0);
|
---|
| 1984 | }
|
---|
| 1985 |
|
---|
| 1986 | void sci1_rxi_handler(void)
|
---|
| 1987 | {
|
---|
| 1988 | sci_rxi_handler(1);
|
---|
| 1989 | }
|
---|
| 1990 |
|
---|
| 1991 | void sci1_txi_handler(void)
|
---|
| 1992 | {
|
---|
| 1993 | sci_txi_handler(1);
|
---|
| 1994 | }
|
---|
| 1995 |
|
---|
| 1996 | void sci1_tei_handler(void)
|
---|
| 1997 | {
|
---|
| 1998 | sci_tei_handler(1);
|
---|
| 1999 | }
|
---|
| 2000 |
|
---|
| 2001 | void sci2_rxi_handler(void)
|
---|
| 2002 | {
|
---|
| 2003 | sci_rxi_handler(2);
|
---|
| 2004 | }
|
---|
| 2005 |
|
---|
| 2006 | void sci2_txi_handler(void)
|
---|
| 2007 | {
|
---|
| 2008 | sci_txi_handler(2);
|
---|
| 2009 | }
|
---|
| 2010 |
|
---|
| 2011 | void sci2_tei_handler(void)
|
---|
| 2012 | {
|
---|
| 2013 | sci_tei_handler(2);
|
---|
| 2014 | }
|
---|
| 2015 |
|
---|
| 2016 | void sci3_rxi_handler(void)
|
---|
| 2017 | {
|
---|
| 2018 | sci_rxi_handler(3);
|
---|
| 2019 | }
|
---|
| 2020 |
|
---|
| 2021 | void sci3_txi_handler(void)
|
---|
| 2022 | {
|
---|
| 2023 | sci_txi_handler(3);
|
---|
| 2024 | }
|
---|
| 2025 |
|
---|
| 2026 | void sci3_tei_handler(void)
|
---|
| 2027 | {
|
---|
| 2028 | sci_tei_handler(3);
|
---|
| 2029 | }
|
---|
| 2030 |
|
---|
| 2031 | void sci4_rxi_handler(void)
|
---|
| 2032 | {
|
---|
| 2033 | sci_rxi_handler(4);
|
---|
| 2034 | }
|
---|
| 2035 |
|
---|
| 2036 | void sci4_txi_handler(void)
|
---|
| 2037 | {
|
---|
| 2038 | sci_txi_handler(4);
|
---|
| 2039 | }
|
---|
| 2040 |
|
---|
| 2041 | void sci4_tei_handler(void)
|
---|
| 2042 | {
|
---|
| 2043 | sci_tei_handler(4);
|
---|
| 2044 | }
|
---|
| 2045 |
|
---|
| 2046 | void sci5_rxi_handler(void)
|
---|
| 2047 | {
|
---|
| 2048 | sci_rxi_handler(5);
|
---|
| 2049 | }
|
---|
| 2050 |
|
---|
| 2051 | void sci5_txi_handler(void)
|
---|
| 2052 | {
|
---|
| 2053 | sci_txi_handler(5);
|
---|
| 2054 | }
|
---|
| 2055 |
|
---|
| 2056 | void sci5_tei_handler(void)
|
---|
| 2057 | {
|
---|
| 2058 | sci_tei_handler(5);
|
---|
| 2059 | }
|
---|
| 2060 |
|
---|
| 2061 | void sci6_rxi_handler(void)
|
---|
| 2062 | {
|
---|
| 2063 | sci_rxi_handler(6);
|
---|
| 2064 | }
|
---|
| 2065 |
|
---|
| 2066 | void sci6_txi_handler(void)
|
---|
| 2067 | {
|
---|
| 2068 | sci_txi_handler(6);
|
---|
| 2069 | }
|
---|
| 2070 |
|
---|
| 2071 | void sci6_tei_handler(void)
|
---|
| 2072 | {
|
---|
| 2073 | sci_tei_handler(6);
|
---|
| 2074 | }
|
---|