1 | /*
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2 | * TOPPERS ATK2
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3 | * Toyohashi Open Platform for Embedded Real-Time Systems
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4 | * Automotive Kernel Version 2
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5 | *
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6 | * Copyright (C) 2012-2015 by Center for Embedded Computing Systems
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7 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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8 | * Copyright (C) 2012-2014 by FUJISOFT INCORPORATED, JAPAN
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9 | * Copyright (C) 2012-2013 by Spansion LLC, USA
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10 | * Copyright (C) 2012-2013 by NEC Communication Systems, Ltd., JAPAN
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11 | * Copyright (C) 2012-2014 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
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12 | * Copyright (C) 2012-2014 by Renesas Electronics Corporation, JAPAN
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13 | * Copyright (C) 2012-2014 by Sunny Giken Inc., JAPAN
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14 | * Copyright (C) 2012-2014 by TOSHIBA CORPORATION, JAPAN
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15 | * Copyright (C) 2012-2014 by Witz Corporation, JAPAN
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16 | *
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17 | * ä¸è¨èä½æ¨©è
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18 | ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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19 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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20 | * å¤ã»åé
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21 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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22 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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23 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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24 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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25 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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26 | * ç¨ã§ããå½¢ã§åé
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27 | å¸ããå ´åã«ã¯ï¼åé
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28 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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29 | * è
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30 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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31 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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32 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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33 | * ç¨ã§ããªãå½¢ã§åé
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34 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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35 | * ã¨ï¼
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36 | * (a) åé
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37 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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38 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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39 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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40 | * (b) åé
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41 | å¸ã®å½¢æ
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42 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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43 | * å ±åãããã¨ï¼
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44 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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45 | * 害ãããï¼ä¸è¨èä½æ¨©è
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46 | ããã³TOPPERSããã¸ã§ã¯ããå
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47 | 責ãããã¨ï¼
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48 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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49 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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50 | ããã³TOPPERSããã¸ã§ã¯ãã
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51 | * å
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52 | 責ãããã¨ï¼
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53 | *
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54 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼AUTOSARï¼AUTomotive Open System ARchitectureï¼ä»
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55 | * æ§ã«åºã¥ãã¦ããï¼ä¸è¨ã®è¨±è«¾ã¯ï¼AUTOSARã®ç¥ç財ç£æ¨©ã許諾ãããã®ã§
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56 | * ã¯ãªãï¼AUTOSARã¯ï¼AUTOSARä»æ§ã«åºã¥ããã½ããã¦ã§ã¢ãåç¨ç®çã§å©
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57 | * ç¨ããè
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58 | ã«å¯¾ãã¦ï¼AUTOSARãã¼ããã¼ã«ãªããã¨ãæ±ãã¦ããï¼
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59 | *
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60 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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61 | ã
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62 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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63 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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64 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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65 | * ã®è²¬ä»»ãè² ããªãï¼
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66 | *
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67 | * $Id: target_config.c 42 2014-07-19 07:10:58Z ertl-honda $
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68 | */
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69 |
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70 | /*
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71 | * ã¿ã¼ã²ããä¾åã¢ã¸ã¥ã¼ã«ï¼RH850F1H_PBç¨ï¼
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72 | */
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73 |
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74 | #include "kernel_impl.h"
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75 | #include "v850_gcc/uart_rlin.h"
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76 | #include "v850_gcc/prc_sil.h"
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77 | #include "target_sysmod.h"
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78 | #ifdef ENABLE_RETURN_MAIN
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79 | #include "interrupt.h"
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80 | #endif /* ENABLE_RETURN_MAIN */
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81 | #ifdef TOPPERS_ENABLE_TRACE
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82 | #include "logtrace/trace_config.h"
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83 | #endif /* TOPPERS_ENABLE_TRACE */
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84 |
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85 | /*
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86 | * æååã®åºå
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87 | */
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88 | void
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89 | target_fput_str(const char8 *c)
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90 | {
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91 | while (*c != '\0') {
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92 | uart_putc(*c);
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93 | c++;
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94 | }
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95 | uart_putc('\n');
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96 | }
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97 |
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98 |
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99 | /*
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100 | * ãã¼ãã®åæè¨å®
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101 | */
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102 | void
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103 | target_port_initialize(void)
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104 | {
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105 | uint16 wk;
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106 |
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107 | #ifdef RLIN3x_USE_PORT0
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108 | /*
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109 | * PORT10(RLIN30)
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110 | */
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111 | /* PFC10 è¨å® */
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112 | wk = sil_reh_mem((void *) PFC(10));
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113 | wk &= ~RLIN30_P10_MASK;
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114 | wk |= (RLIN30_PFC10_INIT & RLIN30_P10_MASK);
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115 | sil_wrh_mem((void *) PFC(10), wk);
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116 |
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117 | /* PFCE10 è¨å® */
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118 | wk = sil_reh_mem((void *) PFCE(10));
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119 | wk &= ~RLIN30_P10_MASK;
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120 | wk |= (RLIN30_PFCE10_INIT & RLIN30_P10_MASK);
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121 | sil_wrh_mem((void *) PFCE(10), wk);
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122 |
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123 | /* PFCAE10 è¨å® */
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124 | wk = sil_reh_mem((void *) PFCAE(10));
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125 | wk &= ~RLIN30_P10_MASK;
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126 | wk |= (RLIN30_PFCAE10_INIT & RLIN30_P10_MASK);
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127 | sil_wrh_mem((void *) PFCAE(10), wk);
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128 |
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129 | /* PM1 è¨å® */
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130 | wk = sil_reh_mem((void *) PM(10));
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131 | wk &= ~RLIN30_P10_MASK;
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132 | wk |= (RLIN30_PM10_INIT & RLIN30_P10_MASK);
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133 | sil_wrh_mem((void *) PM(10), wk);
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134 |
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135 | /* PMC10 è¨å® */
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136 | wk = sil_reh_mem((void *) PMC(10));
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137 | wk &= ~RLIN30_P10_MASK;
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138 | wk |= (RLIN30_PMC10_INIT & RLIN30_P10_MASK);
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139 | sil_wrh_mem((void *) PMC(10), wk);
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140 |
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141 | /* PIBC10 è¨å® */
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142 | wk = sil_reh_mem((void *) PIBC(10));
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143 | wk &= ~RLIN30_P10_MASK;
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144 | wk |= (RLIN30_PIBC10_INIT & RLIN30_P10_MASK);
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145 | sil_wrh_mem((void *) PIBC(10), wk);
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146 |
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147 | #elif defined(RLIN3x_USE_PORT1)
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148 |
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149 | /*
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150 | * PORT0(RLIN31)
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151 | */
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152 | /* PFC0 è¨å® */
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153 | wk = sil_reh_mem((void *) PFC(0));
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154 | wk &= ~RLIN31_P0_MASK;
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155 | wk |= (RLIN31_PFC0_INIT & RLIN31_P0_MASK);
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156 | sil_wrh_mem((void *) PFC(0), wk);
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157 |
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158 | /* PFCE0 è¨å® */
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159 | wk = sil_reh_mem((void *) PFCE(0));
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160 | wk &= ~RLIN31_P0_MASK;
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161 | wk |= (RLIN31_PFCE0_INIT & RLIN31_P0_MASK);
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162 | sil_wrh_mem((void *) PFCE(0), wk);
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163 |
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164 | /* PFCAE0 è¨å® */
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165 | wk = sil_reh_mem((void *) PFCAE(0));
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166 | wk &= ~RLIN31_P0_MASK;
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167 | wk |= (RLIN31_PFCAE0_INIT & RLIN31_P0_MASK);
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168 | sil_wrh_mem((void *) PFCAE(0), wk);
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169 |
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170 | /* PM1 è¨å® */
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171 | wk = sil_reh_mem((void *) PM(0));
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172 | wk &= ~RLIN31_P0_MASK;
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173 | wk |= (RLIN31_PM0_INIT & RLIN31_P0_MASK);
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174 | sil_wrh_mem((void *) PM(0), wk);
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175 |
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176 | /* PMC0 è¨å® */
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177 | wk = sil_reh_mem((void *) PMC(0));
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178 | wk &= ~RLIN31_P0_MASK;
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179 | wk |= (RLIN31_PMC0_INIT & RLIN31_P0_MASK);
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180 | sil_wrh_mem((void *) PMC(0), wk);
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181 |
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182 | /* PIBC0 è¨å® */
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183 | wk = sil_reh_mem((void *) PIBC(0));
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184 | wk &= ~RLIN31_P0_MASK;
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185 | wk |= (RLIN31_PIBC0_INIT & RLIN31_P0_MASK);
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186 | sil_wrh_mem((void *) PIBC(0), wk);
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187 |
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188 | #else
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189 |
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190 | #error define RLIN3x_USE_PORT0 or RLIN3x_USE_PORT1
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191 |
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192 | #endif /* RLIN3x_USE_PORT0 */
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193 | }
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194 |
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195 | /*
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196 | * ã¯ããã¯é¢ä¿ã®åæå
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197 | */
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198 | void
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199 | target_clock_initialize(void)
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200 | {
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201 | uint32 errcnt = 0;
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202 |
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203 | /* Init Main Clock */
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204 | if (EnableMainOSC(MHz(MAINOSC_CLOCK_MHZ)) != UC_SUCCESS) {
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205 | errcnt++;
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206 | }
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207 |
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208 | /* Init PLL0 */
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209 | if (EnablePLL0() != UC_SUCCESS) {
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210 | errcnt++;
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211 | }
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212 |
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213 | /* Init PLL1 */
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214 | if (EnablePLL1() != UC_SUCCESS) {
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215 | errcnt++;
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216 | }
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217 |
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218 | /* Set RLIN Clock */
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219 | if (SetClockSelection(CKSC_ILINS_CTL, CKSC_ILINS_ACT,
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220 | PNO_CtrlProt1, 0x02, /* MainOSC */
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221 | CKSC_ILIND_CTL, CKSC_ILIND_ACT,
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222 | 0x01) != UC_SUCCESS) {
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223 | errcnt++;
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224 | }
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225 |
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226 | /* Set TAUJ Clock */
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227 | if (SetClockSelection(CKSC_ATAUJS_CTL, CKSC_ATAUJS_ACT,
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228 | PNO_CtrlProt0, 0x02, /* MainOSC */
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229 | CKSC_ATAUJD_CTL, CKSC_ATAUJD_ACT,
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230 | 0x02 /* MainOSC/2 */
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231 | ) != UC_SUCCESS) {
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232 | errcnt++;
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233 | }
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234 |
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235 | /*
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236 | * Set CPU Clock
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237 | * èµ·åæã®å¾
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238 | ã¡åããã«ä½¿ç¨ããããæå¾ã«è¨å®ãããã¨ï¼
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239 | */
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240 | if (SetClockSelection(CKSC_CPUCLKS_CTL, CKSC_CPUCLKS_ACT,
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241 | PNO_CtrlProt1, 0x03, /* 120MHz CPLLCLK */
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242 | CKSC_CPUCLKD_CTL, CKSC_CPUCLKD_ACT,
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243 | 0x01) != UC_SUCCESS) {
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244 | errcnt++;
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245 | }
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246 |
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247 | if (errcnt > 0) {
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248 | infinite_loop();
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249 | }
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250 | }
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251 |
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252 | extern void _reset(void);
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253 |
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254 | /*
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255 | * ã¿ã¼ã²ããä¾åã®ãã¼ãã¦ã§ã¢ã®åæå
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256 | * ã¹ã¿ã¼ã¢ããã«ã¼ãã³ããå¼ã³åºãããï¼
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257 | */
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258 | void
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259 | target_hardware_initialize(void)
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260 | {
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261 | #ifdef INIT_IBD_FOR_PE2
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262 | /* PE2ç¨ã®IBDã®è¨å® */
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263 | /* RLIN31 */
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264 | sil_wrw_mem((void*)0xFFFFB9E8, 0x00010002);
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265 | /* TAUJ1I0 */
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266 | sil_wrw_mem((void*)0xFFFFBAA0, 0x00010002);
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267 | #endif /* INIT_IBD_FOR_PE2 */
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268 |
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269 | #ifndef OMIT_CLOCK_INIT
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270 | /* ã¯ããã¯ã®åæè¨å® */
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271 | target_clock_initialize();
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272 | #else
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273 | /* ã¯ããã¯åæåå¾
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274 | ã¡ */
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275 | while(sil_rew_mem((void *)CKSC_CPUCLKS_CTL) != 0x03){}
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276 | #endif /* !OMIT_CLOCK_INIT */
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277 |
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278 | /* ãªã»ãããã¯ã¿ã®åæå */
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279 | __LDSR(2,1,(unsigned int)_reset);
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280 |
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281 | /* ãã¼ãã®åæè¨å® */
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282 | target_port_initialize();
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283 | }
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284 |
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285 | /*
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286 | * ã¿ã¼ã²ããä¾åã®åæå
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287 | */
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288 | void
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289 | target_initialize(void)
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290 | {
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291 | /*
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292 | * V850ä¾åã®åæå
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293 | */
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294 | prc_initialize();
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295 |
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296 |
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297 |
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298 | #ifdef TOPPERS_ENABLE_TRACE
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299 | /*
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300 | * ãã¬ã¼ã¹ãã°æ©è½ã®åæå
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301 | */
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302 | trace_initialize((uintptr) (TRACE_AUTOSTOP));
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303 | #endif /* TOPPERS_ENABLE_TRACE */
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304 | }
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305 |
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306 | /*
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307 | * ã¿ã¼ã²ããä¾åã®çµäºå¦ç
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308 | */
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309 | void
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310 | target_exit(void)
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311 | {
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312 | #ifdef TOPPERS_ENABLE_TRACE
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313 | /*
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314 | * ãã¬ã¼ã¹ãã°ã®ãã³ã
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315 | */
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316 | trace_dump(target_fput_log);
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317 | #endif /* TOPPERS_ENABLE_TRACE */
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318 |
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319 | #ifndef ENABLE_RETURN_MAIN
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320 | /*
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321 | * ã·ã£ãããã¦ã³å¦çã®åºå
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322 | */
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323 | target_fput_str("Kernel Exit...");
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324 | #else
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325 | target_fput_str("Kernel Shutdown...");
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326 | #endif /* ENABLE_RETURN_MAIN */
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327 |
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328 | /*
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329 | * RH850F1H_PBä¾åã®çµäºå¦ç
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330 | */
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331 | prc_terminate();
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332 |
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333 | #ifdef ENABLE_RETURN_MAIN
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334 | p_ctxosap = NULL;
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335 | kerflg = FALSE;
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336 | except_nest_cnt = 0U;
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337 | nested_lock_os_int_cnt = 0U;
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338 | sus_all_cnt = 0U;
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339 | sus_os_cnt = 0U;
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340 |
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341 | /* ã¹ã¿ãã¯ãã¤ã³ã¿ã®åæåã¨main()ã®å¼ã³åºã */
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342 | return_main();
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343 | #endif /* ENABLE_RETURN_MAIN */
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344 |
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345 | infinite_loop();
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346 | }
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347 |
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348 | /*
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349 | * ã¿ã¼ã²ããä¾åã®æååºå
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350 | */
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351 | void
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352 | target_fput_log(char8 c)
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353 | {
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354 | if (c == '\n') {
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355 | uart_putc('\r');
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356 | }
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357 | uart_putc(c);
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358 | }
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