[172] | 1 | /*
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| 2 | * TOPPERS ATK2
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems
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| 4 | * Automotive Kernel Version 2
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| 5 | *
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| 6 | * Copyright (C) 2012-2014 by Center for Embedded Computing Systems
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| 7 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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| 8 | * Copyright (C) 2012-2014 by FUJI SOFT INCORPORATED, JAPAN
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| 9 | * Copyright (C) 2012-2013 by Spansion LLC, USA
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| 10 | * Copyright (C) 2012-2013 by NEC Communication Systems, Ltd., JAPAN
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| 11 | * Copyright (C) 2012-2014 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
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| 12 | * Copyright (C) 2012-2014 by Renesas Electronics Corporation, JAPAN
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| 13 | * Copyright (C) 2012-2014 by Sunny Giken Inc., JAPAN
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| 14 | * Copyright (C) 2012-2014 by TOSHIBA CORPORATION, JAPAN
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| 15 | * Copyright (C) 2012-2014 by Witz Corporation, JAPAN
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| 16 | *
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| 17 | * ä¸è¨èä½æ¨©è
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| 18 | ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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| 19 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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| 20 | * å¤ã»åé
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| 21 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 22 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 23 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 24 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 25 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 26 | * ç¨ã§ããå½¢ã§åé
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| 27 | å¸ããå ´åã«ã¯ï¼åé
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| 28 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 29 | * è
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| 30 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 31 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 32 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 33 | * ç¨ã§ããªãå½¢ã§åé
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| 34 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 35 | * ã¨ï¼
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| 36 | * (a) åé
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| 37 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 38 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 39 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 40 | * (b) åé
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| 41 | å¸ã®å½¢æ
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| 42 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 43 | * å ±åãããã¨ï¼
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| 44 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 45 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 46 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 47 | 責ãããã¨ï¼
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| 48 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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| 49 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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| 50 | ããã³TOPPERSããã¸ã§ã¯ãã
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| 51 | * å
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| 52 | 責ãããã¨ï¼
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| 53 | *
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| 54 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼AUTOSARï¼AUTomotive Open System ARchitectureï¼ä»
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| 55 | * æ§ã«åºã¥ãã¦ããï¼ä¸è¨ã®è¨±è«¾ã¯ï¼AUTOSARã®ç¥ç財ç£æ¨©ã許諾ãããã®ã§
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| 56 | * ã¯ãªãï¼AUTOSARã¯ï¼AUTOSARä»æ§ã«åºã¥ããã½ããã¦ã§ã¢ãåç¨ç®çã§å©
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| 57 | * ç¨ããè
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| 58 | ã«å¯¾ãã¦ï¼AUTOSARãã¼ããã¼ã«ãªããã¨ãæ±ãã¦ããï¼
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| 59 | *
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| 60 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 61 | ã
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| 62 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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| 63 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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| 64 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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| 65 | * ã®è²¬ä»»ãè² ããªãï¼
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| 66 | *
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| 67 | * $Id: v850e2_px4.h 117 2014-12-10 03:58:03Z t_ishikawa $
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| 68 | */
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| 69 |
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| 70 | /*
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| 71 | * V850E2/Px4ã®ãã¼ãã¦ã§ã¢è³æºã®å®ç¾©
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| 72 | */
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| 73 |
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| 74 | #ifndef TOPPERS_V850E2_PX4_H
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| 75 | #define TOPPERS_V850E2_PX4_H
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| 76 |
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| 77 | #define _V850E2M_
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| 78 |
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| 79 | #define VPNECR 0xffff5110
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| 80 | #define VPNADR 0xffff5114
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| 81 | #define VPNTID 0xffff5118
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| 82 | #define VPTTID 0xffff511A
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| 83 | #define VPTECR 0xffff5120
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| 84 | #define VPTADR 0xffff5124
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| 85 |
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| 86 | /*
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| 87 | * ãã¼ãã¬ã¸ã¹ã¿
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| 88 | */
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| 89 | #define PM0 0xffff8300
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| 90 | #define PMC0 0xffff8400
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| 91 | #define PFC0 0xffff8500
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| 92 | #define PFCE0 0xffff8600
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| 93 |
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| 94 | #define P4 0xffff8010
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| 95 | #define PM4 0xffff8310
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| 96 | #define PMC4 0xffff8410
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| 97 | #define PFC4 0xffff8510
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| 98 | #define PFCE4 0xffff8610
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| 99 |
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| 100 | #define FCLA0CTL0 0xFF414000
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| 101 | #define FCLA1CTL2 0xFF414028
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| 102 | #define FCLA1CTL3 0xFF41402c
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| 103 |
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| 104 | #define FCLA27CTL3 0xff41624c
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| 105 | #define FCLA27CTL6 0xff416258
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| 106 |
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| 107 | /*
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| 108 | * Interval Timer(TAUA0)
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| 109 | */
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| 110 | #define TAUA0_BASE0 UINT_C(0xFF808000) /* TAUA0 */
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| 111 | #define TAUA0_BASE1 UINT_C(0xFFFFC400) /* TAUA0 */
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| 112 |
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| 113 | #define TAUA0_IRQ UINT_C(54) /* TAUA0 */
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| 114 | #define TAUA1_IRQ UINT_C(55) /* TAUA1 */
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| 115 | #define TAUA2_IRQ UINT_C(56) /* TAUA2 */
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| 116 | #define TAUA3_IRQ UINT_C(57) /* TAUA3 */
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| 117 | #define TAUA4_IRQ UINT_C(58) /* TAUA4 */
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| 118 | #define TAUA5_IRQ UINT_C(59) /* TAUA5 */
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| 119 | #define TAUA6_IRQ UINT_C(60) /* TAUA6 */
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| 120 | #define TAUA7_IRQ UINT_C(61) /* TAUA7 */
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| 121 | #define TAUA8_IRQ UINT_C(62) /* TAUA8 */
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| 122 | #define TAUA9_IRQ UINT_C(63) /* TAUA9 */
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| 123 | #define TAUA10_IRQ UINT_C(64) /* TAUA10 */
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| 124 | #define TAUA11_IRQ UINT_C(65) /* TAUA11 */
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| 125 | #define TAUA12_IRQ UINT_C(66) /* TAUA12 */
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| 126 | #define TAUA13_IRQ UINT_C(67) /* TAUA13 */
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| 127 | #define TAUA14_IRQ UINT_C(68) /* TAUA14 */
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| 128 | #define TAUA15_IRQ UINT_C(69) /* TAUA15 */
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| 129 |
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| 130 | #define TAUA_CH0 0
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| 131 | #define TAUA_CH1 1
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| 132 | #define TAUA_CH2 2
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| 133 | #define TAUA_CH3 3
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| 134 | #define TAUA_CH4 4
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| 135 | #define TAUA_CH5 5
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| 136 | #define TAUA_CH6 6
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| 137 | #define TAUA_CH7 7
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| 138 | #define TAUA_CH8 8
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| 139 | #define TAUA_CH9 9
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| 140 | #define TAUA_CH10 10
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| 141 | #define TAUA_CH11 11
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| 142 | #define TAUA_CH12 12
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| 143 | #define TAUA_CH13 13
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| 144 | #define TAUA_CH14 14
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| 145 | #define TAUA_CH15 15
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| 146 |
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| 147 | /*
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| 148 | * TAUA0 Timer ãã¼ãã¦ã§ã¢å®ç¾©
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| 149 | */
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| 150 |
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| 151 | /*
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| 152 | * ã¬ã¸ã¹ã¿
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| 153 | */
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| 154 | /* TAUA0 ããªã¹ã±ã¼ã©ã»ã¬ã¸ã¹ã¿ */
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| 155 | #define TAUA0TPS (TAUA0_BASE0 + 0x240U) /* ããªã¹ã±ã¼ã©ã»ã¯ããã¯é¸æã¬ã¸ã¹ */
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| 156 | #define TAUA0BRS (TAUA0_BASE0 + 0x244U) /* ããªã¹ã±ã¼ã©ã»ãã¼ã»ã¬ã¼ãè¨å®ã¬ã¸ã¹ã¿ */
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| 157 |
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| 158 | /* TAUA0 å¶å¾¡ã¬ã¸ã¹ã¿ */
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| 159 | #define TAUA0CDR(CH) (TAUA0_BASE1 + (CH * 4U)) /* ãã¼ã¿ã»ã¬ã¸ã¹ã¿ */
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| 160 | #define TAUA0CNT(CH) (TAUA0_BASE1 + (0x80U + (CH * 4U))) /* ã«ã¦ã³ã¿ã»ã¬ã¸ã¹ã¿ */
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| 161 | #define TAUA0CMOR(CH) (TAUA0_BASE0 + (0x200U + (CH * 4U))) /* ã¢ã¼ãOS ã¬ã¸ã¹ã¿ */
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| 162 | #define TAUA0CMUR(CH) (TAUA0_BASE1 + (0xC0 + (CH * 4U))) /* ã¢ã¼ãã»ã¦ã¼ã¶ã»ã¬ã¸ã¹ã¿ */
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| 163 | #define TAUA0CSR(CH) (TAUA0_BASE1 + (0x140U + (CH * 4U))) /* ã¹ãã¼ã¿ã¹ã»ã¬ã¸ã¹ã¿ */
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| 164 | #define TATA0CSC(CH) (TAUA0_BASE1 + (0x180U + (CH * 4U))) /* ã¹ãã¼ã¿ã¹ã»ã¯ãªã¢ã»ããªã¬ã»ã¬ã¸ã¹ã¿ */
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| 165 | #define TAUA0TS (TAUA0_BASE1 + 0x1C4U) /* ã¹ã¿ã¼ãã»ããªã¬ã»ã¬ã¸ã¹ã¿ */
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| 166 | #define TAUA0TE (TAUA0_BASE1 + 0x1C0U) /* 許å¯ã¹ãã¼ã¿ã¹ã»ã¬ã¸ã¹ã¿ */
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| 167 | #define TAUA0TT (TAUA0_BASE1 + 0x1C8U) /* ã¹ãããã»ããªã¬ã»ã¬ã¸ã¹ã¿ */
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| 168 |
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| 169 | /* TAUA0 åºåã¬ã¸ã¹ã¿ */
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| 170 | #define TAUA0TOE (TAUA0_BASE1 + 0x5CU) /* åºå許å¯ã¬ã¸ã¹ã¿ */
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| 171 | #define TAUA0TO (TAUA0_BASE1 + 0x58U) /* åºåã¬ã¸ã¹ã¿ */
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| 172 | #define TAUA0TOM (TAUA0_BASE0 + 0x248U) /* åºåã¢ã¼ãã»ã¬ã¸ã¹ã¿ */
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| 173 | #define TAUA0TOC (TAUA0_BASE0 + 0x24CU) /* åºåã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ã»ã¬ã¸ã¹ã¿ */
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| 174 |
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| 175 | #define TAUA0TOL (TAUA0_BASE1 + 0x40U) /* åºåã¢ã¯ãã£ãã»ã¬ãã«ã»ã¬ã¸ã¹ã¿ */
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| 176 | #define TAUA0TDE (TAUA0_BASE0 + 0x250U) /* ãããã»ã¿ã¤ã åºå許å¯ã¬ã¸ã¹ã¿ */
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| 177 | #define TAUA0TDM (TAUA0_BASE0 + 0x254U) /* ãããã»ã¿ã¤ã åºåã¢ã¼ãã»ã¬ã¸ã¹ã¿ */
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| 178 | #define TAUA0TDL (TAUA0_BASE1 + 0x54U) /* ãããã»ã¿ã¤ã åºåã¬ãã«ã»ã¬ã¸ã¹ã¿ */
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| 179 |
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| 180 | #define TAUA0TRO (TAUA0_BASE1 + 0x4CU) /* ãªã¢ã«ã¿ã¤ã åºåã¬ã¸ã¹ã¿ */
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| 181 | #define TAUA0TRE (TAUA0_BASE0 + 0x258U) /* ãªã¢ã«ã¿ã¤ã åºå許å¯ã¬ã¸ã¹ã¿ */
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| 182 | #define TAUA0TRC (TAUA0_BASE0 + 0x25CU) /* ãªã¢ã«ã¿ã¤ã åºåå¶å¾¡ã¬ã¸ã¹ã¿ */
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| 183 | #define TAUA0TME (TAUA0_BASE1 + 0x50U) /* å¤èª¿åºå許å¯ã¬ã¸ã¹ã¿ */
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| 184 | /* TAUA0 ãªãã¼ãã»ãã¼ã¿ã»ã¬ã¸ã¹ã¿ */
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| 185 | #define TAUA0RDE (TAUA0_BASE0 + 0x260U) /* ãªãã¼ãã»ãã¼ã¿è¨±å¯ã¬ã¸ã¹ã¿ */
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| 186 | #define TAUA0RDM (TAUA0_BASE0 + 0x264U) /* ãªãã¼ãã»ãã¼ã¿ã»ã¢ã¼ãã»ã¬ã¸ã¹ã¿ */
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| 187 | #define TAUA0RDS (TAUA0_BASE0 + 0x268U) /* ãªãã¼ãã»ãã¼ã¿å¶å¾¡CH é¸æã»ãªãã¼ãã»ãã¼ã¿å¶å¾¡CH é¸æ */
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| 188 | #define TAUA0RDC (TAUA0_BASE0 + 0x26CU) /* ãªãã¼ãã»ãã¼ã¿å¶å¾¡ã¬ã¸ã¹ã¿ */
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| 189 | #define TAUA0RDT (TAUA0_BASE1 + 0x44U) /* ãªãã¼ãã»ãã¼ã¿ã»ããªã¬ã»ã¬ã¸ã¹ã¿ */
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| 190 | #define TAUA0RSF (TAUA0_BASE1 + 0x48U) /* ãªãã¼ãã»ã¹ãã¼ã¿ã¹ã»ã¬ã¸ã¹ã¿ */
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| 191 |
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| 192 | #define MCU_TAUA0_MASK_CK0 ((uint16) 0x000f)
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| 193 | #define MCU_TAUA0_CK0 ((uint16) 0x0000) /* 2^0 */
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| 194 | #define MCU_TAUA00_CMOR ((uint16) 0x0001)
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| 195 | #define MCU_TAUA00_CMUR ((uint8) 0x01)
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| 196 | #define MCU_TAUA00_DI ((uint16) 0x0080)
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| 197 | #define MCU_TAUA00_EI ((uint16) 0x0000)
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| 198 | #define MCU_TAUA00_MASK_ENB ((uint16) 0x0001)
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| 199 | #define MCU_TIMER_STOP ((uint8) 0x0)
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| 200 | #define MCU_TIMER_START ((uint8) 0x1)
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| 201 |
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| 202 | #define ICTAUA0_BASE 0xffff606c /* ãã£ã³ãã«ï¼å²ã込㿠*/
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| 203 | #define ICTAUA0I(CH) (ICTAUA0_BASE + (CH * 0x02))
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| 204 |
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| 205 | /*
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| 206 | * TAUA0 ãã¹ã¯å®ç¾©
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| 207 | */
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| 208 | #define TAUA0_MASK_BIT 0x0xfffe /* bit0 = TAUA0 */
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| 209 |
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| 210 | /*
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| 211 | * UARTE
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| 212 | */
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| 213 | #define URTE0_BASE 0xFF5C0000
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| 214 | #define URTE1_BASE 0xFF5D0000
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| 215 | #define URTE2_BASE0 0xFF5E0000
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| 216 | #define URTE2_BASE1 0xFFFFEC00
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| 217 |
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| 218 | #define URTEnCTL0 (URTE2_BASE1 + 0x00U)
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| 219 | #define URTEnCTL1 (URTE2_BASE0 + 0x40U)
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| 220 | #define URTEnCTL2 (URTE2_BASE0 + 0x44U)
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| 221 | #define URTEnTRG (URTE2_BASE1 + 0x0cU)
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| 222 | #define URTEnSTR0 (URTE2_BASE1 + 0x10U)
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| 223 | #define URTEnSTR1 (URTE2_BASE1 + 0x14U)
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| 224 | #define URTEnSTC (URTE2_BASE1 + 0x18U)
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| 225 | #define URTEnRX (URTE2_BASE1 + 0x1cU)
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| 226 | #define URTEnTX (URTE2_BASE1 + 0x2cU)
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| 227 |
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| 228 | #define URTE2_INTNO UINT_C(197)
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| 229 |
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| 230 | #define INTNO_URTE2_IS 114
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| 231 | #define INTNO_URTE2_IR 115
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| 232 | #define INTNO_URTE2_IT 116
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| 233 |
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| 234 | /*
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| 235 | * INT
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| 236 | */
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| 237 | #define EIC_BASE UINT_C(0xffff6000)
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| 238 | #define EIC_ADDRESS(intno) (EIC_BASE + (intno * 2))
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| 239 | #define PMR UINT_C(0xFFFF6448)
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| 240 | #define ISPR_H UINT_C(0xFFFF6440)
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| 241 | #define ISPC_H UINT_C(0xffff6450)
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| 242 |
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| 243 | #define TMIN_INTNO UINT_C(0)
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| 244 | #define TMAX_INTNO UINT_C(255)
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| 245 | #define TNUM_INT UINT_C(256)
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| 246 |
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| 247 | #include "v850.h"
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| 248 |
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| 249 | #endif /* TOPPERS_V850E2_PX4_H */
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