[172] | 1 | /*
|
---|
| 2 | * TOPPERS ATK2
|
---|
| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems
|
---|
| 4 | * Automotive Kernel Version 2
|
---|
| 5 | *
|
---|
| 6 | * Copyright (C) 2012-2014 by Center for Embedded Computing Systems
|
---|
| 7 | * Graduate School of Information Science, Nagoya Univ., JAPAN
|
---|
| 8 | * Copyright (C) 2012-2014 by FUJI SOFT INCORPORATED, JAPAN
|
---|
| 9 | * Copyright (C) 2012-2013 by Spansion LLC, USA
|
---|
| 10 | * Copyright (C) 2012-2013 by NEC Communication Systems, Ltd., JAPAN
|
---|
| 11 | * Copyright (C) 2012-2014 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
|
---|
| 12 | * Copyright (C) 2012-2014 by Renesas Electronics Corporation, JAPAN
|
---|
| 13 | * Copyright (C) 2012-2014 by Sunny Giken Inc., JAPAN
|
---|
| 14 | * Copyright (C) 2012-2014 by TOSHIBA CORPORATION, JAPAN
|
---|
| 15 | * Copyright (C) 2012-2014 by Witz Corporation, JAPAN
|
---|
| 16 | *
|
---|
| 17 | * ä¸è¨èä½æ¨©è
|
---|
| 18 | ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
|
---|
| 19 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
|
---|
| 20 | * å¤ã»åé
|
---|
| 21 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
|
---|
| 22 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
|
---|
| 23 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
|
---|
| 24 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
|
---|
| 25 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
|
---|
| 26 | * ç¨ã§ããå½¢ã§åé
|
---|
| 27 | å¸ããå ´åã«ã¯ï¼åé
|
---|
| 28 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
|
---|
| 29 | * è
|
---|
| 30 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
|
---|
| 31 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
|
---|
| 32 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
|
---|
| 33 | * ç¨ã§ããªãå½¢ã§åé
|
---|
| 34 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
|
---|
| 35 | * ã¨ï¼
|
---|
| 36 | * (a) åé
|
---|
| 37 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
|
---|
| 38 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
|
---|
| 39 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
|
---|
| 40 | * (b) åé
|
---|
| 41 | å¸ã®å½¢æ
|
---|
| 42 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
|
---|
| 43 | * å ±åãããã¨ï¼
|
---|
| 44 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
|
---|
| 45 | * 害ãããï¼ä¸è¨èä½æ¨©è
|
---|
| 46 | ããã³TOPPERSããã¸ã§ã¯ããå
|
---|
| 47 | 責ãããã¨ï¼
|
---|
| 48 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
|
---|
| 49 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
|
---|
| 50 | ããã³TOPPERSããã¸ã§ã¯ãã
|
---|
| 51 | * å
|
---|
| 52 | 責ãããã¨ï¼
|
---|
| 53 | *
|
---|
| 54 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼AUTOSARï¼AUTomotive Open System ARchitectureï¼ä»
|
---|
| 55 | * æ§ã«åºã¥ãã¦ããï¼ä¸è¨ã®è¨±è«¾ã¯ï¼AUTOSARã®ç¥ç財ç£æ¨©ã許諾ãããã®ã§
|
---|
| 56 | * ã¯ãªãï¼AUTOSARã¯ï¼AUTOSARä»æ§ã«åºã¥ããã½ããã¦ã§ã¢ãåç¨ç®çã§å©
|
---|
| 57 | * ç¨ããè
|
---|
| 58 | ã«å¯¾ãã¦ï¼AUTOSARãã¼ããã¼ã«ãªããã¨ãæ±ãã¦ããï¼
|
---|
| 59 | *
|
---|
| 60 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
|
---|
| 61 | ã
|
---|
| 62 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
|
---|
| 63 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
|
---|
| 64 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
|
---|
| 65 | * ã®è²¬ä»»ãè² ããªãï¼
|
---|
| 66 | *
|
---|
| 67 | * $Id: v850e2_fx4.h 187 2015-06-25 03:39:04Z t_ishikawa $
|
---|
| 68 | */
|
---|
| 69 |
|
---|
| 70 | /*
|
---|
| 71 | * V850E2/Fx4ã®ãã¼ãã¦ã§ã¢è³æºã®å®ç¾©
|
---|
| 72 | */
|
---|
| 73 |
|
---|
| 74 | #ifndef TOPPERS_V850E2_FX4_H
|
---|
| 75 | #define TOPPERS_V850E2_FX4_H
|
---|
| 76 |
|
---|
| 77 | #if defined(V850FG4) || defined(V850FL4)
|
---|
| 78 | #define _V850E2M_
|
---|
| 79 | #elif defined(V850FG4_L)
|
---|
| 80 | #define _V850E2S_
|
---|
| 81 | #endif /* V850FG4 */
|
---|
| 82 |
|
---|
| 83 | /*
|
---|
| 84 | * PORTã¬ã¸ã¹ã¿
|
---|
| 85 | */
|
---|
| 86 | #define PORT_BASE UINT_C(0xff400000)
|
---|
| 87 |
|
---|
| 88 | /* 端åæ©è½è¨å® */
|
---|
| 89 | #define PMC(n) ((PORT_BASE) +0x0400 + (n * 0x04U)) /* ãã¼ãã»ã¢ã¼ãã»ã³ã³ããã¼ã«ã»ã¬ã¸ã¹ã¿ */
|
---|
| 90 | #define PMCSR(n) ((PORT_BASE) +0x0900 + (n * 0x04U)) /* ãã¼ãã»ã¢ã¼ãã»ã³ã³ããã¼ã«ã»ã»ããï¼ãªã»ããã»ã¬ã¸ã¹ã¿ */
|
---|
| 91 | #define PIPC(n) ((PORT_BASE) +0x4200 + (n * 0x04U)) /* ãã¼ãIP ã³ã³ããã¼ã«ã»ã¬ã¸ã¹ã¿ */
|
---|
| 92 | #define PM(n) ((PORT_BASE) +0x0300 + (n * 0x04U)) /* ãã¼ãã»ã¢ã¼ãã»ã¬ã¸ã¹ã¿ */
|
---|
| 93 | #define PMSR(n) ((PORT_BASE) +0x0800 + (n * 0x04U)) /* ãã¼ãã»ã¢ã¼ãã»ã»ããï¼ãªã»ããã»ã¬ã¸ã¹ã¿ */
|
---|
| 94 | #define PIBC(n) ((PORT_BASE) +0x4000 + (n * 0x04U)) /* ãã¼ãå
|
---|
| 95 | ¥åãããã¡ã»ã³ã³ããã¼ã«ã»ã¬ã¸ã¹ã¿ */
|
---|
| 96 | #define PFC(n) ((PORT_BASE) +0x0500 + (n * 0x04U)) /* ãã¼ãæ©è½ã³ã³ããã¼ã«ã»ã¬ã¸ã¹ã¿ */
|
---|
| 97 | #define PFCE(n) ((PORT_BASE) +0x0600 + (n * 0x04U)) /* ãã¼ãæ©è½ã³ã³ããã¼ã«ã»ã¬ã¸ã¹ã¿ */
|
---|
| 98 |
|
---|
| 99 | /* 端åãã¼ã¿å
|
---|
| 100 | ¥åï¼åºå */
|
---|
| 101 | #define PBDC(n) ((PORT_BASE) +0x4100 + (n * 0x04U)) /* ãã¼ãåæ¹åã³ã³ããã¼ã«ã»ã¬ã¸ã¹ã¿ */
|
---|
| 102 | #define PPR(n) ((PORT_BASE) +0x0200 + (n * 0x04U)) /* ãã¼ã端åãªã¼ãã»ã¬ã¸ã¹ã¿ */
|
---|
| 103 | #define P(n) ((PORT_BASE) +0x0000 + (n * 0x04U)) /* ãã¼ãã»ã¬ã¸ã¹ã¿ */
|
---|
| 104 | #define PNOT(n) ((PORT_BASE) +0x0700 + (n * 0x04U)) /* ãã¼ãã»ãããã»ã¬ã¸ã¹ã¿ */
|
---|
| 105 | #define PSR(n) ((PORT_BASE) +0x0100 + (n * 0x04U)) /* ãã¼ãã»ã»ããï¼ãªã»ããã»ã¬ã¸ã¹ã¿ */
|
---|
| 106 |
|
---|
| 107 | #define FCLA27CTL1 0xff416244 /* UARTE3ãã£ã«ã¿ã¬ã¸ã¹ã¿ */
|
---|
| 108 | #define FCLA27CTL3 0xff41624c
|
---|
| 109 | #define FCLA7CTL0 0xff415040
|
---|
| 110 | #define FCLA0CTL2 0xff414008
|
---|
| 111 | #define FCLA0CTL4 0xff414010
|
---|
| 112 |
|
---|
| 113 | /*
|
---|
| 114 | * PLLé¢é£ã®ã¬ã¸ã¹ã¿ã¨å®ç¾©
|
---|
| 115 | */
|
---|
| 116 | #define MOSCC 0xff421018
|
---|
| 117 | #define MOSCE 0xff421010
|
---|
| 118 | #define MOSCS 0xff421014
|
---|
| 119 | #define MOSCST 0xff42101c
|
---|
| 120 | #define OCDIDH 0xff470008
|
---|
| 121 | #define OCDIDL 0xff470000
|
---|
| 122 | #define OCDIDM 0xff470004
|
---|
| 123 | #define OPBT0 0xff47000c
|
---|
| 124 | #define OSCWUFMSK 0xff4201a4
|
---|
| 125 |
|
---|
| 126 | #define SOSCE 0xff421020
|
---|
| 127 | #define SOSCS 0xff421024
|
---|
| 128 | #define SOSCST 0xff42102c
|
---|
| 129 |
|
---|
| 130 | #define CKSC_0_BASE 0xff426000
|
---|
| 131 | #define CKSC_0(n) (CKSC_0_BASE + (0x10 * n))
|
---|
| 132 |
|
---|
| 133 | #define CKSC_1_BASE 0xff42a000
|
---|
| 134 | #define CKSC_1(n) (CKSC_1_BASE + (0x10 * n))
|
---|
| 135 |
|
---|
| 136 | #define CKSC_A_BASE 0xff422000
|
---|
| 137 | #define CKSC_A(n) (CKSC_A_BASE + (0x10 * n))
|
---|
| 138 |
|
---|
| 139 | #define CSCSTAT_0_BASE 0xff426000
|
---|
| 140 | #define CSCSTAT_0(n) (CSCSTAT_0_BASE + (0x10 * n)) + 4
|
---|
| 141 |
|
---|
| 142 | #define CSCSTAT_1_BASE 0xff42a000
|
---|
| 143 | #define CSCSTAT_1(n) (CSCSTAT_1_BASE + (0x10 * n)) + 4
|
---|
| 144 |
|
---|
| 145 | #define CSCSTAT_A_BASE 0xff422000
|
---|
| 146 | #define CSCSTAT_A(n) (CSCSTAT_A_BASE + (0x10 * n)) + 4
|
---|
| 147 |
|
---|
| 148 | #define PLLE_BASE 0xff425000
|
---|
| 149 | #define PLLE(n) (PLLE_BASE + (0x10 * n))
|
---|
| 150 |
|
---|
| 151 | #define PLLS_BASE 0xff425004
|
---|
| 152 | #define PLLS(n) (PLLS_BASE + (0x10 * n))
|
---|
| 153 |
|
---|
| 154 | #define PLLC_BASE 0xff425008
|
---|
| 155 | #define PLLC(n) (PLLC_BASE + (0x10 * n))
|
---|
| 156 |
|
---|
| 157 | #define PLLST_BASE 0xff42500c
|
---|
| 158 | #define PLLST(n) (PLLST_BASE + (0x10 * n))
|
---|
| 159 |
|
---|
| 160 | #define MHz(n) ((n) * 1000 * 1000)
|
---|
| 161 | #define CLK_MHz(num) (num * 1000 * 1000)
|
---|
| 162 |
|
---|
| 163 | /* CKSC_000 CPU, CPU SubSystem */
|
---|
| 164 | #define HIGH_SPEED_INTOSC_DIV2 0x08
|
---|
| 165 | #define HIGH_SPEED_INTOSC_DIV4 0x09
|
---|
| 166 | #define HIGH_SPEED_INTOSC_DIV8 0x0A
|
---|
| 167 | #define HIGH_SPEED_INTOSC_DIV32 0x0B
|
---|
| 168 | #define MAINOSC_DIV1 0x0C
|
---|
| 169 | #define PLL0_DIV1 0x14
|
---|
| 170 | #define PLL0_DIV2 0x15
|
---|
| 171 | #define PLL0_DIV3 0x16
|
---|
| 172 | #define PLL0_DIV4 0x17
|
---|
| 173 | #define PLL0_DIV5 0x18
|
---|
| 174 | #define PLL0_DIV6 0x19
|
---|
| 175 | #define PLL0_DIV8 0x1A
|
---|
| 176 | #define PLL0_DIV10 0x1B
|
---|
| 177 | #define INTOSC_AUTOSELECT 0x3A
|
---|
| 178 |
|
---|
| 179 | /* CKSC_A03 TAUJ0:PCLK */
|
---|
| 180 | #define LOW_SPEED_INTOSC_DIV1 0x01
|
---|
| 181 | #define HIGH_SPEED_INTOSC_DIV1 0x07
|
---|
| 182 | #define SUBOSC 0x12
|
---|
| 183 | #define NO_CLOCKSELECT 0x00
|
---|
| 184 |
|
---|
| 185 | #define PROT_PLLE 2 /* Fx4 Setting */
|
---|
| 186 | #define PROT_CKSC0 0
|
---|
| 187 | #define PROT_CKSC1 1
|
---|
| 188 | #define PROT_MOSCE 2
|
---|
| 189 | #define PROT_SOSCE 2
|
---|
| 190 | #define PROT_ROSCE 2
|
---|
| 191 | #define PROT_CKSCA 2
|
---|
| 192 |
|
---|
| 193 | /* xxxS Register */
|
---|
| 194 | #define CLK_S_STPACK 0x08
|
---|
| 195 | #define CLK_S_CLKEN 0x04
|
---|
| 196 | #define CLK_S_CLKACT 0x02
|
---|
| 197 | #define CLK_S_CLKSTAB 0x01
|
---|
| 198 |
|
---|
| 199 | /* PLL P-Value */
|
---|
| 200 | #define PDIV0R5_200TO400 0x0 /* Div 0.5, 200-400MHz Output */
|
---|
| 201 | #define PDIV1R0_100TO200 0x1 /* Div 1.0, 100-200MHz Output */
|
---|
| 202 | #define PDIV2R0_050TO100 0x2 /* Div 2.0, 50-100MHz Output */
|
---|
| 203 | #define PDIV4R0_025TO050 0x3 /* Div 4.0, 25- 50MHz Output */
|
---|
| 204 |
|
---|
| 205 | #define UC_SUCCESS 0
|
---|
| 206 | #define UC_ERROR 1
|
---|
| 207 | #define UC_INVALIDPARAM 2
|
---|
| 208 | #define UC_PROTREGERROR 3
|
---|
| 209 | #define UC_CLKSTATUSERR 4
|
---|
| 210 | #define UC_CLKNOTENABLE 5
|
---|
| 211 | #define UC_CLKNOTACTIVE 6
|
---|
| 212 | #define UC_CLKNOTSTAB 7
|
---|
| 213 |
|
---|
| 214 | #ifndef TOPPERS_MACRO_ONLY
|
---|
| 215 |
|
---|
| 216 | extern uint32 EnableSubOSC(void);
|
---|
| 217 |
|
---|
| 218 | extern uint32 EnableMainOSC(uint32 clk_in);
|
---|
| 219 |
|
---|
| 220 | extern uint32 SetPLL(uint32 pllno, uint32 mhz, uint32 *outclk);
|
---|
| 221 |
|
---|
| 222 | extern uint32 set_clock_selection(uint32 control, uint32 status, uint8 regno, uint16 sel);
|
---|
| 223 |
|
---|
| 224 | #endif /* TOPPERS_MACRO_ONLY */
|
---|
| 225 |
|
---|
| 226 | /*
|
---|
| 227 | * Interval Timer(TAUA0)
|
---|
| 228 | */
|
---|
| 229 | #define TAUA0_BASE UINT_C(0xFF808000) /* TAUA0 */
|
---|
| 230 |
|
---|
| 231 | #define TAUA0_IRQ UINT_C(20) /* TAUA0 */
|
---|
| 232 | #define TAUA1_IRQ UINT_C(21) /* TAUA1 */
|
---|
| 233 | #define TAUA2_IRQ UINT_C(22) /* TAUA2 */
|
---|
| 234 | #define TAUA3_IRQ UINT_C(23) /* TAUA3 */
|
---|
| 235 | #define TAUA4_IRQ UINT_C(24) /* TAUA4 */
|
---|
| 236 | #define TAUA5_IRQ UINT_C(25) /* TAUA5 */
|
---|
| 237 | #define TAUA6_IRQ UINT_C(26) /* TAUA6 */
|
---|
| 238 | #define TAUA7_IRQ UINT_C(27) /* TAUA7 */
|
---|
| 239 | #define TAUA8_IRQ UINT_C(28) /* TAUA8 */
|
---|
| 240 | #define TAUA9_IRQ UINT_C(29) /* TAUA9 */
|
---|
| 241 | #define TAUA10_IRQ UINT_C(30) /* TAUA10 */
|
---|
| 242 | #define TAUA11_IRQ UINT_C(31) /* TAUA11 */
|
---|
| 243 | #define TAUA12_IRQ UINT_C(32) /* TAUA12 */
|
---|
| 244 | #define TAUA13_IRQ UINT_C(33) /* TAUA13 */
|
---|
| 245 | #define TAUA14_IRQ UINT_C(34) /* TAUA14 */
|
---|
| 246 | #define TAUA15_IRQ UINT_C(35) /* TAUA15 */
|
---|
| 247 |
|
---|
| 248 | #define TAUA_CH0 0
|
---|
| 249 | #define TAUA_CH1 1
|
---|
| 250 | #define TAUA_CH2 2
|
---|
| 251 | #define TAUA_CH3 3
|
---|
| 252 | #define TAUA_CH4 4
|
---|
| 253 | #define TAUA_CH5 5
|
---|
| 254 | #define TAUA_CH6 6
|
---|
| 255 | #define TAUA_CH7 7
|
---|
| 256 | #define TAUA_CH8 8
|
---|
| 257 | #define TAUA_CH9 9
|
---|
| 258 | #define TAUA_CH10 10
|
---|
| 259 | #define TAUA_CH11 11
|
---|
| 260 | #define TAUA_CH12 12
|
---|
| 261 | #define TAUA_CH13 13
|
---|
| 262 | #define TAUA_CH14 14
|
---|
| 263 | #define TAUA_CH15 15
|
---|
| 264 |
|
---|
| 265 | /*
|
---|
| 266 | * TAUA0 Timer ãã¼ãã¦ã§ã¢å®ç¾©
|
---|
| 267 | */
|
---|
| 268 |
|
---|
| 269 | /*
|
---|
| 270 | * ã¬ã¸ã¹ã¿
|
---|
| 271 | */
|
---|
| 272 | /* TAUA0 ããªã¹ã±ã¼ã©ã»ã¬ã¸ã¹ã¿ */
|
---|
| 273 | #define TAUA0TPS (TAUA0_BASE + 0x240U) /* ããªã¹ã±ã¼ã©ã»ã¯ããã¯é¸æã¬ã¸ã¹ */
|
---|
| 274 | #define TAUA0BRS (TAUA0_BASE + 0x244U) /* ããªã¹ã±ã¼ã©ã»ãã¼ã»ã¬ã¼ãè¨å®ã¬ã¸ã¹ã¿ */
|
---|
| 275 |
|
---|
| 276 | /* TAUA0 å¶å¾¡ã¬ã¸ã¹ã¿ */
|
---|
| 277 | #define TAUA0CDR(CH) (TAUA0_BASE + (CH * 4U)) /* ãã¼ã¿ã»ã¬ã¸ã¹ã¿ */
|
---|
| 278 | #define TAUA0CNT(CH) (TAUA0_BASE + (0x80U + (CH * 4U))) /* ã«ã¦ã³ã¿ã»ã¬ã¸ã¹ã¿ */
|
---|
| 279 | #define TAUA0CMOR(CH) (TAUA0_BASE + (0x200U + (CH * 4U))) /* ã¢ã¼ãOS ã¬ã¸ã¹ã¿ */
|
---|
| 280 | #define TAUA0CMUR(CH) (TAUA0_BASE + (0xC0 + (CH * 4U))) /* ã¢ã¼ãã»ã¦ã¼ã¶ã»ã¬ã¸ã¹ã¿ */
|
---|
| 281 | #define TAUA0CSR(CH) (TAUA0_BASE + (0x140U + (CH * 4U))) /* ã¹ãã¼ã¿ã¹ã»ã¬ã¸ã¹ã¿ */
|
---|
| 282 | #define TATA0CSC(CH) (TAUA0_BASE + (0x180U + (CH * 4U))) /* ã¹ãã¼ã¿ã¹ã»ã¯ãªã¢ã»ããªã¬ã»ã¬ã¸ã¹ã¿ */
|
---|
| 283 | #define TAUA0TS (TAUA0_BASE + 0x1C4U) /* ã¹ã¿ã¼ãã»ããªã¬ã»ã¬ã¸ã¹ã¿ */
|
---|
| 284 | #define TAUA0TE (TAUA0_BASE + 0x1C0U) /* 許å¯ã¹ãã¼ã¿ã¹ã»ã¬ã¸ã¹ã¿ */
|
---|
| 285 | #define TAUA0TT (TAUA0_BASE + 0x1C8U) /* ã¹ãããã»ããªã¬ã»ã¬ã¸ã¹ã¿ */
|
---|
| 286 |
|
---|
| 287 | /* TAUA0 åºåã¬ã¸ã¹ã¿ */
|
---|
| 288 | #define TAUA0TOE (TAUA0_BASE + 0x5CU) /* åºå許å¯ã¬ã¸ã¹ã¿ */
|
---|
| 289 | #define TAUA0TO (TAUA0_BASE + 0x58U) /* åºåã¬ã¸ã¹ã¿ */
|
---|
| 290 | #define TAUA0TOM (TAUA0_BASE + 0x248U) /* åºåã¢ã¼ãã»ã¬ã¸ã¹ã¿ */
|
---|
| 291 | #define TAUA0TOC (TAUA0_BASE + 0x24CU) /* åºåã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ã»ã¬ã¸ã¹ã¿ */
|
---|
| 292 |
|
---|
| 293 | #define TAUA0TOL (TAUA0_BASE + 0x40U) /* åºåã¢ã¯ãã£ãã»ã¬ãã«ã»ã¬ã¸ã¹ã¿ */
|
---|
| 294 | #define TAUA0TDE (TAUA0_BASE + 0x250U) /* ãããã»ã¿ã¤ã åºå許å¯ã¬ã¸ã¹ã¿ */
|
---|
| 295 | #define TAUA0TDM (TAUA0_BASE + 0x254U) /* ãããã»ã¿ã¤ã åºåã¢ã¼ãã»ã¬ã¸ã¹ã¿ */
|
---|
| 296 | #define TAUA0TDL (TAUA0_BASE + 0x54U) /* ãããã»ã¿ã¤ã åºåã¬ãã«ã»ã¬ã¸ã¹ã¿ */
|
---|
| 297 |
|
---|
| 298 | #define TAUA0TRO (TAUA0_BASE + 0x4CU) /* ãªã¢ã«ã¿ã¤ã åºåã¬ã¸ã¹ã¿ */
|
---|
| 299 | #define TAUA0TRE (TAUA0_BASE + 0x258U) /* ãªã¢ã«ã¿ã¤ã åºå許å¯ã¬ã¸ã¹ã¿ */
|
---|
| 300 | #define TAUA0TRC (TAUA0_BASE + 0x25CU) /* ãªã¢ã«ã¿ã¤ã åºåå¶å¾¡ã¬ã¸ã¹ã¿ */
|
---|
| 301 | #define TAUA0TME (TAUA0_BASE + 0x50U) /* å¤èª¿åºå許å¯ã¬ã¸ã¹ã¿ */
|
---|
| 302 | /* TAUA0 ãªãã¼ãã»ãã¼ã¿ã»ã¬ã¸ã¹ã¿ */
|
---|
| 303 | #define TAUA0RDE (TAUA0_BASE + 0x260U) /* ãªãã¼ãã»ãã¼ã¿è¨±å¯ã¬ã¸ã¹ã¿ */
|
---|
| 304 | #define TAUA0RDM (TAUA0_BASE + 0x264U) /* ãªãã¼ãã»ãã¼ã¿ã»ã¢ã¼ãã»ã¬ã¸ã¹ã¿ */
|
---|
| 305 | #define TAUA0RDS (TAUA0_BASE + 0x268U) /* ãªãã¼ãã»ãã¼ã¿å¶å¾¡CH é¸æã»ãªãã¼ãã»ãã¼ã¿å¶å¾¡CH é¸æ */
|
---|
| 306 | #define TAUA0RDC (TAUA0_BASE + 0x26CU) /* ãªãã¼ãã»ãã¼ã¿å¶å¾¡ã¬ã¸ã¹ã¿ */
|
---|
| 307 | #define TAUA0RDT (TAUA0_BASE + 0x44U) /* ãªãã¼ãã»ãã¼ã¿ã»ããªã¬ã»ã¬ã¸ã¹ã¿ */
|
---|
| 308 | #define TAUA0RSF (TAUA0_BASE + 0x48U) /* ãªãã¼ãã»ã¹ãã¼ã¿ã¹ã»ã¬ã¸ã¹ã¿ */
|
---|
| 309 |
|
---|
| 310 | #define MCU_TAUA0_MASK_CK0 ((uint16) 0x000f)
|
---|
| 311 | #define MCU_TAUA0_CK0 ((uint16) 0x0000)
|
---|
| 312 | #define MCU_TAUA00_CMOR ((uint16) 0x0001)
|
---|
| 313 | #define MCU_TAUA00_CMUR ((uint8) 0x01)
|
---|
| 314 | #define MCU_TAUA00_DI ((uint16) 0x0080)
|
---|
| 315 | #define MCU_TAUA00_EI ((uint16) 0x0000)
|
---|
| 316 | #define MCU_TAUA00_MASK_ENB ((uint16) 0x0001)
|
---|
| 317 | #define MCU_TIMER_STOP ((uint8) 0x0)
|
---|
| 318 | #define MCU_TIMER_START ((uint8) 0x1)
|
---|
| 319 |
|
---|
| 320 | #define ICTAUA0_BASE 0xffff6028 /* ãã£ã³ãã«ï¼å²ã込㿠*/
|
---|
| 321 | #define ICTAUA0I(CH) (ICTAUA0_BASE + (CH * 0x02))
|
---|
| 322 |
|
---|
| 323 |
|
---|
| 324 | /*
|
---|
| 325 | * TAUA0 ãã¹ã¯å®ç¾©
|
---|
| 326 | */
|
---|
| 327 | #define TAUA0_MASK_BIT 0x0xfffe /* bit0 = TAUA0 */
|
---|
| 328 |
|
---|
| 329 | /*
|
---|
| 330 | * OSTM
|
---|
| 331 | */
|
---|
| 332 | #define OSTM_IRQ UINT_C(147)
|
---|
| 333 |
|
---|
| 334 | #define OSTM0_BASE 0xFF800000
|
---|
| 335 |
|
---|
| 336 | #define OSTM_CMP_W (0xFF800000 + 0x00)
|
---|
| 337 | #define OSTM_CNT_W (0xFF800000 + 0x04)
|
---|
| 338 | #define OSTM_TE (0xFF800000 + 0x10)
|
---|
| 339 | #define OSTM_TS_B (0xFF800000 + 0x14)
|
---|
| 340 | #define OSTM_TT_B (0xFF800000 + 0x18)
|
---|
| 341 | #define OSTM_CTL_B (0xFF800000 + 0x20)
|
---|
| 342 |
|
---|
| 343 | /*
|
---|
| 344 | * UARTE
|
---|
| 345 | */
|
---|
| 346 | #define URTE3_BASE UINT_C(0xff5f0000)
|
---|
| 347 | #define URTE5_BASE UINT_C(0xff610000)
|
---|
| 348 | #define URTE10_BASE UINT_C(0xff660000)
|
---|
| 349 | #define URTEnCTL0 (UARTE_BASE + 0x00U)
|
---|
| 350 | #define URTEnCTL1 (UARTE_BASE + 0x20U)
|
---|
| 351 | #define URTEnCTL2 (UARTE_BASE + 0x24U)
|
---|
| 352 | #define URTEnTRG (UARTE_BASE + 0x04U)
|
---|
| 353 | #define URTEnSTR0 (UARTE_BASE + 0x08U)
|
---|
| 354 | #define URTEnSTR1 (UARTE_BASE + 0x0cU)
|
---|
| 355 | #define URTEnSTC (UARTE_BASE + 0x10U)
|
---|
| 356 | #define URTEnRX (UARTE_BASE + 0x14U)
|
---|
| 357 | #define URTEnTX (UARTE_BASE + 0x18U)
|
---|
| 358 | #define URTEnEMU (UARTE_BASE + 0x34U)
|
---|
| 359 |
|
---|
| 360 | #define INTLMA3IT 0xffff618C /* 転éå®äº */
|
---|
| 361 | #define INTLMA3IR 0xffff618A /* åä¿¡å®äº */
|
---|
| 362 |
|
---|
| 363 | #define INTLMA5IT 0xffff61C4 /* UART5 RX */
|
---|
| 364 | #define INTLMA5IR 0xffff61C6 /* UART5 TX */
|
---|
| 365 |
|
---|
| 366 | #define INTLMA10IT 0xffff6204 /* UART10 TX */
|
---|
| 367 | #define INTLMA10IR 0xffff6202 /* UART10 RX */
|
---|
| 368 |
|
---|
| 369 | #define URTE3_INTNO UINT_C(197)
|
---|
| 370 | #define URTE5_INTNO UINT_C(226)
|
---|
| 371 |
|
---|
| 372 | #ifndef URTE10_INTNO
|
---|
| 373 | #define URTE10_INTNO UINT_C(249)
|
---|
| 374 | #endif /* URTE10_INTNO */
|
---|
| 375 |
|
---|
| 376 | /*
|
---|
| 377 | * TAUJ
|
---|
| 378 | */
|
---|
| 379 | #ifdef V850FG4
|
---|
| 380 | #define TAUFJ0I0_INTNO 135
|
---|
| 381 | #define TAUFJ0I1_INTNO 136
|
---|
| 382 | #define TAUFJ0I2_INTNO 137
|
---|
| 383 | #define TAUFJ0I3_INTNO 138
|
---|
| 384 | #define TAUFJ1I0_INTNO 139
|
---|
| 385 | #define TAUFJ1I1_INTNO 140
|
---|
| 386 | #define TAUFJ1I2_INTNO 141
|
---|
| 387 | #define TAUFJ1I3_INTNO 142
|
---|
| 388 | #elif defined(V850FG4_L)
|
---|
| 389 | #define TAUFJ0I0_INTNO 78
|
---|
| 390 | #define TAUFJ0I1_INTNO 79
|
---|
| 391 | #define TAUFJ0I2_INTNO 80
|
---|
| 392 | #define TAUFJ0I3_INTNO 81
|
---|
| 393 | #endif /* V850FG4 */
|
---|
| 394 |
|
---|
| 395 |
|
---|
| 396 | /*
|
---|
| 397 | * TAUJé¢é£ã¬ã¸ã¹ã¿
|
---|
| 398 | */
|
---|
| 399 | #define TAUJ_BASE(n) ((uint32) (0xff811000U + (n * 0x1000U)))
|
---|
| 400 | #define TAUJTPS(n) (TAUJ_BASE(n) + 0x90U)
|
---|
| 401 | #define TAUJCDR(n, ch) (TAUJ_BASE(n) + (ch * 0x04U))
|
---|
| 402 | #define TAUJCNT(n, ch) (TAUJ_BASE(n) + 0x10U + (ch * 0x04U))
|
---|
| 403 | #define TAUJCMOR(n, ch) (TAUJ_BASE(n) + 0x80U + (ch * 0x04U))
|
---|
| 404 | #define TAUJCMUR(n, ch) (TAUJ_BASE(n) + 0x20U + (ch * 0x04U))
|
---|
| 405 | #define TAUJTS(n) (TAUJ_BASE(n) + 0x54U)
|
---|
| 406 | #define TAUJTT(n) (TAUJ_BASE(n) + 0x58U)
|
---|
| 407 |
|
---|
| 408 | /*
|
---|
| 409 | * INT
|
---|
| 410 | */
|
---|
| 411 | #define EIC_BASE UINT_C(0xffff6000)
|
---|
| 412 | #define EIC_ADDRESS(intno) (EIC_BASE + (intno * 2))
|
---|
| 413 | #define PMR UINT_C(0xFFFF6448)
|
---|
| 414 | #define ISPR_H UINT_C(0xFFFF6440)
|
---|
| 415 | #define ISPC_H UINT_C(0xffff6450)
|
---|
| 416 |
|
---|
| 417 | #define TMIN_INTNO UINT_C(0)
|
---|
| 418 | #define TMAX_INTNO UINT_C(255)
|
---|
| 419 | #define TNUM_INT UINT_C(256)
|
---|
| 420 |
|
---|
| 421 | #include "v850.h"
|
---|
| 422 |
|
---|
| 423 | #endif /* TOPPERS_V850E2_FX4_H */
|
---|