1 | /*
|
---|
2 | * TOPPERS ATK2
|
---|
3 | * Toyohashi Open Platform for Embedded Real-Time Systems
|
---|
4 | * Automotive Kernel Version 2
|
---|
5 | *
|
---|
6 | * Copyright (C) 2012-2014 by Center for Embedded Computing Systems
|
---|
7 | * Graduate School of Information Science, Nagoya Univ., JAPAN
|
---|
8 | * Copyright (C) 2012-2014 by FUJI SOFT INCORPORATED, JAPAN
|
---|
9 | * Copyright (C) 2012-2013 by Spansion LLC, USA
|
---|
10 | * Copyright (C) 2012-2013 by NEC Communication Systems, Ltd., JAPAN
|
---|
11 | * Copyright (C) 2012-2014 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
|
---|
12 | * Copyright (C) 2012-2014 by Renesas Electronics Corporation, JAPAN
|
---|
13 | * Copyright (C) 2012-2014 by Sunny Giken Inc., JAPAN
|
---|
14 | * Copyright (C) 2012-2014 by TOSHIBA CORPORATION, JAPAN
|
---|
15 | * Copyright (C) 2012-2014 by Witz Corporation, JAPAN
|
---|
16 | *
|
---|
17 | * ä¸è¨èä½æ¨©è
|
---|
18 | ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
|
---|
19 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
|
---|
20 | * å¤ã»åé
|
---|
21 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
|
---|
22 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
|
---|
23 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
|
---|
24 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
|
---|
25 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
|
---|
26 | * ç¨ã§ããå½¢ã§åé
|
---|
27 | å¸ããå ´åã«ã¯ï¼åé
|
---|
28 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
|
---|
29 | * è
|
---|
30 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
|
---|
31 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
|
---|
32 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
|
---|
33 | * ç¨ã§ããªãå½¢ã§åé
|
---|
34 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
|
---|
35 | * ã¨ï¼
|
---|
36 | * (a) åé
|
---|
37 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
|
---|
38 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
|
---|
39 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
|
---|
40 | * (b) åé
|
---|
41 | å¸ã®å½¢æ
|
---|
42 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
|
---|
43 | * å ±åãããã¨ï¼
|
---|
44 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
|
---|
45 | * 害ãããï¼ä¸è¨èä½æ¨©è
|
---|
46 | ããã³TOPPERSããã¸ã§ã¯ããå
|
---|
47 | 責ãããã¨ï¼
|
---|
48 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
|
---|
49 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
|
---|
50 | ããã³TOPPERSããã¸ã§ã¯ãã
|
---|
51 | * å
|
---|
52 | 責ãããã¨ï¼
|
---|
53 | *
|
---|
54 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼AUTOSARï¼AUTomotive Open System ARchitectureï¼ä»
|
---|
55 | * æ§ã«åºã¥ãã¦ããï¼ä¸è¨ã®è¨±è«¾ã¯ï¼AUTOSARã®ç¥ç財ç£æ¨©ã許諾ãããã®ã§
|
---|
56 | * ã¯ãªãï¼AUTOSARã¯ï¼AUTOSARä»æ§ã«åºã¥ããã½ããã¦ã§ã¢ãåç¨ç®çã§å©
|
---|
57 | * ç¨ããè
|
---|
58 | ã«å¯¾ãã¦ï¼AUTOSARãã¼ããã¼ã«ãªããã¨ãæ±ãã¦ããï¼
|
---|
59 | *
|
---|
60 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
|
---|
61 | ã
|
---|
62 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
|
---|
63 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
|
---|
64 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
|
---|
65 | * ã®è²¬ä»»ãè² ããªãï¼
|
---|
66 | *
|
---|
67 | * $Id: v850e2_fx4.c 117 2014-12-10 03:58:03Z t_ishikawa $
|
---|
68 | */
|
---|
69 | #include "kernel_impl.h"
|
---|
70 | #include "v850e2_fx4.h"
|
---|
71 | #include "Os.h"
|
---|
72 | #include "prc_sil.h"
|
---|
73 |
|
---|
74 | /*******************************************************************************************/
|
---|
75 | /* Outline : Write protected register */
|
---|
76 | /* Argument : Register address */
|
---|
77 | /* Register data */
|
---|
78 | /* Register No */
|
---|
79 | /* Return value : 0: write success / 1: write error */
|
---|
80 | /* Description : Write protected register */
|
---|
81 | /* */
|
---|
82 | /*******************************************************************************************/
|
---|
83 | static uint32
|
---|
84 | write_protected_reg(uint32 addr, uint32 data, uint8 regno)
|
---|
85 | {
|
---|
86 | uint32 reg_top = 0xff420000;
|
---|
87 | uint32 reg_stat;
|
---|
88 | uint8 wk;
|
---|
89 | SIL_PRE_LOC;
|
---|
90 |
|
---|
91 | if (regno > 2) {
|
---|
92 | return(UC_INVALIDPARAM);
|
---|
93 | }
|
---|
94 |
|
---|
95 | switch (regno) {
|
---|
96 | case 0:
|
---|
97 | reg_top += 0x4000; /* PROTCMD0 */
|
---|
98 | break;
|
---|
99 | case 1:
|
---|
100 | reg_top += 0x8000; /* PROTCMD1 */
|
---|
101 | break;
|
---|
102 | case 2:
|
---|
103 | reg_top += 0x0300; /* PROTCMD2 */
|
---|
104 | break;
|
---|
105 | }
|
---|
106 | reg_stat = reg_top + 4; /* PROTS0/PROTS1/PROTS2 */
|
---|
107 |
|
---|
108 | SIL_LOC_INT();
|
---|
109 | sil_wrb_mem((void *) reg_top, 0xA5);
|
---|
110 |
|
---|
111 | sil_wrw_mem((void *) addr, data);
|
---|
112 | sil_wrw_mem((void *) addr, ~data);
|
---|
113 | sil_wrw_mem((void *) addr, data);
|
---|
114 | SIL_UNL_INT();
|
---|
115 |
|
---|
116 | wk = sil_reb_mem((void *) reg_stat);
|
---|
117 | wk &= 0x01;
|
---|
118 |
|
---|
119 | return((wk == 0) ? UC_SUCCESS : UC_PROTREGERROR);
|
---|
120 | } /* write_protected_reg */
|
---|
121 |
|
---|
122 | /********************************************************************************************/
|
---|
123 | /* Function Name : V850Drv_nop */
|
---|
124 | /* Input : none */
|
---|
125 | /* Output : none */
|
---|
126 | /* Description : nop command */
|
---|
127 | /********************************************************************************************/
|
---|
128 | static void
|
---|
129 | V850Drv_nop(void)
|
---|
130 | {
|
---|
131 | Asm("nop");
|
---|
132 |
|
---|
133 | } /* V850Drv_nop */
|
---|
134 |
|
---|
135 | /*******************************************************************************************/
|
---|
136 | /* Outline : Sub Oscillator enable */
|
---|
137 | /* Argument : - */
|
---|
138 | /* Return value : 0: successfly set / 1: set error */
|
---|
139 | /* Description : Sub Oscillator register setting */
|
---|
140 | /* */
|
---|
141 | /*******************************************************************************************/
|
---|
142 | uint32
|
---|
143 | EnableSubOSC(void)
|
---|
144 | {
|
---|
145 | uint32 ucret;
|
---|
146 |
|
---|
147 | sil_wrw_mem((void *) SOSCST, 0x02); /* stabilization time -> 262ms */
|
---|
148 |
|
---|
149 | ucret = write_protected_reg(SOSCE, 0x01, PROT_SOSCE); /* SubOSC start */
|
---|
150 |
|
---|
151 | if (ucret != UC_SUCCESS) return(ucret);
|
---|
152 |
|
---|
153 | while (((sil_rew_mem((void *) SOSCS)) & CLK_S_CLKSTAB) == 0) { /* Wait stabilization */
|
---|
154 | V850Drv_nop();
|
---|
155 | }
|
---|
156 | return(UC_SUCCESS);
|
---|
157 | } /* EnableSubOSC */
|
---|
158 |
|
---|
159 | /*******************************************************************************************/
|
---|
160 | /* Outline : Main Oscillator enable */
|
---|
161 | /* Argument : Main Cscillator frequency(Hz) */
|
---|
162 | /* Return value : 0: successfly set / 1: set error */
|
---|
163 | /* Description : Main Oscillator register setting */
|
---|
164 | /* */
|
---|
165 | /*******************************************************************************************/
|
---|
166 | uint32
|
---|
167 | EnableMainOSC(uint32 clk_in)
|
---|
168 | {
|
---|
169 | uint8 ampsel;
|
---|
170 | uint32 ucret;
|
---|
171 |
|
---|
172 | if (clk_in == CLK_MHz(4)) {
|
---|
173 | ampsel = 0x03;
|
---|
174 | }
|
---|
175 | else if (CLK_MHz(4) < clk_in && clk_in <= CLK_MHz(8)) {
|
---|
176 | ampsel = 0x02;
|
---|
177 | }
|
---|
178 | else if (CLK_MHz(8) < clk_in && clk_in <= CLK_MHz(16)) {
|
---|
179 | ampsel = 0x01;
|
---|
180 | }
|
---|
181 | else if (CLK_MHz(16) < clk_in && clk_in <= CLK_MHz(20)) {
|
---|
182 | ampsel = 0x00;
|
---|
183 | }
|
---|
184 | else {
|
---|
185 | return(UC_INVALIDPARAM);
|
---|
186 | }
|
---|
187 |
|
---|
188 | sil_wrw_mem((void *) MOSCC, 0x00 | ampsel); /* Normal stabilization time mode */
|
---|
189 | sil_wrw_mem((void *) MOSCST, 0x0F); /* stabilization time -> Max */
|
---|
190 |
|
---|
191 | ucret = write_protected_reg(MOSCE, 0x01, PROT_MOSCE); /* MainOSC start */
|
---|
192 |
|
---|
193 | if (ucret != UC_SUCCESS) return(ucret);
|
---|
194 |
|
---|
195 | while (((sil_rew_mem((void *) MOSCS)) & CLK_S_CLKSTAB) == 0) { /* Wait stabilization */
|
---|
196 | V850Drv_nop();
|
---|
197 | }
|
---|
198 |
|
---|
199 | return(UC_SUCCESS);
|
---|
200 | } /* EnableMainOSC */
|
---|
201 |
|
---|
202 | /*******************************************************************************************/
|
---|
203 | /* Outline : PLL enable */
|
---|
204 | /* Argument : PLL No */
|
---|
205 | /* Multiplying rate */
|
---|
206 | /* Register data */
|
---|
207 | /* Return value : 0: successfly set / 1: set error */
|
---|
208 | /* Description : PLL register setting */
|
---|
209 | /* */
|
---|
210 | /*******************************************************************************************/
|
---|
211 | static uint32
|
---|
212 | EnablePLL(uint32 pllno, uint8 clk_mul, uint8 p_val)
|
---|
213 | {
|
---|
214 | uint32 ucret;
|
---|
215 |
|
---|
216 | if (clk_mul > 50)
|
---|
217 | return(UC_INVALIDPARAM);
|
---|
218 |
|
---|
219 | sil_wrw_mem((void *) PLLC(pllno), (0x800000 | (p_val << 8) | (clk_mul - 1))); /* PLL Mode, P, Nr */
|
---|
220 | sil_wrw_mem((void *) PLLST(pllno), 0x07); /* stabilization time -> Max */
|
---|
221 |
|
---|
222 | ucret = write_protected_reg(PLLE(pllno), 0x01, PROT_PLLE); /* PLL Start */
|
---|
223 |
|
---|
224 | if (ucret != UC_SUCCESS)
|
---|
225 | return(ucret);
|
---|
226 |
|
---|
227 | while (((sil_rew_mem((void *) PLLS(pllno))) & CLK_S_CLKSTAB) == 0) { /* Wait stabilization */
|
---|
228 | /* V850Drv_nop(); */
|
---|
229 | }
|
---|
230 |
|
---|
231 | return(UC_SUCCESS);
|
---|
232 | } /* EnablePLL */
|
---|
233 |
|
---|
234 | /*******************************************************************************************/
|
---|
235 | /* Outline : Set PLL frequency */
|
---|
236 | /* Argument : PLL select No */
|
---|
237 | /* PLL frequency */
|
---|
238 | /* PLL frequency */
|
---|
239 | /* Return value : 0: successfly set / 1: set error */
|
---|
240 | /* Description : Set PLL register from frequency */
|
---|
241 | /* */
|
---|
242 | /*******************************************************************************************/
|
---|
243 | uint32
|
---|
244 | SetPLL(uint32 pllno, uint32 mhz, uint32 *outclk)
|
---|
245 | {
|
---|
246 | uint32 mul;
|
---|
247 |
|
---|
248 | if (mhz < 20) {
|
---|
249 | return(UC_ERROR);
|
---|
250 | }
|
---|
251 | else if (mhz < 50) {
|
---|
252 | mul = (mhz / MAINOSC_CLOCK) * 4;
|
---|
253 | if (mul <= 5 && 51 <= mul)
|
---|
254 | return(UC_ERROR);
|
---|
255 | *outclk = MAINOSC_CLOCK * mul / 4;
|
---|
256 | return(EnablePLL(pllno, mul, PDIV4R0_025TO050));
|
---|
257 | }
|
---|
258 | else if (mhz < 100) {
|
---|
259 | mul = (mhz / MAINOSC_CLOCK) * 2;
|
---|
260 | if (mul <= 5 && 51 <= mul)
|
---|
261 | return(UC_ERROR);
|
---|
262 | *outclk = MAINOSC_CLOCK * mul / 2;
|
---|
263 | return(EnablePLL(pllno, mul, PDIV2R0_050TO100));
|
---|
264 | }
|
---|
265 | else if (mhz < 200) {
|
---|
266 | mul = (mhz / MAINOSC_CLOCK) * 1;
|
---|
267 | if (mul <= 5 && 51 <= mul)
|
---|
268 | return(UC_ERROR);
|
---|
269 | *outclk = MAINOSC_CLOCK * mul / 1;
|
---|
270 | return(EnablePLL(pllno, mul, PDIV1R0_100TO200));
|
---|
271 | }
|
---|
272 | else if (mhz < 400) {
|
---|
273 | mul = (mhz / MAINOSC_CLOCK) / 2;
|
---|
274 | if (mul <= 5 && 51 <= mul)
|
---|
275 | return(UC_ERROR);
|
---|
276 | *outclk = MAINOSC_CLOCK * mul * 2;
|
---|
277 | return(EnablePLL(pllno, mul, PDIV0R5_200TO400));
|
---|
278 | }
|
---|
279 | return(UC_ERROR);
|
---|
280 | } /* SetPLL */
|
---|
281 |
|
---|
282 | /*******************************************************************************************/
|
---|
283 | /* Outline : Clock switcher setting */
|
---|
284 | /* Argument : Control reginster address */
|
---|
285 | /* Status reginster address */
|
---|
286 | /* Register No */
|
---|
287 | /* Select No */
|
---|
288 | /* Return value : 0: successfly set / 1: set error */
|
---|
289 | /* Description : Select clock source of CKSCLK_mn */
|
---|
290 | /* */
|
---|
291 | /*******************************************************************************************/
|
---|
292 | uint32
|
---|
293 | set_clock_selection(uint32 control, uint32 status, uint8 regno, uint16 sel)
|
---|
294 | {
|
---|
295 | uint32 ucret;
|
---|
296 |
|
---|
297 | ucret = write_protected_reg(control, sel << 1, regno);
|
---|
298 | if (ucret != UC_SUCCESS) {
|
---|
299 | return(ucret);
|
---|
300 | }
|
---|
301 |
|
---|
302 | /* Wait for SelectEnable */
|
---|
303 | while (((sil_rew_mem((void *) status)) & 0x01) == 0) {
|
---|
304 | V850Drv_nop();
|
---|
305 | }
|
---|
306 |
|
---|
307 | return(UC_SUCCESS);
|
---|
308 | } /* set_clock_selection */
|
---|