[172] | 1 | /*
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| 2 | * TOPPERS ATK2
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems
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| 4 | * Automotive Kernel Version 2
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| 5 | *
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| 6 | * Copyright (C) 2012-2014 by Center for Embedded Computing Systems
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| 7 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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| 8 | * Copyright (C) 2012-2014 by FUJI SOFT INCORPORATED, JAPAN
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| 9 | * Copyright (C) 2012-2013 by Spansion LLC, USA
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| 10 | * Copyright (C) 2012-2013 by NEC Communication Systems, Ltd., JAPAN
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| 11 | * Copyright (C) 2012-2014 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
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| 12 | * Copyright (C) 2012-2014 by Renesas Electronics Corporation, JAPAN
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| 13 | * Copyright (C) 2012-2014 by Sunny Giken Inc., JAPAN
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| 14 | * Copyright (C) 2012-2014 by TOSHIBA CORPORATION, JAPAN
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| 15 | * Copyright (C) 2012-2014 by Witz Corporation, JAPAN
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| 16 | *
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| 17 | * ä¸è¨èä½æ¨©è
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| 18 | ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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| 19 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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| 20 | * å¤ã»åé
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| 21 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 22 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 23 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 24 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 25 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 26 | * ç¨ã§ããå½¢ã§åé
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| 27 | å¸ããå ´åã«ã¯ï¼åé
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| 28 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 29 | * è
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| 30 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 31 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 32 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 33 | * ç¨ã§ããªãå½¢ã§åé
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| 34 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 35 | * ã¨ï¼
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| 36 | * (a) åé
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| 37 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 38 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 39 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 40 | * (b) åé
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| 41 | å¸ã®å½¢æ
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| 42 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 43 | * å ±åãããã¨ï¼
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| 44 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 45 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 46 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 47 | 責ãããã¨ï¼
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| 48 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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| 49 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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| 50 | ããã³TOPPERSããã¸ã§ã¯ãã
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| 51 | * å
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| 52 | 責ãããã¨ï¼
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| 53 | *
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| 54 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼AUTOSARï¼AUTomotive Open System ARchitectureï¼ä»
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| 55 | * æ§ã«åºã¥ãã¦ããï¼ä¸è¨ã®è¨±è«¾ã¯ï¼AUTOSARã®ç¥ç財ç£æ¨©ã許諾ãããã®ã§
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| 56 | * ã¯ãªãï¼AUTOSARã¯ï¼AUTOSARä»æ§ã«åºã¥ããã½ããã¦ã§ã¢ãåç¨ç®çã§å©
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| 57 | * ç¨ããè
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| 58 | ã«å¯¾ãã¦ï¼AUTOSARãã¼ããã¼ã«ãªããã¨ãæ±ãã¦ããï¼
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| 59 | *
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| 60 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 61 | ã
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| 62 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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| 63 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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| 64 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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| 65 | * ã®è²¬ä»»ãè² ããªãï¼
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| 66 | *
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| 67 | * $Id: v850e2_fx4.c 117 2014-12-10 03:58:03Z t_ishikawa $
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| 68 | */
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| 69 | #include "kernel_impl.h"
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| 70 | #include "v850e2_fx4.h"
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| 71 | #include "Os.h"
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| 72 | #include "prc_sil.h"
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| 73 |
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| 74 | /*******************************************************************************************/
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| 75 | /* Outline : Write protected register */
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| 76 | /* Argument : Register address */
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| 77 | /* Register data */
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| 78 | /* Register No */
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| 79 | /* Return value : 0: write success / 1: write error */
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| 80 | /* Description : Write protected register */
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| 81 | /* */
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| 82 | /*******************************************************************************************/
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| 83 | static uint32
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| 84 | write_protected_reg(uint32 addr, uint32 data, uint8 regno)
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| 85 | {
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| 86 | uint32 reg_top = 0xff420000;
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| 87 | uint32 reg_stat;
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| 88 | uint8 wk;
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| 89 | SIL_PRE_LOC;
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| 90 |
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| 91 | if (regno > 2) {
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| 92 | return(UC_INVALIDPARAM);
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| 93 | }
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| 94 |
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| 95 | switch (regno) {
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| 96 | case 0:
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| 97 | reg_top += 0x4000; /* PROTCMD0 */
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| 98 | break;
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| 99 | case 1:
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| 100 | reg_top += 0x8000; /* PROTCMD1 */
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| 101 | break;
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| 102 | case 2:
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| 103 | reg_top += 0x0300; /* PROTCMD2 */
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| 104 | break;
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| 105 | }
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| 106 | reg_stat = reg_top + 4; /* PROTS0/PROTS1/PROTS2 */
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| 107 |
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| 108 | SIL_LOC_INT();
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| 109 | sil_wrb_mem((void *) reg_top, 0xA5);
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| 110 |
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| 111 | sil_wrw_mem((void *) addr, data);
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| 112 | sil_wrw_mem((void *) addr, ~data);
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| 113 | sil_wrw_mem((void *) addr, data);
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| 114 | SIL_UNL_INT();
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| 115 |
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| 116 | wk = sil_reb_mem((void *) reg_stat);
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| 117 | wk &= 0x01;
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| 118 |
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| 119 | return((wk == 0) ? UC_SUCCESS : UC_PROTREGERROR);
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| 120 | } /* write_protected_reg */
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| 121 |
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| 122 | /********************************************************************************************/
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| 123 | /* Function Name : V850Drv_nop */
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| 124 | /* Input : none */
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| 125 | /* Output : none */
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| 126 | /* Description : nop command */
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| 127 | /********************************************************************************************/
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| 128 | static void
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| 129 | V850Drv_nop(void)
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| 130 | {
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| 131 | Asm("nop");
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| 132 |
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| 133 | } /* V850Drv_nop */
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| 134 |
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| 135 | /*******************************************************************************************/
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| 136 | /* Outline : Sub Oscillator enable */
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| 137 | /* Argument : - */
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| 138 | /* Return value : 0: successfly set / 1: set error */
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| 139 | /* Description : Sub Oscillator register setting */
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| 140 | /* */
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| 141 | /*******************************************************************************************/
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| 142 | uint32
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| 143 | EnableSubOSC(void)
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| 144 | {
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| 145 | uint32 ucret;
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| 146 |
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| 147 | sil_wrw_mem((void *) SOSCST, 0x02); /* stabilization time -> 262ms */
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| 148 |
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| 149 | ucret = write_protected_reg(SOSCE, 0x01, PROT_SOSCE); /* SubOSC start */
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| 150 |
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| 151 | if (ucret != UC_SUCCESS) return(ucret);
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| 152 |
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| 153 | while (((sil_rew_mem((void *) SOSCS)) & CLK_S_CLKSTAB) == 0) { /* Wait stabilization */
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| 154 | V850Drv_nop();
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| 155 | }
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| 156 | return(UC_SUCCESS);
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| 157 | } /* EnableSubOSC */
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| 158 |
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| 159 | /*******************************************************************************************/
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| 160 | /* Outline : Main Oscillator enable */
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| 161 | /* Argument : Main Cscillator frequency(Hz) */
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| 162 | /* Return value : 0: successfly set / 1: set error */
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| 163 | /* Description : Main Oscillator register setting */
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| 164 | /* */
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| 165 | /*******************************************************************************************/
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| 166 | uint32
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| 167 | EnableMainOSC(uint32 clk_in)
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| 168 | {
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| 169 | uint8 ampsel;
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| 170 | uint32 ucret;
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| 171 |
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| 172 | if (clk_in == CLK_MHz(4)) {
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| 173 | ampsel = 0x03;
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| 174 | }
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| 175 | else if (CLK_MHz(4) < clk_in && clk_in <= CLK_MHz(8)) {
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| 176 | ampsel = 0x02;
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| 177 | }
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| 178 | else if (CLK_MHz(8) < clk_in && clk_in <= CLK_MHz(16)) {
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| 179 | ampsel = 0x01;
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| 180 | }
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| 181 | else if (CLK_MHz(16) < clk_in && clk_in <= CLK_MHz(20)) {
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| 182 | ampsel = 0x00;
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| 183 | }
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| 184 | else {
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| 185 | return(UC_INVALIDPARAM);
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| 186 | }
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| 187 |
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| 188 | sil_wrw_mem((void *) MOSCC, 0x00 | ampsel); /* Normal stabilization time mode */
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| 189 | sil_wrw_mem((void *) MOSCST, 0x0F); /* stabilization time -> Max */
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| 190 |
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| 191 | ucret = write_protected_reg(MOSCE, 0x01, PROT_MOSCE); /* MainOSC start */
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| 192 |
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| 193 | if (ucret != UC_SUCCESS) return(ucret);
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| 194 |
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| 195 | while (((sil_rew_mem((void *) MOSCS)) & CLK_S_CLKSTAB) == 0) { /* Wait stabilization */
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| 196 | V850Drv_nop();
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| 197 | }
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| 198 |
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| 199 | return(UC_SUCCESS);
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| 200 | } /* EnableMainOSC */
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| 201 |
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| 202 | /*******************************************************************************************/
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| 203 | /* Outline : PLL enable */
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| 204 | /* Argument : PLL No */
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| 205 | /* Multiplying rate */
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| 206 | /* Register data */
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| 207 | /* Return value : 0: successfly set / 1: set error */
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| 208 | /* Description : PLL register setting */
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| 209 | /* */
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| 210 | /*******************************************************************************************/
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| 211 | static uint32
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| 212 | EnablePLL(uint32 pllno, uint8 clk_mul, uint8 p_val)
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| 213 | {
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| 214 | uint32 ucret;
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| 215 |
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| 216 | if (clk_mul > 50)
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| 217 | return(UC_INVALIDPARAM);
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| 218 |
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| 219 | sil_wrw_mem((void *) PLLC(pllno), (0x800000 | (p_val << 8) | (clk_mul - 1))); /* PLL Mode, P, Nr */
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| 220 | sil_wrw_mem((void *) PLLST(pllno), 0x07); /* stabilization time -> Max */
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| 221 |
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| 222 | ucret = write_protected_reg(PLLE(pllno), 0x01, PROT_PLLE); /* PLL Start */
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| 223 |
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| 224 | if (ucret != UC_SUCCESS)
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| 225 | return(ucret);
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| 226 |
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| 227 | while (((sil_rew_mem((void *) PLLS(pllno))) & CLK_S_CLKSTAB) == 0) { /* Wait stabilization */
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| 228 | /* V850Drv_nop(); */
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| 229 | }
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| 230 |
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| 231 | return(UC_SUCCESS);
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| 232 | } /* EnablePLL */
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| 233 |
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| 234 | /*******************************************************************************************/
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| 235 | /* Outline : Set PLL frequency */
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| 236 | /* Argument : PLL select No */
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| 237 | /* PLL frequency */
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| 238 | /* PLL frequency */
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| 239 | /* Return value : 0: successfly set / 1: set error */
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| 240 | /* Description : Set PLL register from frequency */
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| 241 | /* */
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| 242 | /*******************************************************************************************/
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| 243 | uint32
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| 244 | SetPLL(uint32 pllno, uint32 mhz, uint32 *outclk)
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| 245 | {
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| 246 | uint32 mul;
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| 247 |
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| 248 | if (mhz < 20) {
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| 249 | return(UC_ERROR);
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| 250 | }
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| 251 | else if (mhz < 50) {
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| 252 | mul = (mhz / MAINOSC_CLOCK) * 4;
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| 253 | if (mul <= 5 && 51 <= mul)
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| 254 | return(UC_ERROR);
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| 255 | *outclk = MAINOSC_CLOCK * mul / 4;
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| 256 | return(EnablePLL(pllno, mul, PDIV4R0_025TO050));
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| 257 | }
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| 258 | else if (mhz < 100) {
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| 259 | mul = (mhz / MAINOSC_CLOCK) * 2;
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| 260 | if (mul <= 5 && 51 <= mul)
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| 261 | return(UC_ERROR);
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| 262 | *outclk = MAINOSC_CLOCK * mul / 2;
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| 263 | return(EnablePLL(pllno, mul, PDIV2R0_050TO100));
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| 264 | }
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| 265 | else if (mhz < 200) {
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| 266 | mul = (mhz / MAINOSC_CLOCK) * 1;
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| 267 | if (mul <= 5 && 51 <= mul)
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| 268 | return(UC_ERROR);
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| 269 | *outclk = MAINOSC_CLOCK * mul / 1;
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| 270 | return(EnablePLL(pllno, mul, PDIV1R0_100TO200));
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| 271 | }
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| 272 | else if (mhz < 400) {
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| 273 | mul = (mhz / MAINOSC_CLOCK) / 2;
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| 274 | if (mul <= 5 && 51 <= mul)
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| 275 | return(UC_ERROR);
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| 276 | *outclk = MAINOSC_CLOCK * mul * 2;
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| 277 | return(EnablePLL(pllno, mul, PDIV0R5_200TO400));
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| 278 | }
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| 279 | return(UC_ERROR);
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| 280 | } /* SetPLL */
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| 281 |
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| 282 | /*******************************************************************************************/
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| 283 | /* Outline : Clock switcher setting */
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| 284 | /* Argument : Control reginster address */
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| 285 | /* Status reginster address */
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| 286 | /* Register No */
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| 287 | /* Select No */
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| 288 | /* Return value : 0: successfly set / 1: set error */
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| 289 | /* Description : Select clock source of CKSCLK_mn */
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| 290 | /* */
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| 291 | /*******************************************************************************************/
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| 292 | uint32
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| 293 | set_clock_selection(uint32 control, uint32 status, uint8 regno, uint16 sel)
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| 294 | {
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| 295 | uint32 ucret;
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| 296 |
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| 297 | ucret = write_protected_reg(control, sel << 1, regno);
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| 298 | if (ucret != UC_SUCCESS) {
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| 299 | return(ucret);
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| 300 | }
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| 301 |
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| 302 | /* Wait for SelectEnable */
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| 303 | while (((sil_rew_mem((void *) status)) & 0x01) == 0) {
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| 304 | V850Drv_nop();
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| 305 | }
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| 306 |
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| 307 | return(UC_SUCCESS);
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| 308 | } /* set_clock_selection */
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