[172] | 1 | /*
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| 2 | * TOPPERS ATK2
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems
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| 4 | * Automotive Kernel Version 2
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| 5 | *
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| 6 | * Copyright (C) 2012-2014 by Center for Embedded Computing Systems
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| 7 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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| 8 | *
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| 9 | * ä¸è¨èä½æ¨©è
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| 10 | ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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| 11 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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| 12 | * å¤ã»åé
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| 13 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 14 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 15 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 16 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 17 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 18 | * ç¨ã§ããå½¢ã§åé
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| 19 | å¸ããå ´åã«ã¯ï¼åé
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| 20 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 21 | * è
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| 22 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 23 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 24 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 25 | * ç¨ã§ããªãå½¢ã§åé
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| 26 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 27 | * ã¨ï¼
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| 28 | * (a) åé
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| 29 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 30 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 31 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 32 | * (b) åé
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| 33 | å¸ã®å½¢æ
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| 34 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 35 | * å ±åãããã¨ï¼
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| 36 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 37 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 38 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 39 | 責ãããã¨ï¼
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| 40 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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| 41 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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| 42 | ããã³TOPPERSããã¸ã§ã¯ãã
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| 43 | * å
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| 44 | 責ãããã¨ï¼
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| 45 | *
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| 46 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼AUTOSARï¼AUTomotive Open System ARchitectureï¼ä»
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| 47 | * æ§ã«åºã¥ãã¦ããï¼ä¸è¨ã®è¨±è«¾ã¯ï¼AUTOSARã®ç¥ç財ç£æ¨©ã許諾ãããã®ã§
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| 48 | * ã¯ãªãï¼AUTOSARã¯ï¼AUTOSARä»æ§ã«åºã¥ããã½ããã¦ã§ã¢ãåç¨ç®çã§å©
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| 49 | * ç¨ããè
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| 50 | ã«å¯¾ãã¦ï¼AUTOSARãã¼ããã¼ã«ãªããã¨ãæ±ãã¦ããï¼
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| 51 | *
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| 52 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 53 | ã
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| 54 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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| 55 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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| 56 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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| 57 | * ã®è²¬ä»»ãè² ããªãï¼
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| 58 | *
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| 59 | * $Id: rh850_f1l.c 164 2015-06-03 01:22:29Z t_ishikawa $
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| 60 | */
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| 61 | #include "kernel_impl.h"
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| 62 | #include "rh850_f1l.h"
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| 63 | #include "Os.h"
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| 64 | #include "prc_sil.h"
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| 65 |
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| 66 | /*******************************************************************************************/
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| 67 | /* Outline : Write protected register */
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| 68 | /* Argument : Register address */
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| 69 | /* Register data */
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| 70 | /* Register No */
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| 71 | /* Return value : 0: write success / 1: write error */
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| 72 | /* Description : Write protected register */
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| 73 | /* */
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| 74 | /*******************************************************************************************/
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| 75 | static uint32
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| 76 | write_protected_reg(uint32 addr, uint32 data, uint8 regno)
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| 77 | {
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| 78 | uint8 wk;
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| 79 | const uint32 cmd_reg[19] = {
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| 80 | PROTCMD0, PROTCMD1, CLMA0PCMD, CLMA1PCMD, CLMA2PCMD, PROTCMDCLMA,
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| 81 | JPPCMD0, PPCMD0, PPCMD1, PPCMD2, PPCMD8,
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| 82 | PPCMD9, PPCMD10, PPCMD11, PPCMD12, PPCMD18, PPCMD20,
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| 83 | PROTCMDCVM, FLMDPCMD
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| 84 | };
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| 85 | const uint32 s_reg[19] = {
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| 86 | PROTS0, PROTS1, CLMA0PS, CLMA1PS, CLMA2PS, PROTSCLMA,
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| 87 | JPPROTS0, PPROTS0, PPROTS1, PPROTS2, PPROTS8,
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| 88 | PPROTS9, PPROTS10, PPROTS11, PPROTS12, PPROTS18, PPROTS20,
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| 89 | PROTSCVM, FLMDPS
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| 90 | };
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| 91 | SIL_PRE_LOC;
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| 92 |
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| 93 | if (regno > 19) {
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| 94 | return(UC_INVALIDPARAM);
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| 95 | }
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| 96 |
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| 97 | SIL_LOC_INT();
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| 98 | sil_wrw_mem((void *) cmd_reg[regno], 0xA5);
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| 99 |
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| 100 | sil_wrw_mem((void *) addr, data);
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| 101 | sil_wrw_mem((void *) addr, ~data);
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| 102 | sil_wrw_mem((void *) addr, data);
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| 103 | SIL_UNL_INT();
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| 104 |
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| 105 | wk = sil_rew_mem((void *) s_reg[regno]);
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| 106 | wk &= 0x01;
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| 107 |
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| 108 | return((wk == 0) ? UC_SUCCESS : UC_PROTREGERROR);
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| 109 | } /* write_protected_reg */
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| 110 |
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| 111 |
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| 112 | /*******************************************************************************************/
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| 113 | /* Outline : Sub Oscillator enable */
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| 114 | /* Argument : - */
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| 115 | /* Return value : 0: successfly set / 1: set error */
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| 116 | /* Description : Sub Oscillator register setting */
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| 117 | /* */
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| 118 | /*******************************************************************************************/
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| 119 | uint32
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| 120 | EnableSubOSC(void)
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| 121 | {
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| 122 | /* stop SubOSC */
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| 123 | if (write_protected_reg(SOSCE, 0x00, PNO_CtrlProt0) != UC_SUCCESS) {
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| 124 | return(UC_ERROR);
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| 125 | }
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| 126 |
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| 127 | /* Wait inactive */
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| 128 | while (((sil_rew_mem((void *) SOSCS)) & CLK_S_CLKEN) != 0) {
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| 129 | }
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| 130 |
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| 131 | /* start SubOSC */
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| 132 | if (write_protected_reg(SOSCE, 0x01, PNO_CtrlProt0) != UC_SUCCESS) return(UC_ERROR);
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| 133 |
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| 134 | /* Wait stabilization */
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| 135 | while (((sil_rew_mem((void *) SOSCS)) & CLK_S_CLKEN) == 0) {
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| 136 | }
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| 137 |
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| 138 | return(UC_SUCCESS);
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| 139 | } /* EnableSubOSC */
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| 140 |
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| 141 | /*******************************************************************************************/
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| 142 | /* Outline : Main Oscillator enable */
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| 143 | /* Argument : Main Cscillator frequency(Hz) */
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| 144 | /* Return value : 0: successfly set / 1: set error */
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| 145 | /* Description : Main Oscillator register setting */
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| 146 | /* */
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| 147 | /*******************************************************************************************/
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| 148 | uint32
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| 149 | EnableMainOSC(uint32 clk_in)
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| 150 | {
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| 151 | uint8 ampsel;
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| 152 |
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| 153 | /* stop MainOSC */
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| 154 | if (write_protected_reg(MOSCE, 0x02, PNO_CtrlProt0) != UC_SUCCESS) {
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| 155 | return(UC_ERROR);
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| 156 | }
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| 157 |
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| 158 | if (clk_in == CLK_MHz(8)) {
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| 159 | ampsel = 0x03;
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| 160 | }
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| 161 | else if (CLK_MHz(8) < clk_in && clk_in <= CLK_MHz(16)) {
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| 162 | ampsel = 0x02;
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| 163 | }
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| 164 | else if (CLK_MHz(16) < clk_in && clk_in <= CLK_MHz(20)) {
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| 165 | ampsel = 0x01;
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| 166 | }
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| 167 | else if (CLK_MHz(20) < clk_in && clk_in <= CLK_MHz(24)) {
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| 168 | ampsel = 0x00;
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| 169 | }
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| 170 | else {
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| 171 | return(UC_INVALIDPARAM);
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| 172 | }
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| 173 |
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| 174 | /* Wait inactive */
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| 175 | while (((sil_rew_mem((void *) MOSCS)) & CLK_S_CLKEN) != 0) {
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| 176 | }
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| 177 |
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| 178 | sil_wrw_mem((void *) MOSCC, 0x00 | ampsel); /* Normal stabilization time mode */
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| 179 | sil_wrw_mem((void *) MOSCST, 0x00FF); /* stabilization time -> Max */
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| 180 |
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| 181 | /* MainOSC start */
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| 182 | if (write_protected_reg(MOSCE, 0x01, PNO_CtrlProt0) != UC_SUCCESS) {
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| 183 | return(UC_ERROR);
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| 184 | }
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| 185 |
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| 186 | /* Wait stabilization */
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| 187 | while (((sil_rew_mem((void *) MOSCS)) & CLK_S_CLKEN) == 0) {
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| 188 | }
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| 189 |
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| 190 | return(UC_SUCCESS);
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| 191 | } /* EnableMainOSC */
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| 192 |
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| 193 | /*******************************************************************************************/
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| 194 | /* Outline : PLL enable */
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| 195 | /* Argument : none */
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| 196 | /* Return value : 0: successfly set / 1: set error */
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| 197 | /* Description : PLL register setting */
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| 198 | /* */
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| 199 | /*******************************************************************************************/
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| 200 | uint32
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| 201 | EnablePLL(void)
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| 202 | {
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| 203 | /* stop PLL */
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| 204 | if (write_protected_reg(PLLE, 0x02, PNO_CtrlProt1) != UC_SUCCESS) {
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| 205 | return(UC_ERROR);
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| 206 | }
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| 207 |
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| 208 | sil_wrw_mem((void *) PLLC, (PLLC_OUTBSEL << 16) | ((PLLC_mr - 1) << 11) | ((PLLC_par >> 1) << 8) | (PLLC_nr - 1));
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| 209 |
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| 210 | /* start PLL */
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| 211 | if (write_protected_reg(PLLE, 0x01, PNO_CtrlProt1) != UC_SUCCESS) {
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| 212 | return(UC_ERROR);
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| 213 | }
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| 214 |
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| 215 | /* Wait stabilization */
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| 216 | while (((sil_rew_mem((void *) PLLS)) & CLK_S_CLKEN) == 0) {
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| 217 | }
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| 218 |
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| 219 | return(UC_SUCCESS);
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| 220 | } /* EnablePLL */
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| 221 |
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| 222 | /*******************************************************************************************/
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| 223 | /* Outline : Clock switcher setting */
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| 224 | /* Argument : Selector Control reginster address */
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| 225 | /* Selector Status reginster address */
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| 226 | /* Register No */
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| 227 | /* Select No */
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| 228 | /* Divider Control reginster address */
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| 229 | /* Divider Status reginster address */
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| 230 | /* divider */
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| 231 | /* Return value : 0: successfly set / 1: set error */
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| 232 | /* Description : Select clock source of CKSCLK_mn */
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| 233 | /* */
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| 234 | /*******************************************************************************************/
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| 235 | uint32
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| 236 | SetClockSelection(uint32 s_control, uint32 s_status, uint8 regno, uint16 sel,
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| 237 | uint32 d_control, uint32 d_status, uint8 divider)
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| 238 | {
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| 239 | /* Set Selector */
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| 240 | if (write_protected_reg(s_control, sel, regno) != UC_SUCCESS) {
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| 241 | return(UC_ERROR);
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| 242 | }
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| 243 |
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| 244 | /* Set Divider */
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| 245 | if (d_control != 0) {
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| 246 | if (write_protected_reg(d_control, divider, regno) != UC_SUCCESS) {
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| 247 | return(UC_ERROR);
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| 248 | }
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| 249 | }
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| 250 |
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| 251 | /* Wait untile enable */
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| 252 | while (sil_rew_mem((void *) s_control) != sil_rew_mem((void *) s_status)) {
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| 253 | }
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| 254 |
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| 255 | if (d_control != 0) {
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| 256 | while (sil_rew_mem((void *) d_control) != sil_rew_mem((void *) d_status)) {
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| 257 | }
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| 258 | }
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| 259 |
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| 260 | return(UC_SUCCESS);
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| 261 | }
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