[172] | 1 | /*
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| 2 | * TOPPERS ATK2
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems
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| 4 | * Automotive Kernel Version 2
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| 5 | *
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| 6 | * Copyright (C) 2012-2014 by Center for Embedded Computing Systems
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| 7 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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| 8 | *
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| 9 | * ä¸è¨èä½æ¨©è
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| 10 | ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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| 11 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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| 12 | * å¤ã»åé
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| 13 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 14 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 15 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 16 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 17 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 18 | * ç¨ã§ããå½¢ã§åé
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| 19 | å¸ããå ´åã«ã¯ï¼åé
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| 20 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 21 | * è
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| 22 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 23 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 24 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 25 | * ç¨ã§ããªãå½¢ã§åé
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| 26 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 27 | * ã¨ï¼
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| 28 | * (a) åé
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| 29 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 30 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 31 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 32 | * (b) åé
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| 33 | å¸ã®å½¢æ
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| 34 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 35 | * å ±åãããã¨ï¼
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| 36 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 37 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 38 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 39 | 責ãããã¨ï¼
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| 40 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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| 41 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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| 42 | ããã³TOPPERSããã¸ã§ã¯ãã
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| 43 | * å
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| 44 | 責ãããã¨ï¼
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| 45 | *
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| 46 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼AUTOSARï¼AUTomotive Open System ARchitectureï¼ä»
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| 47 | * æ§ã«åºã¥ãã¦ããï¼ä¸è¨ã®è¨±è«¾ã¯ï¼AUTOSARã®ç¥ç財ç£æ¨©ã許諾ãããã®ã§
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| 48 | * ã¯ãªãï¼AUTOSARã¯ï¼AUTOSARä»æ§ã«åºã¥ããã½ããã¦ã§ã¢ãåç¨ç®çã§å©
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| 49 | * ç¨ããè
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| 50 | ã«å¯¾ãã¦ï¼AUTOSARãã¼ããã¼ã«ãªããã¨ãæ±ãã¦ããï¼
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| 51 | *
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| 52 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 53 | ã
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| 54 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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| 55 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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| 56 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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| 57 | * ã®è²¬ä»»ãè² ããªãï¼
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| 58 | *
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| 59 | * $Id: rh850_f1h.h 187 2015-06-25 03:39:04Z t_ishikawa $
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| 60 | */
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| 61 |
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| 62 | /*
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| 63 | * RH850/F1Lã®ãã¼ãã¦ã§ã¢è³æºã®å®ç¾©
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| 64 | */
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| 65 |
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| 66 | #ifndef TOPPERS_RH850_F1H_H
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| 67 | #define TOPPERS_RH850_F1H_H
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| 68 |
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| 69 | #define _RH850G3M_
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| 70 |
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| 71 | /*
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| 72 | * ä¿è·ã³ãã³ãã¬ã¸ã¹ã¿
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| 73 | */
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| 74 | #define PROTCMD0 0xFFF80000
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| 75 | #define PROTCMD1 0xFFF88000
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| 76 | #define CLMA0PCMD 0xFFF8C010
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| 77 | #define CLMA1PCMD 0xFFF8D010
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| 78 | #define CLMA2PCMD 0xFFF8E010
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| 79 | #define PROTCMDCLMA 0xFFF8C200
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| 80 | #define JPPCMD0 0xFFC204C0
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| 81 | #define PPCMD0 0xFFC14C00
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| 82 | #define PPCMD1 0xFFC14C04
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| 83 | #define PPCMD2 0xFFC14C08
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| 84 | #define PPCMD3 0xFFC14C0C
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| 85 | #define PPCMD8 0xFFC14C20
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| 86 | #define PPCMD9 0xFFC14C24
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| 87 | #define PPCMD10 0xFFC14C28
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| 88 | #define PPCMD11 0xFFC14C2C
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| 89 | #define PPCMD12 0xFFC14C30
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| 90 | #define PPCMD13 0xFFC14C34
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| 91 | #define PPCMD18 0xFFC14C48
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| 92 | #define PPCMD19 0xFFC14C4C
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| 93 | #define PPCMD20 0xFFC14C50
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| 94 | #define PPCMD21 0xFFC14C54
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| 95 | #define PPCMD22 0xFFC14C58
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| 96 | #define PROTCMDCVM 0xFFF83200
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| 97 | #define FLMDPCMD 0xFFA00004
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| 98 |
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| 99 | /*
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| 100 | * ä¿è·ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿
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| 101 | */
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| 102 | #define PROTS0 0xFFF80004
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| 103 | #define PROTS1 0xFFF88004
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| 104 | #define CLMA0PS 0xFFF8C014
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| 105 | #define CLMA1PS 0xFFF8D014
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| 106 | #define CLMA2PS 0xFFF8E014
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| 107 | #define PROTSCLMA 0xFFF8C204
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| 108 | #define JPPROTS0 0xFFC204B0
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| 109 | #define PPROTS0 0xFFC14B00
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| 110 | #define PPROTS1 0xFFC14B04
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| 111 | #define PPROTS2 0xFFC14B08
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| 112 | #define PPROTS3 0xFFC14B0C
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| 113 | #define PPROTS8 0xFFC14B20
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| 114 | #define PPROTS9 0xFFC14B24
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| 115 | #define PPROTS10 0xFFC14B28
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| 116 | #define PPROTS11 0xFFC14B2C
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| 117 | #define PPROTS12 0xFFC14B30
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| 118 | #define PPROTS13 0xFFC14B34
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| 119 | #define PPROTS18 0xFFC14B48
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| 120 | #define PPROTS19 0xFFC14B4C
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| 121 | #define PPROTS20 0xFFC14B50
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| 122 | #define PPROTS21 0xFFC14B54
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| 123 | #define PPROTS22 0xFFC14B58
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| 124 | #define PROTSCVM 0xFFF83204
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| 125 | #define FLMDPS 0xFFA00008
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| 126 |
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| 127 | /*
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| 128 | * ä¿è·ã³ãã³ãã¬ã¸ã¹ã¿ã®çªå·
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| 129 | */
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| 130 | #define PNO_CtrlProt0 0
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| 131 | #define PNO_CtrlProt1 1
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| 132 | #define PNO_ClkMonitorCtrlProt0 2
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| 133 | #define PNO_ClkMonitorCtrlProt1 3
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| 134 | #define PNO_ClkMonitorCtrlProt2 4
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| 135 | #define PNO_ClkMonitorTestProt 5
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| 136 | #define PNO_PortProt0 6
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| 137 | #define PNO_PortProt0_0 7
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| 138 | #define PNO_PortProt0_1 8
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| 139 | #define PNO_PortProt0_2 9
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| 140 | #define PNO_PortProt0_3 10
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| 141 | #define PNO_PortProt0_8 11
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| 142 | #define PNO_PortProt1_9 12
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| 143 | #define PNO_PortProt1_10 13
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| 144 | #define PNO_PortProt1_11 14
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| 145 | #define PNO_PortProt1_12 15
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| 146 | #define PNO_PortProt1_13 16
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| 147 | #define PNO_PortProt1_18 17
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| 148 | #define PNO_PortProt1_19 18
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| 149 | #define PNO_PortProt1_20 19
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| 150 | #define PNO_PortProt1_21 20
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| 151 | #define PNO_PortProt1_22 21
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| 152 | #define PNO_CoreVMonitorProt 22
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| 153 | #define PNO_SelfProgProt 23
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| 154 |
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| 155 | /*
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| 156 | * PORTã¬ã¸ã¹ã¿
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| 157 | */
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| 158 | #define PORT_BASE UINT_C(0xffc10000)
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| 159 |
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| 160 | /* 端åæ©è½è¨å® (USE)*/
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| 161 | #define PMC(n) ((PORT_BASE) +0x0400 + (n * 0x04U)) /* ãã¼ãã»ã¢ã¼ãã»ã³ã³ããã¼ã«ã»ã¬ã¸ã¹ã¿ */
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| 162 | #define PMCSR(n) ((PORT_BASE) +0x0900 + (n * 0x04U)) /* ãã¼ãã»ã¢ã¼ãã»ã³ã³ããã¼ã«ã»ã»ããï¼ãªã»ããã»ã¬ã¸ã¹ã¿ */
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| 163 | #define PIPC(n) ((PORT_BASE) +0x4200 + (n * 0x04U)) /* ãã¼ãIP ã³ã³ããã¼ã«ã»ã¬ã¸ã¹ã¿ */
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| 164 | #define PM(n) ((PORT_BASE) +0x0300 + (n * 0x04U)) /* ãã¼ãã»ã¢ã¼ãã»ã¬ã¸ã¹ã¿ */
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| 165 | #define PMSR(n) ((PORT_BASE) +0x0800 + (n * 0x04U)) /* ãã¼ãã»ã¢ã¼ãã»ã»ããï¼ãªã»ããã»ã¬ã¸ã¹ã¿ */
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| 166 | #define PIBC(n) ((PORT_BASE) +0x4000 + (n * 0x04U)) /* ãã¼ãå
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| 167 | ¥åãããã¡ã»ã³ã³ããã¼ã«ã»ã¬ã¸ã¹ã¿ */
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| 168 | #define PFC(n) ((PORT_BASE) +0x0500 + (n * 0x04U)) /* ãã¼ãæ©è½ã³ã³ããã¼ã«ã»ã¬ã¸ã¹ã¿ */
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| 169 | #define PFCE(n) ((PORT_BASE) +0x0600 + (n * 0x04U)) /* ãã¼ãæ©è½ã³ã³ããã¼ã«æ¡å¼µã»ã¬ã¸ã¹ã¿ */
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| 170 | #define PFCAE(n) ((PORT_BASE) +0x0A00 + (n * 0x04U)) /* ãã¼ãæ©è½ã³ã³ããã¼ã«è¿½å æ¡å¼µã»ã¬ã¸ã¹ã¿ */
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| 171 |
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| 172 | /* 端åãã¼ã¿å
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| 173 | ¥åï¼åºå (USE)*/
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| 174 | #define PBDC(n) ((PORT_BASE) +0x4100 + (n * 0x04U)) /* ãã¼ãåæ¹åã³ã³ããã¼ã«ã»ã¬ã¸ã¹ã¿ */
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| 175 | #define PPR(n) ((PORT_BASE) +0x0200 + (n * 0x04U)) /* ãã¼ã端åãªã¼ãã»ã¬ã¸ã¹ã¿ */
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| 176 | #define P(n) ((PORT_BASE) +0x0000 + (n * 0x04U)) /* ãã¼ãã»ã¬ã¸ã¹ã¿ */
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| 177 | #define PNOT(n) ((PORT_BASE) +0x0700 + (n * 0x04U)) /* ãã¼ãã»ãããã»ã¬ã¸ã¹ã¿ */
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| 178 | #define PSR(n) ((PORT_BASE) +0x0100 + (n * 0x04U)) /* ãã¼ãã»ã»ããï¼ãªã»ããã»ã¬ã¸ã¹ã¿ */
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| 179 |
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| 180 |
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| 181 | #define RLN3xBASE 0xffce2040
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| 182 |
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| 183 | #define RLN3xLWBR_B 0x00000001
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| 184 | #define RLN3xLBRP01_H 0x00000002
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| 185 | #define RLN3xLBRP0_B 0x00000002
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| 186 | #define RLN3xLBRP1_B 0x00000003
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| 187 | #define RLN3xLSTC_B 0x00000004
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| 188 | #define RLN3xLMD_B 0x00000008
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| 189 | #define RLN3xLBFC_B 0x00000009
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| 190 | #define RLN3xLSC_B 0x0000000a
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| 191 | #define RLN3xLWUP_B 0x0000000b
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| 192 | #define RLN3xLIE_B 0x0000000c
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| 193 | #define RLN3xLEDE_B 0x0000000d
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| 194 | #define RLN3xLCUC_B 0x0000000e
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| 195 | #define RLN3xLTRC_B 0x00000010
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| 196 | #define RLN3xLMST_B 0x00000011
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| 197 | #define RLN3xLST_B 0x00000012
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| 198 | #define RLN3xLEST_B 0x00000013
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| 199 | #define RLN3xLDFC_B 0x00000014
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| 200 | #define RLN3xLIDB_B 0x00000015
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| 201 | #define RLN3xLCBR_B 0x00000016
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| 202 | #define RLN3xLUDB0_B 0x00000017
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| 203 | #define RLN3xLDBR1_B 0x00000018
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| 204 | #define RLN3xLDBR2_B 0x00000019
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| 205 | #define RLN3xLDBR3_B 0x0000001a
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| 206 | #define RLN3xLDBR4_B 0x0000001b
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| 207 | #define RLN3xLDBR5_B 0x0000001c
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| 208 | #define RLN3xLDBR6_B 0x0000001d
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| 209 | #define RLN3xLDBR7_B 0x0000001e
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| 210 | #define RLN3xLDBR8_B 0x0000001f
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| 211 | #define RLN3xLUOER_B 0x00000020
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| 212 | #define RLN3xLUOR1_B 0x00000021
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| 213 | #define RLN3xLUTDR_H 0x00000024
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| 214 | #define RLN3xLUTDRL_B 0x00000024
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| 215 | #define RLN3xLUTDRH_B 0x00000025
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| 216 | #define RLN3xLURDR_H 0x00000026
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| 217 | #define RLN3xLURDRL_B 0x00000026
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| 218 | #define RLN3xLURDRH_B 0x00000027
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| 219 | #define RLN3xLUWTDR_H 0x00000028
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| 220 | #define RLN3xLUWTDRL_B 0x00000028
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| 221 | #define RLN3xLUWTDRH_B 0x00000029
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| 222 |
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| 223 |
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| 224 | /*
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| 225 | * OSTM
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| 226 | */
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| 227 | #if 0
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| 228 | #define OSTM_IRQ UINT_C(147)
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| 229 |
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| 230 | #define OSTM0_BASE 0xFFD70000
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| 231 | #define OSTM1_BASE 0xFFD70100
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| 232 | #define OSTM2_BASE 0xFFD70200
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| 233 | #define OSTM3_BASE 0xFFD70300
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| 234 | #define OSTM4_BASE 0xFFD70400
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| 235 | #define OSTM5_BASE 0xFFD71000
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| 236 | #define OSTM6_BASE 0xFFD71100
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| 237 | #define OSTM7_BASE 0xFFD71200
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| 238 | #define OSTM8_BASE 0xFFD71300
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| 239 | #define OSTM9_BASE 0xFFD71400
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| 240 |
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| 241 | #define OSTM_CMP_W 0x00
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| 242 | #define OSTM_CNT_W 0x04
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| 243 | #define OSTM_TE 0x10
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| 244 | #define OSTM_TS_B 0x14
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| 245 | #define OSTM_TT_B 0x18
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| 246 | #define OSTM_CTL_B 0x20
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| 247 | #endif
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| 248 | /*
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| 249 | * PLLé¢é£ã®ã¬ã¸ã¹ã¿ã¨å®ç¾©
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| 250 | */
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| 251 | /* Main OSC */
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| 252 | #define MOSCE 0xfff81100
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| 253 | #define MOSCS 0xfff81104
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| 254 | #define MOSCC 0xfff81108
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| 255 | #define MOSCST 0xfff8110c
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| 256 | #define MOSCSTPM 0xfff81118
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| 257 |
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| 258 | /* Sub OSC */
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| 259 | #define SOSCE 0xfff81200
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| 260 | #define SOSCS 0xfff81204
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| 261 | #define SOSCST 0xfff8120C
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| 262 |
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| 263 | /* PLL */
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| 264 | #define PLL0E 0xfff89000
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| 265 | #define PLL0S 0xfff89004
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| 266 | #define PLL0C 0xfff89008
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| 267 | #define PLL1E 0xfff89100
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| 268 | #define PLL1S 0xfff89104
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| 269 | #define PLL1C 0xfff89108
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| 270 |
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| 271 |
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| 272 | #define CKSC_CPUCLKS_CTL 0xfff8a000
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| 273 | #define CKSC_CPUCLKS_ACT 0xfff8a008
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| 274 | #define CKSC_CPUCLKD_CTL 0xfff8a100
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| 275 | #define CKSC_CPUCLKD_ACT 0xfff8a108
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| 276 |
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| 277 | #define CKSC_ILINS_CTL 0xfff8a400
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| 278 | #define CKSC_ILINS_ACT 0xfff8a408
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| 279 | #define CKSC_ILIND_CTL 0xfff8a800
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| 280 | #define CKSC_ILIND_ACT 0xfff8a808
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| 281 |
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| 282 | #define CKSC_ATAUJS_CTL 0xfff82100
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| 283 | #define CKSC_ATAUJS_ACT 0xfff82108
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| 284 | #define CKSC_ATAUJD_CTL 0xfff82200
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| 285 | #define CKSC_ATAUJD_ACT 0xfff82208
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| 286 |
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| 287 | #define MHz(n) ((n) * 1000 * 1000)
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| 288 | #define CLK_MHz(num) (num * 1000 * 1000)
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| 289 |
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| 290 | /* xxxS Register (USE) */
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| 291 | #define CLK_S_STPACK 0x08
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| 292 | #define CLK_S_CLKEN 0x04
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| 293 | #define CLK_S_CLKACT 0x02
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| 294 | #define CLK_S_CLKSTAB 0x01
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| 295 |
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| 296 |
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| 297 | /* Return Parameter */
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| 298 | #define UC_SUCCESS 0
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| 299 | #define UC_ERROR 1
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| 300 | #define UC_INVALIDPARAM 2
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| 301 | #define UC_PROTREGERROR 3
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| 302 | #define UC_CLKSTATUSERR 4
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| 303 | #define UC_CLKNOTENABLE 5
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| 304 | #define UC_CLKNOTACTIVE 6
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| 305 | #define UC_CLKNOTSTAB 7
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| 306 |
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| 307 | /*
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| 308 | * RLIN3
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| 309 | */
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| 310 | #define RLIN30_BASE 0xffce2000
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| 311 | #define RLIN31_BASE 0xffce2040
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| 312 | #define RLIN32_BASE 0xffce2080
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| 313 | #define RLIN33_BASE 0xffce20c0
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| 314 | #define RLIN34_BASE 0xffce2100
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| 315 | #define RLIN35_BASE 0xffce2140
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| 316 |
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| 317 | /*
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| 318 | * INTC
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| 319 | */
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| 320 | #define INTC1_BASE 0xFFFEEA00
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| 321 | #define INTC2_BASE 0xFFFFB000
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| 322 |
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| 323 | #define INTC2_EIC 0x040
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| 324 | #define INTC2_EIBD 0x880
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| 325 | #define INTC2_INTNO_OFFSET 32
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| 326 |
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| 327 | /* intno 㯠unsigned ãæ³å® */
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| 328 | #define EIC_ADDRESS(intno) (intno <= 31)? (INTC1_BASE + (intno * 2)) : (INTC2_BASE + INTC2_EIC + ((intno - INTC2_INTNO_OFFSET) * 2))
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| 329 |
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| 330 | #define INTC_HAS_IBD
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| 331 |
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| 332 | #define IBD_ADDRESS(intno) (intno <= 31)? (0xFFFEEB00 + (intno * 4)) : (0xFFFFB880 + ((intno - INTC2_INTNO_OFFSET) * 4))
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| 333 |
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| 334 | #define TMIN_INTNO UINT_C(0)
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| 335 | #define TMAX_INTNO UINT_C(350)
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| 336 | #define TNUM_INT UINT_C(351)
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| 337 |
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| 338 | /*
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| 339 | * INTNO
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| 340 | */
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| 341 | #define RLIN30_TX_INTNO UINT_C(34)
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| 342 | #define RLIN30_RX_INTNO UINT_C(35)
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| 343 | #define RLIN30_ER_INTNO UINT_C(36)
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| 344 | #define RLIN31_TX_INTNO UINT_C(121)
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| 345 | #define RLIN31_RX_INTNO UINT_C(122)
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| 346 | #define RLIN31_ER_INTNO UINT_C(123)
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| 347 | #define RLIN35_TX_INTNO UINT_C(237)
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| 348 | #define RLIN35_RX_INTNO UINT_C(238)
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| 349 | #define RLIN35_ER_INTNO UINT_C(239)
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| 350 |
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| 351 | #define TAUFJ0I0_INTNO UINT_C(80)
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| 352 | #define TAUFJ0I1_INTNO UINT_C(81)
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| 353 | #define TAUFJ0I2_INTNO UINT_C(82)
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| 354 | #define TAUFJ0I3_INTNO UINT_C(83)
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| 355 | #define TAUFJ1I0_INTNO UINT_C(168)
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| 356 | #define TAUFJ1I1_INTNO UINT_C(169)
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| 357 | #define TAUFJ1I2_INTNO UINT_C(170)
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| 358 | #define TAUFJ1I3_INTNO UINT_C(171)
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| 359 |
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| 360 | /*
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| 361 | * PEéå²è¾¼ã¿ã¬ã¸ã¹ã¿
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| 362 | */
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| 363 | #define IPIR_CH0 0xfffeec80
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| 364 | #define IPIR_CH1 0xfffeec84
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| 365 | #define IPIR_CH2 0xfffeec88
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| 366 | #define IPIR_CH3 0xfffeec8c
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| 367 |
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| 368 | #define IPIC_ADDR(ch) (IPIR_CH0 + ch * 4)
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| 369 |
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| 370 |
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| 371 | #ifndef TOPPERS_MACRO_ONLY
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| 372 |
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| 373 | extern uint32 EnableSubOSC(void);
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| 374 |
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| 375 | extern uint32 EnableMainOSC(uint32 clk_in);
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| 376 |
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| 377 | extern uint32 EnablePLL0(void);
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| 378 |
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| 379 | extern uint32 EnablePLL1(void);
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| 380 |
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| 381 | extern uint32 SetClockSelection(uint32 s_control, uint32 s_status, uint8 regno, uint16 sel,
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| 382 | uint32 d_control, uint32 d_status, uint8 divider);
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| 383 |
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| 384 | extern void raise_ipir(uint8 ch);
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| 385 |
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| 386 | #endif /* TOPPERS_MACRO_ONLY */
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| 387 |
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| 388 |
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| 389 | #include "v850.h"
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| 390 |
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| 391 | #endif /* TOPPERS_RH850_F1H_H */
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