[172] | 1 | /*
|
---|
| 2 | * TOPPERS ATK2
|
---|
| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems
|
---|
| 4 | * Automotive Kernel Version 2
|
---|
| 5 | *
|
---|
| 6 | * Copyright (C) 2012-2014 by Center for Embedded Computing Systems
|
---|
| 7 | * Graduate School of Information Science, Nagoya Univ., JAPAN
|
---|
| 8 | *
|
---|
| 9 | * ä¸è¨èä½æ¨©è
|
---|
| 10 | ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
|
---|
| 11 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
|
---|
| 12 | * å¤ã»åé
|
---|
| 13 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
|
---|
| 14 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
|
---|
| 15 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
|
---|
| 16 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
|
---|
| 17 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
|
---|
| 18 | * ç¨ã§ããå½¢ã§åé
|
---|
| 19 | å¸ããå ´åã«ã¯ï¼åé
|
---|
| 20 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
|
---|
| 21 | * è
|
---|
| 22 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
|
---|
| 23 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
|
---|
| 24 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
|
---|
| 25 | * ç¨ã§ããªãå½¢ã§åé
|
---|
| 26 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
|
---|
| 27 | * ã¨ï¼
|
---|
| 28 | * (a) åé
|
---|
| 29 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
|
---|
| 30 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
|
---|
| 31 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
|
---|
| 32 | * (b) åé
|
---|
| 33 | å¸ã®å½¢æ
|
---|
| 34 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
|
---|
| 35 | * å ±åãããã¨ï¼
|
---|
| 36 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
|
---|
| 37 | * 害ãããï¼ä¸è¨èä½æ¨©è
|
---|
| 38 | ããã³TOPPERSããã¸ã§ã¯ããå
|
---|
| 39 | 責ãããã¨ï¼
|
---|
| 40 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
|
---|
| 41 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
|
---|
| 42 | ããã³TOPPERSããã¸ã§ã¯ãã
|
---|
| 43 | * å
|
---|
| 44 | 責ãããã¨ï¼
|
---|
| 45 | *
|
---|
| 46 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼AUTOSARï¼AUTomotive Open System ARchitectureï¼ä»
|
---|
| 47 | * æ§ã«åºã¥ãã¦ããï¼ä¸è¨ã®è¨±è«¾ã¯ï¼AUTOSARã®ç¥ç財ç£æ¨©ã許諾ãããã®ã§
|
---|
| 48 | * ã¯ãªãï¼AUTOSARã¯ï¼AUTOSARä»æ§ã«åºã¥ããã½ããã¦ã§ã¢ãåç¨ç®çã§å©
|
---|
| 49 | * ç¨ããè
|
---|
| 50 | ã«å¯¾ãã¦ï¼AUTOSARãã¼ããã¼ã«ãªããã¨ãæ±ãã¦ããï¼
|
---|
| 51 | *
|
---|
| 52 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
|
---|
| 53 | ã
|
---|
| 54 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
|
---|
| 55 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
|
---|
| 56 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
|
---|
| 57 | * ã®è²¬ä»»ãè² ããªãï¼
|
---|
| 58 | *
|
---|
| 59 | * $Id: rh850_f1h.c 164 2015-06-03 01:22:29Z t_ishikawa $
|
---|
| 60 | */
|
---|
| 61 | #include "kernel_impl.h"
|
---|
| 62 | #include "rh850_f1h.h"
|
---|
| 63 | #include "Os.h"
|
---|
| 64 | #include "prc_sil.h"
|
---|
| 65 |
|
---|
| 66 | /*******************************************************************************************/
|
---|
| 67 | /* Outline : Write protected register */
|
---|
| 68 | /* Argument : Register address */
|
---|
| 69 | /* Register data */
|
---|
| 70 | /* Register No */
|
---|
| 71 | /* Return value : 0: write success / 1: write error */
|
---|
| 72 | /* Description : Write protected register */
|
---|
| 73 | /* */
|
---|
| 74 | /*******************************************************************************************/
|
---|
| 75 | static uint32
|
---|
| 76 | write_protected_reg(uint32 addr, uint32 data, uint8 regno)
|
---|
| 77 | {
|
---|
| 78 | uint8 wk;
|
---|
| 79 | const uint32 cmd_reg[24] = {
|
---|
| 80 | PROTCMD0,PROTCMD1,CLMA0PCMD,CLMA1PCMD,CLMA2PCMD,PROTCMDCLMA,
|
---|
| 81 | JPPCMD0,PPCMD0,PPCMD1,PPCMD2,PPCMD3,PPCMD8,
|
---|
| 82 | PPCMD9,PPCMD10,PPCMD11,PPCMD12,PPCMD13,PPCMD18,PPCMD19,PPCMD20,PPCMD21,PPCMD22,
|
---|
| 83 | PROTCMDCVM,FLMDPCMD};
|
---|
| 84 | const uint32 s_reg[24] = {
|
---|
| 85 | PROTS0,PROTS1,CLMA0PS,CLMA1PS,CLMA2PS,PROTSCLMA,
|
---|
| 86 | JPPROTS0,PPROTS0,PPROTS1,PPROTS2,PPROTS3,PPROTS8,
|
---|
| 87 | PPROTS9,PPROTS10,PPROTS11,PPROTS12,PPROTS13,PPROTS18,PPROTS19,PPROTS20,PPROTS21,PPROTS22,
|
---|
| 88 | PROTSCVM,FLMDPS};
|
---|
| 89 | SIL_PRE_LOC;
|
---|
| 90 |
|
---|
| 91 | if (regno > 24) {
|
---|
| 92 | return(UC_INVALIDPARAM);
|
---|
| 93 | }
|
---|
| 94 |
|
---|
| 95 | SIL_LOC_INT();
|
---|
| 96 | sil_wrw_mem((void *) cmd_reg[regno], 0xA5);
|
---|
| 97 |
|
---|
| 98 | sil_wrw_mem((void *) addr, data);
|
---|
| 99 | sil_wrw_mem((void *) addr, ~data);
|
---|
| 100 | sil_wrw_mem((void *) addr, data);
|
---|
| 101 | SIL_UNL_INT();
|
---|
| 102 |
|
---|
| 103 | wk = sil_rew_mem((void *) s_reg[regno]);
|
---|
| 104 | wk &= 0x01;
|
---|
| 105 |
|
---|
| 106 | return((wk == 0) ? UC_SUCCESS : UC_PROTREGERROR);
|
---|
| 107 | } /* write_protected_reg */
|
---|
| 108 |
|
---|
| 109 |
|
---|
| 110 | /*******************************************************************************************/
|
---|
| 111 | /* Outline : Sub Oscillator enable */
|
---|
| 112 | /* Argument : - */
|
---|
| 113 | /* Return value : 0: successfly set / 1: set error */
|
---|
| 114 | /* Description : Sub Oscillator register setting */
|
---|
| 115 | /* */
|
---|
| 116 | /*******************************************************************************************/
|
---|
| 117 | uint32
|
---|
| 118 | EnableSubOSC(void)
|
---|
| 119 | {
|
---|
| 120 | /* stop SubOSC */
|
---|
| 121 | if (write_protected_reg(SOSCE, 0x00, PNO_CtrlProt0) != UC_SUCCESS) return(UC_ERROR);
|
---|
| 122 |
|
---|
| 123 | /* Wait inactive */
|
---|
| 124 | while (((sil_rew_mem((void *) SOSCS)) & CLK_S_CLKEN) != 0) {}
|
---|
| 125 |
|
---|
| 126 | /* start SubOSC */
|
---|
| 127 | if (write_protected_reg(SOSCE, 0x01, PNO_CtrlProt0) != UC_SUCCESS) return(UC_ERROR);
|
---|
| 128 |
|
---|
| 129 | /* Wait stabilization */
|
---|
| 130 | while (((sil_rew_mem((void *) SOSCS)) & CLK_S_CLKEN) == 0) {}
|
---|
| 131 |
|
---|
| 132 | return(UC_SUCCESS);
|
---|
| 133 | } /* EnableSubOSC */
|
---|
| 134 |
|
---|
| 135 | /*******************************************************************************************/
|
---|
| 136 | /* Outline : Main Oscillator enable */
|
---|
| 137 | /* Argument : Main Cscillator frequency(Hz) */
|
---|
| 138 | /* Return value : 0: successfly set / 1: set error */
|
---|
| 139 | /* Description : Main Oscillator register setting */
|
---|
| 140 | /* */
|
---|
| 141 | /*******************************************************************************************/
|
---|
| 142 | uint32
|
---|
| 143 | EnableMainOSC(uint32 clk_in)
|
---|
| 144 | {
|
---|
| 145 | uint8 ampsel;
|
---|
| 146 |
|
---|
| 147 | /* stop MainOSC */
|
---|
| 148 | if (write_protected_reg(MOSCE, 0x02, PNO_CtrlProt0) != UC_SUCCESS) return(UC_ERROR);
|
---|
| 149 |
|
---|
| 150 | if (clk_in == CLK_MHz(8)) {
|
---|
| 151 | ampsel = 0x03;
|
---|
| 152 | } else if (CLK_MHz(8) < clk_in && clk_in <= CLK_MHz(16)) {
|
---|
| 153 | ampsel = 0x02;
|
---|
| 154 | } else if (CLK_MHz(16) < clk_in && clk_in <= CLK_MHz(20)) {
|
---|
| 155 | ampsel = 0x01;
|
---|
| 156 | } else if (CLK_MHz(20) < clk_in && clk_in <= CLK_MHz(24)) {
|
---|
| 157 | ampsel = 0x00;
|
---|
| 158 | } else {
|
---|
| 159 | return(UC_INVALIDPARAM);
|
---|
| 160 | }
|
---|
| 161 |
|
---|
| 162 | /* Wait inactive */
|
---|
| 163 | while (((sil_rew_mem((void *) MOSCS)) & CLK_S_CLKEN) != 0) {}
|
---|
| 164 |
|
---|
| 165 | sil_wrw_mem((void *) MOSCC, 0x00 | ampsel); /* Normal stabilization time mode */
|
---|
| 166 | sil_wrw_mem((void *) MOSCST, 0x00FF); /* stabilization time -> Max */
|
---|
| 167 |
|
---|
| 168 | /* MainOSC start */
|
---|
| 169 | if (write_protected_reg(MOSCE, 0x01, PNO_CtrlProt0) != UC_SUCCESS) return(UC_ERROR);
|
---|
| 170 |
|
---|
| 171 | /* Wait stabilization */
|
---|
| 172 | while (((sil_rew_mem((void *) MOSCS)) & CLK_S_CLKEN) == 0) {}
|
---|
| 173 |
|
---|
| 174 | return(UC_SUCCESS);
|
---|
| 175 | } /* EnableMainOSC */
|
---|
| 176 |
|
---|
| 177 | /*******************************************************************************************/
|
---|
| 178 | /* Outline : PLL0 enable */
|
---|
| 179 | /* Argument : none */
|
---|
| 180 | /* Return value : 0: successfly set / 1: set error */
|
---|
| 181 | /* Description : PLL register setting */
|
---|
| 182 | /* */
|
---|
| 183 | /*******************************************************************************************/
|
---|
| 184 | uint32
|
---|
| 185 | EnablePLL0(void)
|
---|
| 186 | {
|
---|
| 187 | /* stop PLL */
|
---|
| 188 | if (write_protected_reg(PLL0E, 0x02, PNO_CtrlProt1) != UC_SUCCESS) return(UC_ERROR);
|
---|
| 189 |
|
---|
| 190 | sil_wrw_mem((void*) PLL0C,
|
---|
| 191 | (PLL0C_FVV<<29) | (PLL0C_MF<<24) | (PLL0C_ADJ<<20) |
|
---|
| 192 | (PLL0C_MD<<14) | (PLL0C_SMD<<13) | (PLL0C_M<<11) |
|
---|
| 193 | (PLL0C_P<<8) | (PLL0C_N));
|
---|
| 194 |
|
---|
| 195 | /* start PLL */
|
---|
| 196 | if (write_protected_reg(PLL0E, 0x01, PNO_CtrlProt1) != UC_SUCCESS) return(UC_ERROR);
|
---|
| 197 |
|
---|
| 198 | /* Wait stabilization */
|
---|
| 199 | while (((sil_rew_mem((void *) PLL0S)) & CLK_S_CLKEN) == 0) {}
|
---|
| 200 |
|
---|
| 201 | return(UC_SUCCESS);
|
---|
| 202 | } /* EnablePLL0 */
|
---|
| 203 |
|
---|
| 204 |
|
---|
| 205 | /*******************************************************************************************/
|
---|
| 206 | /* Outline : PLL1 enable */
|
---|
| 207 | /* Argument : none */
|
---|
| 208 | /* Return value : 0: successfly set / 1: set error */
|
---|
| 209 | /* Description : PLL register setting */
|
---|
| 210 | /* */
|
---|
| 211 | /*******************************************************************************************/
|
---|
| 212 | uint32
|
---|
| 213 | EnablePLL1(void)
|
---|
| 214 | {
|
---|
| 215 | /* stop PLL */
|
---|
| 216 | if (write_protected_reg(PLL1E, 0x02, PNO_CtrlProt1) != UC_SUCCESS) return(UC_ERROR);
|
---|
| 217 |
|
---|
| 218 | sil_wrw_mem((void*) PLL1C, (PLL1C_M<<11) | (PLL1C_PA<<8) | PLL1C_N);
|
---|
| 219 |
|
---|
| 220 | /* start PLL */
|
---|
| 221 | if (write_protected_reg(PLL1E, 0x01, PNO_CtrlProt1) != UC_SUCCESS) return(UC_ERROR);
|
---|
| 222 |
|
---|
| 223 | /* Wait stabilization */
|
---|
| 224 | while (((sil_rew_mem((void *) PLL1S)) & CLK_S_CLKEN) == 0) {}
|
---|
| 225 |
|
---|
| 226 | return(UC_SUCCESS);
|
---|
| 227 | } /* EnablePLL1 */
|
---|
| 228 |
|
---|
| 229 | /*******************************************************************************************/
|
---|
| 230 | /* Outline : Clock switcher setting */
|
---|
| 231 | /* Argument : Selector Control reginster address */
|
---|
| 232 | /* Selector Status reginster address */
|
---|
| 233 | /* Register No */
|
---|
| 234 | /* Select No */
|
---|
| 235 | /* Divider Control reginster address */
|
---|
| 236 | /* Divider Status reginster address */
|
---|
| 237 | /* divider */
|
---|
| 238 | /* Return value : 0: successfly set / 1: set error */
|
---|
| 239 | /* Description : Select clock source of CKSCLK_mn */
|
---|
| 240 | /* */
|
---|
| 241 | /*******************************************************************************************/
|
---|
| 242 | uint32
|
---|
| 243 | SetClockSelection(uint32 s_control, uint32 s_status, uint8 regno, uint16 sel,
|
---|
| 244 | uint32 d_control, uint32 d_status, uint8 divider)
|
---|
| 245 | {
|
---|
| 246 | /* Set Selector */
|
---|
| 247 | if (write_protected_reg(s_control, sel, regno) != UC_SUCCESS) { return(UC_ERROR);}
|
---|
| 248 |
|
---|
| 249 | /* Set Divider */
|
---|
| 250 | if (d_control != 0) {
|
---|
| 251 | if (write_protected_reg(d_control, divider, regno) != UC_SUCCESS) { return(UC_ERROR);}
|
---|
| 252 | }
|
---|
| 253 |
|
---|
| 254 | /* Wait untile enable */
|
---|
| 255 | while (sil_rew_mem((void *) s_control) != sil_rew_mem((void *) s_status)) {};
|
---|
| 256 | if (d_control != 0) {
|
---|
| 257 | while (sil_rew_mem((void *) d_control) != sil_rew_mem((void *) d_status)) {};
|
---|
| 258 | }
|
---|
| 259 |
|
---|
| 260 | return(UC_SUCCESS);
|
---|
| 261 | }
|
---|
| 262 |
|
---|
| 263 | void
|
---|
| 264 | raise_ipir(uint8 ch) {
|
---|
| 265 | if (current_cpuid() == 1) {
|
---|
| 266 | sil_wrw_mem((void*)IPIC_ADDR(ch), 2);
|
---|
| 267 | }
|
---|
| 268 | else {
|
---|
| 269 | sil_wrw_mem((void*)IPIC_ADDR(ch), 1);
|
---|
| 270 | }
|
---|
| 271 | }
|
---|