1 | /*
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2 | * TOPPERS ATK2
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3 | * Toyohashi Open Platform for Embedded Real-Time Systems
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4 | * Automotive Kernel Version 2
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5 | *
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6 | * Copyright (C) 2012-2014 by Center for Embedded Computing Systems
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7 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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8 | * Copyright (C) 2012-2014 by FUJI SOFT INCORPORATED, JAPAN
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9 | * Copyright (C) 2012-2013 by Spansion LLC, USA
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10 | * Copyright (C) 2012-2013 by NEC Communication Systems, Ltd., JAPAN
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11 | * Copyright (C) 2012-2014 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
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12 | * Copyright (C) 2012-2014 by Renesas Electronics Corporation, JAPAN
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13 | * Copyright (C) 2012-2014 by Sunny Giken Inc., JAPAN
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14 | * Copyright (C) 2012-2014 by TOSHIBA CORPORATION, JAPAN
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15 | * Copyright (C) 2012-2014 by Witz Corporation, JAPAN
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16 | *
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17 | * ä¸è¨èä½æ¨©è
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18 | ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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19 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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20 | * å¤ã»åé
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21 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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22 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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23 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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24 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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25 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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26 | * ç¨ã§ããå½¢ã§åé
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27 | å¸ããå ´åã«ã¯ï¼åé
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28 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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29 | * è
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30 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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31 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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32 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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33 | * ç¨ã§ããªãå½¢ã§åé
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34 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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35 | * ã¨ï¼
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36 | * (a) åé
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37 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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38 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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39 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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40 | * (b) åé
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41 | å¸ã®å½¢æ
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42 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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43 | * å ±åãããã¨ï¼
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44 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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45 | * 害ãããï¼ä¸è¨èä½æ¨©è
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46 | ããã³TOPPERSããã¸ã§ã¯ããå
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47 | 責ãããã¨ï¼
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48 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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49 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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50 | ããã³TOPPERSããã¸ã§ã¯ãã
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51 | * å
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52 | 責ãããã¨ï¼
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53 | *
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54 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼AUTOSARï¼AUTomotive Open System ARchitectureï¼ä»
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55 | * æ§ã«åºã¥ãã¦ããï¼ä¸è¨ã®è¨±è«¾ã¯ï¼AUTOSARã®ç¥ç財ç£æ¨©ã許諾ãããã®ã§
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56 | * ã¯ãªãï¼AUTOSARã¯ï¼AUTOSARä»æ§ã«åºã¥ããã½ããã¦ã§ã¢ãåç¨ç®çã§å©
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57 | * ç¨ããè
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58 | ã«å¯¾ãã¦ï¼AUTOSARãã¼ããã¼ã«ãªããã¨ãæ±ãã¦ããï¼
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59 | *
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60 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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61 | ã
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62 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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63 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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64 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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65 | * ã®è²¬ä»»ãè² ããªãï¼
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66 | *
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67 | * $Id: prc_insn.h 187 2015-06-25 03:39:04Z t_ishikawa $
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68 | */
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69 |
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70 | /*
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71 | * ããã»ããµã®ç¹æ®å½ä»¤ã®ã¤ã³ã©ã¤ã³é¢æ°å®ç¾©ï¼V850ç¨ï¼
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72 | */
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73 | #ifndef TOPPERS_PRC_INSN_H
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74 | #define TOPPERS_PRC_INSN_H
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75 |
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76 | #ifndef TOPPERS_MACRO_ONLY
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77 |
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78 | #define V850_MEMORY_CHANGED Asm("" ::: "memory");
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79 | #define SYNCM Asm("syncm");
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80 |
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81 | LOCAL_INLINE uint32
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82 | current_psw(void)
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83 | {
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84 | volatile uint32 psw;
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85 | Asm(" ldsr r0,31 \n" /* Select CPU function grp */
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86 | "\t stsr 5 , %0 \n"
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87 | : "=r" (psw) :);
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88 | return(psw);
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89 | }
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90 |
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91 | LOCAL_INLINE void
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92 | set_psw(uint32 psw)
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93 | {
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94 | Asm(" ldsr r0,31 \n" /* Select CPU function grp */
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95 | "\t ldsr %0 , 5 \n"
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96 | : : "r" (psw));
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97 | return;
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98 | }
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99 |
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100 | LOCAL_INLINE void
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101 | set_psw_wo_fgs(uint32 psw)
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102 | {
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103 | Asm("\t ldsr %0 , 5 \n"
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104 | : : "r" (psw));
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105 | return;
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106 | }
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107 |
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108 | LOCAL_INLINE void
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109 | disable_int(void)
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110 | {
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111 | Asm(" di");
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112 | }
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113 |
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114 | LOCAL_INLINE void
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115 | enable_int(void)
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116 | {
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117 | Asm(" ei");
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118 | }
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119 |
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120 | LOCAL_INLINE void
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121 | set_bit(uint8 bit_offset, uint32 addr)
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122 | {
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123 | uint32 any;
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124 |
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125 | Asm("mov %1 , %0;"
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126 | "set1 %2 , 0[%0]" : "=r" (any) : "i" (addr), "i" (bit_offset));
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127 | }
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128 |
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129 | LOCAL_INLINE void
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130 | clr_bit(uint8 bit_offset, uint32 addr)
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131 | {
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132 | uint32 any;
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133 |
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134 | Asm("mov %1 , %0;"
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135 | "clr1 %2 , 0[%0]" : "=r" (any) : "i" (addr), "i" (bit_offset));
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136 | }
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137 |
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138 | #ifdef __v850e2v3__
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139 |
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140 | #define LDSR_REG(reg, val) {\
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141 | Asm("\tldsr %0, " #reg \
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142 | : : "r"(val) : "memory" ); \
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143 | }
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144 |
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145 | #define STSR_REG(reg, val) {\
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146 | Asm("\tstsr " #reg ", %0" \
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147 | : "=r"(val) : : "memory" ); \
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148 | }
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149 |
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150 |
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151 | #elif defined(__v850e3v5__)
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152 |
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153 | /*
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154 | * V850E3V5ç¨ã®å²è¾¼ã¿ã³ã³ããã¼ã©æä½ã«ã¼ãã³
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155 | */
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156 | LOCAL_INLINE void
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157 | set_pmr(uint16 pmr)
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158 | {
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159 | uint32 psw;
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160 |
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161 | /* PMR must be set in di sate(PSW.ID = 1) */
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162 | psw = current_psw();
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163 | disable_int();
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164 |
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165 | Asm("ldsr %0, sr11, 2" ::"r" (pmr));
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166 |
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167 | set_psw_wo_fgs(psw);
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168 | Asm("syncp");
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169 | }
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170 |
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171 | LOCAL_INLINE uint16
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172 | get_ispr(void)
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173 | {
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174 | uint16 ispr;
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175 | Asm("stsr sr10, %0, 2" : "=r" (ispr) :);
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176 | return(ispr);
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177 | }
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178 |
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179 | LOCAL_INLINE void
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180 | clear_ispr(void)
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181 | {
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182 | uint32 psw;
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183 |
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184 | /* ISPR must be set in di sate(PSW.ID = 1) */
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185 | psw = current_psw();
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186 | disable_int();
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187 |
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188 | Asm("ldsr %0, sr13, 2" ::"r" (1)); /* INTCFG = 1; ISPR ãæ¸ãæãå¯è½ã« */
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189 | Asm("ldsr %0, sr10, 2" ::"r" (0)); /* ISPR = 0 */
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190 | Asm("ldsr %0, sr13, 2" ::"r" (0)); /* INTCFG = 0; ISPR ãæ¸ãæãç¦æ¢ã«(èªåæ´æ°ã«) */
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191 |
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192 | set_psw_wo_fgs(psw);
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193 | Asm("syncp");
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194 | }
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195 |
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196 | LOCAL_INLINE uint32
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197 | current_cpuid(void)
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198 | {
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199 | uint32 htcfg0_val;
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200 | Asm("stsr sr0, %0, 2":"=r"(htcfg0_val):);
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201 | return(((htcfg0_val >> 16) & 0x03));
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202 | }
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203 |
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204 | #define LDSR_REG(reg, sel, val) {\
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205 | uint32 sval = val; \
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206 | Asm("ldsr %0, "#reg", "#sel"\n"\
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207 | ::"r"(sval));\
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208 | }
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209 |
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210 | #define STSR_REG(reg, sel, val) {\
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211 | Asm("stsr "#reg", %0, "#sel"\n"\
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212 | :"=r"(val) );\
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213 | }
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214 |
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215 | #define MPA_WRITE(mpuid, mpla, mpua, mpat) { \
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216 | __LDSR(mpuid*4, 6, mpla); \
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217 | __LDSR(mpuid*4+1, 6, mpua); \
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218 | __LDSR(mpuid*4+2, 6, mpat); \
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219 | }
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220 |
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221 | LOCAL_INLINE void
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222 | set_intbp(uint32 intbp)
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223 | {
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224 | uint32 psw;
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225 |
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226 | /* INTBP must be set in di sate(PSW.ID = 1) */
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227 | psw = current_psw();
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228 | disable_int();
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229 |
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230 | Asm("\t ldsr %0, 4, 1 \n"
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231 | : : "r" (intbp) :);
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232 |
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233 | set_psw_wo_fgs(psw);
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234 |
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235 | return;
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236 | }
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237 |
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238 | #else /* __v850e3v5__ */
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239 | #error please define ether __v850e2v3__ or __v850e3v5__
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240 | #endif /* __v850e2v3__ */
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241 |
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242 | #endif /* TOPPERS_MACRO_ONLY */
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243 |
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244 | #endif /* TOPPERS_PRC_INSN_H */
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