[172] | 1 | $
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| 2 | $ TOPPERS ATK2
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| 3 | $ Toyohashi Open Platform for Embedded Real-Time Systems
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| 4 | $ Automotive Kernel Version 2
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| 5 | $
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| 6 | $ Copyright (C) 2014-2015 by Center for Embedded Computing Systems
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| 7 | $ Graduate School of Information Science, Nagoya Univ., JAPAN
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| 8 | $
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| 9 | $ ä¸è¨èä½æ¨©è
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| 10 | ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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| 11 | $ ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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| 12 | $ å¤ã»åé
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| 13 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 14 | $ (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 15 | $ 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 16 | $ ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 17 | $ (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 18 | $ ç¨ã§ããå½¢ã§åé
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| 19 | å¸ããå ´åã«ã¯ï¼åé
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| 20 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 21 | $ è
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| 22 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 23 | $ ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 24 | $ (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 25 | $ ç¨ã§ããªãå½¢ã§åé
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| 26 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 27 | $ ã¨ï¼
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| 28 | $ (a) åé
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| 29 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 30 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 31 | $ ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 32 | $ (b) åé
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| 33 | å¸ã®å½¢æ
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| 34 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 35 | $ å ±åãããã¨ï¼
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| 36 | $ (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 37 | $ 害ãããï¼ä¸è¨èä½æ¨©è
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| 38 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 39 | 責ãããã¨ï¼
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| 40 | $ ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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| 41 | $ ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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| 42 | ããã³TOPPERSããã¸ã§ã¯ãã
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| 43 | $ å
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| 44 | 責ãããã¨ï¼
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| 45 | $
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| 46 | $ AUTOSARï¼AUTomotive Open System ARchitectureï¼ã¯ï¼AUTOSARä»æ§ã«åºã¥
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| 47 | $ ããã½ããã¦ã§ã¢ãåç¨ç®çã§å©ç¨ããè
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| 48 | ã«å¯¾ãã¦ï¼AUTOSARãã¼ããã¼ã«
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| 49 | $ ãªããã¨ãæ±ãã¦ããï¼
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| 50 | $
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| 51 | $ æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 52 | ã
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| 53 | $ ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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| 54 | $ ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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| 55 | $ ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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| 56 | $ ã®è²¬ä»»ãè² ããªãï¼
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| 57 | $
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| 58 | $ $Id: ldscript.tf 189 2015-06-26 01:54:57Z t_ishikawa $
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| 59 | $
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| 60 |
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| 61 | $ =====================================================================
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| 62 | $ ãªã³ã«ã¹ã¯ãªããï¼ldscript.pyï¼ã®çæ
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| 63 | $ =====================================================================
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| 64 |
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| 65 | $
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| 66 | $ çæãããã¡ã¤ã«ã®æå®
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| 67 | $
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| 68 | $FILE "ldscript.py"$
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| 69 | # This file is generated by ccrh/ldscript.tf$NL$
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| 70 | $NL$
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| 71 | import os.path$NL$
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| 72 | import os$NL$
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| 73 | import shutil$NL$
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| 74 | os.chdir(os.path.dirname(project.Path))$NL$
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| 75 | proj_rel_dir = "../"$NL$
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| 76 | common.Source(proj_rel_dir + "def.py")$NL$
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| 77 | src_abs_path = os.path.abspath(proj_rel_dir + SRCDIR)$NL$
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| 78 | # call common file$NL$
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| 79 | common.Source(src_abs_path + "/arch/ccrh/common.py")$NL$
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| 80 | $NL$
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| 81 |
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| 82 | $
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| 83 | $ å¤æ°ã®åæå
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| 84 | $
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| 85 | $reset_lma = 0$
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| 86 |
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| 87 | $provide_gp = 0$
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| 88 | $data_flg = 0$
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| 89 |
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| 90 | $reg_initdata = REG.REGNAME[STANDARD_ROM]$
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| 91 | $ROMtoRAMsection = "ROMtoRAMsection"$
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| 92 | $AlignSection = "AlignSection"$
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| 93 |
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| 94 | # initialize variables$NL$
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| 95 | $FOREACH regid REG.ORDER_LIST$
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| 96 | $REG.REGNAME[regid]$ = []$NL$
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| 97 | $END$
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| 98 | $ROMtoRAMsection$ = []$NL$
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| 99 | $AlignSection$ = []$NL$
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| 100 | $NL$
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| 101 |
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| 102 | $
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| 103 | $ ãªã³ã¯æå®ã®çæ
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| 104 | $
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| 105 | # preprocess for OsMemorySection$NL$
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| 106 | $ ã¿ã¼ã²ããä¾åã®ã»ã¯ã·ã§ã³è¨è¿°ã®çæ
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| 107 | $IF ISFUNCTION("GENERATE_SECTION_FIRST")$
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| 108 | $GENERATE_SECTION_FIRST()$
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| 109 | $END$
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| 110 |
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| 111 | $FOREACH moid MO_ORDER$
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| 112 | $IF MO.LINKER[moid]$
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| 113 | $ // ã»ã¯ã·ã§ã³ã®éå§è¨è¿°ã®çæ
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| 114 | $IF (MO.SEFLAG[moid] & 0x01) != 0$
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| 115 | $ // ã»ã¯ã·ã§ã³ãé
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| 116 | ç½®ãããªã¼ã¸ã§ã³ã®åå¾
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| 117 | $reg = REG.REGNAME[MO.MEMREG[moid]]$
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| 118 | $IF !OMIT_IDATA && !EQ(MO.ILABEL[moid], "")$
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| 119 | $AlignSection$.append("$MO.SECTION[moid]$.R")$NL$
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| 120 | $END$
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| 121 | $AlignSection$.append("$MO.SECTION[moid]$")$NL$
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| 122 | $END$
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| 123 |
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| 124 | $ // ãªã³ã¯ãããã¡ã¤ã«è¨è¿°ã®çæ
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| 125 | $section_dscr = SECTION_DESCRIPTION(MO.SECTION[moid])$
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| 126 | $IF MO.TYPE[moid] == TOPPERS_ATTSEC$
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| 127 | $IF !OMIT_IDATA && !EQ(MO.ILABEL[moid], "")$
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| 128 | $reg$.append("$MO.SECTION[moid]$.R")$NL$
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| 129 | $reg_initdata$.append("$MO.SECTION[moid]$")$NL$
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| 130 | $ROMtoRAMsection$.append($FORMAT("\'%1%=%1%.R\'", MO.SECTION[moid])$)$NL$
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| 131 | $ELSE$
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| 132 | $reg$.append("$MO.SECTION[moid]$")$NL$
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| 133 | $END$
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| 134 | $ELSE$
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| 135 | $ // ã¦ã¼ã¶ã¹ã¿ãã¯é å
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| 136 | $reg$.append("$MO.SECTION[moid]$")$NL$
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| 137 | $END$
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| 138 |
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| 139 | $ // ã¢ã©ã¤ã³è¨è¿°ã®çæ
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| 140 | $IF (MO.SEFLAG[moid] & 0x20) != 0$
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| 141 | $IF !OMIT_IDATA && !EQ(MO.ILABEL[moid], "")$
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| 142 | $AlignSection$.append("$MO.SECTION[moid]$.R")$NL$
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| 143 | $END$
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| 144 | $AlignSection$.append("$MO.SECTION[moid]$")$NL$
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| 145 | $END$
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| 146 |
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| 147 | $ // ã¡ã¢ãªãªã¼ã¸ã§ã³æ«ã§ã¢ã©ã¤ã³ãããããã®ããã¼ã»ã¯ã·ã§ã³ã®çæ
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| 148 | $IF (MO.SEFLAG[moid] & 0x80) != 0$
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| 149 | $IF !OMIT_IDATA && !EQ(MO.ILABEL[moid], "")$
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| 150 | $AlignSection$.append("$MO.SECTION[moid]$.R")$NL$
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| 151 | $END$
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| 152 | $AlignSection$.append("$MO.SECTION[moid]$")$NL$
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| 153 | $END$
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| 154 |
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| 155 | $preid = moid$
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| 156 | $END$
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| 157 | $END$
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| 158 | $NL$
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| 159 |
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| 160 | # preprocess for OsLinkSection$NL$
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| 161 | $FOREACH lsid RANGE(1, numls)$
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| 162 | $REG.REGNAME[LNKSEC.MEMREG[lsid]]$.append("$LNKSEC.SECTION[lsid]$")$NL$
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| 163 | $END$
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| 164 | $NL$
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| 165 |
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| 166 | sections = ""$NL$
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| 167 | $FOREACH regid REG.ORDER_LIST$
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| 168 | if sections != "":$NL$
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| 169 | $TAB$sections += ","$NL$
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| 170 | sections += ",".join($REG.REGNAME[regid]$)$NL$
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| 171 | sections += $FORMAT("\"/%x\"", +REG.BASE[regid])$$NL$
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| 172 | $END$
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| 173 |
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| 174 | $NL$
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| 175 | wd_abs_path = os.path.abspath('..')$NL$
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| 176 | project.Change(wd_abs_path + r'\atk2-sc3.mtpj')$NL$
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| 177 | project.Close(True)$NL$
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| 178 | inputstr = ReadFile('../atk2-sc3.mtpj')$NL$
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| 179 | print sections$NL$
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| 180 | # build.Link.SectionStartAddress = sections$NL$
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| 181 | inputstr = NewSetItemXml(inputstr, 'LinkOptionStart-0', sections)$NL$
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| 182 | inputstr = ChangeItemXml(inputstr, 'LinkOptionStart-0', sections)$NL$
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| 183 | print $ROMtoRAMsection$$NL$
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| 184 | # build.Link.SectionROMtoRAM = $ROMtoRAMsection$$NL$
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| 185 | inputstr = NewSetItemXml(inputstr, 'LinkOptionRom-0', "\n".join($ROMtoRAMsection$))$NL$
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| 186 | inputstr = ChangeItemXml(inputstr, 'LinkOptionRom-0', "\n".join($ROMtoRAMsection$))$NL$
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| 187 | print sorted(set($AlignSection$), key=$AlignSection$.index)$NL$
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| 188 | # build.Link.SectionAlignment = sorted(set($AlignSection$), key=$AlignSection$.index)$NL$
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| 189 | inputstr = NewSetItemXml(inputstr, 'LinkOptionAlignedSection-0',
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| 190 | "\n".join(sorted(set($AlignSection$), key=$AlignSection$.index)))$NL$
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| 191 | inputstr = ChangeItemXml(inputstr, 'LinkOptionAlignedSection-0',
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| 192 | "\n".join(sorted(set($AlignSection$), key=$AlignSection$.index)))$NL$
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| 193 | WriteFile('../atk2-sc3.mtpj', inputstr)$NL$
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| 194 | $NL$
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| 195 | inputstr = ReadFile('../cfg_pass4/cfg_pass4.mtsp')$NL$
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| 196 | print sections$NL$
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| 197 | # build.Link.SectionStartAddress = sections$NL$
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| 198 | inputstr = NewSetItemXml(inputstr, 'LinkOptionStart-0', sections)$NL$
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| 199 | inputstr = ChangeItemXml(inputstr, 'LinkOptionStart-0', sections)$NL$
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| 200 | print $ROMtoRAMsection$$NL$
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| 201 | # build.Link.SectionROMtoRAM = $ROMtoRAMsection$$NL$
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| 202 | inputstr = NewSetItemXml(inputstr, 'LinkOptionRom-0', "\n".join($ROMtoRAMsection$))$NL$
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| 203 | inputstr = ChangeItemXml(inputstr, 'LinkOptionRom-0', "\n".join($ROMtoRAMsection$))$NL$
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| 204 | print sorted(set($AlignSection$), key=$AlignSection$.index)$NL$
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| 205 | # build.Link.SectionAlignment = sorted(set($AlignSection$), key=$AlignSection$.index)$NL$
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| 206 | inputstr = NewSetItemXml(inputstr, 'LinkOptionAlignedSection-0',
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| 207 | "\n".join(sorted(set($AlignSection$), key=$AlignSection$.index)))$NL$
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| 208 | inputstr = ChangeItemXml(inputstr, 'LinkOptionAlignedSection-0',
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| 209 | "\n".join(sorted(set($AlignSection$), key=$AlignSection$.index)))$NL$
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| 210 | WriteFile('../cfg_pass4/cfg_pass4.mtsp', inputstr)$NL$
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| 211 | $NL$
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| 212 | wd_abs_path = os.path.abspath('..')$NL$
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| 213 | project.Open(wd_abs_path + r'\atk2-sc3.mtpj')$NL$
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| 214 | project.Change(wd_abs_path + r'\cfg\cfg.mtsp')$NL$
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| 215 | $NL$
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| 216 |
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