source: atk1_sh2/trunk/config/sh2-gnu/cq7144a/sys_defs.h@ 4

Last change on this file since 4 was 4, checked in by msugi, 14 years ago

Interface誌2006年8月号添付のTOPPERS/OSEK用SH2をTOPPERS/ATK1に対応させました.多少のバグフィックスも行っています.

File size: 9.2 KB
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1/*
2 * TOPPERS/OSEK Kernel
3 * Toyohashi Open Platform for Embedded Real-Time Systems/
4 * OSEK Kernel
5 *
6 * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
7 * Toyohashi Univ. of Technology, JAPAN
8 * Copyright (C) 2003 by Naoki Saito
9 * Nagoya Municipal Industrial Research Institute, JAPAN
10 * Copyright (C) 2004 by Embedded and Real-Time Systems Laboratory
11 * Graduate School of Information Science, Nagoya Univ., JAPAN
12 * Copyright (C) 2004-2006 by Witz Corporation, JAPAN
13 *
14 * ã‹L’˜ìŒ ŽÒ‚́CˆÈ‰º‚Ì (1)`(4) ‚ÌðŒ‚©CFree Software Foundation
15 * ‚É‚æ‚Á‚ÄŒö•\‚³‚ê‚Ä‚¢‚é GNU General Public License ‚Ì Version 2 ‚É‹L
16 * q‚³‚ê‚Ä‚¢‚éðŒ‚ð–ž‚½‚·ê‡‚ÉŒÀ‚èC–{ƒ\ƒtƒgƒEƒFƒAi–{ƒ\ƒtƒgƒEƒFƒA
17 * ‚ð‰ü•Ï‚µ‚½‚à‚Ì‚ðŠÜ‚ށDˆÈ‰º“¯‚¶j‚ðŽg—pE•¡»E‰ü•ÏEÄ”z•ziˆÈ‰ºC
18 * —˜—p‚ƌĂԁj‚·‚邱‚Ƃ𖳏ž‚Å‹–‘ø‚·‚éD
19 * (1) –{ƒ\ƒtƒgƒEƒFƒA‚ðƒ\[ƒXƒR[ƒh‚ÌŒ`‚Å—˜—p‚·‚éê‡‚ɂ́Cã‹L‚Ì’˜ì
20 * Œ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L‚Ì–³•ÛØ‹K’肪C‚»‚Ì‚Ü‚Ü‚ÌŒ`‚Ń\[
21 * ƒXƒR[ƒh’†‚ÉŠÜ‚Ü‚ê‚Ä‚¢‚邱‚ƁD
22 * (2) –{ƒ\ƒtƒgƒEƒFƒA‚ðCƒ‰ƒCƒuƒ‰ƒŠŒ`Ž®‚ȂǁC‘¼‚̃\ƒtƒgƒEƒFƒAŠJ”­‚ÉŽg
23 * —p‚Å‚«‚éŒ`‚ōĔz•z‚·‚éê‡‚ɂ́CÄ”z•z‚É”º‚¤ƒhƒLƒ…
24ƒƒ“ƒgi—˜—p
25 * ŽÒƒ}ƒjƒ…
26ƒAƒ‹‚Ȃǁj‚ɁCã‹L‚Ì’˜ìŒ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L
27 * ‚Ì–³•ÛØ‹K’è‚ðŒfÚ‚·‚邱‚ƁD
28 * (3) –{ƒ\ƒtƒgƒEƒFƒA‚ðC‹@Ší‚É‘g‚ݍž‚ނȂǁC‘¼‚̃\ƒtƒgƒEƒFƒAŠJ”­‚ÉŽg
29 * —p‚Å‚«‚È‚¢Œ`‚ōĔz•z‚·‚éê‡‚ɂ́CŽŸ‚Ì‚¢‚¸‚ê‚©‚ÌðŒ‚ð–ž‚½‚·‚±
30 * ‚ƁD
31 * (a) Ä”z•z‚É”º‚¤ƒhƒLƒ…
32ƒƒ“ƒgi—˜—pŽÒƒ}ƒjƒ…
33ƒAƒ‹‚Ȃǁj‚ɁCã‹L‚Ì’˜
34 * ìŒ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L‚Ì–³•ÛØ‹K’è‚ðŒfÚ‚·‚邱‚ƁD
35 * (b) Ä”z•z‚ÌŒ`‘Ô‚ðC•Ê‚É’è‚ß‚é•û–@‚É‚æ‚Á‚āCTOPPERSƒvƒƒWƒFƒNƒg‚É
36 * •ñ‚·‚邱‚ƁD
37 * (4) –{ƒ\ƒtƒgƒEƒFƒA‚Ì—˜—p‚É‚æ‚è’¼Ú“I‚Ü‚½‚͊ԐړI‚ɐ¶‚¶‚é‚¢‚©‚Ȃ鑹
38 * ŠQ‚©‚ç‚àCã‹L’˜ìŒ ŽÒ‚¨‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚ð–Ɛӂ·‚邱‚ƁD
39 *
40 * –{ƒ\ƒtƒgƒEƒFƒA‚́C–³•ÛØ‚Å’ñ‹Ÿ‚³‚ê‚Ä‚¢‚é‚à‚Ì‚Å‚ ‚éDã‹L’˜ìŒ ŽÒ‚¨
41 * ‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚́C–{ƒ\ƒtƒgƒEƒFƒA‚ÉŠÖ‚µ‚āC‚»‚Ì“K—p‰Â”\«‚à
42 * ŠÜ‚߂āC‚¢‚©‚È‚é•ÛØ‚às‚í‚È‚¢D‚Ü‚½C–{ƒ\ƒtƒgƒEƒFƒA‚Ì—˜—p‚É‚æ‚è’¼
43 * Ú“I‚Ü‚½‚͊ԐړI‚ɐ¶‚¶‚½‚¢‚©‚Ȃ鑹ŠQ‚ÉŠÖ‚µ‚Ä‚àC‚»‚̐ӔC‚𕉂í‚È‚¢D
44 *
45 */
46
47/*
48 * ƒ^[ƒQƒbƒgƒVƒXƒeƒ€‚Ɉˑ¶‚·‚é’è‹`iCQ7144A—pj
49 */
50
51#ifndef _SYS_DEFS_H_
52#define _SYS_DEFS_H_
53
54/*
55 * ƒXƒ^ƒbƒNæ“ª”Ô’n
56 */
57
58#define STACK_TOP (0xFFFFFFFC)
59
60/*
61 * Š„‚荞‚݃xƒNƒ^‚̐擪”Ô’n
62 */
63
64#define VECTOR_TOP (0x0)
65
66/*
67 * ƒ^[ƒQƒbƒgŽ¯•Êƒ}ƒNƒ(ƒVƒXƒeƒ€–¼‚Ì’è‹`)
68 */
69#define INTERFACE
70
71/*
72 * ‹N“®ƒƒbƒZ[ƒW‚̃^[ƒQƒbƒgƒVƒXƒeƒ€–¼
73 */
74#define TARGET_NAME "SH2/CQ7144A"
75
76/*
77 * ŠO•”RAM‚ðŽg—p‚·‚é‚©‚Ì’è‹`
78 */
79
80#define USE_SRAM
81
82/*
83 * Š„ž‚ݔԍ†‚Ì’è‹`
84 */
85
86#define INT_ILGL_OP (4) /* 4 +0x0010 ˆê”Ê•s“––½—ß */
87 /* 5 +0x0014 ƒVƒXƒeƒ€—\–ñ */
88#define INT_SLOT_ILGL (6) /* 6 +0x0018 ƒXƒƒbƒg•s“––½—ß */
89 /* 7 +0x001C ƒVƒXƒeƒ€—\–ñ */
90 /* 8 +0x0020 ƒVƒXƒeƒ€—\–ñ */
91#define INT_AUD_ADRERR (9) /* 9 +0x0024 CPU/AUD ADDRESS ERROR */
92#define INT_DMAC_ADRERR (10) /* 10 +0x0028 DMAC/DTC ADDRESS ERROR */
93#define INT_NMI (11) /* 11 +0x002C NMI */
94#define INT_USRBRK (12) /* 12 +0x0030 ƒ†[ƒUƒuƒŒ[ƒN */
95 /* 13 +0x0034 ƒVƒXƒeƒ€—\–ñ */
96#define INT_HUDI (14) /* 14 +0x0038 H-UDI*/
97 /* 15 +0x003C ƒVƒXƒeƒ€—\–ñ */
98 /* F */
99 /* 31 +0x007C ƒVƒXƒeƒ€—\–ñ */
100#define INT_TRAP20 (32) /* 32 +0x0080 ƒgƒ‰ƒbƒv–½—ß */
101#define INT_TRAP21 (33) /* 33 +0x0084 ƒgƒ‰ƒbƒv–½—ß */
102#define INT_TRAP22 (34) /* 34 +0x0088 ƒgƒ‰ƒbƒv–½—ß */
103#define INT_TRAP23 (35) /* 35 +0x008C ƒgƒ‰ƒbƒv–½—ß */
104#define INT_TRAP24 (36) /* 36 +0x0090 ƒgƒ‰ƒbƒv–½—ß */
105#define INT_TRAP25 (37) /* 37 +0x0094 ƒgƒ‰ƒbƒv–½—ß */
106#define INT_TRAP26 (38) /* 38 +0x0098 ƒgƒ‰ƒbƒv–½—ß */
107#define INT_TRAP27 (39) /* 39 +0x009C ƒgƒ‰ƒbƒv–½—ß */
108#define INT_TRAP28 (40) /* 40 +0x00A0 ƒgƒ‰ƒbƒv–½—ß */
109#define INT_TRAP29 (41) /* 41 +0x00A4 ƒgƒ‰ƒbƒv–½—ß */
110#define INT_TRAP30 (42) /* 42 +0x00A8 ƒgƒ‰ƒbƒv–½—ß */
111#define INT_TRAP31 (43) /* 43 +0x00AC ƒgƒ‰ƒbƒv–½—ß */
112#define INT_TRAP32 (44) /* 44 +0x00B0 ƒgƒ‰ƒbƒv–½—ß */
113#define INT_TRAP33 (45) /* 45 +0x00B4 ƒgƒ‰ƒbƒv–½—ß */
114#define INT_TRAP34 (46) /* 46 +0x00B8 ƒgƒ‰ƒbƒv–½—ß */
115#define INT_TRAP35 (47) /* 47 +0x00BC ƒgƒ‰ƒbƒv–½—ß */
116#define INT_TRAP36 (48) /* 48 +0x00C0 ƒgƒ‰ƒbƒv–½—ß */
117#define INT_TRAP37 (49) /* 49 +0x00C4 ƒgƒ‰ƒbƒv–½—ß */
118#define INT_TRAP38 (50) /* 50 +0x00C8 ƒgƒ‰ƒbƒv–½—ß */
119#define INT_TRAP39 (51) /* 51 +0x00CC ƒgƒ‰ƒbƒv–½—ß */
120#define INT_TRAP40 (52) /* 52 +0x00D0 ƒgƒ‰ƒbƒv–½—ß */
121#define INT_TRAP41 (53) /* 53 +0x00D4 ƒgƒ‰ƒbƒv–½—ß */
122#define INT_TRAP42 (54) /* 54 +0x00D8 ƒgƒ‰ƒbƒv–½—ß */
123#define INT_TRAP43 (55) /* 55 +0x00DC ƒgƒ‰ƒbƒv–½—ß */
124#define INT_TRAP44 (56) /* 56 +0x00E0 ƒgƒ‰ƒbƒv–½—ß */
125#define INT_TRAP45 (57) /* 57 +0x00E4 ƒgƒ‰ƒbƒv–½—ß */
126#define INT_TRAP46 (58) /* 58 +0x00E8 ƒgƒ‰ƒbƒv–½—ß */
127#define INT_TRAP47 (59) /* 59 +0x00EC ƒgƒ‰ƒbƒv–½—ß */
128#define INT_TRAP48 (60) /* 60 +0x00F0 ƒgƒ‰ƒbƒv–½—ß */
129#define INT_TRAP49 (61) /* 61 +0x00F4 ƒgƒ‰ƒbƒv–½—ß */
130#define INT_TRAP50 (62) /* 62 +0x00F8 ƒgƒ‰ƒbƒv–½—ß */
131#define INT_TRAP51 (63) /* 63 +0x00FC ƒgƒ‰ƒbƒv–½—ß */
132#define INT_IRQ0 (64) /* 64 +0x0100 IPRA15-IPRA12 IRQ0*/
133#define INT_IRQ1 (65) /* 65 +0x0104 IPRA11-IPRA8 IRQ1*/
134#define INT_IRQ2 (66) /* 66 +0x0108 IPRA7-IPRA4 IRQ2*/
135#define INT_IRQ3 (67) /* 67 +0x010C IPRA3-IPRA0 IRQ3*/
136#define INT_IRQ4 (68) /* 68 +0x0110 IPRB15-IPRB12 IRQ4*/
137#define INT_IRQ5 (69) /* 69 +0x0114 IPRB11-IPRB8 IRQ5*/
138#define INT_IRQ6 (70) /* 70 +0x0118 IPRB7-IPRB4 IRQ6*/
139#define INT_IRQ7 (71) /* 71 +0x011C IPRB3-IPRB0 IRQ7*/
140#define INT_DEI0 (72) /* 72 +0x0120 IPRC15-IPRC12 DEI0 */
141#define INT_DEI1 (76) /* 76 +0x0130 IPRC11-IPRC8 DEI1 */
142#define INT_DEI2 (80) /* 80 +0x0140 IPRC7-IPRC4 DEI2 */
143#define INT_DEI3 (84) /* 84 +0x0150 IPRC3-IPRC0 DEI3 */
144#define INT_TGIA0 (88) /* 88 +0x0160 IPRD15-IPRD12 TGIA_0 */
145#define INT_TGIB0 (89) /* 89 +0x0164 IPRD15-IPRD12 TGIB_0 */
146#define INT_TGIC0 (90) /* 90 +0x0168 IPRD15-IPRD12 TGIC_0 */
147#define INT_TGID0 (91) /* 91 +0x016C IPRD15-IPRD12 TGID_0 */
148#define INT_TCIV0 (92) /* 92 +0x0170 IPRD11-IPRD8 TCIV_0 */
149#define INT_TGIA1 (96) /* 96 +0x0180 IPRD7-IPRD4 TGIA_1 */
150#define INT_TGIB1 (97) /* 97 +0x0184 IPRD7-IPRD4 TGIB_1 */
151#define INT_TCIV1 (100) /* 100 +0x0190 IPRD3-IPRD0 TCIV_1 */
152#define INT_TCIU1 (101) /* 101 +0x0194 IPRD3-IPRD0 TCIU_1 */
153#define INT_TGIA2 (104) /* 104 +0x01A0 IPRE15-IPRE12 TGIA_2 */
154#define INT_TGIB2 (105) /* 105 +0x01A4 IPRE15-IPRE12 TGIB_2 */
155#define INT_TCIV2 (108) /* 108 +0x01B0 IPRE11-IPRE8 TCIV_2 */
156#define INT_TCIU2 (109) /* 109 +0x01B4 IPRE11-IPRE8 TCIU_2 */
157#define INT_TGIA3 (112) /* 112 +0x01C0 IPRE7-IPRE4 TGIA_3 */
158#define INT_TGIB3 (113) /* 113 +0x01C4 IPRE7-IPRE4 TGIB_3 */
159#define INT_TGIC3 (114) /* 114 +0x01C8 IPRE7-IPRE4 TGIC_3 */
160#define INT_TGID3 (115) /* 115 +0x01CC IPRE7-IPRE4 TGID_3 */
161#define INT_TCIV3 (116) /* 116 +0x01D0 IPRE3-IPRE0 TCIV_3 */
162#define INT_TGIA4 (120) /* 120 +0x01E0 IPRF15-IPRF12 TGIA_4 */
163#define INT_TGIB4 (121) /* 121 +0x01E4 IPRF15-IPRF12 TGIB_4 */
164#define INT_TGIC4 (122) /* 122 +0x01E8 IPRF15-IPRF12 TGIC_4 */
165#define INT_TGID4 (123) /* 123 +0x01EC IPRF15-IPRF12 TGID_4 */
166#define INT_TCIV4 (124) /* 124 +0x01F0 IPRF11-IPRF8 TCIV_4 */
167#define INT_ERI0 (128) /* 128 +0x0200 IPRF7-IPRF4 ERI_0 */
168#define INT_RXI0 (129) /* 129 +0x0204 IPRF7-IPRF4 RXI_0 */
169#define INT_TXI0 (130) /* 130 +0x0208 IPRF7-IPRF4 TXI_0 */
170#define INT_TEI0 (131) /* 131 +0x020C IPRF7-IPRF4 TEI_0 */
171#define INT_ERI1 (132) /* 132 +0x0210 IPRF3-IPRF0 ERI_1 */
172#define INT_RXI1 (133) /* 133 +0x0214 IPRF3-IPRF0 RXI_1 */
173#define INT_TXI1 (134) /* 134 +0x0218 IPRF3-IPRF0 TXI_1 */
174#define INT_TEI1 (135) /* 135 +0x021C IPRF3-IPRF0 TEI_1 */
175#define INT_ADI0 (136) /* 136 +0x0220 IPRG15-IPRG12 ADI0 */
176#define INT_ADI1 (137) /* 137 +0x0224 IPRG15-IPRG12 ADI1 */
177#define INT_SWDTEND (140) /* 140 +0x0230 IPRG11-IPRG8 SWDTEND */
178#define CMI0 (144) /* 144 +0x0240 IPRG7-IPRG4 CMI0 */
179#define CMI1 (148) /* 148 +0x0250 IPRG3-IPRG0 CMI1 */
180#define ITI (152) /* 152 +0x0260 IPRH15-IPRH12 ITI */
181 /* 153 +0x0264 ƒVƒXƒeƒ€—\–ñ */
182 /* 154 +0x0268 ƒVƒXƒeƒ€—\–ñ */
183 /* 155 +0x026C ƒVƒXƒeƒ€—\–ñ */
184#define MTUOEI /* 156 +0x0270 IPRH11-IPRH8 MTUOEI */
185 /* 160 +0x0280 ƒVƒXƒeƒ€—\–ñ */
186 /* F */
187 /* 167 +0x029C ƒVƒXƒeƒ€—\–ñ */
188#define INT_ERI2 (128) /* 168 +0x02A0 IPRI15-IPRI12 ERI_2 */
189#define INT_RXI2 (129) /* 169 +0x02A4 IPRI15-IPRI12 RXI_2 */
190#define INT_TXI2 (130) /* 170 +0x02A8 IPRI15-IPRI12 TXI_2 */
191#define INT_TEI2 (131) /* 171 +0x02AC IPRI15-IPRI12 TEI_2 */
192#define INT_ERI3 (128) /* 172 +0x02B0 IPRI11-IPRI8 ERI_3 */
193#define INT_RXI3 (129) /* 173 +0x02B4 IPRI11-IPRI8 RXI_3 */
194#define INT_TXI3 (130) /* 174 +0x02B8 IPRI11-IPRI8 TXI_3 */
195#define INT_TEI3 (131) /* 175 +0x02BC IPRI11-IPRI8 TEI_3 */
196 /* 176 +0x02C0 ƒVƒXƒeƒ€—\–ñ */
197 /* F */
198 /* 191 +0x02FC ƒVƒXƒeƒ€—\–ñ */
199
200#endif /* _SYS_DEFS_H_ */
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