source: asp_wio_terminal/trunk/target/samd51_gcc/lib/port.h@ 460

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1/**
2 * \brief Component description for PORT
3 *
4 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
5 *
6 * Subject to your compliance with these terms, you may use Microchip software and any derivatives
7 * exclusively with Microchip products. It is your responsibility to comply with third party license
8 * terms applicable to your use of third party software (including open source software) that may
9 * accompany Microchip software.
10 *
11 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
12 * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
13 * FITNESS FOR A PARTICULAR PURPOSE.
14 *
15 * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
16 * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
17 * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
18 * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
19 * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
20 *
21 */
22
23/* file generated from device description version 2020-03-12T17:26:00Z */
24#ifndef _SAMD51_PORT_COMPONENT_H_
25#define _SAMD51_PORT_COMPONENT_H_
26
27/* ************************************************************************** */
28/* SOFTWARE API DEFINITION FOR PORT */
29/* ************************************************************************** */
30
31/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) Data Direction -------- */
32#define PORT_DIR_RESETVALUE _U_(0x00) /**< (PORT_DIR) Data Direction Reset Value */
33
34#define PORT_DIR_DIR_Pos _U_(0) /**< (PORT_DIR) Port Data Direction Position */
35#define PORT_DIR_DIR_Msk (_U_(0xFFFFFFFF) << PORT_DIR_DIR_Pos) /**< (PORT_DIR) Port Data Direction Mask */
36#define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
37#define PORT_DIR_Msk _U_(0xFFFFFFFF) /**< (PORT_DIR) Register Mask */
38
39
40/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) Data Direction Clear -------- */
41#define PORT_DIRCLR_RESETVALUE _U_(0x00) /**< (PORT_DIRCLR) Data Direction Clear Reset Value */
42
43#define PORT_DIRCLR_DIRCLR_Pos _U_(0) /**< (PORT_DIRCLR) Port Data Direction Clear Position */
44#define PORT_DIRCLR_DIRCLR_Msk (_U_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos) /**< (PORT_DIRCLR) Port Data Direction Clear Mask */
45#define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
46#define PORT_DIRCLR_Msk _U_(0xFFFFFFFF) /**< (PORT_DIRCLR) Register Mask */
47
48
49/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) Data Direction Set -------- */
50#define PORT_DIRSET_RESETVALUE _U_(0x00) /**< (PORT_DIRSET) Data Direction Set Reset Value */
51
52#define PORT_DIRSET_DIRSET_Pos _U_(0) /**< (PORT_DIRSET) Port Data Direction Set Position */
53#define PORT_DIRSET_DIRSET_Msk (_U_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos) /**< (PORT_DIRSET) Port Data Direction Set Mask */
54#define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
55#define PORT_DIRSET_Msk _U_(0xFFFFFFFF) /**< (PORT_DIRSET) Register Mask */
56
57
58/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) Data Direction Toggle -------- */
59#define PORT_DIRTGL_RESETVALUE _U_(0x00) /**< (PORT_DIRTGL) Data Direction Toggle Reset Value */
60
61#define PORT_DIRTGL_DIRTGL_Pos _U_(0) /**< (PORT_DIRTGL) Port Data Direction Toggle Position */
62#define PORT_DIRTGL_DIRTGL_Msk (_U_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos) /**< (PORT_DIRTGL) Port Data Direction Toggle Mask */
63#define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
64#define PORT_DIRTGL_Msk _U_(0xFFFFFFFF) /**< (PORT_DIRTGL) Register Mask */
65
66
67/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) Data Output Value -------- */
68#define PORT_OUT_RESETVALUE _U_(0x00) /**< (PORT_OUT) Data Output Value Reset Value */
69
70#define PORT_OUT_OUT_Pos _U_(0) /**< (PORT_OUT) PORT Data Output Value Position */
71#define PORT_OUT_OUT_Msk (_U_(0xFFFFFFFF) << PORT_OUT_OUT_Pos) /**< (PORT_OUT) PORT Data Output Value Mask */
72#define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
73#define PORT_OUT_Msk _U_(0xFFFFFFFF) /**< (PORT_OUT) Register Mask */
74
75
76/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) Data Output Value Clear -------- */
77#define PORT_OUTCLR_RESETVALUE _U_(0x00) /**< (PORT_OUTCLR) Data Output Value Clear Reset Value */
78
79#define PORT_OUTCLR_OUTCLR_Pos _U_(0) /**< (PORT_OUTCLR) PORT Data Output Value Clear Position */
80#define PORT_OUTCLR_OUTCLR_Msk (_U_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos) /**< (PORT_OUTCLR) PORT Data Output Value Clear Mask */
81#define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
82#define PORT_OUTCLR_Msk _U_(0xFFFFFFFF) /**< (PORT_OUTCLR) Register Mask */
83
84
85/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) Data Output Value Set -------- */
86#define PORT_OUTSET_RESETVALUE _U_(0x00) /**< (PORT_OUTSET) Data Output Value Set Reset Value */
87
88#define PORT_OUTSET_OUTSET_Pos _U_(0) /**< (PORT_OUTSET) PORT Data Output Value Set Position */
89#define PORT_OUTSET_OUTSET_Msk (_U_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos) /**< (PORT_OUTSET) PORT Data Output Value Set Mask */
90#define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
91#define PORT_OUTSET_Msk _U_(0xFFFFFFFF) /**< (PORT_OUTSET) Register Mask */
92
93
94/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) Data Output Value Toggle -------- */
95#define PORT_OUTTGL_RESETVALUE _U_(0x00) /**< (PORT_OUTTGL) Data Output Value Toggle Reset Value */
96
97#define PORT_OUTTGL_OUTTGL_Pos _U_(0) /**< (PORT_OUTTGL) PORT Data Output Value Toggle Position */
98#define PORT_OUTTGL_OUTTGL_Msk (_U_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos) /**< (PORT_OUTTGL) PORT Data Output Value Toggle Mask */
99#define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
100#define PORT_OUTTGL_Msk _U_(0xFFFFFFFF) /**< (PORT_OUTTGL) Register Mask */
101
102
103/* -------- PORT_IN : (PORT Offset: 0x20) ( R/ 32) Data Input Value -------- */
104#define PORT_IN_RESETVALUE _U_(0x00) /**< (PORT_IN) Data Input Value Reset Value */
105
106#define PORT_IN_IN_Pos _U_(0) /**< (PORT_IN) PORT Data Input Value Position */
107#define PORT_IN_IN_Msk (_U_(0xFFFFFFFF) << PORT_IN_IN_Pos) /**< (PORT_IN) PORT Data Input Value Mask */
108#define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
109#define PORT_IN_Msk _U_(0xFFFFFFFF) /**< (PORT_IN) Register Mask */
110
111
112/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) Control -------- */
113#define PORT_CTRL_RESETVALUE _U_(0x00) /**< (PORT_CTRL) Control Reset Value */
114
115#define PORT_CTRL_SAMPLING_Pos _U_(0) /**< (PORT_CTRL) Input Sampling Mode Position */
116#define PORT_CTRL_SAMPLING_Msk (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos) /**< (PORT_CTRL) Input Sampling Mode Mask */
117#define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
118#define PORT_CTRL_Msk _U_(0xFFFFFFFF) /**< (PORT_CTRL) Register Mask */
119
120
121/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) Write Configuration -------- */
122#define PORT_WRCONFIG_RESETVALUE _U_(0x00) /**< (PORT_WRCONFIG) Write Configuration Reset Value */
123
124#define PORT_WRCONFIG_PINMASK_Pos _U_(0) /**< (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration Position */
125#define PORT_WRCONFIG_PINMASK_Msk (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos) /**< (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration Mask */
126#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
127#define PORT_WRCONFIG_PMUXEN_Pos _U_(16) /**< (PORT_WRCONFIG) Peripheral Multiplexer Enable Position */
128#define PORT_WRCONFIG_PMUXEN_Msk (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos) /**< (PORT_WRCONFIG) Peripheral Multiplexer Enable Mask */
129#define PORT_WRCONFIG_PMUXEN(value) (PORT_WRCONFIG_PMUXEN_Msk & ((value) << PORT_WRCONFIG_PMUXEN_Pos))
130#define PORT_WRCONFIG_INEN_Pos _U_(17) /**< (PORT_WRCONFIG) Input Enable Position */
131#define PORT_WRCONFIG_INEN_Msk (_U_(0x1) << PORT_WRCONFIG_INEN_Pos) /**< (PORT_WRCONFIG) Input Enable Mask */
132#define PORT_WRCONFIG_INEN(value) (PORT_WRCONFIG_INEN_Msk & ((value) << PORT_WRCONFIG_INEN_Pos))
133#define PORT_WRCONFIG_PULLEN_Pos _U_(18) /**< (PORT_WRCONFIG) Pull Enable Position */
134#define PORT_WRCONFIG_PULLEN_Msk (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos) /**< (PORT_WRCONFIG) Pull Enable Mask */
135#define PORT_WRCONFIG_PULLEN(value) (PORT_WRCONFIG_PULLEN_Msk & ((value) << PORT_WRCONFIG_PULLEN_Pos))
136#define PORT_WRCONFIG_DRVSTR_Pos _U_(22) /**< (PORT_WRCONFIG) Output Driver Strength Selection Position */
137#define PORT_WRCONFIG_DRVSTR_Msk (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos) /**< (PORT_WRCONFIG) Output Driver Strength Selection Mask */
138#define PORT_WRCONFIG_DRVSTR(value) (PORT_WRCONFIG_DRVSTR_Msk & ((value) << PORT_WRCONFIG_DRVSTR_Pos))
139#define PORT_WRCONFIG_PMUX_Pos _U_(24) /**< (PORT_WRCONFIG) Peripheral Multiplexing Position */
140#define PORT_WRCONFIG_PMUX_Msk (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos) /**< (PORT_WRCONFIG) Peripheral Multiplexing Mask */
141#define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
142#define PORT_WRCONFIG_WRPMUX_Pos _U_(28) /**< (PORT_WRCONFIG) Write PMUX Position */
143#define PORT_WRCONFIG_WRPMUX_Msk (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos) /**< (PORT_WRCONFIG) Write PMUX Mask */
144#define PORT_WRCONFIG_WRPMUX(value) (PORT_WRCONFIG_WRPMUX_Msk & ((value) << PORT_WRCONFIG_WRPMUX_Pos))
145#define PORT_WRCONFIG_WRPINCFG_Pos _U_(30) /**< (PORT_WRCONFIG) Write PINCFG Position */
146#define PORT_WRCONFIG_WRPINCFG_Msk (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos) /**< (PORT_WRCONFIG) Write PINCFG Mask */
147#define PORT_WRCONFIG_WRPINCFG(value) (PORT_WRCONFIG_WRPINCFG_Msk & ((value) << PORT_WRCONFIG_WRPINCFG_Pos))
148#define PORT_WRCONFIG_HWSEL_Pos _U_(31) /**< (PORT_WRCONFIG) Half-Word Select Position */
149#define PORT_WRCONFIG_HWSEL_Msk (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos) /**< (PORT_WRCONFIG) Half-Word Select Mask */
150#define PORT_WRCONFIG_HWSEL(value) (PORT_WRCONFIG_HWSEL_Msk & ((value) << PORT_WRCONFIG_HWSEL_Pos))
151#define PORT_WRCONFIG_Msk _U_(0xDF47FFFF) /**< (PORT_WRCONFIG) Register Mask */
152
153
154/* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) Event Input Control -------- */
155#define PORT_EVCTRL_RESETVALUE _U_(0x00) /**< (PORT_EVCTRL) Event Input Control Reset Value */
156
157#define PORT_EVCTRL_PID0_Pos _U_(0) /**< (PORT_EVCTRL) PORT Event Pin Identifier 0 Position */
158#define PORT_EVCTRL_PID0_Msk (_U_(0x1F) << PORT_EVCTRL_PID0_Pos) /**< (PORT_EVCTRL) PORT Event Pin Identifier 0 Mask */
159#define PORT_EVCTRL_PID0(value) (PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos))
160#define PORT_EVCTRL_EVACT0_Pos _U_(5) /**< (PORT_EVCTRL) PORT Event Action 0 Position */
161#define PORT_EVCTRL_EVACT0_Msk (_U_(0x3) << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) PORT Event Action 0 Mask */
162#define PORT_EVCTRL_EVACT0(value) (PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos))
163#define PORT_EVCTRL_EVACT0_OUT_Val _U_(0x0) /**< (PORT_EVCTRL) Event output to pin */
164#define PORT_EVCTRL_EVACT0_SET_Val _U_(0x1) /**< (PORT_EVCTRL) Set output register of pin on event */
165#define PORT_EVCTRL_EVACT0_CLR_Val _U_(0x2) /**< (PORT_EVCTRL) Clear output register of pin on event */
166#define PORT_EVCTRL_EVACT0_TGL_Val _U_(0x3) /**< (PORT_EVCTRL) Toggle output register of pin on event */
167#define PORT_EVCTRL_EVACT0_OUT (PORT_EVCTRL_EVACT0_OUT_Val << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) Event output to pin Position */
168#define PORT_EVCTRL_EVACT0_SET (PORT_EVCTRL_EVACT0_SET_Val << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) Set output register of pin on event Position */
169#define PORT_EVCTRL_EVACT0_CLR (PORT_EVCTRL_EVACT0_CLR_Val << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) Clear output register of pin on event Position */
170#define PORT_EVCTRL_EVACT0_TGL (PORT_EVCTRL_EVACT0_TGL_Val << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) Toggle output register of pin on event Position */
171#define PORT_EVCTRL_PORTEI0_Pos _U_(7) /**< (PORT_EVCTRL) PORT Event Input Enable 0 Position */
172#define PORT_EVCTRL_PORTEI0_Msk (_U_(0x1) << PORT_EVCTRL_PORTEI0_Pos) /**< (PORT_EVCTRL) PORT Event Input Enable 0 Mask */
173#define PORT_EVCTRL_PORTEI0(value) (PORT_EVCTRL_PORTEI0_Msk & ((value) << PORT_EVCTRL_PORTEI0_Pos))
174#define PORT_EVCTRL_PID1_Pos _U_(8) /**< (PORT_EVCTRL) PORT Event Pin Identifier 1 Position */
175#define PORT_EVCTRL_PID1_Msk (_U_(0x1F) << PORT_EVCTRL_PID1_Pos) /**< (PORT_EVCTRL) PORT Event Pin Identifier 1 Mask */
176#define PORT_EVCTRL_PID1(value) (PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos))
177#define PORT_EVCTRL_EVACT1_Pos _U_(13) /**< (PORT_EVCTRL) PORT Event Action 1 Position */
178#define PORT_EVCTRL_EVACT1_Msk (_U_(0x3) << PORT_EVCTRL_EVACT1_Pos) /**< (PORT_EVCTRL) PORT Event Action 1 Mask */
179#define PORT_EVCTRL_EVACT1(value) (PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos))
180#define PORT_EVCTRL_PORTEI1_Pos _U_(15) /**< (PORT_EVCTRL) PORT Event Input Enable 1 Position */
181#define PORT_EVCTRL_PORTEI1_Msk (_U_(0x1) << PORT_EVCTRL_PORTEI1_Pos) /**< (PORT_EVCTRL) PORT Event Input Enable 1 Mask */
182#define PORT_EVCTRL_PORTEI1(value) (PORT_EVCTRL_PORTEI1_Msk & ((value) << PORT_EVCTRL_PORTEI1_Pos))
183#define PORT_EVCTRL_PID2_Pos _U_(16) /**< (PORT_EVCTRL) PORT Event Pin Identifier 2 Position */
184#define PORT_EVCTRL_PID2_Msk (_U_(0x1F) << PORT_EVCTRL_PID2_Pos) /**< (PORT_EVCTRL) PORT Event Pin Identifier 2 Mask */
185#define PORT_EVCTRL_PID2(value) (PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos))
186#define PORT_EVCTRL_EVACT2_Pos _U_(21) /**< (PORT_EVCTRL) PORT Event Action 2 Position */
187#define PORT_EVCTRL_EVACT2_Msk (_U_(0x3) << PORT_EVCTRL_EVACT2_Pos) /**< (PORT_EVCTRL) PORT Event Action 2 Mask */
188#define PORT_EVCTRL_EVACT2(value) (PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos))
189#define PORT_EVCTRL_PORTEI2_Pos _U_(23) /**< (PORT_EVCTRL) PORT Event Input Enable 2 Position */
190#define PORT_EVCTRL_PORTEI2_Msk (_U_(0x1) << PORT_EVCTRL_PORTEI2_Pos) /**< (PORT_EVCTRL) PORT Event Input Enable 2 Mask */
191#define PORT_EVCTRL_PORTEI2(value) (PORT_EVCTRL_PORTEI2_Msk & ((value) << PORT_EVCTRL_PORTEI2_Pos))
192#define PORT_EVCTRL_PID3_Pos _U_(24) /**< (PORT_EVCTRL) PORT Event Pin Identifier 3 Position */
193#define PORT_EVCTRL_PID3_Msk (_U_(0x1F) << PORT_EVCTRL_PID3_Pos) /**< (PORT_EVCTRL) PORT Event Pin Identifier 3 Mask */
194#define PORT_EVCTRL_PID3(value) (PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos))
195#define PORT_EVCTRL_EVACT3_Pos _U_(29) /**< (PORT_EVCTRL) PORT Event Action 3 Position */
196#define PORT_EVCTRL_EVACT3_Msk (_U_(0x3) << PORT_EVCTRL_EVACT3_Pos) /**< (PORT_EVCTRL) PORT Event Action 3 Mask */
197#define PORT_EVCTRL_EVACT3(value) (PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos))
198#define PORT_EVCTRL_PORTEI3_Pos _U_(31) /**< (PORT_EVCTRL) PORT Event Input Enable 3 Position */
199#define PORT_EVCTRL_PORTEI3_Msk (_U_(0x1) << PORT_EVCTRL_PORTEI3_Pos) /**< (PORT_EVCTRL) PORT Event Input Enable 3 Mask */
200#define PORT_EVCTRL_PORTEI3(value) (PORT_EVCTRL_PORTEI3_Msk & ((value) << PORT_EVCTRL_PORTEI3_Pos))
201#define PORT_EVCTRL_Msk _U_(0xFFFFFFFF) /**< (PORT_EVCTRL) Register Mask */
202
203
204/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) Peripheral Multiplexing -------- */
205#define PORT_PMUX_RESETVALUE _U_(0x00) /**< (PORT_PMUX) Peripheral Multiplexing Reset Value */
206
207#define PORT_PMUX_PMUXE_Pos _U_(0) /**< (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin Position */
208#define PORT_PMUX_PMUXE_Msk (_U_(0xF) << PORT_PMUX_PMUXE_Pos) /**< (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin Mask */
209#define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
210#define PORT_PMUX_PMUXO_Pos _U_(4) /**< (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin Position */
211#define PORT_PMUX_PMUXO_Msk (_U_(0xF) << PORT_PMUX_PMUXO_Pos) /**< (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin Mask */
212#define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
213#define PORT_PMUX_Msk _U_(0xFF) /**< (PORT_PMUX) Register Mask */
214
215
216/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) Pin Configuration -------- */
217#define PORT_PINCFG_RESETVALUE _U_(0x00) /**< (PORT_PINCFG) Pin Configuration Reset Value */
218
219#define PORT_PINCFG_PMUXEN_Pos _U_(0) /**< (PORT_PINCFG) Peripheral Multiplexer Enable Position */
220#define PORT_PINCFG_PMUXEN_Msk (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos) /**< (PORT_PINCFG) Peripheral Multiplexer Enable Mask */
221#define PORT_PINCFG_PMUXEN(value) (PORT_PINCFG_PMUXEN_Msk & ((value) << PORT_PINCFG_PMUXEN_Pos))
222#define PORT_PINCFG_INEN_Pos _U_(1) /**< (PORT_PINCFG) Input Enable Position */
223#define PORT_PINCFG_INEN_Msk (_U_(0x1) << PORT_PINCFG_INEN_Pos) /**< (PORT_PINCFG) Input Enable Mask */
224#define PORT_PINCFG_INEN(value) (PORT_PINCFG_INEN_Msk & ((value) << PORT_PINCFG_INEN_Pos))
225#define PORT_PINCFG_PULLEN_Pos _U_(2) /**< (PORT_PINCFG) Pull Enable Position */
226#define PORT_PINCFG_PULLEN_Msk (_U_(0x1) << PORT_PINCFG_PULLEN_Pos) /**< (PORT_PINCFG) Pull Enable Mask */
227#define PORT_PINCFG_PULLEN(value) (PORT_PINCFG_PULLEN_Msk & ((value) << PORT_PINCFG_PULLEN_Pos))
228#define PORT_PINCFG_DRVSTR_Pos _U_(6) /**< (PORT_PINCFG) Output Driver Strength Selection Position */
229#define PORT_PINCFG_DRVSTR_Msk (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos) /**< (PORT_PINCFG) Output Driver Strength Selection Mask */
230#define PORT_PINCFG_DRVSTR(value) (PORT_PINCFG_DRVSTR_Msk & ((value) << PORT_PINCFG_DRVSTR_Pos))
231#define PORT_PINCFG_Msk _U_(0x47) /**< (PORT_PINCFG) Register Mask */
232
233
234/** \brief PORT register offsets definitions */
235#define PORT_DIR_REG_OFST (0x00) /**< (PORT_DIR) Data Direction Offset */
236#define PORT_DIRCLR_REG_OFST (0x04) /**< (PORT_DIRCLR) Data Direction Clear Offset */
237#define PORT_DIRSET_REG_OFST (0x08) /**< (PORT_DIRSET) Data Direction Set Offset */
238#define PORT_DIRTGL_REG_OFST (0x0C) /**< (PORT_DIRTGL) Data Direction Toggle Offset */
239#define PORT_OUT_REG_OFST (0x10) /**< (PORT_OUT) Data Output Value Offset */
240#define PORT_OUTCLR_REG_OFST (0x14) /**< (PORT_OUTCLR) Data Output Value Clear Offset */
241#define PORT_OUTSET_REG_OFST (0x18) /**< (PORT_OUTSET) Data Output Value Set Offset */
242#define PORT_OUTTGL_REG_OFST (0x1C) /**< (PORT_OUTTGL) Data Output Value Toggle Offset */
243#define PORT_IN_REG_OFST (0x20) /**< (PORT_IN) Data Input Value Offset */
244#define PORT_CTRL_REG_OFST (0x24) /**< (PORT_CTRL) Control Offset */
245#define PORT_WRCONFIG_REG_OFST (0x28) /**< (PORT_WRCONFIG) Write Configuration Offset */
246#define PORT_EVCTRL_REG_OFST (0x2C) /**< (PORT_EVCTRL) Event Input Control Offset */
247#define PORT_PMUX_REG_OFST (0x30) /**< (PORT_PMUX) Peripheral Multiplexing Offset */
248#define PORT_PINCFG_REG_OFST (0x40) /**< (PORT_PINCFG) Pin Configuration Offset */
249
250#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
251/** \brief GROUP register API structure */
252typedef struct
253{
254 __IO uint32_t PORT_DIR; /**< Offset: 0x00 (R/W 32) Data Direction */
255 __IO uint32_t PORT_DIRCLR; /**< Offset: 0x04 (R/W 32) Data Direction Clear */
256 __IO uint32_t PORT_DIRSET; /**< Offset: 0x08 (R/W 32) Data Direction Set */
257 __IO uint32_t PORT_DIRTGL; /**< Offset: 0x0C (R/W 32) Data Direction Toggle */
258 __IO uint32_t PORT_OUT; /**< Offset: 0x10 (R/W 32) Data Output Value */
259 __IO uint32_t PORT_OUTCLR; /**< Offset: 0x14 (R/W 32) Data Output Value Clear */
260 __IO uint32_t PORT_OUTSET; /**< Offset: 0x18 (R/W 32) Data Output Value Set */
261 __IO uint32_t PORT_OUTTGL; /**< Offset: 0x1C (R/W 32) Data Output Value Toggle */
262 __I uint32_t PORT_IN; /**< Offset: 0x20 (R/ 32) Data Input Value */
263 __IO uint32_t PORT_CTRL; /**< Offset: 0x24 (R/W 32) Control */
264 __O uint32_t PORT_WRCONFIG; /**< Offset: 0x28 ( /W 32) Write Configuration */
265 __IO uint32_t PORT_EVCTRL; /**< Offset: 0x2C (R/W 32) Event Input Control */
266 __IO uint8_t PORT_PMUX[16]; /**< Offset: 0x30 (R/W 8) Peripheral Multiplexing */
267 __IO uint8_t PORT_PINCFG[32]; /**< Offset: 0x40 (R/W 8) Pin Configuration */
268 __I uint8_t Reserved1[0x20];
269} port_group_registers_t;
270
271#define PORT_GROUP_NUMBER _U_(4)
272
273/** \brief PORT register API structure */
274typedef struct
275{ /* Port Module */
276 port_group_registers_t GROUP[PORT_GROUP_NUMBER]; /**< Offset: 0x00 */
277} port_registers_t;
278
279
280#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
281#endif /* _SAMD51_PORT_COMPONENT_H_ */
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