| 1 | /**
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| 2 | * \brief Component description for PORT
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| 3 | *
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| 4 | * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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| 5 | *
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| 6 | * Subject to your compliance with these terms, you may use Microchip software and any derivatives
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| 7 | * exclusively with Microchip products. It is your responsibility to comply with third party license
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| 8 | * terms applicable to your use of third party software (including open source software) that may
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| 9 | * accompany Microchip software.
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| 10 | *
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| 11 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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| 12 | * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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| 13 | * FITNESS FOR A PARTICULAR PURPOSE.
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| 14 | *
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| 15 | * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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| 16 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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| 17 | * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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| 18 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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| 19 | * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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| 20 | *
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| 21 | */
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| 22 |
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| 23 | /* file generated from device description version 2020-03-12T17:26:00Z */
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| 24 | #ifndef _SAMD51_PORT_COMPONENT_H_
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| 25 | #define _SAMD51_PORT_COMPONENT_H_
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| 26 |
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| 27 | /* ************************************************************************** */
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| 28 | /* SOFTWARE API DEFINITION FOR PORT */
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| 29 | /* ************************************************************************** */
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| 30 |
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| 31 | /* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) Data Direction -------- */
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| 32 | #define PORT_DIR_RESETVALUE _U_(0x00) /**< (PORT_DIR) Data Direction Reset Value */
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| 33 |
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| 34 | #define PORT_DIR_DIR_Pos _U_(0) /**< (PORT_DIR) Port Data Direction Position */
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| 35 | #define PORT_DIR_DIR_Msk (_U_(0xFFFFFFFF) << PORT_DIR_DIR_Pos) /**< (PORT_DIR) Port Data Direction Mask */
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| 36 | #define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
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| 37 | #define PORT_DIR_Msk _U_(0xFFFFFFFF) /**< (PORT_DIR) Register Mask */
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| 38 |
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| 39 |
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| 40 | /* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) Data Direction Clear -------- */
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| 41 | #define PORT_DIRCLR_RESETVALUE _U_(0x00) /**< (PORT_DIRCLR) Data Direction Clear Reset Value */
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| 42 |
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| 43 | #define PORT_DIRCLR_DIRCLR_Pos _U_(0) /**< (PORT_DIRCLR) Port Data Direction Clear Position */
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| 44 | #define PORT_DIRCLR_DIRCLR_Msk (_U_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos) /**< (PORT_DIRCLR) Port Data Direction Clear Mask */
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| 45 | #define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
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| 46 | #define PORT_DIRCLR_Msk _U_(0xFFFFFFFF) /**< (PORT_DIRCLR) Register Mask */
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| 47 |
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| 48 |
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| 49 | /* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) Data Direction Set -------- */
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| 50 | #define PORT_DIRSET_RESETVALUE _U_(0x00) /**< (PORT_DIRSET) Data Direction Set Reset Value */
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| 51 |
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| 52 | #define PORT_DIRSET_DIRSET_Pos _U_(0) /**< (PORT_DIRSET) Port Data Direction Set Position */
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| 53 | #define PORT_DIRSET_DIRSET_Msk (_U_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos) /**< (PORT_DIRSET) Port Data Direction Set Mask */
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| 54 | #define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
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| 55 | #define PORT_DIRSET_Msk _U_(0xFFFFFFFF) /**< (PORT_DIRSET) Register Mask */
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| 56 |
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| 57 |
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| 58 | /* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) Data Direction Toggle -------- */
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| 59 | #define PORT_DIRTGL_RESETVALUE _U_(0x00) /**< (PORT_DIRTGL) Data Direction Toggle Reset Value */
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| 60 |
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| 61 | #define PORT_DIRTGL_DIRTGL_Pos _U_(0) /**< (PORT_DIRTGL) Port Data Direction Toggle Position */
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| 62 | #define PORT_DIRTGL_DIRTGL_Msk (_U_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos) /**< (PORT_DIRTGL) Port Data Direction Toggle Mask */
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| 63 | #define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
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| 64 | #define PORT_DIRTGL_Msk _U_(0xFFFFFFFF) /**< (PORT_DIRTGL) Register Mask */
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| 65 |
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| 66 |
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| 67 | /* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) Data Output Value -------- */
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| 68 | #define PORT_OUT_RESETVALUE _U_(0x00) /**< (PORT_OUT) Data Output Value Reset Value */
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| 69 |
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| 70 | #define PORT_OUT_OUT_Pos _U_(0) /**< (PORT_OUT) PORT Data Output Value Position */
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| 71 | #define PORT_OUT_OUT_Msk (_U_(0xFFFFFFFF) << PORT_OUT_OUT_Pos) /**< (PORT_OUT) PORT Data Output Value Mask */
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| 72 | #define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
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| 73 | #define PORT_OUT_Msk _U_(0xFFFFFFFF) /**< (PORT_OUT) Register Mask */
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| 74 |
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| 75 |
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| 76 | /* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) Data Output Value Clear -------- */
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| 77 | #define PORT_OUTCLR_RESETVALUE _U_(0x00) /**< (PORT_OUTCLR) Data Output Value Clear Reset Value */
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| 78 |
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| 79 | #define PORT_OUTCLR_OUTCLR_Pos _U_(0) /**< (PORT_OUTCLR) PORT Data Output Value Clear Position */
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| 80 | #define PORT_OUTCLR_OUTCLR_Msk (_U_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos) /**< (PORT_OUTCLR) PORT Data Output Value Clear Mask */
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| 81 | #define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
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| 82 | #define PORT_OUTCLR_Msk _U_(0xFFFFFFFF) /**< (PORT_OUTCLR) Register Mask */
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| 83 |
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| 84 |
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| 85 | /* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) Data Output Value Set -------- */
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| 86 | #define PORT_OUTSET_RESETVALUE _U_(0x00) /**< (PORT_OUTSET) Data Output Value Set Reset Value */
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| 87 |
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| 88 | #define PORT_OUTSET_OUTSET_Pos _U_(0) /**< (PORT_OUTSET) PORT Data Output Value Set Position */
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| 89 | #define PORT_OUTSET_OUTSET_Msk (_U_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos) /**< (PORT_OUTSET) PORT Data Output Value Set Mask */
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| 90 | #define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
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| 91 | #define PORT_OUTSET_Msk _U_(0xFFFFFFFF) /**< (PORT_OUTSET) Register Mask */
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| 92 |
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| 93 |
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| 94 | /* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) Data Output Value Toggle -------- */
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| 95 | #define PORT_OUTTGL_RESETVALUE _U_(0x00) /**< (PORT_OUTTGL) Data Output Value Toggle Reset Value */
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| 96 |
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| 97 | #define PORT_OUTTGL_OUTTGL_Pos _U_(0) /**< (PORT_OUTTGL) PORT Data Output Value Toggle Position */
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| 98 | #define PORT_OUTTGL_OUTTGL_Msk (_U_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos) /**< (PORT_OUTTGL) PORT Data Output Value Toggle Mask */
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| 99 | #define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
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| 100 | #define PORT_OUTTGL_Msk _U_(0xFFFFFFFF) /**< (PORT_OUTTGL) Register Mask */
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| 101 |
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| 102 |
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| 103 | /* -------- PORT_IN : (PORT Offset: 0x20) ( R/ 32) Data Input Value -------- */
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| 104 | #define PORT_IN_RESETVALUE _U_(0x00) /**< (PORT_IN) Data Input Value Reset Value */
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| 105 |
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| 106 | #define PORT_IN_IN_Pos _U_(0) /**< (PORT_IN) PORT Data Input Value Position */
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| 107 | #define PORT_IN_IN_Msk (_U_(0xFFFFFFFF) << PORT_IN_IN_Pos) /**< (PORT_IN) PORT Data Input Value Mask */
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| 108 | #define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
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| 109 | #define PORT_IN_Msk _U_(0xFFFFFFFF) /**< (PORT_IN) Register Mask */
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| 110 |
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| 111 |
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| 112 | /* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) Control -------- */
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| 113 | #define PORT_CTRL_RESETVALUE _U_(0x00) /**< (PORT_CTRL) Control Reset Value */
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| 114 |
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| 115 | #define PORT_CTRL_SAMPLING_Pos _U_(0) /**< (PORT_CTRL) Input Sampling Mode Position */
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| 116 | #define PORT_CTRL_SAMPLING_Msk (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos) /**< (PORT_CTRL) Input Sampling Mode Mask */
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| 117 | #define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
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| 118 | #define PORT_CTRL_Msk _U_(0xFFFFFFFF) /**< (PORT_CTRL) Register Mask */
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| 119 |
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| 120 |
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| 121 | /* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) Write Configuration -------- */
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| 122 | #define PORT_WRCONFIG_RESETVALUE _U_(0x00) /**< (PORT_WRCONFIG) Write Configuration Reset Value */
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| 123 |
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| 124 | #define PORT_WRCONFIG_PINMASK_Pos _U_(0) /**< (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration Position */
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| 125 | #define PORT_WRCONFIG_PINMASK_Msk (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos) /**< (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration Mask */
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| 126 | #define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
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| 127 | #define PORT_WRCONFIG_PMUXEN_Pos _U_(16) /**< (PORT_WRCONFIG) Peripheral Multiplexer Enable Position */
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| 128 | #define PORT_WRCONFIG_PMUXEN_Msk (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos) /**< (PORT_WRCONFIG) Peripheral Multiplexer Enable Mask */
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| 129 | #define PORT_WRCONFIG_PMUXEN(value) (PORT_WRCONFIG_PMUXEN_Msk & ((value) << PORT_WRCONFIG_PMUXEN_Pos))
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| 130 | #define PORT_WRCONFIG_INEN_Pos _U_(17) /**< (PORT_WRCONFIG) Input Enable Position */
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| 131 | #define PORT_WRCONFIG_INEN_Msk (_U_(0x1) << PORT_WRCONFIG_INEN_Pos) /**< (PORT_WRCONFIG) Input Enable Mask */
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| 132 | #define PORT_WRCONFIG_INEN(value) (PORT_WRCONFIG_INEN_Msk & ((value) << PORT_WRCONFIG_INEN_Pos))
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| 133 | #define PORT_WRCONFIG_PULLEN_Pos _U_(18) /**< (PORT_WRCONFIG) Pull Enable Position */
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| 134 | #define PORT_WRCONFIG_PULLEN_Msk (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos) /**< (PORT_WRCONFIG) Pull Enable Mask */
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| 135 | #define PORT_WRCONFIG_PULLEN(value) (PORT_WRCONFIG_PULLEN_Msk & ((value) << PORT_WRCONFIG_PULLEN_Pos))
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| 136 | #define PORT_WRCONFIG_DRVSTR_Pos _U_(22) /**< (PORT_WRCONFIG) Output Driver Strength Selection Position */
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| 137 | #define PORT_WRCONFIG_DRVSTR_Msk (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos) /**< (PORT_WRCONFIG) Output Driver Strength Selection Mask */
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| 138 | #define PORT_WRCONFIG_DRVSTR(value) (PORT_WRCONFIG_DRVSTR_Msk & ((value) << PORT_WRCONFIG_DRVSTR_Pos))
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| 139 | #define PORT_WRCONFIG_PMUX_Pos _U_(24) /**< (PORT_WRCONFIG) Peripheral Multiplexing Position */
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| 140 | #define PORT_WRCONFIG_PMUX_Msk (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos) /**< (PORT_WRCONFIG) Peripheral Multiplexing Mask */
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| 141 | #define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
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| 142 | #define PORT_WRCONFIG_WRPMUX_Pos _U_(28) /**< (PORT_WRCONFIG) Write PMUX Position */
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| 143 | #define PORT_WRCONFIG_WRPMUX_Msk (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos) /**< (PORT_WRCONFIG) Write PMUX Mask */
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| 144 | #define PORT_WRCONFIG_WRPMUX(value) (PORT_WRCONFIG_WRPMUX_Msk & ((value) << PORT_WRCONFIG_WRPMUX_Pos))
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| 145 | #define PORT_WRCONFIG_WRPINCFG_Pos _U_(30) /**< (PORT_WRCONFIG) Write PINCFG Position */
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| 146 | #define PORT_WRCONFIG_WRPINCFG_Msk (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos) /**< (PORT_WRCONFIG) Write PINCFG Mask */
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| 147 | #define PORT_WRCONFIG_WRPINCFG(value) (PORT_WRCONFIG_WRPINCFG_Msk & ((value) << PORT_WRCONFIG_WRPINCFG_Pos))
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| 148 | #define PORT_WRCONFIG_HWSEL_Pos _U_(31) /**< (PORT_WRCONFIG) Half-Word Select Position */
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| 149 | #define PORT_WRCONFIG_HWSEL_Msk (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos) /**< (PORT_WRCONFIG) Half-Word Select Mask */
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| 150 | #define PORT_WRCONFIG_HWSEL(value) (PORT_WRCONFIG_HWSEL_Msk & ((value) << PORT_WRCONFIG_HWSEL_Pos))
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| 151 | #define PORT_WRCONFIG_Msk _U_(0xDF47FFFF) /**< (PORT_WRCONFIG) Register Mask */
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| 152 |
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| 153 |
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| 154 | /* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) Event Input Control -------- */
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| 155 | #define PORT_EVCTRL_RESETVALUE _U_(0x00) /**< (PORT_EVCTRL) Event Input Control Reset Value */
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| 156 |
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| 157 | #define PORT_EVCTRL_PID0_Pos _U_(0) /**< (PORT_EVCTRL) PORT Event Pin Identifier 0 Position */
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| 158 | #define PORT_EVCTRL_PID0_Msk (_U_(0x1F) << PORT_EVCTRL_PID0_Pos) /**< (PORT_EVCTRL) PORT Event Pin Identifier 0 Mask */
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| 159 | #define PORT_EVCTRL_PID0(value) (PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos))
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| 160 | #define PORT_EVCTRL_EVACT0_Pos _U_(5) /**< (PORT_EVCTRL) PORT Event Action 0 Position */
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| 161 | #define PORT_EVCTRL_EVACT0_Msk (_U_(0x3) << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) PORT Event Action 0 Mask */
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| 162 | #define PORT_EVCTRL_EVACT0(value) (PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos))
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| 163 | #define PORT_EVCTRL_EVACT0_OUT_Val _U_(0x0) /**< (PORT_EVCTRL) Event output to pin */
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| 164 | #define PORT_EVCTRL_EVACT0_SET_Val _U_(0x1) /**< (PORT_EVCTRL) Set output register of pin on event */
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| 165 | #define PORT_EVCTRL_EVACT0_CLR_Val _U_(0x2) /**< (PORT_EVCTRL) Clear output register of pin on event */
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| 166 | #define PORT_EVCTRL_EVACT0_TGL_Val _U_(0x3) /**< (PORT_EVCTRL) Toggle output register of pin on event */
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| 167 | #define PORT_EVCTRL_EVACT0_OUT (PORT_EVCTRL_EVACT0_OUT_Val << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) Event output to pin Position */
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| 168 | #define PORT_EVCTRL_EVACT0_SET (PORT_EVCTRL_EVACT0_SET_Val << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) Set output register of pin on event Position */
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| 169 | #define PORT_EVCTRL_EVACT0_CLR (PORT_EVCTRL_EVACT0_CLR_Val << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) Clear output register of pin on event Position */
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| 170 | #define PORT_EVCTRL_EVACT0_TGL (PORT_EVCTRL_EVACT0_TGL_Val << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) Toggle output register of pin on event Position */
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| 171 | #define PORT_EVCTRL_PORTEI0_Pos _U_(7) /**< (PORT_EVCTRL) PORT Event Input Enable 0 Position */
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| 172 | #define PORT_EVCTRL_PORTEI0_Msk (_U_(0x1) << PORT_EVCTRL_PORTEI0_Pos) /**< (PORT_EVCTRL) PORT Event Input Enable 0 Mask */
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| 173 | #define PORT_EVCTRL_PORTEI0(value) (PORT_EVCTRL_PORTEI0_Msk & ((value) << PORT_EVCTRL_PORTEI0_Pos))
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| 174 | #define PORT_EVCTRL_PID1_Pos _U_(8) /**< (PORT_EVCTRL) PORT Event Pin Identifier 1 Position */
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| 175 | #define PORT_EVCTRL_PID1_Msk (_U_(0x1F) << PORT_EVCTRL_PID1_Pos) /**< (PORT_EVCTRL) PORT Event Pin Identifier 1 Mask */
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| 176 | #define PORT_EVCTRL_PID1(value) (PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos))
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| 177 | #define PORT_EVCTRL_EVACT1_Pos _U_(13) /**< (PORT_EVCTRL) PORT Event Action 1 Position */
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| 178 | #define PORT_EVCTRL_EVACT1_Msk (_U_(0x3) << PORT_EVCTRL_EVACT1_Pos) /**< (PORT_EVCTRL) PORT Event Action 1 Mask */
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| 179 | #define PORT_EVCTRL_EVACT1(value) (PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos))
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| 180 | #define PORT_EVCTRL_PORTEI1_Pos _U_(15) /**< (PORT_EVCTRL) PORT Event Input Enable 1 Position */
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| 181 | #define PORT_EVCTRL_PORTEI1_Msk (_U_(0x1) << PORT_EVCTRL_PORTEI1_Pos) /**< (PORT_EVCTRL) PORT Event Input Enable 1 Mask */
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| 182 | #define PORT_EVCTRL_PORTEI1(value) (PORT_EVCTRL_PORTEI1_Msk & ((value) << PORT_EVCTRL_PORTEI1_Pos))
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| 183 | #define PORT_EVCTRL_PID2_Pos _U_(16) /**< (PORT_EVCTRL) PORT Event Pin Identifier 2 Position */
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| 184 | #define PORT_EVCTRL_PID2_Msk (_U_(0x1F) << PORT_EVCTRL_PID2_Pos) /**< (PORT_EVCTRL) PORT Event Pin Identifier 2 Mask */
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| 185 | #define PORT_EVCTRL_PID2(value) (PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos))
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| 186 | #define PORT_EVCTRL_EVACT2_Pos _U_(21) /**< (PORT_EVCTRL) PORT Event Action 2 Position */
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| 187 | #define PORT_EVCTRL_EVACT2_Msk (_U_(0x3) << PORT_EVCTRL_EVACT2_Pos) /**< (PORT_EVCTRL) PORT Event Action 2 Mask */
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| 188 | #define PORT_EVCTRL_EVACT2(value) (PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos))
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| 189 | #define PORT_EVCTRL_PORTEI2_Pos _U_(23) /**< (PORT_EVCTRL) PORT Event Input Enable 2 Position */
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| 190 | #define PORT_EVCTRL_PORTEI2_Msk (_U_(0x1) << PORT_EVCTRL_PORTEI2_Pos) /**< (PORT_EVCTRL) PORT Event Input Enable 2 Mask */
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| 191 | #define PORT_EVCTRL_PORTEI2(value) (PORT_EVCTRL_PORTEI2_Msk & ((value) << PORT_EVCTRL_PORTEI2_Pos))
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| 192 | #define PORT_EVCTRL_PID3_Pos _U_(24) /**< (PORT_EVCTRL) PORT Event Pin Identifier 3 Position */
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| 193 | #define PORT_EVCTRL_PID3_Msk (_U_(0x1F) << PORT_EVCTRL_PID3_Pos) /**< (PORT_EVCTRL) PORT Event Pin Identifier 3 Mask */
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| 194 | #define PORT_EVCTRL_PID3(value) (PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos))
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| 195 | #define PORT_EVCTRL_EVACT3_Pos _U_(29) /**< (PORT_EVCTRL) PORT Event Action 3 Position */
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| 196 | #define PORT_EVCTRL_EVACT3_Msk (_U_(0x3) << PORT_EVCTRL_EVACT3_Pos) /**< (PORT_EVCTRL) PORT Event Action 3 Mask */
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| 197 | #define PORT_EVCTRL_EVACT3(value) (PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos))
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| 198 | #define PORT_EVCTRL_PORTEI3_Pos _U_(31) /**< (PORT_EVCTRL) PORT Event Input Enable 3 Position */
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| 199 | #define PORT_EVCTRL_PORTEI3_Msk (_U_(0x1) << PORT_EVCTRL_PORTEI3_Pos) /**< (PORT_EVCTRL) PORT Event Input Enable 3 Mask */
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| 200 | #define PORT_EVCTRL_PORTEI3(value) (PORT_EVCTRL_PORTEI3_Msk & ((value) << PORT_EVCTRL_PORTEI3_Pos))
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| 201 | #define PORT_EVCTRL_Msk _U_(0xFFFFFFFF) /**< (PORT_EVCTRL) Register Mask */
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| 202 |
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| 203 |
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| 204 | /* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) Peripheral Multiplexing -------- */
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| 205 | #define PORT_PMUX_RESETVALUE _U_(0x00) /**< (PORT_PMUX) Peripheral Multiplexing Reset Value */
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| 206 |
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| 207 | #define PORT_PMUX_PMUXE_Pos _U_(0) /**< (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin Position */
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| 208 | #define PORT_PMUX_PMUXE_Msk (_U_(0xF) << PORT_PMUX_PMUXE_Pos) /**< (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin Mask */
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| 209 | #define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
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| 210 | #define PORT_PMUX_PMUXO_Pos _U_(4) /**< (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin Position */
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| 211 | #define PORT_PMUX_PMUXO_Msk (_U_(0xF) << PORT_PMUX_PMUXO_Pos) /**< (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin Mask */
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| 212 | #define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
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| 213 | #define PORT_PMUX_Msk _U_(0xFF) /**< (PORT_PMUX) Register Mask */
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| 214 |
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| 215 |
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| 216 | /* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) Pin Configuration -------- */
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| 217 | #define PORT_PINCFG_RESETVALUE _U_(0x00) /**< (PORT_PINCFG) Pin Configuration Reset Value */
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| 218 |
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| 219 | #define PORT_PINCFG_PMUXEN_Pos _U_(0) /**< (PORT_PINCFG) Peripheral Multiplexer Enable Position */
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| 220 | #define PORT_PINCFG_PMUXEN_Msk (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos) /**< (PORT_PINCFG) Peripheral Multiplexer Enable Mask */
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| 221 | #define PORT_PINCFG_PMUXEN(value) (PORT_PINCFG_PMUXEN_Msk & ((value) << PORT_PINCFG_PMUXEN_Pos))
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| 222 | #define PORT_PINCFG_INEN_Pos _U_(1) /**< (PORT_PINCFG) Input Enable Position */
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| 223 | #define PORT_PINCFG_INEN_Msk (_U_(0x1) << PORT_PINCFG_INEN_Pos) /**< (PORT_PINCFG) Input Enable Mask */
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| 224 | #define PORT_PINCFG_INEN(value) (PORT_PINCFG_INEN_Msk & ((value) << PORT_PINCFG_INEN_Pos))
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| 225 | #define PORT_PINCFG_PULLEN_Pos _U_(2) /**< (PORT_PINCFG) Pull Enable Position */
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| 226 | #define PORT_PINCFG_PULLEN_Msk (_U_(0x1) << PORT_PINCFG_PULLEN_Pos) /**< (PORT_PINCFG) Pull Enable Mask */
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| 227 | #define PORT_PINCFG_PULLEN(value) (PORT_PINCFG_PULLEN_Msk & ((value) << PORT_PINCFG_PULLEN_Pos))
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| 228 | #define PORT_PINCFG_DRVSTR_Pos _U_(6) /**< (PORT_PINCFG) Output Driver Strength Selection Position */
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| 229 | #define PORT_PINCFG_DRVSTR_Msk (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos) /**< (PORT_PINCFG) Output Driver Strength Selection Mask */
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| 230 | #define PORT_PINCFG_DRVSTR(value) (PORT_PINCFG_DRVSTR_Msk & ((value) << PORT_PINCFG_DRVSTR_Pos))
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| 231 | #define PORT_PINCFG_Msk _U_(0x47) /**< (PORT_PINCFG) Register Mask */
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| 232 |
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| 233 |
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| 234 | /** \brief PORT register offsets definitions */
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| 235 | #define PORT_DIR_REG_OFST (0x00) /**< (PORT_DIR) Data Direction Offset */
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| 236 | #define PORT_DIRCLR_REG_OFST (0x04) /**< (PORT_DIRCLR) Data Direction Clear Offset */
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| 237 | #define PORT_DIRSET_REG_OFST (0x08) /**< (PORT_DIRSET) Data Direction Set Offset */
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| 238 | #define PORT_DIRTGL_REG_OFST (0x0C) /**< (PORT_DIRTGL) Data Direction Toggle Offset */
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| 239 | #define PORT_OUT_REG_OFST (0x10) /**< (PORT_OUT) Data Output Value Offset */
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| 240 | #define PORT_OUTCLR_REG_OFST (0x14) /**< (PORT_OUTCLR) Data Output Value Clear Offset */
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| 241 | #define PORT_OUTSET_REG_OFST (0x18) /**< (PORT_OUTSET) Data Output Value Set Offset */
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| 242 | #define PORT_OUTTGL_REG_OFST (0x1C) /**< (PORT_OUTTGL) Data Output Value Toggle Offset */
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| 243 | #define PORT_IN_REG_OFST (0x20) /**< (PORT_IN) Data Input Value Offset */
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| 244 | #define PORT_CTRL_REG_OFST (0x24) /**< (PORT_CTRL) Control Offset */
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| 245 | #define PORT_WRCONFIG_REG_OFST (0x28) /**< (PORT_WRCONFIG) Write Configuration Offset */
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| 246 | #define PORT_EVCTRL_REG_OFST (0x2C) /**< (PORT_EVCTRL) Event Input Control Offset */
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| 247 | #define PORT_PMUX_REG_OFST (0x30) /**< (PORT_PMUX) Peripheral Multiplexing Offset */
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| 248 | #define PORT_PINCFG_REG_OFST (0x40) /**< (PORT_PINCFG) Pin Configuration Offset */
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| 249 |
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| 250 | #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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| 251 | /** \brief GROUP register API structure */
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| 252 | typedef struct
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| 253 | {
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| 254 | __IO uint32_t PORT_DIR; /**< Offset: 0x00 (R/W 32) Data Direction */
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| 255 | __IO uint32_t PORT_DIRCLR; /**< Offset: 0x04 (R/W 32) Data Direction Clear */
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| 256 | __IO uint32_t PORT_DIRSET; /**< Offset: 0x08 (R/W 32) Data Direction Set */
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| 257 | __IO uint32_t PORT_DIRTGL; /**< Offset: 0x0C (R/W 32) Data Direction Toggle */
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| 258 | __IO uint32_t PORT_OUT; /**< Offset: 0x10 (R/W 32) Data Output Value */
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| 259 | __IO uint32_t PORT_OUTCLR; /**< Offset: 0x14 (R/W 32) Data Output Value Clear */
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| 260 | __IO uint32_t PORT_OUTSET; /**< Offset: 0x18 (R/W 32) Data Output Value Set */
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| 261 | __IO uint32_t PORT_OUTTGL; /**< Offset: 0x1C (R/W 32) Data Output Value Toggle */
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| 262 | __I uint32_t PORT_IN; /**< Offset: 0x20 (R/ 32) Data Input Value */
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| 263 | __IO uint32_t PORT_CTRL; /**< Offset: 0x24 (R/W 32) Control */
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| 264 | __O uint32_t PORT_WRCONFIG; /**< Offset: 0x28 ( /W 32) Write Configuration */
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| 265 | __IO uint32_t PORT_EVCTRL; /**< Offset: 0x2C (R/W 32) Event Input Control */
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| 266 | __IO uint8_t PORT_PMUX[16]; /**< Offset: 0x30 (R/W 8) Peripheral Multiplexing */
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| 267 | __IO uint8_t PORT_PINCFG[32]; /**< Offset: 0x40 (R/W 8) Pin Configuration */
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| 268 | __I uint8_t Reserved1[0x20];
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| 269 | } port_group_registers_t;
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| 270 |
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| 271 | #define PORT_GROUP_NUMBER _U_(4)
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| 272 |
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| 273 | /** \brief PORT register API structure */
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| 274 | typedef struct
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| 275 | { /* Port Module */
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| 276 | port_group_registers_t GROUP[PORT_GROUP_NUMBER]; /**< Offset: 0x00 */
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| 277 | } port_registers_t;
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| 278 |
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| 279 |
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| 280 | #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 281 | #endif /* _SAMD51_PORT_COMPONENT_H_ */
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