1 | /*******************************************************************************
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2 | CLOCK PLIB
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3 |
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4 | Company:
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5 | Microchip Technology Inc.
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6 |
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7 | File Name:
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8 | plib_clock.c
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9 |
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10 | Summary:
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11 | CLOCK PLIB Implementation File.
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12 |
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13 | Description:
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14 | None
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15 |
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16 | *******************************************************************************/
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17 |
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18 | /*******************************************************************************
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19 | * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries.
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20 | *
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21 | * Subject to your compliance with these terms, you may use Microchip software
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22 | * and any derivatives exclusively with Microchip products. It is your
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23 | * responsibility to comply with third party license terms applicable to your
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24 | * use of third party software (including open source software) that may
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25 | * accompany Microchip software.
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26 | *
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27 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
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28 | * EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED
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29 | * WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
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30 | * PARTICULAR PURPOSE.
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31 | *
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32 | * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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33 | * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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34 | * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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35 | * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE
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36 | * FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN
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37 | * ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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38 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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39 | *******************************************************************************/
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40 |
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41 | #include "plib_clock.h"
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42 | #include "atsamd51p19a.h"
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43 |
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44 | static void OSCCTRL_Initialize(void)
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45 | {
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46 |
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47 | /****************** XOSC1 Initialization ********************************/
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48 |
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49 | /* Configure External Oscillator */
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50 | OSCCTRL_REGS->OSCCTRL_XOSCCTRL[1] = OSCCTRL_XOSCCTRL_STARTUP(0) | OSCCTRL_XOSCCTRL_IMULT(6) | OSCCTRL_XOSCCTRL_IPTAT(3) | OSCCTRL_XOSCCTRL_XTALEN_Msk | OSCCTRL_XOSCCTRL_ENABLE_Msk;
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51 |
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52 | while((OSCCTRL_REGS->OSCCTRL_STATUS & OSCCTRL_STATUS_XOSCRDY1_Msk) != OSCCTRL_STATUS_XOSCRDY1_Msk)
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53 | {
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54 | /* Waiting for the XOSC Ready state */
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55 | }
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56 | }
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57 |
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58 | static void OSC32KCTRL_Initialize(void)
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59 | {
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60 | /****************** XOSC32K initialization ******************************/
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61 |
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62 | /* Configure 32K External Oscillator */
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63 | OSC32KCTRL_REGS->OSC32KCTRL_XOSC32K = OSC32KCTRL_XOSC32K_STARTUP(2) | OSC32KCTRL_XOSC32K_ENABLE_Msk | OSC32KCTRL_XOSC32K_CGM(1) | OSC32KCTRL_XOSC32K_EN32K_Msk | OSC32KCTRL_XOSC32K_XTALEN_Msk;
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64 |
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65 |
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66 | while(!((OSC32KCTRL_REGS->OSC32KCTRL_STATUS & OSC32KCTRL_STATUS_XOSC32KRDY_Msk) == OSC32KCTRL_STATUS_XOSC32KRDY_Msk))
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67 | {
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68 | /* Waiting for the XOSC32K Ready state */
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69 | }
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70 |
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71 | OSC32KCTRL_REGS->OSC32KCTRL_RTCCTRL = OSC32KCTRL_RTCCTRL_RTCSEL(0);
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72 | }
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73 |
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74 | static void FDPLL0_Initialize(void)
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75 | {
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76 | GCLK_REGS->GCLK_PCHCTRL[1] = GCLK_PCHCTRL_GEN(0x2) | GCLK_PCHCTRL_CHEN_Msk;
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77 | while ((GCLK_REGS->GCLK_PCHCTRL[1] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk)
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78 | {
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79 | /* Wait for synchronization */
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80 | }
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81 |
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82 | /****************** DPLL0 Initialization *********************************/
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83 |
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84 | /* Configure DPLL */
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85 | OSCCTRL_REGS->DPLL[0].OSCCTRL_DPLLCTRLB = OSCCTRL_DPLLCTRLB_FILTER(0) | OSCCTRL_DPLLCTRLB_LTIME(0x0)| OSCCTRL_DPLLCTRLB_REFCLK(0) ;
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86 |
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87 |
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88 | OSCCTRL_REGS->DPLL[0].OSCCTRL_DPLLRATIO = OSCCTRL_DPLLRATIO_LDRFRAC(0) | OSCCTRL_DPLLRATIO_LDR(199);
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89 |
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90 | while((OSCCTRL_REGS->DPLL[0].OSCCTRL_DPLLSYNCBUSY & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk) == OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk)
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91 | {
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92 | /* Waiting for the synchronization */
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93 | }
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94 |
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95 | /* Enable DPLL */
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96 | OSCCTRL_REGS->DPLL[0].OSCCTRL_DPLLCTRLA = OSCCTRL_DPLLCTRLA_ENABLE_Msk ;
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97 |
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98 | while((OSCCTRL_REGS->DPLL[0].OSCCTRL_DPLLSYNCBUSY & OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk) == OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk )
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99 | {
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100 | /* Waiting for the DPLL enable synchronization */
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101 | }
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102 |
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103 | while((OSCCTRL_REGS->DPLL[0].OSCCTRL_DPLLSTATUS & (OSCCTRL_DPLLSTATUS_LOCK_Msk | OSCCTRL_DPLLSTATUS_CLKRDY_Msk)) !=
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104 | (OSCCTRL_DPLLSTATUS_LOCK_Msk | OSCCTRL_DPLLSTATUS_CLKRDY_Msk))
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105 | {
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106 | /* Waiting for the Ready state */
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107 | }
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108 | }
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109 |
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110 | static void FDPLL1_Initialize(void)
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111 | {
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112 | GCLK_REGS->GCLK_PCHCTRL[2] = GCLK_PCHCTRL_GEN(0x2) | GCLK_PCHCTRL_CHEN_Msk;
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113 | while ((GCLK_REGS->GCLK_PCHCTRL[1] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk)
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114 | {
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115 | /* Wait for synchronization */
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116 | }
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117 |
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118 | /****************** DPLL1 Initialization *********************************/
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119 |
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120 | /* Configure DPLL */
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121 | OSCCTRL_REGS->DPLL[1].OSCCTRL_DPLLCTRLB = OSCCTRL_DPLLCTRLB_FILTER(0) | OSCCTRL_DPLLCTRLB_LTIME(0x0)| OSCCTRL_DPLLCTRLB_REFCLK(0) ;
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122 |
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123 |
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124 | OSCCTRL_REGS->DPLL[1].OSCCTRL_DPLLRATIO = OSCCTRL_DPLLRATIO_LDRFRAC(0) | OSCCTRL_DPLLRATIO_LDR(159);
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125 |
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126 | while((OSCCTRL_REGS->DPLL[1].OSCCTRL_DPLLSYNCBUSY & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk) == OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk)
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127 | {
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128 | /* Waiting for the synchronization */
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129 | }
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130 |
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131 | /* Enable DPLL */
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132 | OSCCTRL_REGS->DPLL[1].OSCCTRL_DPLLCTRLA = OSCCTRL_DPLLCTRLA_ENABLE_Msk ;
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133 |
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134 | while((OSCCTRL_REGS->DPLL[1].OSCCTRL_DPLLSYNCBUSY & OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk) == OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk )
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135 | {
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136 | /* Waiting for the DPLL enable synchronization */
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137 | }
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138 |
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139 | while((OSCCTRL_REGS->DPLL[1].OSCCTRL_DPLLSTATUS & (OSCCTRL_DPLLSTATUS_LOCK_Msk | OSCCTRL_DPLLSTATUS_CLKRDY_Msk)) !=
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140 | (OSCCTRL_DPLLSTATUS_LOCK_Msk | OSCCTRL_DPLLSTATUS_CLKRDY_Msk))
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141 | {
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142 | /* Waiting for the Ready state */
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143 | }
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144 | }
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145 |
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146 | static void DFLL_Initialize(void)
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147 | {
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148 | }
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149 |
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150 |
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151 | static void GCLK0_Initialize(void)
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152 | {
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153 |
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154 | /* selection of the CPU clock Division */
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155 | MCLK_REGS->MCLK_CPUDIV = MCLK_CPUDIV_DIV(0x01);
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156 |
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157 | while((MCLK_REGS->MCLK_INTFLAG & MCLK_INTFLAG_CKRDY_Msk) != MCLK_INTFLAG_CKRDY_Msk)
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158 | {
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159 | /* Wait for the Main Clock to be Ready */
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160 | }
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161 | GCLK_REGS->GCLK_GENCTRL[0] = GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_SRC(7) | GCLK_GENCTRL_GENEN_Msk;
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162 |
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163 | while((GCLK_REGS->GCLK_SYNCBUSY & GCLK_SYNCBUSY_GENCTRL_GCLK0) == GCLK_SYNCBUSY_GENCTRL_GCLK0)
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164 | {
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165 | /* wait for the Generator 0 synchronization */
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166 | }
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167 | }
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168 |
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169 | static void GCLK1_Initialize(void)
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170 | {
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171 | GCLK_REGS->GCLK_GENCTRL[1] = GCLK_GENCTRL_DIV(2) | GCLK_GENCTRL_SRC(7) | GCLK_GENCTRL_GENEN_Msk;
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172 |
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173 | while((GCLK_REGS->GCLK_SYNCBUSY & GCLK_SYNCBUSY_GENCTRL_GCLK1) == GCLK_SYNCBUSY_GENCTRL_GCLK1)
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174 | {
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175 | /* wait for the Generator 1 synchronization */
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176 | }
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177 | }
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178 |
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179 | static void GCLK2_Initialize(void)
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180 | {
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181 | GCLK_REGS->GCLK_GENCTRL[2] = GCLK_GENCTRL_DIV(32) | GCLK_GENCTRL_SRC(1) | GCLK_GENCTRL_GENEN_Msk;
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182 |
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183 | while((GCLK_REGS->GCLK_SYNCBUSY & GCLK_SYNCBUSY_GENCTRL_GCLK2) == GCLK_SYNCBUSY_GENCTRL_GCLK2)
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184 | {
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185 | /* wait for the Generator 2 synchronization */
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186 | }
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187 | }
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188 |
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189 | static void GCLK3_Initialize(void)
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190 | {
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191 | GCLK_REGS->GCLK_GENCTRL[3] = GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_SRC(8) | GCLK_GENCTRL_GENEN_Msk;
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192 |
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193 | while((GCLK_REGS->GCLK_SYNCBUSY & GCLK_SYNCBUSY_GENCTRL_GCLK3) == GCLK_SYNCBUSY_GENCTRL_GCLK3)
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194 | {
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195 | /* wait for the Generator 3 synchronization */
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196 | }
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197 | }
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198 |
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199 | void CLOCK_Initialize (void)
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200 | {
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201 | /* Function to Initialize the Oscillators */
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202 | OSCCTRL_Initialize();
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203 |
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204 | /* Function to Initialize the 32KHz Oscillators */
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205 | OSC32KCTRL_Initialize();
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206 |
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207 | DFLL_Initialize();
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208 | GCLK2_Initialize();
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209 | FDPLL0_Initialize();
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210 | FDPLL1_Initialize();
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211 | GCLK0_Initialize();
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212 | GCLK1_Initialize();
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213 | GCLK3_Initialize();
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214 |
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215 |
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216 |
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217 | /* Selection of the Generator and write Lock for SERCOM2_CORE */
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218 | GCLK_REGS->GCLK_PCHCTRL[23] = GCLK_PCHCTRL_GEN(0x1) | GCLK_PCHCTRL_CHEN_Msk;
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219 |
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220 | while ((GCLK_REGS->GCLK_PCHCTRL[23] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk)
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221 | {
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222 | /* Wait for synchronization */
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223 | }
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224 | /* Selection of the Generator and write Lock for SERCOM7_CORE */
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225 | GCLK_REGS->GCLK_PCHCTRL[37] = GCLK_PCHCTRL_GEN(0x3) | GCLK_PCHCTRL_CHEN_Msk;
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226 |
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227 | while ((GCLK_REGS->GCLK_PCHCTRL[37] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk)
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228 | {
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229 | /* Wait for synchronization */
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230 | }
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231 |
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232 | /* Configure the AHB Bridge Clocks */
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233 | MCLK_REGS->MCLK_AHBMASK = 0xffffff;
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234 |
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235 | /* Configure the APBA Bridge Clocks */
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236 | MCLK_REGS->MCLK_APBAMASK = 0x7ff;
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237 |
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238 | /* Configure the APBB Bridge Clocks */
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239 | MCLK_REGS->MCLK_APBBMASK = 0x18256;
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240 |
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241 | /* Configure the APBD Bridge Clocks */
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242 | MCLK_REGS->MCLK_APBDMASK = 0x8;
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243 |
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244 |
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245 | }
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