source: asp_wio_terminal/trunk/target/samd51_gcc/lib/oscctrl.h@ 460

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1/**
2 * \brief Component description for OSCCTRL
3 *
4 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
5 *
6 * Subject to your compliance with these terms, you may use Microchip software and any derivatives
7 * exclusively with Microchip products. It is your responsibility to comply with third party license
8 * terms applicable to your use of third party software (including open source software) that may
9 * accompany Microchip software.
10 *
11 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
12 * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
13 * FITNESS FOR A PARTICULAR PURPOSE.
14 *
15 * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
16 * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
17 * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
18 * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
19 * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
20 *
21 */
22
23/* file generated from device description version 2020-03-12T17:26:00Z */
24#ifndef _SAMD51_OSCCTRL_COMPONENT_H_
25#define _SAMD51_OSCCTRL_COMPONENT_H_
26
27/* ************************************************************************** */
28/* SOFTWARE API DEFINITION FOR OSCCTRL */
29/* ************************************************************************** */
30
31/* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x00) (R/W 8) DPLL Control A -------- */
32#define OSCCTRL_DPLLCTRLA_RESETVALUE _U_(0x80) /**< (OSCCTRL_DPLLCTRLA) DPLL Control A Reset Value */
33
34#define OSCCTRL_DPLLCTRLA_ENABLE_Pos _U_(1) /**< (OSCCTRL_DPLLCTRLA) DPLL Enable Position */
35#define OSCCTRL_DPLLCTRLA_ENABLE_Msk (_U_(0x1) << OSCCTRL_DPLLCTRLA_ENABLE_Pos) /**< (OSCCTRL_DPLLCTRLA) DPLL Enable Mask */
36#define OSCCTRL_DPLLCTRLA_ENABLE(value) (OSCCTRL_DPLLCTRLA_ENABLE_Msk & ((value) << OSCCTRL_DPLLCTRLA_ENABLE_Pos))
37#define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos _U_(6) /**< (OSCCTRL_DPLLCTRLA) Run in Standby Position */
38#define OSCCTRL_DPLLCTRLA_RUNSTDBY_Msk (_U_(0x1) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) /**< (OSCCTRL_DPLLCTRLA) Run in Standby Mask */
39#define OSCCTRL_DPLLCTRLA_RUNSTDBY(value) (OSCCTRL_DPLLCTRLA_RUNSTDBY_Msk & ((value) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos))
40#define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos _U_(7) /**< (OSCCTRL_DPLLCTRLA) On Demand Control Position */
41#define OSCCTRL_DPLLCTRLA_ONDEMAND_Msk (_U_(0x1) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos) /**< (OSCCTRL_DPLLCTRLA) On Demand Control Mask */
42#define OSCCTRL_DPLLCTRLA_ONDEMAND(value) (OSCCTRL_DPLLCTRLA_ONDEMAND_Msk & ((value) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos))
43#define OSCCTRL_DPLLCTRLA_Msk _U_(0xC2) /**< (OSCCTRL_DPLLCTRLA) Register Mask */
44
45
46/* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x04) (R/W 32) DPLL Ratio Control -------- */
47#define OSCCTRL_DPLLRATIO_RESETVALUE _U_(0x00) /**< (OSCCTRL_DPLLRATIO) DPLL Ratio Control Reset Value */
48
49#define OSCCTRL_DPLLRATIO_LDR_Pos _U_(0) /**< (OSCCTRL_DPLLRATIO) Loop Divider Ratio Position */
50#define OSCCTRL_DPLLRATIO_LDR_Msk (_U_(0x1FFF) << OSCCTRL_DPLLRATIO_LDR_Pos) /**< (OSCCTRL_DPLLRATIO) Loop Divider Ratio Mask */
51#define OSCCTRL_DPLLRATIO_LDR(value) (OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos))
52#define OSCCTRL_DPLLRATIO_LDRFRAC_Pos _U_(16) /**< (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part Position */
53#define OSCCTRL_DPLLRATIO_LDRFRAC_Msk (_U_(0x1F) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos) /**< (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part Mask */
54#define OSCCTRL_DPLLRATIO_LDRFRAC(value) (OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos))
55#define OSCCTRL_DPLLRATIO_Msk _U_(0x001F1FFF) /**< (OSCCTRL_DPLLRATIO) Register Mask */
56
57
58/* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x08) (R/W 32) DPLL Control B -------- */
59#define OSCCTRL_DPLLCTRLB_RESETVALUE _U_(0x20) /**< (OSCCTRL_DPLLCTRLB) DPLL Control B Reset Value */
60
61#define OSCCTRL_DPLLCTRLB_FILTER_Pos _U_(0) /**< (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection Position */
62#define OSCCTRL_DPLLCTRLB_FILTER_Msk (_U_(0xF) << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection Mask */
63#define OSCCTRL_DPLLCTRLB_FILTER(value) (OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos))
64#define OSCCTRL_DPLLCTRLB_FILTER_FILTER1_Val _U_(0x0) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 0.76 */
65#define OSCCTRL_DPLLCTRLB_FILTER_FILTER2_Val _U_(0x1) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 131Khz and Damping Factor = 1.08 */
66#define OSCCTRL_DPLLCTRLB_FILTER_FILTER3_Val _U_(0x2) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 0.38 */
67#define OSCCTRL_DPLLCTRLB_FILTER_FILTER4_Val _U_(0x3) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 0.54 */
68#define OSCCTRL_DPLLCTRLB_FILTER_FILTER5_Val _U_(0x4) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 131Khz and Damping Factor = 0.56 */
69#define OSCCTRL_DPLLCTRLB_FILTER_FILTER6_Val _U_(0x5) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 185Khz and Damping Factor = 0.79 */
70#define OSCCTRL_DPLLCTRLB_FILTER_FILTER7_Val _U_(0x6) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 0.28 */
71#define OSCCTRL_DPLLCTRLB_FILTER_FILTER8_Val _U_(0x7) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 0.39 */
72#define OSCCTRL_DPLLCTRLB_FILTER_FILTER9_Val _U_(0x8) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 1.49 */
73#define OSCCTRL_DPLLCTRLB_FILTER_FILTER10_Val _U_(0x9) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 2.11 */
74#define OSCCTRL_DPLLCTRLB_FILTER_FILTER11_Val _U_(0xA) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 23.2Khz and Damping Factor = 0.75 */
75#define OSCCTRL_DPLLCTRLB_FILTER_FILTER12_Val _U_(0xB) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 32.8Khz and Damping Factor = 1.06 */
76#define OSCCTRL_DPLLCTRLB_FILTER_FILTER13_Val _U_(0xC) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 1.07 */
77#define OSCCTRL_DPLLCTRLB_FILTER_FILTER14_Val _U_(0xD) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 1.51 */
78#define OSCCTRL_DPLLCTRLB_FILTER_FILTER15_Val _U_(0xE) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 32.8Khz and Damping Factor = 0.53 */
79#define OSCCTRL_DPLLCTRLB_FILTER_FILTER16_Val _U_(0xF) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 0.75 */
80#define OSCCTRL_DPLLCTRLB_FILTER_FILTER1 (OSCCTRL_DPLLCTRLB_FILTER_FILTER1_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 0.76 Position */
81#define OSCCTRL_DPLLCTRLB_FILTER_FILTER2 (OSCCTRL_DPLLCTRLB_FILTER_FILTER2_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 131Khz and Damping Factor = 1.08 Position */
82#define OSCCTRL_DPLLCTRLB_FILTER_FILTER3 (OSCCTRL_DPLLCTRLB_FILTER_FILTER3_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 0.38 Position */
83#define OSCCTRL_DPLLCTRLB_FILTER_FILTER4 (OSCCTRL_DPLLCTRLB_FILTER_FILTER4_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 0.54 Position */
84#define OSCCTRL_DPLLCTRLB_FILTER_FILTER5 (OSCCTRL_DPLLCTRLB_FILTER_FILTER5_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 131Khz and Damping Factor = 0.56 Position */
85#define OSCCTRL_DPLLCTRLB_FILTER_FILTER6 (OSCCTRL_DPLLCTRLB_FILTER_FILTER6_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 185Khz and Damping Factor = 0.79 Position */
86#define OSCCTRL_DPLLCTRLB_FILTER_FILTER7 (OSCCTRL_DPLLCTRLB_FILTER_FILTER7_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 0.28 Position */
87#define OSCCTRL_DPLLCTRLB_FILTER_FILTER8 (OSCCTRL_DPLLCTRLB_FILTER_FILTER8_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 0.39 Position */
88#define OSCCTRL_DPLLCTRLB_FILTER_FILTER9 (OSCCTRL_DPLLCTRLB_FILTER_FILTER9_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 1.49 Position */
89#define OSCCTRL_DPLLCTRLB_FILTER_FILTER10 (OSCCTRL_DPLLCTRLB_FILTER_FILTER10_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 2.11 Position */
90#define OSCCTRL_DPLLCTRLB_FILTER_FILTER11 (OSCCTRL_DPLLCTRLB_FILTER_FILTER11_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 23.2Khz and Damping Factor = 0.75 Position */
91#define OSCCTRL_DPLLCTRLB_FILTER_FILTER12 (OSCCTRL_DPLLCTRLB_FILTER_FILTER12_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 32.8Khz and Damping Factor = 1.06 Position */
92#define OSCCTRL_DPLLCTRLB_FILTER_FILTER13 (OSCCTRL_DPLLCTRLB_FILTER_FILTER13_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 1.07 Position */
93#define OSCCTRL_DPLLCTRLB_FILTER_FILTER14 (OSCCTRL_DPLLCTRLB_FILTER_FILTER14_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 1.51 Position */
94#define OSCCTRL_DPLLCTRLB_FILTER_FILTER15 (OSCCTRL_DPLLCTRLB_FILTER_FILTER15_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 32.8Khz and Damping Factor = 0.53 Position */
95#define OSCCTRL_DPLLCTRLB_FILTER_FILTER16 (OSCCTRL_DPLLCTRLB_FILTER_FILTER16_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 0.75 Position */
96#define OSCCTRL_DPLLCTRLB_WUF_Pos _U_(4) /**< (OSCCTRL_DPLLCTRLB) Wake Up Fast Position */
97#define OSCCTRL_DPLLCTRLB_WUF_Msk (_U_(0x1) << OSCCTRL_DPLLCTRLB_WUF_Pos) /**< (OSCCTRL_DPLLCTRLB) Wake Up Fast Mask */
98#define OSCCTRL_DPLLCTRLB_WUF(value) (OSCCTRL_DPLLCTRLB_WUF_Msk & ((value) << OSCCTRL_DPLLCTRLB_WUF_Pos))
99#define OSCCTRL_DPLLCTRLB_REFCLK_Pos _U_(5) /**< (OSCCTRL_DPLLCTRLB) Reference Clock Selection Position */
100#define OSCCTRL_DPLLCTRLB_REFCLK_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /**< (OSCCTRL_DPLLCTRLB) Reference Clock Selection Mask */
101#define OSCCTRL_DPLLCTRLB_REFCLK(value) (OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos))
102#define OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val _U_(0x0) /**< (OSCCTRL_DPLLCTRLB) Dedicated GCLK clock reference */
103#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val _U_(0x1) /**< (OSCCTRL_DPLLCTRLB) XOSC32K clock reference */
104#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val _U_(0x2) /**< (OSCCTRL_DPLLCTRLB) XOSC0 clock reference */
105#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val _U_(0x3) /**< (OSCCTRL_DPLLCTRLB) XOSC1 clock reference */
106#define OSCCTRL_DPLLCTRLB_REFCLK_GCLK (OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /**< (OSCCTRL_DPLLCTRLB) Dedicated GCLK clock reference Position */
107#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /**< (OSCCTRL_DPLLCTRLB) XOSC32K clock reference Position */
108#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /**< (OSCCTRL_DPLLCTRLB) XOSC0 clock reference Position */
109#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /**< (OSCCTRL_DPLLCTRLB) XOSC1 clock reference Position */
110#define OSCCTRL_DPLLCTRLB_LTIME_Pos _U_(8) /**< (OSCCTRL_DPLLCTRLB) Lock Time Position */
111#define OSCCTRL_DPLLCTRLB_LTIME_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_LTIME_Pos) /**< (OSCCTRL_DPLLCTRLB) Lock Time Mask */
112#define OSCCTRL_DPLLCTRLB_LTIME(value) (OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos))
113#define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val _U_(0x0) /**< (OSCCTRL_DPLLCTRLB) No time-out. Automatic lock */
114#define OSCCTRL_DPLLCTRLB_LTIME_800US_Val _U_(0x4) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 800us */
115#define OSCCTRL_DPLLCTRLB_LTIME_900US_Val _U_(0x5) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 900us */
116#define OSCCTRL_DPLLCTRLB_LTIME_1MS_Val _U_(0x6) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1ms */
117#define OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val _U_(0x7) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1.1ms */
118#define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT (OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /**< (OSCCTRL_DPLLCTRLB) No time-out. Automatic lock Position */
119#define OSCCTRL_DPLLCTRLB_LTIME_800US (OSCCTRL_DPLLCTRLB_LTIME_800US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 800us Position */
120#define OSCCTRL_DPLLCTRLB_LTIME_900US (OSCCTRL_DPLLCTRLB_LTIME_900US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 900us Position */
121#define OSCCTRL_DPLLCTRLB_LTIME_1MS (OSCCTRL_DPLLCTRLB_LTIME_1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1ms Position */
122#define OSCCTRL_DPLLCTRLB_LTIME_1P1MS (OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1.1ms Position */
123#define OSCCTRL_DPLLCTRLB_LBYPASS_Pos _U_(11) /**< (OSCCTRL_DPLLCTRLB) Lock Bypass Position */
124#define OSCCTRL_DPLLCTRLB_LBYPASS_Msk (_U_(0x1) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) /**< (OSCCTRL_DPLLCTRLB) Lock Bypass Mask */
125#define OSCCTRL_DPLLCTRLB_LBYPASS(value) (OSCCTRL_DPLLCTRLB_LBYPASS_Msk & ((value) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos))
126#define OSCCTRL_DPLLCTRLB_DCOFILTER_Pos _U_(12) /**< (OSCCTRL_DPLLCTRLB) Sigma-Delta DCO Filter Selection Position */
127#define OSCCTRL_DPLLCTRLB_DCOFILTER_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Sigma-Delta DCO Filter Selection Mask */
128#define OSCCTRL_DPLLCTRLB_DCOFILTER(value) (OSCCTRL_DPLLCTRLB_DCOFILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos))
129#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER1_Val _U_(0x0) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21 */
130#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER2_Val _U_(0x1) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6 */
131#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER3_Val _U_(0x2) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1 */
132#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER4_Val _U_(0x3) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8 */
133#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER5_Val _U_(0x4) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64 */
134#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER6_Val _U_(0x5) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55 */
135#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER7_Val _U_(0x6) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45 */
136#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER8_Val _U_(0x7) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4 */
137#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER1 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER1_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21 Position */
138#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER2 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER2_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6 Position */
139#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER3 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER3_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1 Position */
140#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER4 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER4_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8 Position */
141#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER5 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER5_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64 Position */
142#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER6 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER6_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55 Position */
143#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER7 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER7_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45 Position */
144#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER8 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER8_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4 Position */
145#define OSCCTRL_DPLLCTRLB_DCOEN_Pos _U_(15) /**< (OSCCTRL_DPLLCTRLB) DCO Filter Enable Position */
146#define OSCCTRL_DPLLCTRLB_DCOEN_Msk (_U_(0x1) << OSCCTRL_DPLLCTRLB_DCOEN_Pos) /**< (OSCCTRL_DPLLCTRLB) DCO Filter Enable Mask */
147#define OSCCTRL_DPLLCTRLB_DCOEN(value) (OSCCTRL_DPLLCTRLB_DCOEN_Msk & ((value) << OSCCTRL_DPLLCTRLB_DCOEN_Pos))
148#define OSCCTRL_DPLLCTRLB_DIV_Pos _U_(16) /**< (OSCCTRL_DPLLCTRLB) Clock Divider Position */
149#define OSCCTRL_DPLLCTRLB_DIV_Msk (_U_(0x7FF) << OSCCTRL_DPLLCTRLB_DIV_Pos) /**< (OSCCTRL_DPLLCTRLB) Clock Divider Mask */
150#define OSCCTRL_DPLLCTRLB_DIV(value) (OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos))
151#define OSCCTRL_DPLLCTRLB_Msk _U_(0x07FFFFFF) /**< (OSCCTRL_DPLLCTRLB) Register Mask */
152
153
154/* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x0C) ( R/ 32) DPLL Synchronization Busy -------- */
155#define OSCCTRL_DPLLSYNCBUSY_RESETVALUE _U_(0x00) /**< (OSCCTRL_DPLLSYNCBUSY) DPLL Synchronization Busy Reset Value */
156
157#define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos _U_(1) /**< (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status Position */
158#define OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos) /**< (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status Mask */
159#define OSCCTRL_DPLLSYNCBUSY_ENABLE(value) (OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk & ((value) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos))
160#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos _U_(2) /**< (OSCCTRL_DPLLSYNCBUSY) DPLL Loop Divider Ratio Synchronization Status Position */
161#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos) /**< (OSCCTRL_DPLLSYNCBUSY) DPLL Loop Divider Ratio Synchronization Status Mask */
162#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO(value) (OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk & ((value) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos))
163#define OSCCTRL_DPLLSYNCBUSY_Msk _U_(0x00000006) /**< (OSCCTRL_DPLLSYNCBUSY) Register Mask */
164
165
166/* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x10) ( R/ 32) DPLL Status -------- */
167#define OSCCTRL_DPLLSTATUS_RESETVALUE _U_(0x00) /**< (OSCCTRL_DPLLSTATUS) DPLL Status Reset Value */
168
169#define OSCCTRL_DPLLSTATUS_LOCK_Pos _U_(0) /**< (OSCCTRL_DPLLSTATUS) DPLL Lock Status Position */
170#define OSCCTRL_DPLLSTATUS_LOCK_Msk (_U_(0x1) << OSCCTRL_DPLLSTATUS_LOCK_Pos) /**< (OSCCTRL_DPLLSTATUS) DPLL Lock Status Mask */
171#define OSCCTRL_DPLLSTATUS_LOCK(value) (OSCCTRL_DPLLSTATUS_LOCK_Msk & ((value) << OSCCTRL_DPLLSTATUS_LOCK_Pos))
172#define OSCCTRL_DPLLSTATUS_CLKRDY_Pos _U_(1) /**< (OSCCTRL_DPLLSTATUS) DPLL Clock Ready Position */
173#define OSCCTRL_DPLLSTATUS_CLKRDY_Msk (_U_(0x1) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos) /**< (OSCCTRL_DPLLSTATUS) DPLL Clock Ready Mask */
174#define OSCCTRL_DPLLSTATUS_CLKRDY(value) (OSCCTRL_DPLLSTATUS_CLKRDY_Msk & ((value) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos))
175#define OSCCTRL_DPLLSTATUS_Msk _U_(0x00000003) /**< (OSCCTRL_DPLLSTATUS) Register Mask */
176
177
178/* -------- OSCCTRL_EVCTRL : (OSCCTRL Offset: 0x00) (R/W 8) Event Control -------- */
179#define OSCCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< (OSCCTRL_EVCTRL) Event Control Reset Value */
180
181#define OSCCTRL_EVCTRL_CFDEO0_Pos _U_(0) /**< (OSCCTRL_EVCTRL) Clock 0 Failure Detector Event Output Enable Position */
182#define OSCCTRL_EVCTRL_CFDEO0_Msk (_U_(0x1) << OSCCTRL_EVCTRL_CFDEO0_Pos) /**< (OSCCTRL_EVCTRL) Clock 0 Failure Detector Event Output Enable Mask */
183#define OSCCTRL_EVCTRL_CFDEO0(value) (OSCCTRL_EVCTRL_CFDEO0_Msk & ((value) << OSCCTRL_EVCTRL_CFDEO0_Pos))
184#define OSCCTRL_EVCTRL_CFDEO1_Pos _U_(1) /**< (OSCCTRL_EVCTRL) Clock 1 Failure Detector Event Output Enable Position */
185#define OSCCTRL_EVCTRL_CFDEO1_Msk (_U_(0x1) << OSCCTRL_EVCTRL_CFDEO1_Pos) /**< (OSCCTRL_EVCTRL) Clock 1 Failure Detector Event Output Enable Mask */
186#define OSCCTRL_EVCTRL_CFDEO1(value) (OSCCTRL_EVCTRL_CFDEO1_Msk & ((value) << OSCCTRL_EVCTRL_CFDEO1_Pos))
187#define OSCCTRL_EVCTRL_Msk _U_(0x03) /**< (OSCCTRL_EVCTRL) Register Mask */
188
189#define OSCCTRL_EVCTRL_CFDEO_Pos _U_(0) /**< (OSCCTRL_EVCTRL Position) Clock x Failure Detector Event Output Enable */
190#define OSCCTRL_EVCTRL_CFDEO_Msk (_U_(0x3) << OSCCTRL_EVCTRL_CFDEO_Pos) /**< (OSCCTRL_EVCTRL Mask) CFDEO */
191#define OSCCTRL_EVCTRL_CFDEO(value) (OSCCTRL_EVCTRL_CFDEO_Msk & ((value) << OSCCTRL_EVCTRL_CFDEO_Pos))
192
193/* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Clear -------- */
194#define OSCCTRL_INTENCLR_RESETVALUE _U_(0x00) /**< (OSCCTRL_INTENCLR) Interrupt Enable Clear Reset Value */
195
196#define OSCCTRL_INTENCLR_XOSCRDY0_Pos _U_(0) /**< (OSCCTRL_INTENCLR) XOSC 0 Ready Interrupt Enable Position */
197#define OSCCTRL_INTENCLR_XOSCRDY0_Msk (_U_(0x1) << OSCCTRL_INTENCLR_XOSCRDY0_Pos) /**< (OSCCTRL_INTENCLR) XOSC 0 Ready Interrupt Enable Mask */
198#define OSCCTRL_INTENCLR_XOSCRDY0(value) (OSCCTRL_INTENCLR_XOSCRDY0_Msk & ((value) << OSCCTRL_INTENCLR_XOSCRDY0_Pos))
199#define OSCCTRL_INTENCLR_XOSCRDY1_Pos _U_(1) /**< (OSCCTRL_INTENCLR) XOSC 1 Ready Interrupt Enable Position */
200#define OSCCTRL_INTENCLR_XOSCRDY1_Msk (_U_(0x1) << OSCCTRL_INTENCLR_XOSCRDY1_Pos) /**< (OSCCTRL_INTENCLR) XOSC 1 Ready Interrupt Enable Mask */
201#define OSCCTRL_INTENCLR_XOSCRDY1(value) (OSCCTRL_INTENCLR_XOSCRDY1_Msk & ((value) << OSCCTRL_INTENCLR_XOSCRDY1_Pos))
202#define OSCCTRL_INTENCLR_XOSCFAIL0_Pos _U_(2) /**< (OSCCTRL_INTENCLR) XOSC 0 Clock Failure Detector Interrupt Enable Position */
203#define OSCCTRL_INTENCLR_XOSCFAIL0_Msk (_U_(0x1) << OSCCTRL_INTENCLR_XOSCFAIL0_Pos) /**< (OSCCTRL_INTENCLR) XOSC 0 Clock Failure Detector Interrupt Enable Mask */
204#define OSCCTRL_INTENCLR_XOSCFAIL0(value) (OSCCTRL_INTENCLR_XOSCFAIL0_Msk & ((value) << OSCCTRL_INTENCLR_XOSCFAIL0_Pos))
205#define OSCCTRL_INTENCLR_XOSCFAIL1_Pos _U_(3) /**< (OSCCTRL_INTENCLR) XOSC 1 Clock Failure Detector Interrupt Enable Position */
206#define OSCCTRL_INTENCLR_XOSCFAIL1_Msk (_U_(0x1) << OSCCTRL_INTENCLR_XOSCFAIL1_Pos) /**< (OSCCTRL_INTENCLR) XOSC 1 Clock Failure Detector Interrupt Enable Mask */
207#define OSCCTRL_INTENCLR_XOSCFAIL1(value) (OSCCTRL_INTENCLR_XOSCFAIL1_Msk & ((value) << OSCCTRL_INTENCLR_XOSCFAIL1_Pos))
208#define OSCCTRL_INTENCLR_DFLLRDY_Pos _U_(8) /**< (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable Position */
209#define OSCCTRL_INTENCLR_DFLLRDY_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRDY_Pos) /**< (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable Mask */
210#define OSCCTRL_INTENCLR_DFLLRDY(value) (OSCCTRL_INTENCLR_DFLLRDY_Msk & ((value) << OSCCTRL_INTENCLR_DFLLRDY_Pos))
211#define OSCCTRL_INTENCLR_DFLLOOB_Pos _U_(9) /**< (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable Position */
212#define OSCCTRL_INTENCLR_DFLLOOB_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DFLLOOB_Pos) /**< (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable Mask */
213#define OSCCTRL_INTENCLR_DFLLOOB(value) (OSCCTRL_INTENCLR_DFLLOOB_Msk & ((value) << OSCCTRL_INTENCLR_DFLLOOB_Pos))
214#define OSCCTRL_INTENCLR_DFLLLCKF_Pos _U_(10) /**< (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable Position */
215#define OSCCTRL_INTENCLR_DFLLLCKF_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKF_Pos) /**< (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable Mask */
216#define OSCCTRL_INTENCLR_DFLLLCKF(value) (OSCCTRL_INTENCLR_DFLLLCKF_Msk & ((value) << OSCCTRL_INTENCLR_DFLLLCKF_Pos))
217#define OSCCTRL_INTENCLR_DFLLLCKC_Pos _U_(11) /**< (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable Position */
218#define OSCCTRL_INTENCLR_DFLLLCKC_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKC_Pos) /**< (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable Mask */
219#define OSCCTRL_INTENCLR_DFLLLCKC(value) (OSCCTRL_INTENCLR_DFLLLCKC_Msk & ((value) << OSCCTRL_INTENCLR_DFLLLCKC_Pos))
220#define OSCCTRL_INTENCLR_DFLLRCS_Pos _U_(12) /**< (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable Position */
221#define OSCCTRL_INTENCLR_DFLLRCS_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRCS_Pos) /**< (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable Mask */
222#define OSCCTRL_INTENCLR_DFLLRCS(value) (OSCCTRL_INTENCLR_DFLLRCS_Msk & ((value) << OSCCTRL_INTENCLR_DFLLRCS_Pos))
223#define OSCCTRL_INTENCLR_DPLL0LCKR_Pos _U_(16) /**< (OSCCTRL_INTENCLR) DPLL0 Lock Rise Interrupt Enable Position */
224#define OSCCTRL_INTENCLR_DPLL0LCKR_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKR_Pos) /**< (OSCCTRL_INTENCLR) DPLL0 Lock Rise Interrupt Enable Mask */
225#define OSCCTRL_INTENCLR_DPLL0LCKR(value) (OSCCTRL_INTENCLR_DPLL0LCKR_Msk & ((value) << OSCCTRL_INTENCLR_DPLL0LCKR_Pos))
226#define OSCCTRL_INTENCLR_DPLL0LCKF_Pos _U_(17) /**< (OSCCTRL_INTENCLR) DPLL0 Lock Fall Interrupt Enable Position */
227#define OSCCTRL_INTENCLR_DPLL0LCKF_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKF_Pos) /**< (OSCCTRL_INTENCLR) DPLL0 Lock Fall Interrupt Enable Mask */
228#define OSCCTRL_INTENCLR_DPLL0LCKF(value) (OSCCTRL_INTENCLR_DPLL0LCKF_Msk & ((value) << OSCCTRL_INTENCLR_DPLL0LCKF_Pos))
229#define OSCCTRL_INTENCLR_DPLL0LTO_Pos _U_(18) /**< (OSCCTRL_INTENCLR) DPLL0 Lock Timeout Interrupt Enable Position */
230#define OSCCTRL_INTENCLR_DPLL0LTO_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LTO_Pos) /**< (OSCCTRL_INTENCLR) DPLL0 Lock Timeout Interrupt Enable Mask */
231#define OSCCTRL_INTENCLR_DPLL0LTO(value) (OSCCTRL_INTENCLR_DPLL0LTO_Msk & ((value) << OSCCTRL_INTENCLR_DPLL0LTO_Pos))
232#define OSCCTRL_INTENCLR_DPLL0LDRTO_Pos _U_(19) /**< (OSCCTRL_INTENCLR) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable Position */
233#define OSCCTRL_INTENCLR_DPLL0LDRTO_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LDRTO_Pos) /**< (OSCCTRL_INTENCLR) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable Mask */
234#define OSCCTRL_INTENCLR_DPLL0LDRTO(value) (OSCCTRL_INTENCLR_DPLL0LDRTO_Msk & ((value) << OSCCTRL_INTENCLR_DPLL0LDRTO_Pos))
235#define OSCCTRL_INTENCLR_DPLL1LCKR_Pos _U_(24) /**< (OSCCTRL_INTENCLR) DPLL1 Lock Rise Interrupt Enable Position */
236#define OSCCTRL_INTENCLR_DPLL1LCKR_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKR_Pos) /**< (OSCCTRL_INTENCLR) DPLL1 Lock Rise Interrupt Enable Mask */
237#define OSCCTRL_INTENCLR_DPLL1LCKR(value) (OSCCTRL_INTENCLR_DPLL1LCKR_Msk & ((value) << OSCCTRL_INTENCLR_DPLL1LCKR_Pos))
238#define OSCCTRL_INTENCLR_DPLL1LCKF_Pos _U_(25) /**< (OSCCTRL_INTENCLR) DPLL1 Lock Fall Interrupt Enable Position */
239#define OSCCTRL_INTENCLR_DPLL1LCKF_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKF_Pos) /**< (OSCCTRL_INTENCLR) DPLL1 Lock Fall Interrupt Enable Mask */
240#define OSCCTRL_INTENCLR_DPLL1LCKF(value) (OSCCTRL_INTENCLR_DPLL1LCKF_Msk & ((value) << OSCCTRL_INTENCLR_DPLL1LCKF_Pos))
241#define OSCCTRL_INTENCLR_DPLL1LTO_Pos _U_(26) /**< (OSCCTRL_INTENCLR) DPLL1 Lock Timeout Interrupt Enable Position */
242#define OSCCTRL_INTENCLR_DPLL1LTO_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LTO_Pos) /**< (OSCCTRL_INTENCLR) DPLL1 Lock Timeout Interrupt Enable Mask */
243#define OSCCTRL_INTENCLR_DPLL1LTO(value) (OSCCTRL_INTENCLR_DPLL1LTO_Msk & ((value) << OSCCTRL_INTENCLR_DPLL1LTO_Pos))
244#define OSCCTRL_INTENCLR_DPLL1LDRTO_Pos _U_(27) /**< (OSCCTRL_INTENCLR) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable Position */
245#define OSCCTRL_INTENCLR_DPLL1LDRTO_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LDRTO_Pos) /**< (OSCCTRL_INTENCLR) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable Mask */
246#define OSCCTRL_INTENCLR_DPLL1LDRTO(value) (OSCCTRL_INTENCLR_DPLL1LDRTO_Msk & ((value) << OSCCTRL_INTENCLR_DPLL1LDRTO_Pos))
247#define OSCCTRL_INTENCLR_Msk _U_(0x0F0F1F0F) /**< (OSCCTRL_INTENCLR) Register Mask */
248
249#define OSCCTRL_INTENCLR_XOSCRDY_Pos _U_(0) /**< (OSCCTRL_INTENCLR Position) XOSC x Ready Interrupt Enable */
250#define OSCCTRL_INTENCLR_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCRDY_Pos) /**< (OSCCTRL_INTENCLR Mask) XOSCRDY */
251#define OSCCTRL_INTENCLR_XOSCRDY(value) (OSCCTRL_INTENCLR_XOSCRDY_Msk & ((value) << OSCCTRL_INTENCLR_XOSCRDY_Pos))
252#define OSCCTRL_INTENCLR_XOSCFAIL_Pos _U_(2) /**< (OSCCTRL_INTENCLR Position) XOSC x Clock Failure Detector Interrupt Enable */
253#define OSCCTRL_INTENCLR_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCFAIL_Pos) /**< (OSCCTRL_INTENCLR Mask) XOSCFAIL */
254#define OSCCTRL_INTENCLR_XOSCFAIL(value) (OSCCTRL_INTENCLR_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENCLR_XOSCFAIL_Pos))
255
256/* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Enable Set -------- */
257#define OSCCTRL_INTENSET_RESETVALUE _U_(0x00) /**< (OSCCTRL_INTENSET) Interrupt Enable Set Reset Value */
258
259#define OSCCTRL_INTENSET_XOSCRDY0_Pos _U_(0) /**< (OSCCTRL_INTENSET) XOSC 0 Ready Interrupt Enable Position */
260#define OSCCTRL_INTENSET_XOSCRDY0_Msk (_U_(0x1) << OSCCTRL_INTENSET_XOSCRDY0_Pos) /**< (OSCCTRL_INTENSET) XOSC 0 Ready Interrupt Enable Mask */
261#define OSCCTRL_INTENSET_XOSCRDY0(value) (OSCCTRL_INTENSET_XOSCRDY0_Msk & ((value) << OSCCTRL_INTENSET_XOSCRDY0_Pos))
262#define OSCCTRL_INTENSET_XOSCRDY1_Pos _U_(1) /**< (OSCCTRL_INTENSET) XOSC 1 Ready Interrupt Enable Position */
263#define OSCCTRL_INTENSET_XOSCRDY1_Msk (_U_(0x1) << OSCCTRL_INTENSET_XOSCRDY1_Pos) /**< (OSCCTRL_INTENSET) XOSC 1 Ready Interrupt Enable Mask */
264#define OSCCTRL_INTENSET_XOSCRDY1(value) (OSCCTRL_INTENSET_XOSCRDY1_Msk & ((value) << OSCCTRL_INTENSET_XOSCRDY1_Pos))
265#define OSCCTRL_INTENSET_XOSCFAIL0_Pos _U_(2) /**< (OSCCTRL_INTENSET) XOSC 0 Clock Failure Detector Interrupt Enable Position */
266#define OSCCTRL_INTENSET_XOSCFAIL0_Msk (_U_(0x1) << OSCCTRL_INTENSET_XOSCFAIL0_Pos) /**< (OSCCTRL_INTENSET) XOSC 0 Clock Failure Detector Interrupt Enable Mask */
267#define OSCCTRL_INTENSET_XOSCFAIL0(value) (OSCCTRL_INTENSET_XOSCFAIL0_Msk & ((value) << OSCCTRL_INTENSET_XOSCFAIL0_Pos))
268#define OSCCTRL_INTENSET_XOSCFAIL1_Pos _U_(3) /**< (OSCCTRL_INTENSET) XOSC 1 Clock Failure Detector Interrupt Enable Position */
269#define OSCCTRL_INTENSET_XOSCFAIL1_Msk (_U_(0x1) << OSCCTRL_INTENSET_XOSCFAIL1_Pos) /**< (OSCCTRL_INTENSET) XOSC 1 Clock Failure Detector Interrupt Enable Mask */
270#define OSCCTRL_INTENSET_XOSCFAIL1(value) (OSCCTRL_INTENSET_XOSCFAIL1_Msk & ((value) << OSCCTRL_INTENSET_XOSCFAIL1_Pos))
271#define OSCCTRL_INTENSET_DFLLRDY_Pos _U_(8) /**< (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable Position */
272#define OSCCTRL_INTENSET_DFLLRDY_Msk (_U_(0x1) << OSCCTRL_INTENSET_DFLLRDY_Pos) /**< (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable Mask */
273#define OSCCTRL_INTENSET_DFLLRDY(value) (OSCCTRL_INTENSET_DFLLRDY_Msk & ((value) << OSCCTRL_INTENSET_DFLLRDY_Pos))
274#define OSCCTRL_INTENSET_DFLLOOB_Pos _U_(9) /**< (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable Position */
275#define OSCCTRL_INTENSET_DFLLOOB_Msk (_U_(0x1) << OSCCTRL_INTENSET_DFLLOOB_Pos) /**< (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable Mask */
276#define OSCCTRL_INTENSET_DFLLOOB(value) (OSCCTRL_INTENSET_DFLLOOB_Msk & ((value) << OSCCTRL_INTENSET_DFLLOOB_Pos))
277#define OSCCTRL_INTENSET_DFLLLCKF_Pos _U_(10) /**< (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable Position */
278#define OSCCTRL_INTENSET_DFLLLCKF_Msk (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKF_Pos) /**< (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable Mask */
279#define OSCCTRL_INTENSET_DFLLLCKF(value) (OSCCTRL_INTENSET_DFLLLCKF_Msk & ((value) << OSCCTRL_INTENSET_DFLLLCKF_Pos))
280#define OSCCTRL_INTENSET_DFLLLCKC_Pos _U_(11) /**< (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable Position */
281#define OSCCTRL_INTENSET_DFLLLCKC_Msk (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKC_Pos) /**< (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable Mask */
282#define OSCCTRL_INTENSET_DFLLLCKC(value) (OSCCTRL_INTENSET_DFLLLCKC_Msk & ((value) << OSCCTRL_INTENSET_DFLLLCKC_Pos))
283#define OSCCTRL_INTENSET_DFLLRCS_Pos _U_(12) /**< (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable Position */
284#define OSCCTRL_INTENSET_DFLLRCS_Msk (_U_(0x1) << OSCCTRL_INTENSET_DFLLRCS_Pos) /**< (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable Mask */
285#define OSCCTRL_INTENSET_DFLLRCS(value) (OSCCTRL_INTENSET_DFLLRCS_Msk & ((value) << OSCCTRL_INTENSET_DFLLRCS_Pos))
286#define OSCCTRL_INTENSET_DPLL0LCKR_Pos _U_(16) /**< (OSCCTRL_INTENSET) DPLL0 Lock Rise Interrupt Enable Position */
287#define OSCCTRL_INTENSET_DPLL0LCKR_Msk (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKR_Pos) /**< (OSCCTRL_INTENSET) DPLL0 Lock Rise Interrupt Enable Mask */
288#define OSCCTRL_INTENSET_DPLL0LCKR(value) (OSCCTRL_INTENSET_DPLL0LCKR_Msk & ((value) << OSCCTRL_INTENSET_DPLL0LCKR_Pos))
289#define OSCCTRL_INTENSET_DPLL0LCKF_Pos _U_(17) /**< (OSCCTRL_INTENSET) DPLL0 Lock Fall Interrupt Enable Position */
290#define OSCCTRL_INTENSET_DPLL0LCKF_Msk (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKF_Pos) /**< (OSCCTRL_INTENSET) DPLL0 Lock Fall Interrupt Enable Mask */
291#define OSCCTRL_INTENSET_DPLL0LCKF(value) (OSCCTRL_INTENSET_DPLL0LCKF_Msk & ((value) << OSCCTRL_INTENSET_DPLL0LCKF_Pos))
292#define OSCCTRL_INTENSET_DPLL0LTO_Pos _U_(18) /**< (OSCCTRL_INTENSET) DPLL0 Lock Timeout Interrupt Enable Position */
293#define OSCCTRL_INTENSET_DPLL0LTO_Msk (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LTO_Pos) /**< (OSCCTRL_INTENSET) DPLL0 Lock Timeout Interrupt Enable Mask */
294#define OSCCTRL_INTENSET_DPLL0LTO(value) (OSCCTRL_INTENSET_DPLL0LTO_Msk & ((value) << OSCCTRL_INTENSET_DPLL0LTO_Pos))
295#define OSCCTRL_INTENSET_DPLL0LDRTO_Pos _U_(19) /**< (OSCCTRL_INTENSET) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable Position */
296#define OSCCTRL_INTENSET_DPLL0LDRTO_Msk (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LDRTO_Pos) /**< (OSCCTRL_INTENSET) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable Mask */
297#define OSCCTRL_INTENSET_DPLL0LDRTO(value) (OSCCTRL_INTENSET_DPLL0LDRTO_Msk & ((value) << OSCCTRL_INTENSET_DPLL0LDRTO_Pos))
298#define OSCCTRL_INTENSET_DPLL1LCKR_Pos _U_(24) /**< (OSCCTRL_INTENSET) DPLL1 Lock Rise Interrupt Enable Position */
299#define OSCCTRL_INTENSET_DPLL1LCKR_Msk (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKR_Pos) /**< (OSCCTRL_INTENSET) DPLL1 Lock Rise Interrupt Enable Mask */
300#define OSCCTRL_INTENSET_DPLL1LCKR(value) (OSCCTRL_INTENSET_DPLL1LCKR_Msk & ((value) << OSCCTRL_INTENSET_DPLL1LCKR_Pos))
301#define OSCCTRL_INTENSET_DPLL1LCKF_Pos _U_(25) /**< (OSCCTRL_INTENSET) DPLL1 Lock Fall Interrupt Enable Position */
302#define OSCCTRL_INTENSET_DPLL1LCKF_Msk (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKF_Pos) /**< (OSCCTRL_INTENSET) DPLL1 Lock Fall Interrupt Enable Mask */
303#define OSCCTRL_INTENSET_DPLL1LCKF(value) (OSCCTRL_INTENSET_DPLL1LCKF_Msk & ((value) << OSCCTRL_INTENSET_DPLL1LCKF_Pos))
304#define OSCCTRL_INTENSET_DPLL1LTO_Pos _U_(26) /**< (OSCCTRL_INTENSET) DPLL1 Lock Timeout Interrupt Enable Position */
305#define OSCCTRL_INTENSET_DPLL1LTO_Msk (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LTO_Pos) /**< (OSCCTRL_INTENSET) DPLL1 Lock Timeout Interrupt Enable Mask */
306#define OSCCTRL_INTENSET_DPLL1LTO(value) (OSCCTRL_INTENSET_DPLL1LTO_Msk & ((value) << OSCCTRL_INTENSET_DPLL1LTO_Pos))
307#define OSCCTRL_INTENSET_DPLL1LDRTO_Pos _U_(27) /**< (OSCCTRL_INTENSET) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable Position */
308#define OSCCTRL_INTENSET_DPLL1LDRTO_Msk (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LDRTO_Pos) /**< (OSCCTRL_INTENSET) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable Mask */
309#define OSCCTRL_INTENSET_DPLL1LDRTO(value) (OSCCTRL_INTENSET_DPLL1LDRTO_Msk & ((value) << OSCCTRL_INTENSET_DPLL1LDRTO_Pos))
310#define OSCCTRL_INTENSET_Msk _U_(0x0F0F1F0F) /**< (OSCCTRL_INTENSET) Register Mask */
311
312#define OSCCTRL_INTENSET_XOSCRDY_Pos _U_(0) /**< (OSCCTRL_INTENSET Position) XOSC x Ready Interrupt Enable */
313#define OSCCTRL_INTENSET_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCRDY_Pos) /**< (OSCCTRL_INTENSET Mask) XOSCRDY */
314#define OSCCTRL_INTENSET_XOSCRDY(value) (OSCCTRL_INTENSET_XOSCRDY_Msk & ((value) << OSCCTRL_INTENSET_XOSCRDY_Pos))
315#define OSCCTRL_INTENSET_XOSCFAIL_Pos _U_(2) /**< (OSCCTRL_INTENSET Position) XOSC x Clock Failure Detector Interrupt Enable */
316#define OSCCTRL_INTENSET_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCFAIL_Pos) /**< (OSCCTRL_INTENSET Mask) XOSCFAIL */
317#define OSCCTRL_INTENSET_XOSCFAIL(value) (OSCCTRL_INTENSET_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENSET_XOSCFAIL_Pos))
318
319/* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x0C) (R/W 32) Interrupt Flag Status and Clear -------- */
320#define OSCCTRL_INTFLAG_RESETVALUE _U_(0x00) /**< (OSCCTRL_INTFLAG) Interrupt Flag Status and Clear Reset Value */
321
322#define OSCCTRL_INTFLAG_XOSCRDY0_Pos _U_(0) /**< (OSCCTRL_INTFLAG) XOSC 0 Ready Position */
323#define OSCCTRL_INTFLAG_XOSCRDY0_Msk (_U_(0x1) << OSCCTRL_INTFLAG_XOSCRDY0_Pos) /**< (OSCCTRL_INTFLAG) XOSC 0 Ready Mask */
324#define OSCCTRL_INTFLAG_XOSCRDY0(value) (OSCCTRL_INTFLAG_XOSCRDY0_Msk & ((value) << OSCCTRL_INTFLAG_XOSCRDY0_Pos))
325#define OSCCTRL_INTFLAG_XOSCRDY1_Pos _U_(1) /**< (OSCCTRL_INTFLAG) XOSC 1 Ready Position */
326#define OSCCTRL_INTFLAG_XOSCRDY1_Msk (_U_(0x1) << OSCCTRL_INTFLAG_XOSCRDY1_Pos) /**< (OSCCTRL_INTFLAG) XOSC 1 Ready Mask */
327#define OSCCTRL_INTFLAG_XOSCRDY1(value) (OSCCTRL_INTFLAG_XOSCRDY1_Msk & ((value) << OSCCTRL_INTFLAG_XOSCRDY1_Pos))
328#define OSCCTRL_INTFLAG_XOSCFAIL0_Pos _U_(2) /**< (OSCCTRL_INTFLAG) XOSC 0 Clock Failure Detector Position */
329#define OSCCTRL_INTFLAG_XOSCFAIL0_Msk (_U_(0x1) << OSCCTRL_INTFLAG_XOSCFAIL0_Pos) /**< (OSCCTRL_INTFLAG) XOSC 0 Clock Failure Detector Mask */
330#define OSCCTRL_INTFLAG_XOSCFAIL0(value) (OSCCTRL_INTFLAG_XOSCFAIL0_Msk & ((value) << OSCCTRL_INTFLAG_XOSCFAIL0_Pos))
331#define OSCCTRL_INTFLAG_XOSCFAIL1_Pos _U_(3) /**< (OSCCTRL_INTFLAG) XOSC 1 Clock Failure Detector Position */
332#define OSCCTRL_INTFLAG_XOSCFAIL1_Msk (_U_(0x1) << OSCCTRL_INTFLAG_XOSCFAIL1_Pos) /**< (OSCCTRL_INTFLAG) XOSC 1 Clock Failure Detector Mask */
333#define OSCCTRL_INTFLAG_XOSCFAIL1(value) (OSCCTRL_INTFLAG_XOSCFAIL1_Msk & ((value) << OSCCTRL_INTFLAG_XOSCFAIL1_Pos))
334#define OSCCTRL_INTFLAG_DFLLRDY_Pos _U_(8) /**< (OSCCTRL_INTFLAG) DFLL Ready Position */
335#define OSCCTRL_INTFLAG_DFLLRDY_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRDY_Pos) /**< (OSCCTRL_INTFLAG) DFLL Ready Mask */
336#define OSCCTRL_INTFLAG_DFLLRDY(value) (OSCCTRL_INTFLAG_DFLLRDY_Msk & ((value) << OSCCTRL_INTFLAG_DFLLRDY_Pos))
337#define OSCCTRL_INTFLAG_DFLLOOB_Pos _U_(9) /**< (OSCCTRL_INTFLAG) DFLL Out Of Bounds Position */
338#define OSCCTRL_INTFLAG_DFLLOOB_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DFLLOOB_Pos) /**< (OSCCTRL_INTFLAG) DFLL Out Of Bounds Mask */
339#define OSCCTRL_INTFLAG_DFLLOOB(value) (OSCCTRL_INTFLAG_DFLLOOB_Msk & ((value) << OSCCTRL_INTFLAG_DFLLOOB_Pos))
340#define OSCCTRL_INTFLAG_DFLLLCKF_Pos _U_(10) /**< (OSCCTRL_INTFLAG) DFLL Lock Fine Position */
341#define OSCCTRL_INTFLAG_DFLLLCKF_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKF_Pos) /**< (OSCCTRL_INTFLAG) DFLL Lock Fine Mask */
342#define OSCCTRL_INTFLAG_DFLLLCKF(value) (OSCCTRL_INTFLAG_DFLLLCKF_Msk & ((value) << OSCCTRL_INTFLAG_DFLLLCKF_Pos))
343#define OSCCTRL_INTFLAG_DFLLLCKC_Pos _U_(11) /**< (OSCCTRL_INTFLAG) DFLL Lock Coarse Position */
344#define OSCCTRL_INTFLAG_DFLLLCKC_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKC_Pos) /**< (OSCCTRL_INTFLAG) DFLL Lock Coarse Mask */
345#define OSCCTRL_INTFLAG_DFLLLCKC(value) (OSCCTRL_INTFLAG_DFLLLCKC_Msk & ((value) << OSCCTRL_INTFLAG_DFLLLCKC_Pos))
346#define OSCCTRL_INTFLAG_DFLLRCS_Pos _U_(12) /**< (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped Position */
347#define OSCCTRL_INTFLAG_DFLLRCS_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRCS_Pos) /**< (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped Mask */
348#define OSCCTRL_INTFLAG_DFLLRCS(value) (OSCCTRL_INTFLAG_DFLLRCS_Msk & ((value) << OSCCTRL_INTFLAG_DFLLRCS_Pos))
349#define OSCCTRL_INTFLAG_DPLL0LCKR_Pos _U_(16) /**< (OSCCTRL_INTFLAG) DPLL0 Lock Rise Position */
350#define OSCCTRL_INTFLAG_DPLL0LCKR_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKR_Pos) /**< (OSCCTRL_INTFLAG) DPLL0 Lock Rise Mask */
351#define OSCCTRL_INTFLAG_DPLL0LCKR(value) (OSCCTRL_INTFLAG_DPLL0LCKR_Msk & ((value) << OSCCTRL_INTFLAG_DPLL0LCKR_Pos))
352#define OSCCTRL_INTFLAG_DPLL0LCKF_Pos _U_(17) /**< (OSCCTRL_INTFLAG) DPLL0 Lock Fall Position */
353#define OSCCTRL_INTFLAG_DPLL0LCKF_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKF_Pos) /**< (OSCCTRL_INTFLAG) DPLL0 Lock Fall Mask */
354#define OSCCTRL_INTFLAG_DPLL0LCKF(value) (OSCCTRL_INTFLAG_DPLL0LCKF_Msk & ((value) << OSCCTRL_INTFLAG_DPLL0LCKF_Pos))
355#define OSCCTRL_INTFLAG_DPLL0LTO_Pos _U_(18) /**< (OSCCTRL_INTFLAG) DPLL0 Lock Timeout Position */
356#define OSCCTRL_INTFLAG_DPLL0LTO_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LTO_Pos) /**< (OSCCTRL_INTFLAG) DPLL0 Lock Timeout Mask */
357#define OSCCTRL_INTFLAG_DPLL0LTO(value) (OSCCTRL_INTFLAG_DPLL0LTO_Msk & ((value) << OSCCTRL_INTFLAG_DPLL0LTO_Pos))
358#define OSCCTRL_INTFLAG_DPLL0LDRTO_Pos _U_(19) /**< (OSCCTRL_INTFLAG) DPLL0 Loop Divider Ratio Update Complete Position */
359#define OSCCTRL_INTFLAG_DPLL0LDRTO_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LDRTO_Pos) /**< (OSCCTRL_INTFLAG) DPLL0 Loop Divider Ratio Update Complete Mask */
360#define OSCCTRL_INTFLAG_DPLL0LDRTO(value) (OSCCTRL_INTFLAG_DPLL0LDRTO_Msk & ((value) << OSCCTRL_INTFLAG_DPLL0LDRTO_Pos))
361#define OSCCTRL_INTFLAG_DPLL1LCKR_Pos _U_(24) /**< (OSCCTRL_INTFLAG) DPLL1 Lock Rise Position */
362#define OSCCTRL_INTFLAG_DPLL1LCKR_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKR_Pos) /**< (OSCCTRL_INTFLAG) DPLL1 Lock Rise Mask */
363#define OSCCTRL_INTFLAG_DPLL1LCKR(value) (OSCCTRL_INTFLAG_DPLL1LCKR_Msk & ((value) << OSCCTRL_INTFLAG_DPLL1LCKR_Pos))
364#define OSCCTRL_INTFLAG_DPLL1LCKF_Pos _U_(25) /**< (OSCCTRL_INTFLAG) DPLL1 Lock Fall Position */
365#define OSCCTRL_INTFLAG_DPLL1LCKF_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKF_Pos) /**< (OSCCTRL_INTFLAG) DPLL1 Lock Fall Mask */
366#define OSCCTRL_INTFLAG_DPLL1LCKF(value) (OSCCTRL_INTFLAG_DPLL1LCKF_Msk & ((value) << OSCCTRL_INTFLAG_DPLL1LCKF_Pos))
367#define OSCCTRL_INTFLAG_DPLL1LTO_Pos _U_(26) /**< (OSCCTRL_INTFLAG) DPLL1 Lock Timeout Position */
368#define OSCCTRL_INTFLAG_DPLL1LTO_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LTO_Pos) /**< (OSCCTRL_INTFLAG) DPLL1 Lock Timeout Mask */
369#define OSCCTRL_INTFLAG_DPLL1LTO(value) (OSCCTRL_INTFLAG_DPLL1LTO_Msk & ((value) << OSCCTRL_INTFLAG_DPLL1LTO_Pos))
370#define OSCCTRL_INTFLAG_DPLL1LDRTO_Pos _U_(27) /**< (OSCCTRL_INTFLAG) DPLL1 Loop Divider Ratio Update Complete Position */
371#define OSCCTRL_INTFLAG_DPLL1LDRTO_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LDRTO_Pos) /**< (OSCCTRL_INTFLAG) DPLL1 Loop Divider Ratio Update Complete Mask */
372#define OSCCTRL_INTFLAG_DPLL1LDRTO(value) (OSCCTRL_INTFLAG_DPLL1LDRTO_Msk & ((value) << OSCCTRL_INTFLAG_DPLL1LDRTO_Pos))
373#define OSCCTRL_INTFLAG_Msk _U_(0x0F0F1F0F) /**< (OSCCTRL_INTFLAG) Register Mask */
374
375#define OSCCTRL_INTFLAG_XOSCRDY_Pos _U_(0) /**< (OSCCTRL_INTFLAG Position) XOSC x Ready */
376#define OSCCTRL_INTFLAG_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCRDY_Pos) /**< (OSCCTRL_INTFLAG Mask) XOSCRDY */
377#define OSCCTRL_INTFLAG_XOSCRDY(value) (OSCCTRL_INTFLAG_XOSCRDY_Msk & ((value) << OSCCTRL_INTFLAG_XOSCRDY_Pos))
378#define OSCCTRL_INTFLAG_XOSCFAIL_Pos _U_(2) /**< (OSCCTRL_INTFLAG Position) XOSC x Clock Failure Detector */
379#define OSCCTRL_INTFLAG_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCFAIL_Pos) /**< (OSCCTRL_INTFLAG Mask) XOSCFAIL */
380#define OSCCTRL_INTFLAG_XOSCFAIL(value) (OSCCTRL_INTFLAG_XOSCFAIL_Msk & ((value) << OSCCTRL_INTFLAG_XOSCFAIL_Pos))
381
382/* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x10) ( R/ 32) Status -------- */
383#define OSCCTRL_STATUS_RESETVALUE _U_(0x00) /**< (OSCCTRL_STATUS) Status Reset Value */
384
385#define OSCCTRL_STATUS_XOSCRDY0_Pos _U_(0) /**< (OSCCTRL_STATUS) XOSC 0 Ready Position */
386#define OSCCTRL_STATUS_XOSCRDY0_Msk (_U_(0x1) << OSCCTRL_STATUS_XOSCRDY0_Pos) /**< (OSCCTRL_STATUS) XOSC 0 Ready Mask */
387#define OSCCTRL_STATUS_XOSCRDY0(value) (OSCCTRL_STATUS_XOSCRDY0_Msk & ((value) << OSCCTRL_STATUS_XOSCRDY0_Pos))
388#define OSCCTRL_STATUS_XOSCRDY1_Pos _U_(1) /**< (OSCCTRL_STATUS) XOSC 1 Ready Position */
389#define OSCCTRL_STATUS_XOSCRDY1_Msk (_U_(0x1) << OSCCTRL_STATUS_XOSCRDY1_Pos) /**< (OSCCTRL_STATUS) XOSC 1 Ready Mask */
390#define OSCCTRL_STATUS_XOSCRDY1(value) (OSCCTRL_STATUS_XOSCRDY1_Msk & ((value) << OSCCTRL_STATUS_XOSCRDY1_Pos))
391#define OSCCTRL_STATUS_XOSCFAIL0_Pos _U_(2) /**< (OSCCTRL_STATUS) XOSC 0 Clock Failure Detector Position */
392#define OSCCTRL_STATUS_XOSCFAIL0_Msk (_U_(0x1) << OSCCTRL_STATUS_XOSCFAIL0_Pos) /**< (OSCCTRL_STATUS) XOSC 0 Clock Failure Detector Mask */
393#define OSCCTRL_STATUS_XOSCFAIL0(value) (OSCCTRL_STATUS_XOSCFAIL0_Msk & ((value) << OSCCTRL_STATUS_XOSCFAIL0_Pos))
394#define OSCCTRL_STATUS_XOSCFAIL1_Pos _U_(3) /**< (OSCCTRL_STATUS) XOSC 1 Clock Failure Detector Position */
395#define OSCCTRL_STATUS_XOSCFAIL1_Msk (_U_(0x1) << OSCCTRL_STATUS_XOSCFAIL1_Pos) /**< (OSCCTRL_STATUS) XOSC 1 Clock Failure Detector Mask */
396#define OSCCTRL_STATUS_XOSCFAIL1(value) (OSCCTRL_STATUS_XOSCFAIL1_Msk & ((value) << OSCCTRL_STATUS_XOSCFAIL1_Pos))
397#define OSCCTRL_STATUS_XOSCCKSW0_Pos _U_(4) /**< (OSCCTRL_STATUS) XOSC 0 Clock Switch Position */
398#define OSCCTRL_STATUS_XOSCCKSW0_Msk (_U_(0x1) << OSCCTRL_STATUS_XOSCCKSW0_Pos) /**< (OSCCTRL_STATUS) XOSC 0 Clock Switch Mask */
399#define OSCCTRL_STATUS_XOSCCKSW0(value) (OSCCTRL_STATUS_XOSCCKSW0_Msk & ((value) << OSCCTRL_STATUS_XOSCCKSW0_Pos))
400#define OSCCTRL_STATUS_XOSCCKSW1_Pos _U_(5) /**< (OSCCTRL_STATUS) XOSC 1 Clock Switch Position */
401#define OSCCTRL_STATUS_XOSCCKSW1_Msk (_U_(0x1) << OSCCTRL_STATUS_XOSCCKSW1_Pos) /**< (OSCCTRL_STATUS) XOSC 1 Clock Switch Mask */
402#define OSCCTRL_STATUS_XOSCCKSW1(value) (OSCCTRL_STATUS_XOSCCKSW1_Msk & ((value) << OSCCTRL_STATUS_XOSCCKSW1_Pos))
403#define OSCCTRL_STATUS_DFLLRDY_Pos _U_(8) /**< (OSCCTRL_STATUS) DFLL Ready Position */
404#define OSCCTRL_STATUS_DFLLRDY_Msk (_U_(0x1) << OSCCTRL_STATUS_DFLLRDY_Pos) /**< (OSCCTRL_STATUS) DFLL Ready Mask */
405#define OSCCTRL_STATUS_DFLLRDY(value) (OSCCTRL_STATUS_DFLLRDY_Msk & ((value) << OSCCTRL_STATUS_DFLLRDY_Pos))
406#define OSCCTRL_STATUS_DFLLOOB_Pos _U_(9) /**< (OSCCTRL_STATUS) DFLL Out Of Bounds Position */
407#define OSCCTRL_STATUS_DFLLOOB_Msk (_U_(0x1) << OSCCTRL_STATUS_DFLLOOB_Pos) /**< (OSCCTRL_STATUS) DFLL Out Of Bounds Mask */
408#define OSCCTRL_STATUS_DFLLOOB(value) (OSCCTRL_STATUS_DFLLOOB_Msk & ((value) << OSCCTRL_STATUS_DFLLOOB_Pos))
409#define OSCCTRL_STATUS_DFLLLCKF_Pos _U_(10) /**< (OSCCTRL_STATUS) DFLL Lock Fine Position */
410#define OSCCTRL_STATUS_DFLLLCKF_Msk (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKF_Pos) /**< (OSCCTRL_STATUS) DFLL Lock Fine Mask */
411#define OSCCTRL_STATUS_DFLLLCKF(value) (OSCCTRL_STATUS_DFLLLCKF_Msk & ((value) << OSCCTRL_STATUS_DFLLLCKF_Pos))
412#define OSCCTRL_STATUS_DFLLLCKC_Pos _U_(11) /**< (OSCCTRL_STATUS) DFLL Lock Coarse Position */
413#define OSCCTRL_STATUS_DFLLLCKC_Msk (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKC_Pos) /**< (OSCCTRL_STATUS) DFLL Lock Coarse Mask */
414#define OSCCTRL_STATUS_DFLLLCKC(value) (OSCCTRL_STATUS_DFLLLCKC_Msk & ((value) << OSCCTRL_STATUS_DFLLLCKC_Pos))
415#define OSCCTRL_STATUS_DFLLRCS_Pos _U_(12) /**< (OSCCTRL_STATUS) DFLL Reference Clock Stopped Position */
416#define OSCCTRL_STATUS_DFLLRCS_Msk (_U_(0x1) << OSCCTRL_STATUS_DFLLRCS_Pos) /**< (OSCCTRL_STATUS) DFLL Reference Clock Stopped Mask */
417#define OSCCTRL_STATUS_DFLLRCS(value) (OSCCTRL_STATUS_DFLLRCS_Msk & ((value) << OSCCTRL_STATUS_DFLLRCS_Pos))
418#define OSCCTRL_STATUS_DPLL0LCKR_Pos _U_(16) /**< (OSCCTRL_STATUS) DPLL0 Lock Rise Position */
419#define OSCCTRL_STATUS_DPLL0LCKR_Msk (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKR_Pos) /**< (OSCCTRL_STATUS) DPLL0 Lock Rise Mask */
420#define OSCCTRL_STATUS_DPLL0LCKR(value) (OSCCTRL_STATUS_DPLL0LCKR_Msk & ((value) << OSCCTRL_STATUS_DPLL0LCKR_Pos))
421#define OSCCTRL_STATUS_DPLL0LCKF_Pos _U_(17) /**< (OSCCTRL_STATUS) DPLL0 Lock Fall Position */
422#define OSCCTRL_STATUS_DPLL0LCKF_Msk (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKF_Pos) /**< (OSCCTRL_STATUS) DPLL0 Lock Fall Mask */
423#define OSCCTRL_STATUS_DPLL0LCKF(value) (OSCCTRL_STATUS_DPLL0LCKF_Msk & ((value) << OSCCTRL_STATUS_DPLL0LCKF_Pos))
424#define OSCCTRL_STATUS_DPLL0TO_Pos _U_(18) /**< (OSCCTRL_STATUS) DPLL0 Timeout Position */
425#define OSCCTRL_STATUS_DPLL0TO_Msk (_U_(0x1) << OSCCTRL_STATUS_DPLL0TO_Pos) /**< (OSCCTRL_STATUS) DPLL0 Timeout Mask */
426#define OSCCTRL_STATUS_DPLL0TO(value) (OSCCTRL_STATUS_DPLL0TO_Msk & ((value) << OSCCTRL_STATUS_DPLL0TO_Pos))
427#define OSCCTRL_STATUS_DPLL0LDRTO_Pos _U_(19) /**< (OSCCTRL_STATUS) DPLL0 Loop Divider Ratio Update Complete Position */
428#define OSCCTRL_STATUS_DPLL0LDRTO_Msk (_U_(0x1) << OSCCTRL_STATUS_DPLL0LDRTO_Pos) /**< (OSCCTRL_STATUS) DPLL0 Loop Divider Ratio Update Complete Mask */
429#define OSCCTRL_STATUS_DPLL0LDRTO(value) (OSCCTRL_STATUS_DPLL0LDRTO_Msk & ((value) << OSCCTRL_STATUS_DPLL0LDRTO_Pos))
430#define OSCCTRL_STATUS_DPLL1LCKR_Pos _U_(24) /**< (OSCCTRL_STATUS) DPLL1 Lock Rise Position */
431#define OSCCTRL_STATUS_DPLL1LCKR_Msk (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKR_Pos) /**< (OSCCTRL_STATUS) DPLL1 Lock Rise Mask */
432#define OSCCTRL_STATUS_DPLL1LCKR(value) (OSCCTRL_STATUS_DPLL1LCKR_Msk & ((value) << OSCCTRL_STATUS_DPLL1LCKR_Pos))
433#define OSCCTRL_STATUS_DPLL1LCKF_Pos _U_(25) /**< (OSCCTRL_STATUS) DPLL1 Lock Fall Position */
434#define OSCCTRL_STATUS_DPLL1LCKF_Msk (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKF_Pos) /**< (OSCCTRL_STATUS) DPLL1 Lock Fall Mask */
435#define OSCCTRL_STATUS_DPLL1LCKF(value) (OSCCTRL_STATUS_DPLL1LCKF_Msk & ((value) << OSCCTRL_STATUS_DPLL1LCKF_Pos))
436#define OSCCTRL_STATUS_DPLL1TO_Pos _U_(26) /**< (OSCCTRL_STATUS) DPLL1 Timeout Position */
437#define OSCCTRL_STATUS_DPLL1TO_Msk (_U_(0x1) << OSCCTRL_STATUS_DPLL1TO_Pos) /**< (OSCCTRL_STATUS) DPLL1 Timeout Mask */
438#define OSCCTRL_STATUS_DPLL1TO(value) (OSCCTRL_STATUS_DPLL1TO_Msk & ((value) << OSCCTRL_STATUS_DPLL1TO_Pos))
439#define OSCCTRL_STATUS_DPLL1LDRTO_Pos _U_(27) /**< (OSCCTRL_STATUS) DPLL1 Loop Divider Ratio Update Complete Position */
440#define OSCCTRL_STATUS_DPLL1LDRTO_Msk (_U_(0x1) << OSCCTRL_STATUS_DPLL1LDRTO_Pos) /**< (OSCCTRL_STATUS) DPLL1 Loop Divider Ratio Update Complete Mask */
441#define OSCCTRL_STATUS_DPLL1LDRTO(value) (OSCCTRL_STATUS_DPLL1LDRTO_Msk & ((value) << OSCCTRL_STATUS_DPLL1LDRTO_Pos))
442#define OSCCTRL_STATUS_Msk _U_(0x0F0F1F3F) /**< (OSCCTRL_STATUS) Register Mask */
443
444#define OSCCTRL_STATUS_XOSCRDY_Pos _U_(0) /**< (OSCCTRL_STATUS Position) XOSC x Ready */
445#define OSCCTRL_STATUS_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCRDY_Pos) /**< (OSCCTRL_STATUS Mask) XOSCRDY */
446#define OSCCTRL_STATUS_XOSCRDY(value) (OSCCTRL_STATUS_XOSCRDY_Msk & ((value) << OSCCTRL_STATUS_XOSCRDY_Pos))
447#define OSCCTRL_STATUS_XOSCFAIL_Pos _U_(2) /**< (OSCCTRL_STATUS Position) XOSC x Clock Failure Detector */
448#define OSCCTRL_STATUS_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCFAIL_Pos) /**< (OSCCTRL_STATUS Mask) XOSCFAIL */
449#define OSCCTRL_STATUS_XOSCFAIL(value) (OSCCTRL_STATUS_XOSCFAIL_Msk & ((value) << OSCCTRL_STATUS_XOSCFAIL_Pos))
450#define OSCCTRL_STATUS_XOSCCKSW_Pos _U_(4) /**< (OSCCTRL_STATUS Position) XOSC x Clock Switch */
451#define OSCCTRL_STATUS_XOSCCKSW_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCCKSW_Pos) /**< (OSCCTRL_STATUS Mask) XOSCCKSW */
452#define OSCCTRL_STATUS_XOSCCKSW(value) (OSCCTRL_STATUS_XOSCCKSW_Msk & ((value) << OSCCTRL_STATUS_XOSCCKSW_Pos))
453
454/* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x14) (R/W 32) External Multipurpose Crystal Oscillator Control -------- */
455#define OSCCTRL_XOSCCTRL_RESETVALUE _U_(0x80) /**< (OSCCTRL_XOSCCTRL) External Multipurpose Crystal Oscillator Control Reset Value */
456
457#define OSCCTRL_XOSCCTRL_ENABLE_Pos _U_(1) /**< (OSCCTRL_XOSCCTRL) Oscillator Enable Position */
458#define OSCCTRL_XOSCCTRL_ENABLE_Msk (_U_(0x1) << OSCCTRL_XOSCCTRL_ENABLE_Pos) /**< (OSCCTRL_XOSCCTRL) Oscillator Enable Mask */
459#define OSCCTRL_XOSCCTRL_ENABLE(value) (OSCCTRL_XOSCCTRL_ENABLE_Msk & ((value) << OSCCTRL_XOSCCTRL_ENABLE_Pos))
460#define OSCCTRL_XOSCCTRL_XTALEN_Pos _U_(2) /**< (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable Position */
461#define OSCCTRL_XOSCCTRL_XTALEN_Msk (_U_(0x1) << OSCCTRL_XOSCCTRL_XTALEN_Pos) /**< (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable Mask */
462#define OSCCTRL_XOSCCTRL_XTALEN(value) (OSCCTRL_XOSCCTRL_XTALEN_Msk & ((value) << OSCCTRL_XOSCCTRL_XTALEN_Pos))
463#define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos _U_(6) /**< (OSCCTRL_XOSCCTRL) Run in Standby Position */
464#define OSCCTRL_XOSCCTRL_RUNSTDBY_Msk (_U_(0x1) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) /**< (OSCCTRL_XOSCCTRL) Run in Standby Mask */
465#define OSCCTRL_XOSCCTRL_RUNSTDBY(value) (OSCCTRL_XOSCCTRL_RUNSTDBY_Msk & ((value) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos))
466#define OSCCTRL_XOSCCTRL_ONDEMAND_Pos _U_(7) /**< (OSCCTRL_XOSCCTRL) On Demand Control Position */
467#define OSCCTRL_XOSCCTRL_ONDEMAND_Msk (_U_(0x1) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) /**< (OSCCTRL_XOSCCTRL) On Demand Control Mask */
468#define OSCCTRL_XOSCCTRL_ONDEMAND(value) (OSCCTRL_XOSCCTRL_ONDEMAND_Msk & ((value) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos))
469#define OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos _U_(8) /**< (OSCCTRL_XOSCCTRL) Low Buffer Gain Enable Position */
470#define OSCCTRL_XOSCCTRL_LOWBUFGAIN_Msk (_U_(0x1) << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) /**< (OSCCTRL_XOSCCTRL) Low Buffer Gain Enable Mask */
471#define OSCCTRL_XOSCCTRL_LOWBUFGAIN(value) (OSCCTRL_XOSCCTRL_LOWBUFGAIN_Msk & ((value) << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos))
472#define OSCCTRL_XOSCCTRL_IPTAT_Pos _U_(9) /**< (OSCCTRL_XOSCCTRL) Oscillator Current Reference Position */
473#define OSCCTRL_XOSCCTRL_IPTAT_Msk (_U_(0x3) << OSCCTRL_XOSCCTRL_IPTAT_Pos) /**< (OSCCTRL_XOSCCTRL) Oscillator Current Reference Mask */
474#define OSCCTRL_XOSCCTRL_IPTAT(value) (OSCCTRL_XOSCCTRL_IPTAT_Msk & ((value) << OSCCTRL_XOSCCTRL_IPTAT_Pos))
475#define OSCCTRL_XOSCCTRL_IMULT_Pos _U_(11) /**< (OSCCTRL_XOSCCTRL) Oscillator Current Multiplier Position */
476#define OSCCTRL_XOSCCTRL_IMULT_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_IMULT_Pos) /**< (OSCCTRL_XOSCCTRL) Oscillator Current Multiplier Mask */
477#define OSCCTRL_XOSCCTRL_IMULT(value) (OSCCTRL_XOSCCTRL_IMULT_Msk & ((value) << OSCCTRL_XOSCCTRL_IMULT_Pos))
478#define OSCCTRL_XOSCCTRL_ENALC_Pos _U_(15) /**< (OSCCTRL_XOSCCTRL) Automatic Loop Control Enable Position */
479#define OSCCTRL_XOSCCTRL_ENALC_Msk (_U_(0x1) << OSCCTRL_XOSCCTRL_ENALC_Pos) /**< (OSCCTRL_XOSCCTRL) Automatic Loop Control Enable Mask */
480#define OSCCTRL_XOSCCTRL_ENALC(value) (OSCCTRL_XOSCCTRL_ENALC_Msk & ((value) << OSCCTRL_XOSCCTRL_ENALC_Pos))
481#define OSCCTRL_XOSCCTRL_CFDEN_Pos _U_(16) /**< (OSCCTRL_XOSCCTRL) Clock Failure Detector Enable Position */
482#define OSCCTRL_XOSCCTRL_CFDEN_Msk (_U_(0x1) << OSCCTRL_XOSCCTRL_CFDEN_Pos) /**< (OSCCTRL_XOSCCTRL) Clock Failure Detector Enable Mask */
483#define OSCCTRL_XOSCCTRL_CFDEN(value) (OSCCTRL_XOSCCTRL_CFDEN_Msk & ((value) << OSCCTRL_XOSCCTRL_CFDEN_Pos))
484#define OSCCTRL_XOSCCTRL_SWBEN_Pos _U_(17) /**< (OSCCTRL_XOSCCTRL) Xosc Clock Switch Enable Position */
485#define OSCCTRL_XOSCCTRL_SWBEN_Msk (_U_(0x1) << OSCCTRL_XOSCCTRL_SWBEN_Pos) /**< (OSCCTRL_XOSCCTRL) Xosc Clock Switch Enable Mask */
486#define OSCCTRL_XOSCCTRL_SWBEN(value) (OSCCTRL_XOSCCTRL_SWBEN_Msk & ((value) << OSCCTRL_XOSCCTRL_SWBEN_Pos))
487#define OSCCTRL_XOSCCTRL_STARTUP_Pos _U_(20) /**< (OSCCTRL_XOSCCTRL) Start-Up Time Position */
488#define OSCCTRL_XOSCCTRL_STARTUP_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) Start-Up Time Mask */
489#define OSCCTRL_XOSCCTRL_STARTUP(value) (OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos))
490#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE1_Val _U_(0x0) /**< (OSCCTRL_XOSCCTRL) 31 us */
491#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE2_Val _U_(0x1) /**< (OSCCTRL_XOSCCTRL) 61 us */
492#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE4_Val _U_(0x2) /**< (OSCCTRL_XOSCCTRL) 122 us */
493#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE8_Val _U_(0x3) /**< (OSCCTRL_XOSCCTRL) 244 us */
494#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE16_Val _U_(0x4) /**< (OSCCTRL_XOSCCTRL) 488 us */
495#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE32_Val _U_(0x5) /**< (OSCCTRL_XOSCCTRL) 977 us */
496#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE64_Val _U_(0x6) /**< (OSCCTRL_XOSCCTRL) 1953 us */
497#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE128_Val _U_(0x7) /**< (OSCCTRL_XOSCCTRL) 3906 us */
498#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE256_Val _U_(0x8) /**< (OSCCTRL_XOSCCTRL) 7813 us */
499#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE512_Val _U_(0x9) /**< (OSCCTRL_XOSCCTRL) 15625 us */
500#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE1024_Val _U_(0xA) /**< (OSCCTRL_XOSCCTRL) 31250 us */
501#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE2048_Val _U_(0xB) /**< (OSCCTRL_XOSCCTRL) 62500 us */
502#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE4096_Val _U_(0xC) /**< (OSCCTRL_XOSCCTRL) 125000 us */
503#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE8192_Val _U_(0xD) /**< (OSCCTRL_XOSCCTRL) 250000 us */
504#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE16384_Val _U_(0xE) /**< (OSCCTRL_XOSCCTRL) 500000 us */
505#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE32768_Val _U_(0xF) /**< (OSCCTRL_XOSCCTRL) 1000000 us */
506#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE1 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE1_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 31 us Position */
507#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE2 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE2_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 61 us Position */
508#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE4 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE4_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 122 us Position */
509#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE8 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE8_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 244 us Position */
510#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE16 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE16_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 488 us Position */
511#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE32 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE32_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 977 us Position */
512#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE64 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE64_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 1953 us Position */
513#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE128 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE128_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 3906 us Position */
514#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE256 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE256_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 7813 us Position */
515#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE512 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE512_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 15625 us Position */
516#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE1024 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE1024_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 31250 us Position */
517#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE2048 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE2048_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 62500 us Position */
518#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE4096 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE4096_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 125000 us Position */
519#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE8192 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE8192_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 250000 us Position */
520#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE16384 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE16384_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 500000 us Position */
521#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE32768 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE32768_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 1000000 us Position */
522#define OSCCTRL_XOSCCTRL_CFDPRESC_Pos _U_(24) /**< (OSCCTRL_XOSCCTRL) Clock Failure Detector Prescaler Position */
523#define OSCCTRL_XOSCCTRL_CFDPRESC_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) Clock Failure Detector Prescaler Mask */
524#define OSCCTRL_XOSCCTRL_CFDPRESC(value) (OSCCTRL_XOSCCTRL_CFDPRESC_Msk & ((value) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos))
525#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV1_Val _U_(0x0) /**< (OSCCTRL_XOSCCTRL) 48 MHz */
526#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV2_Val _U_(0x1) /**< (OSCCTRL_XOSCCTRL) 24 MHz */
527#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV4_Val _U_(0x2) /**< (OSCCTRL_XOSCCTRL) 12 MHz */
528#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV8_Val _U_(0x3) /**< (OSCCTRL_XOSCCTRL) 6 MHz */
529#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV16_Val _U_(0x4) /**< (OSCCTRL_XOSCCTRL) 3 MHz */
530#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV32_Val _U_(0x5) /**< (OSCCTRL_XOSCCTRL) 1.5 MHz */
531#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV64_Val _U_(0x6) /**< (OSCCTRL_XOSCCTRL) 0.75 MHz */
532#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV128_Val _U_(0x7) /**< (OSCCTRL_XOSCCTRL) 0.3125 MHz */
533#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV1 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV1_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 48 MHz Position */
534#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV2 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV2_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 24 MHz Position */
535#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV4 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV4_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 12 MHz Position */
536#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV8 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV8_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 6 MHz Position */
537#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV16 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV16_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 3 MHz Position */
538#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV32 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV32_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 1.5 MHz Position */
539#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV64 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV64_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 0.75 MHz Position */
540#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV128 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV128_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 0.3125 MHz Position */
541#define OSCCTRL_XOSCCTRL_Msk _U_(0x0FF3FFC6) /**< (OSCCTRL_XOSCCTRL) Register Mask */
542
543
544/* -------- OSCCTRL_DFLLCTRLA : (OSCCTRL Offset: 0x1C) (R/W 8) DFLL48M Control A -------- */
545#define OSCCTRL_DFLLCTRLA_RESETVALUE _U_(0x82) /**< (OSCCTRL_DFLLCTRLA) DFLL48M Control A Reset Value */
546
547#define OSCCTRL_DFLLCTRLA_ENABLE_Pos _U_(1) /**< (OSCCTRL_DFLLCTRLA) DFLL Enable Position */
548#define OSCCTRL_DFLLCTRLA_ENABLE_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLA_ENABLE_Pos) /**< (OSCCTRL_DFLLCTRLA) DFLL Enable Mask */
549#define OSCCTRL_DFLLCTRLA_ENABLE(value) (OSCCTRL_DFLLCTRLA_ENABLE_Msk & ((value) << OSCCTRL_DFLLCTRLA_ENABLE_Pos))
550#define OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos _U_(6) /**< (OSCCTRL_DFLLCTRLA) Run in Standby Position */
551#define OSCCTRL_DFLLCTRLA_RUNSTDBY_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos) /**< (OSCCTRL_DFLLCTRLA) Run in Standby Mask */
552#define OSCCTRL_DFLLCTRLA_RUNSTDBY(value) (OSCCTRL_DFLLCTRLA_RUNSTDBY_Msk & ((value) << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos))
553#define OSCCTRL_DFLLCTRLA_ONDEMAND_Pos _U_(7) /**< (OSCCTRL_DFLLCTRLA) On Demand Control Position */
554#define OSCCTRL_DFLLCTRLA_ONDEMAND_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos) /**< (OSCCTRL_DFLLCTRLA) On Demand Control Mask */
555#define OSCCTRL_DFLLCTRLA_ONDEMAND(value) (OSCCTRL_DFLLCTRLA_ONDEMAND_Msk & ((value) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos))
556#define OSCCTRL_DFLLCTRLA_Msk _U_(0xC2) /**< (OSCCTRL_DFLLCTRLA) Register Mask */
557
558
559/* -------- OSCCTRL_DFLLCTRLB : (OSCCTRL Offset: 0x20) (R/W 8) DFLL48M Control B -------- */
560#define OSCCTRL_DFLLCTRLB_RESETVALUE _U_(0x00) /**< (OSCCTRL_DFLLCTRLB) DFLL48M Control B Reset Value */
561
562#define OSCCTRL_DFLLCTRLB_MODE_Pos _U_(0) /**< (OSCCTRL_DFLLCTRLB) Operating Mode Selection Position */
563#define OSCCTRL_DFLLCTRLB_MODE_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLB_MODE_Pos) /**< (OSCCTRL_DFLLCTRLB) Operating Mode Selection Mask */
564#define OSCCTRL_DFLLCTRLB_MODE(value) (OSCCTRL_DFLLCTRLB_MODE_Msk & ((value) << OSCCTRL_DFLLCTRLB_MODE_Pos))
565#define OSCCTRL_DFLLCTRLB_STABLE_Pos _U_(1) /**< (OSCCTRL_DFLLCTRLB) Stable DFLL Frequency Position */
566#define OSCCTRL_DFLLCTRLB_STABLE_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLB_STABLE_Pos) /**< (OSCCTRL_DFLLCTRLB) Stable DFLL Frequency Mask */
567#define OSCCTRL_DFLLCTRLB_STABLE(value) (OSCCTRL_DFLLCTRLB_STABLE_Msk & ((value) << OSCCTRL_DFLLCTRLB_STABLE_Pos))
568#define OSCCTRL_DFLLCTRLB_LLAW_Pos _U_(2) /**< (OSCCTRL_DFLLCTRLB) Lose Lock After Wake Position */
569#define OSCCTRL_DFLLCTRLB_LLAW_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLB_LLAW_Pos) /**< (OSCCTRL_DFLLCTRLB) Lose Lock After Wake Mask */
570#define OSCCTRL_DFLLCTRLB_LLAW(value) (OSCCTRL_DFLLCTRLB_LLAW_Msk & ((value) << OSCCTRL_DFLLCTRLB_LLAW_Pos))
571#define OSCCTRL_DFLLCTRLB_USBCRM_Pos _U_(3) /**< (OSCCTRL_DFLLCTRLB) USB Clock Recovery Mode Position */
572#define OSCCTRL_DFLLCTRLB_USBCRM_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLB_USBCRM_Pos) /**< (OSCCTRL_DFLLCTRLB) USB Clock Recovery Mode Mask */
573#define OSCCTRL_DFLLCTRLB_USBCRM(value) (OSCCTRL_DFLLCTRLB_USBCRM_Msk & ((value) << OSCCTRL_DFLLCTRLB_USBCRM_Pos))
574#define OSCCTRL_DFLLCTRLB_CCDIS_Pos _U_(4) /**< (OSCCTRL_DFLLCTRLB) Chill Cycle Disable Position */
575#define OSCCTRL_DFLLCTRLB_CCDIS_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLB_CCDIS_Pos) /**< (OSCCTRL_DFLLCTRLB) Chill Cycle Disable Mask */
576#define OSCCTRL_DFLLCTRLB_CCDIS(value) (OSCCTRL_DFLLCTRLB_CCDIS_Msk & ((value) << OSCCTRL_DFLLCTRLB_CCDIS_Pos))
577#define OSCCTRL_DFLLCTRLB_QLDIS_Pos _U_(5) /**< (OSCCTRL_DFLLCTRLB) Quick Lock Disable Position */
578#define OSCCTRL_DFLLCTRLB_QLDIS_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLB_QLDIS_Pos) /**< (OSCCTRL_DFLLCTRLB) Quick Lock Disable Mask */
579#define OSCCTRL_DFLLCTRLB_QLDIS(value) (OSCCTRL_DFLLCTRLB_QLDIS_Msk & ((value) << OSCCTRL_DFLLCTRLB_QLDIS_Pos))
580#define OSCCTRL_DFLLCTRLB_BPLCKC_Pos _U_(6) /**< (OSCCTRL_DFLLCTRLB) Bypass Coarse Lock Position */
581#define OSCCTRL_DFLLCTRLB_BPLCKC_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLB_BPLCKC_Pos) /**< (OSCCTRL_DFLLCTRLB) Bypass Coarse Lock Mask */
582#define OSCCTRL_DFLLCTRLB_BPLCKC(value) (OSCCTRL_DFLLCTRLB_BPLCKC_Msk & ((value) << OSCCTRL_DFLLCTRLB_BPLCKC_Pos))
583#define OSCCTRL_DFLLCTRLB_WAITLOCK_Pos _U_(7) /**< (OSCCTRL_DFLLCTRLB) Wait Lock Position */
584#define OSCCTRL_DFLLCTRLB_WAITLOCK_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos) /**< (OSCCTRL_DFLLCTRLB) Wait Lock Mask */
585#define OSCCTRL_DFLLCTRLB_WAITLOCK(value) (OSCCTRL_DFLLCTRLB_WAITLOCK_Msk & ((value) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos))
586#define OSCCTRL_DFLLCTRLB_Msk _U_(0xFF) /**< (OSCCTRL_DFLLCTRLB) Register Mask */
587
588
589/* -------- OSCCTRL_DFLLVAL : (OSCCTRL Offset: 0x24) (R/W 32) DFLL48M Value -------- */
590#define OSCCTRL_DFLLVAL_RESETVALUE _U_(0x00) /**< (OSCCTRL_DFLLVAL) DFLL48M Value Reset Value */
591
592#define OSCCTRL_DFLLVAL_FINE_Pos _U_(0) /**< (OSCCTRL_DFLLVAL) Fine Value Position */
593#define OSCCTRL_DFLLVAL_FINE_Msk (_U_(0xFF) << OSCCTRL_DFLLVAL_FINE_Pos) /**< (OSCCTRL_DFLLVAL) Fine Value Mask */
594#define OSCCTRL_DFLLVAL_FINE(value) (OSCCTRL_DFLLVAL_FINE_Msk & ((value) << OSCCTRL_DFLLVAL_FINE_Pos))
595#define OSCCTRL_DFLLVAL_COARSE_Pos _U_(10) /**< (OSCCTRL_DFLLVAL) Coarse Value Position */
596#define OSCCTRL_DFLLVAL_COARSE_Msk (_U_(0x3F) << OSCCTRL_DFLLVAL_COARSE_Pos) /**< (OSCCTRL_DFLLVAL) Coarse Value Mask */
597#define OSCCTRL_DFLLVAL_COARSE(value) (OSCCTRL_DFLLVAL_COARSE_Msk & ((value) << OSCCTRL_DFLLVAL_COARSE_Pos))
598#define OSCCTRL_DFLLVAL_DIFF_Pos _U_(16) /**< (OSCCTRL_DFLLVAL) Multiplication Ratio Difference Position */
599#define OSCCTRL_DFLLVAL_DIFF_Msk (_U_(0xFFFF) << OSCCTRL_DFLLVAL_DIFF_Pos) /**< (OSCCTRL_DFLLVAL) Multiplication Ratio Difference Mask */
600#define OSCCTRL_DFLLVAL_DIFF(value) (OSCCTRL_DFLLVAL_DIFF_Msk & ((value) << OSCCTRL_DFLLVAL_DIFF_Pos))
601#define OSCCTRL_DFLLVAL_Msk _U_(0xFFFFFCFF) /**< (OSCCTRL_DFLLVAL) Register Mask */
602
603
604/* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x28) (R/W 32) DFLL48M Multiplier -------- */
605#define OSCCTRL_DFLLMUL_RESETVALUE _U_(0x00) /**< (OSCCTRL_DFLLMUL) DFLL48M Multiplier Reset Value */
606
607#define OSCCTRL_DFLLMUL_MUL_Pos _U_(0) /**< (OSCCTRL_DFLLMUL) DFLL Multiply Factor Position */
608#define OSCCTRL_DFLLMUL_MUL_Msk (_U_(0xFFFF) << OSCCTRL_DFLLMUL_MUL_Pos) /**< (OSCCTRL_DFLLMUL) DFLL Multiply Factor Mask */
609#define OSCCTRL_DFLLMUL_MUL(value) (OSCCTRL_DFLLMUL_MUL_Msk & ((value) << OSCCTRL_DFLLMUL_MUL_Pos))
610#define OSCCTRL_DFLLMUL_FSTEP_Pos _U_(16) /**< (OSCCTRL_DFLLMUL) Fine Maximum Step Position */
611#define OSCCTRL_DFLLMUL_FSTEP_Msk (_U_(0xFF) << OSCCTRL_DFLLMUL_FSTEP_Pos) /**< (OSCCTRL_DFLLMUL) Fine Maximum Step Mask */
612#define OSCCTRL_DFLLMUL_FSTEP(value) (OSCCTRL_DFLLMUL_FSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_FSTEP_Pos))
613#define OSCCTRL_DFLLMUL_CSTEP_Pos _U_(26) /**< (OSCCTRL_DFLLMUL) Coarse Maximum Step Position */
614#define OSCCTRL_DFLLMUL_CSTEP_Msk (_U_(0x3F) << OSCCTRL_DFLLMUL_CSTEP_Pos) /**< (OSCCTRL_DFLLMUL) Coarse Maximum Step Mask */
615#define OSCCTRL_DFLLMUL_CSTEP(value) (OSCCTRL_DFLLMUL_CSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_CSTEP_Pos))
616#define OSCCTRL_DFLLMUL_Msk _U_(0xFCFFFFFF) /**< (OSCCTRL_DFLLMUL) Register Mask */
617
618
619/* -------- OSCCTRL_DFLLSYNC : (OSCCTRL Offset: 0x2C) (R/W 8) DFLL48M Synchronization -------- */
620#define OSCCTRL_DFLLSYNC_RESETVALUE _U_(0x00) /**< (OSCCTRL_DFLLSYNC) DFLL48M Synchronization Reset Value */
621
622#define OSCCTRL_DFLLSYNC_ENABLE_Pos _U_(1) /**< (OSCCTRL_DFLLSYNC) ENABLE Synchronization Busy Position */
623#define OSCCTRL_DFLLSYNC_ENABLE_Msk (_U_(0x1) << OSCCTRL_DFLLSYNC_ENABLE_Pos) /**< (OSCCTRL_DFLLSYNC) ENABLE Synchronization Busy Mask */
624#define OSCCTRL_DFLLSYNC_ENABLE(value) (OSCCTRL_DFLLSYNC_ENABLE_Msk & ((value) << OSCCTRL_DFLLSYNC_ENABLE_Pos))
625#define OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos _U_(2) /**< (OSCCTRL_DFLLSYNC) DFLLCTRLB Synchronization Busy Position */
626#define OSCCTRL_DFLLSYNC_DFLLCTRLB_Msk (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos) /**< (OSCCTRL_DFLLSYNC) DFLLCTRLB Synchronization Busy Mask */
627#define OSCCTRL_DFLLSYNC_DFLLCTRLB(value) (OSCCTRL_DFLLSYNC_DFLLCTRLB_Msk & ((value) << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos))
628#define OSCCTRL_DFLLSYNC_DFLLVAL_Pos _U_(3) /**< (OSCCTRL_DFLLSYNC) DFLLVAL Synchronization Busy Position */
629#define OSCCTRL_DFLLSYNC_DFLLVAL_Msk (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLVAL_Pos) /**< (OSCCTRL_DFLLSYNC) DFLLVAL Synchronization Busy Mask */
630#define OSCCTRL_DFLLSYNC_DFLLVAL(value) (OSCCTRL_DFLLSYNC_DFLLVAL_Msk & ((value) << OSCCTRL_DFLLSYNC_DFLLVAL_Pos))
631#define OSCCTRL_DFLLSYNC_DFLLMUL_Pos _U_(4) /**< (OSCCTRL_DFLLSYNC) DFLLMUL Synchronization Busy Position */
632#define OSCCTRL_DFLLSYNC_DFLLMUL_Msk (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLMUL_Pos) /**< (OSCCTRL_DFLLSYNC) DFLLMUL Synchronization Busy Mask */
633#define OSCCTRL_DFLLSYNC_DFLLMUL(value) (OSCCTRL_DFLLSYNC_DFLLMUL_Msk & ((value) << OSCCTRL_DFLLSYNC_DFLLMUL_Pos))
634#define OSCCTRL_DFLLSYNC_Msk _U_(0x1E) /**< (OSCCTRL_DFLLSYNC) Register Mask */
635
636
637/** \brief OSCCTRL register offsets definitions */
638#define OSCCTRL_DPLLCTRLA_REG_OFST (0x00) /**< (OSCCTRL_DPLLCTRLA) DPLL Control A Offset */
639#define OSCCTRL_DPLLRATIO_REG_OFST (0x04) /**< (OSCCTRL_DPLLRATIO) DPLL Ratio Control Offset */
640#define OSCCTRL_DPLLCTRLB_REG_OFST (0x08) /**< (OSCCTRL_DPLLCTRLB) DPLL Control B Offset */
641#define OSCCTRL_DPLLSYNCBUSY_REG_OFST (0x0C) /**< (OSCCTRL_DPLLSYNCBUSY) DPLL Synchronization Busy Offset */
642#define OSCCTRL_DPLLSTATUS_REG_OFST (0x10) /**< (OSCCTRL_DPLLSTATUS) DPLL Status Offset */
643#define OSCCTRL_EVCTRL_REG_OFST (0x00) /**< (OSCCTRL_EVCTRL) Event Control Offset */
644#define OSCCTRL_INTENCLR_REG_OFST (0x04) /**< (OSCCTRL_INTENCLR) Interrupt Enable Clear Offset */
645#define OSCCTRL_INTENSET_REG_OFST (0x08) /**< (OSCCTRL_INTENSET) Interrupt Enable Set Offset */
646#define OSCCTRL_INTFLAG_REG_OFST (0x0C) /**< (OSCCTRL_INTFLAG) Interrupt Flag Status and Clear Offset */
647#define OSCCTRL_STATUS_REG_OFST (0x10) /**< (OSCCTRL_STATUS) Status Offset */
648#define OSCCTRL_XOSCCTRL_REG_OFST (0x14) /**< (OSCCTRL_XOSCCTRL) External Multipurpose Crystal Oscillator Control Offset */
649#define OSCCTRL_DFLLCTRLA_REG_OFST (0x1C) /**< (OSCCTRL_DFLLCTRLA) DFLL48M Control A Offset */
650#define OSCCTRL_DFLLCTRLB_REG_OFST (0x20) /**< (OSCCTRL_DFLLCTRLB) DFLL48M Control B Offset */
651#define OSCCTRL_DFLLVAL_REG_OFST (0x24) /**< (OSCCTRL_DFLLVAL) DFLL48M Value Offset */
652#define OSCCTRL_DFLLMUL_REG_OFST (0x28) /**< (OSCCTRL_DFLLMUL) DFLL48M Multiplier Offset */
653#define OSCCTRL_DFLLSYNC_REG_OFST (0x2C) /**< (OSCCTRL_DFLLSYNC) DFLL48M Synchronization Offset */
654
655#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
656/** \brief DPLL register API structure */
657typedef struct
658{
659 __IO uint8_t OSCCTRL_DPLLCTRLA; /**< Offset: 0x00 (R/W 8) DPLL Control A */
660 __I uint8_t Reserved1[0x03];
661 __IO uint32_t OSCCTRL_DPLLRATIO; /**< Offset: 0x04 (R/W 32) DPLL Ratio Control */
662 __IO uint32_t OSCCTRL_DPLLCTRLB; /**< Offset: 0x08 (R/W 32) DPLL Control B */
663 __I uint32_t OSCCTRL_DPLLSYNCBUSY; /**< Offset: 0x0C (R/ 32) DPLL Synchronization Busy */
664 __I uint32_t OSCCTRL_DPLLSTATUS; /**< Offset: 0x10 (R/ 32) DPLL Status */
665} oscctrl_dpll_registers_t;
666
667#define OSCCTRL_DPLL_NUMBER _U_(2)
668
669/** \brief OSCCTRL register API structure */
670typedef struct
671{ /* Oscillators Control */
672 __IO uint8_t OSCCTRL_EVCTRL; /**< Offset: 0x00 (R/W 8) Event Control */
673 __I uint8_t Reserved1[0x03];
674 __IO uint32_t OSCCTRL_INTENCLR; /**< Offset: 0x04 (R/W 32) Interrupt Enable Clear */
675 __IO uint32_t OSCCTRL_INTENSET; /**< Offset: 0x08 (R/W 32) Interrupt Enable Set */
676 __IO uint32_t OSCCTRL_INTFLAG; /**< Offset: 0x0C (R/W 32) Interrupt Flag Status and Clear */
677 __I uint32_t OSCCTRL_STATUS; /**< Offset: 0x10 (R/ 32) Status */
678 __IO uint32_t OSCCTRL_XOSCCTRL[2]; /**< Offset: 0x14 (R/W 32) External Multipurpose Crystal Oscillator Control */
679 __IO uint8_t OSCCTRL_DFLLCTRLA; /**< Offset: 0x1C (R/W 8) DFLL48M Control A */
680 __I uint8_t Reserved2[0x03];
681 __IO uint8_t OSCCTRL_DFLLCTRLB; /**< Offset: 0x20 (R/W 8) DFLL48M Control B */
682 __I uint8_t Reserved3[0x03];
683 __IO uint32_t OSCCTRL_DFLLVAL; /**< Offset: 0x24 (R/W 32) DFLL48M Value */
684 __IO uint32_t OSCCTRL_DFLLMUL; /**< Offset: 0x28 (R/W 32) DFLL48M Multiplier */
685 __IO uint8_t OSCCTRL_DFLLSYNC; /**< Offset: 0x2C (R/W 8) DFLL48M Synchronization */
686 __I uint8_t Reserved4[0x03];
687 oscctrl_dpll_registers_t DPLL[OSCCTRL_DPLL_NUMBER]; /**< Offset: 0x30 */
688} oscctrl_registers_t;
689
690
691#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
692#endif /* _SAMD51_OSCCTRL_COMPONENT_H_ */
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