| 1 | /**
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| 2 | * \brief Component description for MCLK
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| 3 | *
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| 4 | * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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| 5 | *
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| 6 | * Subject to your compliance with these terms, you may use Microchip software and any derivatives
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| 7 | * exclusively with Microchip products. It is your responsibility to comply with third party license
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| 8 | * terms applicable to your use of third party software (including open source software) that may
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| 9 | * accompany Microchip software.
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| 10 | *
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| 11 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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| 12 | * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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| 13 | * FITNESS FOR A PARTICULAR PURPOSE.
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| 14 | *
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| 15 | * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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| 16 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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| 17 | * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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| 18 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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| 19 | * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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| 20 | *
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| 21 | */
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| 22 |
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| 23 | /* file generated from device description version 2020-03-12T17:26:00Z */
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| 24 | #ifndef _SAMD51_MCLK_COMPONENT_H_
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| 25 | #define _SAMD51_MCLK_COMPONENT_H_
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| 26 |
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| 27 | /* ************************************************************************** */
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| 28 | /* SOFTWARE API DEFINITION FOR MCLK */
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| 29 | /* ************************************************************************** */
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| 30 |
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| 31 | /* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W 8) Interrupt Enable Clear -------- */
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| 32 | #define MCLK_INTENCLR_RESETVALUE _U_(0x00) /**< (MCLK_INTENCLR) Interrupt Enable Clear Reset Value */
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| 33 |
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| 34 | #define MCLK_INTENCLR_CKRDY_Pos _U_(0) /**< (MCLK_INTENCLR) Clock Ready Interrupt Enable Position */
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| 35 | #define MCLK_INTENCLR_CKRDY_Msk (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos) /**< (MCLK_INTENCLR) Clock Ready Interrupt Enable Mask */
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| 36 | #define MCLK_INTENCLR_CKRDY(value) (MCLK_INTENCLR_CKRDY_Msk & ((value) << MCLK_INTENCLR_CKRDY_Pos))
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| 37 | #define MCLK_INTENCLR_Msk _U_(0x01) /**< (MCLK_INTENCLR) Register Mask */
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| 38 |
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| 39 |
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| 40 | /* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W 8) Interrupt Enable Set -------- */
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| 41 | #define MCLK_INTENSET_RESETVALUE _U_(0x00) /**< (MCLK_INTENSET) Interrupt Enable Set Reset Value */
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| 42 |
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| 43 | #define MCLK_INTENSET_CKRDY_Pos _U_(0) /**< (MCLK_INTENSET) Clock Ready Interrupt Enable Position */
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| 44 | #define MCLK_INTENSET_CKRDY_Msk (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos) /**< (MCLK_INTENSET) Clock Ready Interrupt Enable Mask */
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| 45 | #define MCLK_INTENSET_CKRDY(value) (MCLK_INTENSET_CKRDY_Msk & ((value) << MCLK_INTENSET_CKRDY_Pos))
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| 46 | #define MCLK_INTENSET_Msk _U_(0x01) /**< (MCLK_INTENSET) Register Mask */
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| 47 |
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| 48 |
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| 49 | /* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W 8) Interrupt Flag Status and Clear -------- */
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| 50 | #define MCLK_INTFLAG_RESETVALUE _U_(0x01) /**< (MCLK_INTFLAG) Interrupt Flag Status and Clear Reset Value */
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| 51 |
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| 52 | #define MCLK_INTFLAG_CKRDY_Pos _U_(0) /**< (MCLK_INTFLAG) Clock Ready Position */
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| 53 | #define MCLK_INTFLAG_CKRDY_Msk (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos) /**< (MCLK_INTFLAG) Clock Ready Mask */
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| 54 | #define MCLK_INTFLAG_CKRDY(value) (MCLK_INTFLAG_CKRDY_Msk & ((value) << MCLK_INTFLAG_CKRDY_Pos))
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| 55 | #define MCLK_INTFLAG_Msk _U_(0x01) /**< (MCLK_INTFLAG) Register Mask */
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| 56 |
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| 57 |
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| 58 | /* -------- MCLK_HSDIV : (MCLK Offset: 0x04) ( R/ 8) HS Clock Division -------- */
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| 59 | #define MCLK_HSDIV_RESETVALUE _U_(0x01) /**< (MCLK_HSDIV) HS Clock Division Reset Value */
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| 60 |
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| 61 | #define MCLK_HSDIV_DIV_Pos _U_(0) /**< (MCLK_HSDIV) CPU Clock Division Factor Position */
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| 62 | #define MCLK_HSDIV_DIV_Msk (_U_(0xFF) << MCLK_HSDIV_DIV_Pos) /**< (MCLK_HSDIV) CPU Clock Division Factor Mask */
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| 63 | #define MCLK_HSDIV_DIV(value) (MCLK_HSDIV_DIV_Msk & ((value) << MCLK_HSDIV_DIV_Pos))
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| 64 | #define MCLK_HSDIV_DIV_DIV1_Val _U_(0x1) /**< (MCLK_HSDIV) Divide by 1 */
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| 65 | #define MCLK_HSDIV_DIV_DIV1 (MCLK_HSDIV_DIV_DIV1_Val << MCLK_HSDIV_DIV_Pos) /**< (MCLK_HSDIV) Divide by 1 Position */
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| 66 | #define MCLK_HSDIV_Msk _U_(0xFF) /**< (MCLK_HSDIV) Register Mask */
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| 67 |
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| 68 |
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| 69 | /* -------- MCLK_CPUDIV : (MCLK Offset: 0x05) (R/W 8) CPU Clock Division -------- */
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| 70 | #define MCLK_CPUDIV_RESETVALUE _U_(0x01) /**< (MCLK_CPUDIV) CPU Clock Division Reset Value */
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| 71 |
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| 72 | #define MCLK_CPUDIV_DIV_Pos _U_(0) /**< (MCLK_CPUDIV) Low-Power Clock Division Factor Position */
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| 73 | #define MCLK_CPUDIV_DIV_Msk (_U_(0xFF) << MCLK_CPUDIV_DIV_Pos) /**< (MCLK_CPUDIV) Low-Power Clock Division Factor Mask */
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| 74 | #define MCLK_CPUDIV_DIV(value) (MCLK_CPUDIV_DIV_Msk & ((value) << MCLK_CPUDIV_DIV_Pos))
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| 75 | #define MCLK_CPUDIV_DIV_DIV1_Val _U_(0x1) /**< (MCLK_CPUDIV) Divide by 1 */
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| 76 | #define MCLK_CPUDIV_DIV_DIV2_Val _U_(0x2) /**< (MCLK_CPUDIV) Divide by 2 */
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| 77 | #define MCLK_CPUDIV_DIV_DIV4_Val _U_(0x4) /**< (MCLK_CPUDIV) Divide by 4 */
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| 78 | #define MCLK_CPUDIV_DIV_DIV8_Val _U_(0x8) /**< (MCLK_CPUDIV) Divide by 8 */
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| 79 | #define MCLK_CPUDIV_DIV_DIV16_Val _U_(0x10) /**< (MCLK_CPUDIV) Divide by 16 */
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| 80 | #define MCLK_CPUDIV_DIV_DIV32_Val _U_(0x20) /**< (MCLK_CPUDIV) Divide by 32 */
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| 81 | #define MCLK_CPUDIV_DIV_DIV64_Val _U_(0x40) /**< (MCLK_CPUDIV) Divide by 64 */
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| 82 | #define MCLK_CPUDIV_DIV_DIV128_Val _U_(0x80) /**< (MCLK_CPUDIV) Divide by 128 */
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| 83 | #define MCLK_CPUDIV_DIV_DIV1 (MCLK_CPUDIV_DIV_DIV1_Val << MCLK_CPUDIV_DIV_Pos) /**< (MCLK_CPUDIV) Divide by 1 Position */
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| 84 | #define MCLK_CPUDIV_DIV_DIV2 (MCLK_CPUDIV_DIV_DIV2_Val << MCLK_CPUDIV_DIV_Pos) /**< (MCLK_CPUDIV) Divide by 2 Position */
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| 85 | #define MCLK_CPUDIV_DIV_DIV4 (MCLK_CPUDIV_DIV_DIV4_Val << MCLK_CPUDIV_DIV_Pos) /**< (MCLK_CPUDIV) Divide by 4 Position */
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| 86 | #define MCLK_CPUDIV_DIV_DIV8 (MCLK_CPUDIV_DIV_DIV8_Val << MCLK_CPUDIV_DIV_Pos) /**< (MCLK_CPUDIV) Divide by 8 Position */
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| 87 | #define MCLK_CPUDIV_DIV_DIV16 (MCLK_CPUDIV_DIV_DIV16_Val << MCLK_CPUDIV_DIV_Pos) /**< (MCLK_CPUDIV) Divide by 16 Position */
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| 88 | #define MCLK_CPUDIV_DIV_DIV32 (MCLK_CPUDIV_DIV_DIV32_Val << MCLK_CPUDIV_DIV_Pos) /**< (MCLK_CPUDIV) Divide by 32 Position */
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| 89 | #define MCLK_CPUDIV_DIV_DIV64 (MCLK_CPUDIV_DIV_DIV64_Val << MCLK_CPUDIV_DIV_Pos) /**< (MCLK_CPUDIV) Divide by 64 Position */
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| 90 | #define MCLK_CPUDIV_DIV_DIV128 (MCLK_CPUDIV_DIV_DIV128_Val << MCLK_CPUDIV_DIV_Pos) /**< (MCLK_CPUDIV) Divide by 128 Position */
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| 91 | #define MCLK_CPUDIV_Msk _U_(0xFF) /**< (MCLK_CPUDIV) Register Mask */
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| 92 |
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| 93 |
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| 94 | /* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */
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| 95 | #define MCLK_AHBMASK_RESETVALUE _U_(0xFFFFFF) /**< (MCLK_AHBMASK) AHB Mask Reset Value */
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| 96 |
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| 97 | #define MCLK_AHBMASK_HPB0_Pos _U_(0) /**< (MCLK_AHBMASK) HPB0 AHB Clock Mask Position */
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| 98 | #define MCLK_AHBMASK_HPB0_Msk (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos) /**< (MCLK_AHBMASK) HPB0 AHB Clock Mask Mask */
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| 99 | #define MCLK_AHBMASK_HPB0(value) (MCLK_AHBMASK_HPB0_Msk & ((value) << MCLK_AHBMASK_HPB0_Pos))
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| 100 | #define MCLK_AHBMASK_HPB1_Pos _U_(1) /**< (MCLK_AHBMASK) HPB1 AHB Clock Mask Position */
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| 101 | #define MCLK_AHBMASK_HPB1_Msk (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos) /**< (MCLK_AHBMASK) HPB1 AHB Clock Mask Mask */
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| 102 | #define MCLK_AHBMASK_HPB1(value) (MCLK_AHBMASK_HPB1_Msk & ((value) << MCLK_AHBMASK_HPB1_Pos))
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| 103 | #define MCLK_AHBMASK_HPB2_Pos _U_(2) /**< (MCLK_AHBMASK) HPB2 AHB Clock Mask Position */
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| 104 | #define MCLK_AHBMASK_HPB2_Msk (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos) /**< (MCLK_AHBMASK) HPB2 AHB Clock Mask Mask */
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| 105 | #define MCLK_AHBMASK_HPB2(value) (MCLK_AHBMASK_HPB2_Msk & ((value) << MCLK_AHBMASK_HPB2_Pos))
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| 106 | #define MCLK_AHBMASK_HPB3_Pos _U_(3) /**< (MCLK_AHBMASK) HPB3 AHB Clock Mask Position */
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| 107 | #define MCLK_AHBMASK_HPB3_Msk (_U_(0x1) << MCLK_AHBMASK_HPB3_Pos) /**< (MCLK_AHBMASK) HPB3 AHB Clock Mask Mask */
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| 108 | #define MCLK_AHBMASK_HPB3(value) (MCLK_AHBMASK_HPB3_Msk & ((value) << MCLK_AHBMASK_HPB3_Pos))
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| 109 | #define MCLK_AHBMASK_DSU_Pos _U_(4) /**< (MCLK_AHBMASK) DSU AHB Clock Mask Position */
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| 110 | #define MCLK_AHBMASK_DSU_Msk (_U_(0x1) << MCLK_AHBMASK_DSU_Pos) /**< (MCLK_AHBMASK) DSU AHB Clock Mask Mask */
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| 111 | #define MCLK_AHBMASK_DSU(value) (MCLK_AHBMASK_DSU_Msk & ((value) << MCLK_AHBMASK_DSU_Pos))
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| 112 | #define MCLK_AHBMASK_HMATRIX_Pos _U_(5) /**< (MCLK_AHBMASK) HMATRIX AHB Clock Mask Position */
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| 113 | #define MCLK_AHBMASK_HMATRIX_Msk (_U_(0x1) << MCLK_AHBMASK_HMATRIX_Pos) /**< (MCLK_AHBMASK) HMATRIX AHB Clock Mask Mask */
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| 114 | #define MCLK_AHBMASK_HMATRIX(value) (MCLK_AHBMASK_HMATRIX_Msk & ((value) << MCLK_AHBMASK_HMATRIX_Pos))
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| 115 | #define MCLK_AHBMASK_NVMCTRL_Pos _U_(6) /**< (MCLK_AHBMASK) NVMCTRL AHB Clock Mask Position */
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| 116 | #define MCLK_AHBMASK_NVMCTRL_Msk (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos) /**< (MCLK_AHBMASK) NVMCTRL AHB Clock Mask Mask */
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| 117 | #define MCLK_AHBMASK_NVMCTRL(value) (MCLK_AHBMASK_NVMCTRL_Msk & ((value) << MCLK_AHBMASK_NVMCTRL_Pos))
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| 118 | #define MCLK_AHBMASK_HSRAM_Pos _U_(7) /**< (MCLK_AHBMASK) HSRAM AHB Clock Mask Position */
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| 119 | #define MCLK_AHBMASK_HSRAM_Msk (_U_(0x1) << MCLK_AHBMASK_HSRAM_Pos) /**< (MCLK_AHBMASK) HSRAM AHB Clock Mask Mask */
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| 120 | #define MCLK_AHBMASK_HSRAM(value) (MCLK_AHBMASK_HSRAM_Msk & ((value) << MCLK_AHBMASK_HSRAM_Pos))
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| 121 | #define MCLK_AHBMASK_CMCC_Pos _U_(8) /**< (MCLK_AHBMASK) CMCC AHB Clock Mask Position */
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| 122 | #define MCLK_AHBMASK_CMCC_Msk (_U_(0x1) << MCLK_AHBMASK_CMCC_Pos) /**< (MCLK_AHBMASK) CMCC AHB Clock Mask Mask */
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| 123 | #define MCLK_AHBMASK_CMCC(value) (MCLK_AHBMASK_CMCC_Msk & ((value) << MCLK_AHBMASK_CMCC_Pos))
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| 124 | #define MCLK_AHBMASK_DMAC_Pos _U_(9) /**< (MCLK_AHBMASK) DMAC AHB Clock Mask Position */
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| 125 | #define MCLK_AHBMASK_DMAC_Msk (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos) /**< (MCLK_AHBMASK) DMAC AHB Clock Mask Mask */
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| 126 | #define MCLK_AHBMASK_DMAC(value) (MCLK_AHBMASK_DMAC_Msk & ((value) << MCLK_AHBMASK_DMAC_Pos))
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| 127 | #define MCLK_AHBMASK_USB_Pos _U_(10) /**< (MCLK_AHBMASK) USB AHB Clock Mask Position */
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| 128 | #define MCLK_AHBMASK_USB_Msk (_U_(0x1) << MCLK_AHBMASK_USB_Pos) /**< (MCLK_AHBMASK) USB AHB Clock Mask Mask */
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| 129 | #define MCLK_AHBMASK_USB(value) (MCLK_AHBMASK_USB_Msk & ((value) << MCLK_AHBMASK_USB_Pos))
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| 130 | #define MCLK_AHBMASK_BKUPRAM_Pos _U_(11) /**< (MCLK_AHBMASK) BKUPRAM AHB Clock Mask Position */
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| 131 | #define MCLK_AHBMASK_BKUPRAM_Msk (_U_(0x1) << MCLK_AHBMASK_BKUPRAM_Pos) /**< (MCLK_AHBMASK) BKUPRAM AHB Clock Mask Mask */
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| 132 | #define MCLK_AHBMASK_BKUPRAM(value) (MCLK_AHBMASK_BKUPRAM_Msk & ((value) << MCLK_AHBMASK_BKUPRAM_Pos))
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| 133 | #define MCLK_AHBMASK_PAC_Pos _U_(12) /**< (MCLK_AHBMASK) PAC AHB Clock Mask Position */
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| 134 | #define MCLK_AHBMASK_PAC_Msk (_U_(0x1) << MCLK_AHBMASK_PAC_Pos) /**< (MCLK_AHBMASK) PAC AHB Clock Mask Mask */
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| 135 | #define MCLK_AHBMASK_PAC(value) (MCLK_AHBMASK_PAC_Msk & ((value) << MCLK_AHBMASK_PAC_Pos))
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| 136 | #define MCLK_AHBMASK_QSPI_Pos _U_(13) /**< (MCLK_AHBMASK) QSPI AHB Clock Mask Position */
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| 137 | #define MCLK_AHBMASK_QSPI_Msk (_U_(0x1) << MCLK_AHBMASK_QSPI_Pos) /**< (MCLK_AHBMASK) QSPI AHB Clock Mask Mask */
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| 138 | #define MCLK_AHBMASK_QSPI(value) (MCLK_AHBMASK_QSPI_Msk & ((value) << MCLK_AHBMASK_QSPI_Pos))
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| 139 | #define MCLK_AHBMASK_SDHC0_Pos _U_(15) /**< (MCLK_AHBMASK) SDHC0 AHB Clock Mask Position */
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| 140 | #define MCLK_AHBMASK_SDHC0_Msk (_U_(0x1) << MCLK_AHBMASK_SDHC0_Pos) /**< (MCLK_AHBMASK) SDHC0 AHB Clock Mask Mask */
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| 141 | #define MCLK_AHBMASK_SDHC0(value) (MCLK_AHBMASK_SDHC0_Msk & ((value) << MCLK_AHBMASK_SDHC0_Pos))
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| 142 | #define MCLK_AHBMASK_SDHC1_Pos _U_(16) /**< (MCLK_AHBMASK) SDHC1 AHB Clock Mask Position */
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| 143 | #define MCLK_AHBMASK_SDHC1_Msk (_U_(0x1) << MCLK_AHBMASK_SDHC1_Pos) /**< (MCLK_AHBMASK) SDHC1 AHB Clock Mask Mask */
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| 144 | #define MCLK_AHBMASK_SDHC1(value) (MCLK_AHBMASK_SDHC1_Msk & ((value) << MCLK_AHBMASK_SDHC1_Pos))
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| 145 | #define MCLK_AHBMASK_ICM_Pos _U_(19) /**< (MCLK_AHBMASK) ICM AHB Clock Mask Position */
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| 146 | #define MCLK_AHBMASK_ICM_Msk (_U_(0x1) << MCLK_AHBMASK_ICM_Pos) /**< (MCLK_AHBMASK) ICM AHB Clock Mask Mask */
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| 147 | #define MCLK_AHBMASK_ICM(value) (MCLK_AHBMASK_ICM_Msk & ((value) << MCLK_AHBMASK_ICM_Pos))
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| 148 | #define MCLK_AHBMASK_PUKCC_Pos _U_(20) /**< (MCLK_AHBMASK) PUKCC AHB Clock Mask Position */
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| 149 | #define MCLK_AHBMASK_PUKCC_Msk (_U_(0x1) << MCLK_AHBMASK_PUKCC_Pos) /**< (MCLK_AHBMASK) PUKCC AHB Clock Mask Mask */
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| 150 | #define MCLK_AHBMASK_PUKCC(value) (MCLK_AHBMASK_PUKCC_Msk & ((value) << MCLK_AHBMASK_PUKCC_Pos))
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| 151 | #define MCLK_AHBMASK_QSPI_2X_Pos _U_(21) /**< (MCLK_AHBMASK) QSPI_2X AHB Clock Mask Position */
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| 152 | #define MCLK_AHBMASK_QSPI_2X_Msk (_U_(0x1) << MCLK_AHBMASK_QSPI_2X_Pos) /**< (MCLK_AHBMASK) QSPI_2X AHB Clock Mask Mask */
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| 153 | #define MCLK_AHBMASK_QSPI_2X(value) (MCLK_AHBMASK_QSPI_2X_Msk & ((value) << MCLK_AHBMASK_QSPI_2X_Pos))
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| 154 | #define MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos _U_(22) /**< (MCLK_AHBMASK) NVMCTRL_SMEEPROM AHB Clock Mask Position */
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| 155 | #define MCLK_AHBMASK_NVMCTRL_SMEEPROM_Msk (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos) /**< (MCLK_AHBMASK) NVMCTRL_SMEEPROM AHB Clock Mask Mask */
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| 156 | #define MCLK_AHBMASK_NVMCTRL_SMEEPROM(value) (MCLK_AHBMASK_NVMCTRL_SMEEPROM_Msk & ((value) << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos))
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| 157 | #define MCLK_AHBMASK_NVMCTRL_CACHE_Pos _U_(23) /**< (MCLK_AHBMASK) NVMCTRL_CACHE AHB Clock Mask Position */
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| 158 | #define MCLK_AHBMASK_NVMCTRL_CACHE_Msk (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_CACHE_Pos) /**< (MCLK_AHBMASK) NVMCTRL_CACHE AHB Clock Mask Mask */
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| 159 | #define MCLK_AHBMASK_NVMCTRL_CACHE(value) (MCLK_AHBMASK_NVMCTRL_CACHE_Msk & ((value) << MCLK_AHBMASK_NVMCTRL_CACHE_Pos))
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| 160 | #define MCLK_AHBMASK_Msk _U_(0x00F9BFFF) /**< (MCLK_AHBMASK) Register Mask */
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| 161 |
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| 162 | #define MCLK_AHBMASK_HPB_Pos _U_(0) /**< (MCLK_AHBMASK Position) HPBx AHB Clock Mask */
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| 163 | #define MCLK_AHBMASK_HPB_Msk (_U_(0xF) << MCLK_AHBMASK_HPB_Pos) /**< (MCLK_AHBMASK Mask) HPB */
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| 164 | #define MCLK_AHBMASK_HPB(value) (MCLK_AHBMASK_HPB_Msk & ((value) << MCLK_AHBMASK_HPB_Pos))
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| 165 | #define MCLK_AHBMASK_SDHC_Pos _U_(15) /**< (MCLK_AHBMASK Position) SDHCx AHB Clock Mask */
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| 166 | #define MCLK_AHBMASK_SDHC_Msk (_U_(0x3) << MCLK_AHBMASK_SDHC_Pos) /**< (MCLK_AHBMASK Mask) SDHC */
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| 167 | #define MCLK_AHBMASK_SDHC(value) (MCLK_AHBMASK_SDHC_Msk & ((value) << MCLK_AHBMASK_SDHC_Pos))
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| 168 |
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| 169 | /* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */
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| 170 | #define MCLK_APBAMASK_RESETVALUE _U_(0x7FF) /**< (MCLK_APBAMASK) APBA Mask Reset Value */
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| 171 |
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| 172 | #define MCLK_APBAMASK_PAC_Pos _U_(0) /**< (MCLK_APBAMASK) PAC APB Clock Enable Position */
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| 173 | #define MCLK_APBAMASK_PAC_Msk (_U_(0x1) << MCLK_APBAMASK_PAC_Pos) /**< (MCLK_APBAMASK) PAC APB Clock Enable Mask */
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| 174 | #define MCLK_APBAMASK_PAC(value) (MCLK_APBAMASK_PAC_Msk & ((value) << MCLK_APBAMASK_PAC_Pos))
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| 175 | #define MCLK_APBAMASK_PM_Pos _U_(1) /**< (MCLK_APBAMASK) PM APB Clock Enable Position */
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| 176 | #define MCLK_APBAMASK_PM_Msk (_U_(0x1) << MCLK_APBAMASK_PM_Pos) /**< (MCLK_APBAMASK) PM APB Clock Enable Mask */
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| 177 | #define MCLK_APBAMASK_PM(value) (MCLK_APBAMASK_PM_Msk & ((value) << MCLK_APBAMASK_PM_Pos))
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| 178 | #define MCLK_APBAMASK_MCLK_Pos _U_(2) /**< (MCLK_APBAMASK) MCLK APB Clock Enable Position */
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| 179 | #define MCLK_APBAMASK_MCLK_Msk (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos) /**< (MCLK_APBAMASK) MCLK APB Clock Enable Mask */
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| 180 | #define MCLK_APBAMASK_MCLK(value) (MCLK_APBAMASK_MCLK_Msk & ((value) << MCLK_APBAMASK_MCLK_Pos))
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| 181 | #define MCLK_APBAMASK_RSTC_Pos _U_(3) /**< (MCLK_APBAMASK) RSTC APB Clock Enable Position */
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| 182 | #define MCLK_APBAMASK_RSTC_Msk (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos) /**< (MCLK_APBAMASK) RSTC APB Clock Enable Mask */
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| 183 | #define MCLK_APBAMASK_RSTC(value) (MCLK_APBAMASK_RSTC_Msk & ((value) << MCLK_APBAMASK_RSTC_Pos))
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| 184 | #define MCLK_APBAMASK_OSCCTRL_Pos _U_(4) /**< (MCLK_APBAMASK) OSCCTRL APB Clock Enable Position */
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| 185 | #define MCLK_APBAMASK_OSCCTRL_Msk (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos) /**< (MCLK_APBAMASK) OSCCTRL APB Clock Enable Mask */
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| 186 | #define MCLK_APBAMASK_OSCCTRL(value) (MCLK_APBAMASK_OSCCTRL_Msk & ((value) << MCLK_APBAMASK_OSCCTRL_Pos))
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| 187 | #define MCLK_APBAMASK_OSC32KCTRL_Pos _U_(5) /**< (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable Position */
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| 188 | #define MCLK_APBAMASK_OSC32KCTRL_Msk (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos) /**< (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable Mask */
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| 189 | #define MCLK_APBAMASK_OSC32KCTRL(value) (MCLK_APBAMASK_OSC32KCTRL_Msk & ((value) << MCLK_APBAMASK_OSC32KCTRL_Pos))
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| 190 | #define MCLK_APBAMASK_SUPC_Pos _U_(6) /**< (MCLK_APBAMASK) SUPC APB Clock Enable Position */
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| 191 | #define MCLK_APBAMASK_SUPC_Msk (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos) /**< (MCLK_APBAMASK) SUPC APB Clock Enable Mask */
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| 192 | #define MCLK_APBAMASK_SUPC(value) (MCLK_APBAMASK_SUPC_Msk & ((value) << MCLK_APBAMASK_SUPC_Pos))
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| 193 | #define MCLK_APBAMASK_GCLK_Pos _U_(7) /**< (MCLK_APBAMASK) GCLK APB Clock Enable Position */
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| 194 | #define MCLK_APBAMASK_GCLK_Msk (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos) /**< (MCLK_APBAMASK) GCLK APB Clock Enable Mask */
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| 195 | #define MCLK_APBAMASK_GCLK(value) (MCLK_APBAMASK_GCLK_Msk & ((value) << MCLK_APBAMASK_GCLK_Pos))
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| 196 | #define MCLK_APBAMASK_WDT_Pos _U_(8) /**< (MCLK_APBAMASK) WDT APB Clock Enable Position */
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| 197 | #define MCLK_APBAMASK_WDT_Msk (_U_(0x1) << MCLK_APBAMASK_WDT_Pos) /**< (MCLK_APBAMASK) WDT APB Clock Enable Mask */
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| 198 | #define MCLK_APBAMASK_WDT(value) (MCLK_APBAMASK_WDT_Msk & ((value) << MCLK_APBAMASK_WDT_Pos))
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| 199 | #define MCLK_APBAMASK_RTC_Pos _U_(9) /**< (MCLK_APBAMASK) RTC APB Clock Enable Position */
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| 200 | #define MCLK_APBAMASK_RTC_Msk (_U_(0x1) << MCLK_APBAMASK_RTC_Pos) /**< (MCLK_APBAMASK) RTC APB Clock Enable Mask */
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| 201 | #define MCLK_APBAMASK_RTC(value) (MCLK_APBAMASK_RTC_Msk & ((value) << MCLK_APBAMASK_RTC_Pos))
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| 202 | #define MCLK_APBAMASK_EIC_Pos _U_(10) /**< (MCLK_APBAMASK) EIC APB Clock Enable Position */
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| 203 | #define MCLK_APBAMASK_EIC_Msk (_U_(0x1) << MCLK_APBAMASK_EIC_Pos) /**< (MCLK_APBAMASK) EIC APB Clock Enable Mask */
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| 204 | #define MCLK_APBAMASK_EIC(value) (MCLK_APBAMASK_EIC_Msk & ((value) << MCLK_APBAMASK_EIC_Pos))
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| 205 | #define MCLK_APBAMASK_FREQM_Pos _U_(11) /**< (MCLK_APBAMASK) FREQM APB Clock Enable Position */
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| 206 | #define MCLK_APBAMASK_FREQM_Msk (_U_(0x1) << MCLK_APBAMASK_FREQM_Pos) /**< (MCLK_APBAMASK) FREQM APB Clock Enable Mask */
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| 207 | #define MCLK_APBAMASK_FREQM(value) (MCLK_APBAMASK_FREQM_Msk & ((value) << MCLK_APBAMASK_FREQM_Pos))
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| 208 | #define MCLK_APBAMASK_SERCOM0_Pos _U_(12) /**< (MCLK_APBAMASK) SERCOM0 APB Clock Enable Position */
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| 209 | #define MCLK_APBAMASK_SERCOM0_Msk (_U_(0x1) << MCLK_APBAMASK_SERCOM0_Pos) /**< (MCLK_APBAMASK) SERCOM0 APB Clock Enable Mask */
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| 210 | #define MCLK_APBAMASK_SERCOM0(value) (MCLK_APBAMASK_SERCOM0_Msk & ((value) << MCLK_APBAMASK_SERCOM0_Pos))
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| 211 | #define MCLK_APBAMASK_SERCOM1_Pos _U_(13) /**< (MCLK_APBAMASK) SERCOM1 APB Clock Enable Position */
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| 212 | #define MCLK_APBAMASK_SERCOM1_Msk (_U_(0x1) << MCLK_APBAMASK_SERCOM1_Pos) /**< (MCLK_APBAMASK) SERCOM1 APB Clock Enable Mask */
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| 213 | #define MCLK_APBAMASK_SERCOM1(value) (MCLK_APBAMASK_SERCOM1_Msk & ((value) << MCLK_APBAMASK_SERCOM1_Pos))
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| 214 | #define MCLK_APBAMASK_TC0_Pos _U_(14) /**< (MCLK_APBAMASK) TC0 APB Clock Enable Position */
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| 215 | #define MCLK_APBAMASK_TC0_Msk (_U_(0x1) << MCLK_APBAMASK_TC0_Pos) /**< (MCLK_APBAMASK) TC0 APB Clock Enable Mask */
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| 216 | #define MCLK_APBAMASK_TC0(value) (MCLK_APBAMASK_TC0_Msk & ((value) << MCLK_APBAMASK_TC0_Pos))
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| 217 | #define MCLK_APBAMASK_TC1_Pos _U_(15) /**< (MCLK_APBAMASK) TC1 APB Clock Enable Position */
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| 218 | #define MCLK_APBAMASK_TC1_Msk (_U_(0x1) << MCLK_APBAMASK_TC1_Pos) /**< (MCLK_APBAMASK) TC1 APB Clock Enable Mask */
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| 219 | #define MCLK_APBAMASK_TC1(value) (MCLK_APBAMASK_TC1_Msk & ((value) << MCLK_APBAMASK_TC1_Pos))
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| 220 | #define MCLK_APBAMASK_Msk _U_(0x0000FFFF) /**< (MCLK_APBAMASK) Register Mask */
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| 221 |
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| 222 | #define MCLK_APBAMASK_SERCOM_Pos _U_(12) /**< (MCLK_APBAMASK Position) SERCOMx APB Clock Enable */
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| 223 | #define MCLK_APBAMASK_SERCOM_Msk (_U_(0x3) << MCLK_APBAMASK_SERCOM_Pos) /**< (MCLK_APBAMASK Mask) SERCOM */
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| 224 | #define MCLK_APBAMASK_SERCOM(value) (MCLK_APBAMASK_SERCOM_Msk & ((value) << MCLK_APBAMASK_SERCOM_Pos))
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| 225 | #define MCLK_APBAMASK_TC_Pos _U_(14) /**< (MCLK_APBAMASK Position) TCx APB Clock Enable */
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| 226 | #define MCLK_APBAMASK_TC_Msk (_U_(0x3) << MCLK_APBAMASK_TC_Pos) /**< (MCLK_APBAMASK Mask) TC */
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| 227 | #define MCLK_APBAMASK_TC(value) (MCLK_APBAMASK_TC_Msk & ((value) << MCLK_APBAMASK_TC_Pos))
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| 228 |
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| 229 | /* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */
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| 230 | #define MCLK_APBBMASK_RESETVALUE _U_(0x18056) /**< (MCLK_APBBMASK) APBB Mask Reset Value */
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| 231 |
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| 232 | #define MCLK_APBBMASK_USB_Pos _U_(0) /**< (MCLK_APBBMASK) USB APB Clock Enable Position */
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| 233 | #define MCLK_APBBMASK_USB_Msk (_U_(0x1) << MCLK_APBBMASK_USB_Pos) /**< (MCLK_APBBMASK) USB APB Clock Enable Mask */
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| 234 | #define MCLK_APBBMASK_USB(value) (MCLK_APBBMASK_USB_Msk & ((value) << MCLK_APBBMASK_USB_Pos))
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| 235 | #define MCLK_APBBMASK_DSU_Pos _U_(1) /**< (MCLK_APBBMASK) DSU APB Clock Enable Position */
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| 236 | #define MCLK_APBBMASK_DSU_Msk (_U_(0x1) << MCLK_APBBMASK_DSU_Pos) /**< (MCLK_APBBMASK) DSU APB Clock Enable Mask */
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| 237 | #define MCLK_APBBMASK_DSU(value) (MCLK_APBBMASK_DSU_Msk & ((value) << MCLK_APBBMASK_DSU_Pos))
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| 238 | #define MCLK_APBBMASK_NVMCTRL_Pos _U_(2) /**< (MCLK_APBBMASK) NVMCTRL APB Clock Enable Position */
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| 239 | #define MCLK_APBBMASK_NVMCTRL_Msk (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos) /**< (MCLK_APBBMASK) NVMCTRL APB Clock Enable Mask */
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| 240 | #define MCLK_APBBMASK_NVMCTRL(value) (MCLK_APBBMASK_NVMCTRL_Msk & ((value) << MCLK_APBBMASK_NVMCTRL_Pos))
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| 241 | #define MCLK_APBBMASK_PORT_Pos _U_(4) /**< (MCLK_APBBMASK) PORT APB Clock Enable Position */
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| 242 | #define MCLK_APBBMASK_PORT_Msk (_U_(0x1) << MCLK_APBBMASK_PORT_Pos) /**< (MCLK_APBBMASK) PORT APB Clock Enable Mask */
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| 243 | #define MCLK_APBBMASK_PORT(value) (MCLK_APBBMASK_PORT_Msk & ((value) << MCLK_APBBMASK_PORT_Pos))
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| 244 | #define MCLK_APBBMASK_HMATRIX_Pos _U_(6) /**< (MCLK_APBBMASK) HMATRIX APB Clock Enable Position */
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| 245 | #define MCLK_APBBMASK_HMATRIX_Msk (_U_(0x1) << MCLK_APBBMASK_HMATRIX_Pos) /**< (MCLK_APBBMASK) HMATRIX APB Clock Enable Mask */
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| 246 | #define MCLK_APBBMASK_HMATRIX(value) (MCLK_APBBMASK_HMATRIX_Msk & ((value) << MCLK_APBBMASK_HMATRIX_Pos))
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| 247 | #define MCLK_APBBMASK_EVSYS_Pos _U_(7) /**< (MCLK_APBBMASK) EVSYS APB Clock Enable Position */
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| 248 | #define MCLK_APBBMASK_EVSYS_Msk (_U_(0x1) << MCLK_APBBMASK_EVSYS_Pos) /**< (MCLK_APBBMASK) EVSYS APB Clock Enable Mask */
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| 249 | #define MCLK_APBBMASK_EVSYS(value) (MCLK_APBBMASK_EVSYS_Msk & ((value) << MCLK_APBBMASK_EVSYS_Pos))
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| 250 | #define MCLK_APBBMASK_SERCOM2_Pos _U_(9) /**< (MCLK_APBBMASK) SERCOM2 APB Clock Enable Position */
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| 251 | #define MCLK_APBBMASK_SERCOM2_Msk (_U_(0x1) << MCLK_APBBMASK_SERCOM2_Pos) /**< (MCLK_APBBMASK) SERCOM2 APB Clock Enable Mask */
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| 252 | #define MCLK_APBBMASK_SERCOM2(value) (MCLK_APBBMASK_SERCOM2_Msk & ((value) << MCLK_APBBMASK_SERCOM2_Pos))
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| 253 | #define MCLK_APBBMASK_SERCOM3_Pos _U_(10) /**< (MCLK_APBBMASK) SERCOM3 APB Clock Enable Position */
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| 254 | #define MCLK_APBBMASK_SERCOM3_Msk (_U_(0x1) << MCLK_APBBMASK_SERCOM3_Pos) /**< (MCLK_APBBMASK) SERCOM3 APB Clock Enable Mask */
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| 255 | #define MCLK_APBBMASK_SERCOM3(value) (MCLK_APBBMASK_SERCOM3_Msk & ((value) << MCLK_APBBMASK_SERCOM3_Pos))
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| 256 | #define MCLK_APBBMASK_TCC0_Pos _U_(11) /**< (MCLK_APBBMASK) TCC0 APB Clock Enable Position */
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| 257 | #define MCLK_APBBMASK_TCC0_Msk (_U_(0x1) << MCLK_APBBMASK_TCC0_Pos) /**< (MCLK_APBBMASK) TCC0 APB Clock Enable Mask */
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| 258 | #define MCLK_APBBMASK_TCC0(value) (MCLK_APBBMASK_TCC0_Msk & ((value) << MCLK_APBBMASK_TCC0_Pos))
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| 259 | #define MCLK_APBBMASK_TCC1_Pos _U_(12) /**< (MCLK_APBBMASK) TCC1 APB Clock Enable Position */
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| 260 | #define MCLK_APBBMASK_TCC1_Msk (_U_(0x1) << MCLK_APBBMASK_TCC1_Pos) /**< (MCLK_APBBMASK) TCC1 APB Clock Enable Mask */
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| 261 | #define MCLK_APBBMASK_TCC1(value) (MCLK_APBBMASK_TCC1_Msk & ((value) << MCLK_APBBMASK_TCC1_Pos))
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| 262 | #define MCLK_APBBMASK_TC2_Pos _U_(13) /**< (MCLK_APBBMASK) TC2 APB Clock Enable Position */
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| 263 | #define MCLK_APBBMASK_TC2_Msk (_U_(0x1) << MCLK_APBBMASK_TC2_Pos) /**< (MCLK_APBBMASK) TC2 APB Clock Enable Mask */
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| 264 | #define MCLK_APBBMASK_TC2(value) (MCLK_APBBMASK_TC2_Msk & ((value) << MCLK_APBBMASK_TC2_Pos))
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| 265 | #define MCLK_APBBMASK_TC3_Pos _U_(14) /**< (MCLK_APBBMASK) TC3 APB Clock Enable Position */
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| 266 | #define MCLK_APBBMASK_TC3_Msk (_U_(0x1) << MCLK_APBBMASK_TC3_Pos) /**< (MCLK_APBBMASK) TC3 APB Clock Enable Mask */
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| 267 | #define MCLK_APBBMASK_TC3(value) (MCLK_APBBMASK_TC3_Msk & ((value) << MCLK_APBBMASK_TC3_Pos))
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| 268 | #define MCLK_APBBMASK_RAMECC_Pos _U_(16) /**< (MCLK_APBBMASK) RAMECC APB Clock Enable Position */
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| 269 | #define MCLK_APBBMASK_RAMECC_Msk (_U_(0x1) << MCLK_APBBMASK_RAMECC_Pos) /**< (MCLK_APBBMASK) RAMECC APB Clock Enable Mask */
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| 270 | #define MCLK_APBBMASK_RAMECC(value) (MCLK_APBBMASK_RAMECC_Msk & ((value) << MCLK_APBBMASK_RAMECC_Pos))
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| 271 | #define MCLK_APBBMASK_Msk _U_(0x00017ED7) /**< (MCLK_APBBMASK) Register Mask */
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| 272 |
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| 273 | #define MCLK_APBBMASK_SERCOM_Pos _U_(9) /**< (MCLK_APBBMASK Position) SERCOM2 APB Clock Enable */
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| 274 | #define MCLK_APBBMASK_SERCOM_Msk (_U_(0x3) << MCLK_APBBMASK_SERCOM_Pos) /**< (MCLK_APBBMASK Mask) SERCOM */
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| 275 | #define MCLK_APBBMASK_SERCOM(value) (MCLK_APBBMASK_SERCOM_Msk & ((value) << MCLK_APBBMASK_SERCOM_Pos))
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| 276 | #define MCLK_APBBMASK_TCC_Pos _U_(11) /**< (MCLK_APBBMASK Position) TCCx APB Clock Enable */
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| 277 | #define MCLK_APBBMASK_TCC_Msk (_U_(0x3) << MCLK_APBBMASK_TCC_Pos) /**< (MCLK_APBBMASK Mask) TCC */
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| 278 | #define MCLK_APBBMASK_TCC(value) (MCLK_APBBMASK_TCC_Msk & ((value) << MCLK_APBBMASK_TCC_Pos))
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| 279 | #define MCLK_APBBMASK_TC_Pos _U_(13) /**< (MCLK_APBBMASK Position) TC2 APB Clock Enable */
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| 280 | #define MCLK_APBBMASK_TC_Msk (_U_(0x3) << MCLK_APBBMASK_TC_Pos) /**< (MCLK_APBBMASK Mask) TC */
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| 281 | #define MCLK_APBBMASK_TC(value) (MCLK_APBBMASK_TC_Msk & ((value) << MCLK_APBBMASK_TC_Pos))
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| 282 |
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| 283 | /* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */
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| 284 | #define MCLK_APBCMASK_RESETVALUE _U_(0x2000) /**< (MCLK_APBCMASK) APBC Mask Reset Value */
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| 285 |
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| 286 | #define MCLK_APBCMASK_TCC2_Pos _U_(3) /**< (MCLK_APBCMASK) TCC2 APB Clock Enable Position */
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| 287 | #define MCLK_APBCMASK_TCC2_Msk (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos) /**< (MCLK_APBCMASK) TCC2 APB Clock Enable Mask */
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| 288 | #define MCLK_APBCMASK_TCC2(value) (MCLK_APBCMASK_TCC2_Msk & ((value) << MCLK_APBCMASK_TCC2_Pos))
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| 289 | #define MCLK_APBCMASK_TCC3_Pos _U_(4) /**< (MCLK_APBCMASK) TCC3 APB Clock Enable Position */
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| 290 | #define MCLK_APBCMASK_TCC3_Msk (_U_(0x1) << MCLK_APBCMASK_TCC3_Pos) /**< (MCLK_APBCMASK) TCC3 APB Clock Enable Mask */
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| 291 | #define MCLK_APBCMASK_TCC3(value) (MCLK_APBCMASK_TCC3_Msk & ((value) << MCLK_APBCMASK_TCC3_Pos))
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| 292 | #define MCLK_APBCMASK_TC4_Pos _U_(5) /**< (MCLK_APBCMASK) TC4 APB Clock Enable Position */
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| 293 | #define MCLK_APBCMASK_TC4_Msk (_U_(0x1) << MCLK_APBCMASK_TC4_Pos) /**< (MCLK_APBCMASK) TC4 APB Clock Enable Mask */
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| 294 | #define MCLK_APBCMASK_TC4(value) (MCLK_APBCMASK_TC4_Msk & ((value) << MCLK_APBCMASK_TC4_Pos))
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| 295 | #define MCLK_APBCMASK_TC5_Pos _U_(6) /**< (MCLK_APBCMASK) TC5 APB Clock Enable Position */
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| 296 | #define MCLK_APBCMASK_TC5_Msk (_U_(0x1) << MCLK_APBCMASK_TC5_Pos) /**< (MCLK_APBCMASK) TC5 APB Clock Enable Mask */
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| 297 | #define MCLK_APBCMASK_TC5(value) (MCLK_APBCMASK_TC5_Msk & ((value) << MCLK_APBCMASK_TC5_Pos))
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| 298 | #define MCLK_APBCMASK_PDEC_Pos _U_(7) /**< (MCLK_APBCMASK) PDEC APB Clock Enable Position */
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| 299 | #define MCLK_APBCMASK_PDEC_Msk (_U_(0x1) << MCLK_APBCMASK_PDEC_Pos) /**< (MCLK_APBCMASK) PDEC APB Clock Enable Mask */
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| 300 | #define MCLK_APBCMASK_PDEC(value) (MCLK_APBCMASK_PDEC_Msk & ((value) << MCLK_APBCMASK_PDEC_Pos))
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| 301 | #define MCLK_APBCMASK_AC_Pos _U_(8) /**< (MCLK_APBCMASK) AC APB Clock Enable Position */
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| 302 | #define MCLK_APBCMASK_AC_Msk (_U_(0x1) << MCLK_APBCMASK_AC_Pos) /**< (MCLK_APBCMASK) AC APB Clock Enable Mask */
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| 303 | #define MCLK_APBCMASK_AC(value) (MCLK_APBCMASK_AC_Msk & ((value) << MCLK_APBCMASK_AC_Pos))
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| 304 | #define MCLK_APBCMASK_AES_Pos _U_(9) /**< (MCLK_APBCMASK) AES APB Clock Enable Position */
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| 305 | #define MCLK_APBCMASK_AES_Msk (_U_(0x1) << MCLK_APBCMASK_AES_Pos) /**< (MCLK_APBCMASK) AES APB Clock Enable Mask */
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| 306 | #define MCLK_APBCMASK_AES(value) (MCLK_APBCMASK_AES_Msk & ((value) << MCLK_APBCMASK_AES_Pos))
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| 307 | #define MCLK_APBCMASK_TRNG_Pos _U_(10) /**< (MCLK_APBCMASK) TRNG APB Clock Enable Position */
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| 308 | #define MCLK_APBCMASK_TRNG_Msk (_U_(0x1) << MCLK_APBCMASK_TRNG_Pos) /**< (MCLK_APBCMASK) TRNG APB Clock Enable Mask */
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| 309 | #define MCLK_APBCMASK_TRNG(value) (MCLK_APBCMASK_TRNG_Msk & ((value) << MCLK_APBCMASK_TRNG_Pos))
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| 310 | #define MCLK_APBCMASK_ICM_Pos _U_(11) /**< (MCLK_APBCMASK) ICM APB Clock Enable Position */
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| 311 | #define MCLK_APBCMASK_ICM_Msk (_U_(0x1) << MCLK_APBCMASK_ICM_Pos) /**< (MCLK_APBCMASK) ICM APB Clock Enable Mask */
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| 312 | #define MCLK_APBCMASK_ICM(value) (MCLK_APBCMASK_ICM_Msk & ((value) << MCLK_APBCMASK_ICM_Pos))
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| 313 | #define MCLK_APBCMASK_QSPI_Pos _U_(13) /**< (MCLK_APBCMASK) QSPI APB Clock Enable Position */
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| 314 | #define MCLK_APBCMASK_QSPI_Msk (_U_(0x1) << MCLK_APBCMASK_QSPI_Pos) /**< (MCLK_APBCMASK) QSPI APB Clock Enable Mask */
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| 315 | #define MCLK_APBCMASK_QSPI(value) (MCLK_APBCMASK_QSPI_Msk & ((value) << MCLK_APBCMASK_QSPI_Pos))
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| 316 | #define MCLK_APBCMASK_CCL_Pos _U_(14) /**< (MCLK_APBCMASK) CCL APB Clock Enable Position */
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| 317 | #define MCLK_APBCMASK_CCL_Msk (_U_(0x1) << MCLK_APBCMASK_CCL_Pos) /**< (MCLK_APBCMASK) CCL APB Clock Enable Mask */
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| 318 | #define MCLK_APBCMASK_CCL(value) (MCLK_APBCMASK_CCL_Msk & ((value) << MCLK_APBCMASK_CCL_Pos))
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| 319 | #define MCLK_APBCMASK_Msk _U_(0x00006FF8) /**< (MCLK_APBCMASK) Register Mask */
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| 320 |
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| 321 | #define MCLK_APBCMASK_TCC_Pos _U_(3) /**< (MCLK_APBCMASK Position) TCC2 APB Clock Enable */
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| 322 | #define MCLK_APBCMASK_TCC_Msk (_U_(0x3) << MCLK_APBCMASK_TCC_Pos) /**< (MCLK_APBCMASK Mask) TCC */
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| 323 | #define MCLK_APBCMASK_TCC(value) (MCLK_APBCMASK_TCC_Msk & ((value) << MCLK_APBCMASK_TCC_Pos))
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| 324 | #define MCLK_APBCMASK_TC_Pos _U_(5) /**< (MCLK_APBCMASK Position) TC4 APB Clock Enable */
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| 325 | #define MCLK_APBCMASK_TC_Msk (_U_(0x3) << MCLK_APBCMASK_TC_Pos) /**< (MCLK_APBCMASK Mask) TC */
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| 326 | #define MCLK_APBCMASK_TC(value) (MCLK_APBCMASK_TC_Msk & ((value) << MCLK_APBCMASK_TC_Pos))
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| 327 |
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| 328 | /* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */
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| 329 | #define MCLK_APBDMASK_RESETVALUE _U_(0x00) /**< (MCLK_APBDMASK) APBD Mask Reset Value */
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| 330 |
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| 331 | #define MCLK_APBDMASK_SERCOM4_Pos _U_(0) /**< (MCLK_APBDMASK) SERCOM4 APB Clock Enable Position */
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| 332 | #define MCLK_APBDMASK_SERCOM4_Msk (_U_(0x1) << MCLK_APBDMASK_SERCOM4_Pos) /**< (MCLK_APBDMASK) SERCOM4 APB Clock Enable Mask */
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| 333 | #define MCLK_APBDMASK_SERCOM4(value) (MCLK_APBDMASK_SERCOM4_Msk & ((value) << MCLK_APBDMASK_SERCOM4_Pos))
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| 334 | #define MCLK_APBDMASK_SERCOM5_Pos _U_(1) /**< (MCLK_APBDMASK) SERCOM5 APB Clock Enable Position */
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| 335 | #define MCLK_APBDMASK_SERCOM5_Msk (_U_(0x1) << MCLK_APBDMASK_SERCOM5_Pos) /**< (MCLK_APBDMASK) SERCOM5 APB Clock Enable Mask */
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| 336 | #define MCLK_APBDMASK_SERCOM5(value) (MCLK_APBDMASK_SERCOM5_Msk & ((value) << MCLK_APBDMASK_SERCOM5_Pos))
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| 337 | #define MCLK_APBDMASK_SERCOM6_Pos _U_(2) /**< (MCLK_APBDMASK) SERCOM6 APB Clock Enable Position */
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| 338 | #define MCLK_APBDMASK_SERCOM6_Msk (_U_(0x1) << MCLK_APBDMASK_SERCOM6_Pos) /**< (MCLK_APBDMASK) SERCOM6 APB Clock Enable Mask */
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| 339 | #define MCLK_APBDMASK_SERCOM6(value) (MCLK_APBDMASK_SERCOM6_Msk & ((value) << MCLK_APBDMASK_SERCOM6_Pos))
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| 340 | #define MCLK_APBDMASK_SERCOM7_Pos _U_(3) /**< (MCLK_APBDMASK) SERCOM7 APB Clock Enable Position */
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| 341 | #define MCLK_APBDMASK_SERCOM7_Msk (_U_(0x1) << MCLK_APBDMASK_SERCOM7_Pos) /**< (MCLK_APBDMASK) SERCOM7 APB Clock Enable Mask */
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| 342 | #define MCLK_APBDMASK_SERCOM7(value) (MCLK_APBDMASK_SERCOM7_Msk & ((value) << MCLK_APBDMASK_SERCOM7_Pos))
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| 343 | #define MCLK_APBDMASK_TCC4_Pos _U_(4) /**< (MCLK_APBDMASK) TCC4 APB Clock Enable Position */
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| 344 | #define MCLK_APBDMASK_TCC4_Msk (_U_(0x1) << MCLK_APBDMASK_TCC4_Pos) /**< (MCLK_APBDMASK) TCC4 APB Clock Enable Mask */
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| 345 | #define MCLK_APBDMASK_TCC4(value) (MCLK_APBDMASK_TCC4_Msk & ((value) << MCLK_APBDMASK_TCC4_Pos))
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| 346 | #define MCLK_APBDMASK_TC6_Pos _U_(5) /**< (MCLK_APBDMASK) TC6 APB Clock Enable Position */
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| 347 | #define MCLK_APBDMASK_TC6_Msk (_U_(0x1) << MCLK_APBDMASK_TC6_Pos) /**< (MCLK_APBDMASK) TC6 APB Clock Enable Mask */
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| 348 | #define MCLK_APBDMASK_TC6(value) (MCLK_APBDMASK_TC6_Msk & ((value) << MCLK_APBDMASK_TC6_Pos))
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| 349 | #define MCLK_APBDMASK_TC7_Pos _U_(6) /**< (MCLK_APBDMASK) TC7 APB Clock Enable Position */
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| 350 | #define MCLK_APBDMASK_TC7_Msk (_U_(0x1) << MCLK_APBDMASK_TC7_Pos) /**< (MCLK_APBDMASK) TC7 APB Clock Enable Mask */
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| 351 | #define MCLK_APBDMASK_TC7(value) (MCLK_APBDMASK_TC7_Msk & ((value) << MCLK_APBDMASK_TC7_Pos))
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| 352 | #define MCLK_APBDMASK_ADC0_Pos _U_(7) /**< (MCLK_APBDMASK) ADC0 APB Clock Enable Position */
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| 353 | #define MCLK_APBDMASK_ADC0_Msk (_U_(0x1) << MCLK_APBDMASK_ADC0_Pos) /**< (MCLK_APBDMASK) ADC0 APB Clock Enable Mask */
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| 354 | #define MCLK_APBDMASK_ADC0(value) (MCLK_APBDMASK_ADC0_Msk & ((value) << MCLK_APBDMASK_ADC0_Pos))
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| 355 | #define MCLK_APBDMASK_ADC1_Pos _U_(8) /**< (MCLK_APBDMASK) ADC1 APB Clock Enable Position */
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| 356 | #define MCLK_APBDMASK_ADC1_Msk (_U_(0x1) << MCLK_APBDMASK_ADC1_Pos) /**< (MCLK_APBDMASK) ADC1 APB Clock Enable Mask */
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| 357 | #define MCLK_APBDMASK_ADC1(value) (MCLK_APBDMASK_ADC1_Msk & ((value) << MCLK_APBDMASK_ADC1_Pos))
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| 358 | #define MCLK_APBDMASK_DAC_Pos _U_(9) /**< (MCLK_APBDMASK) DAC APB Clock Enable Position */
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| 359 | #define MCLK_APBDMASK_DAC_Msk (_U_(0x1) << MCLK_APBDMASK_DAC_Pos) /**< (MCLK_APBDMASK) DAC APB Clock Enable Mask */
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| 360 | #define MCLK_APBDMASK_DAC(value) (MCLK_APBDMASK_DAC_Msk & ((value) << MCLK_APBDMASK_DAC_Pos))
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| 361 | #define MCLK_APBDMASK_I2S_Pos _U_(10) /**< (MCLK_APBDMASK) I2S APB Clock Enable Position */
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| 362 | #define MCLK_APBDMASK_I2S_Msk (_U_(0x1) << MCLK_APBDMASK_I2S_Pos) /**< (MCLK_APBDMASK) I2S APB Clock Enable Mask */
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| 363 | #define MCLK_APBDMASK_I2S(value) (MCLK_APBDMASK_I2S_Msk & ((value) << MCLK_APBDMASK_I2S_Pos))
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| 364 | #define MCLK_APBDMASK_PCC_Pos _U_(11) /**< (MCLK_APBDMASK) PCC APB Clock Enable Position */
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| 365 | #define MCLK_APBDMASK_PCC_Msk (_U_(0x1) << MCLK_APBDMASK_PCC_Pos) /**< (MCLK_APBDMASK) PCC APB Clock Enable Mask */
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| 366 | #define MCLK_APBDMASK_PCC(value) (MCLK_APBDMASK_PCC_Msk & ((value) << MCLK_APBDMASK_PCC_Pos))
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| 367 | #define MCLK_APBDMASK_Msk _U_(0x00000FFF) /**< (MCLK_APBDMASK) Register Mask */
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| 368 |
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| 369 | #define MCLK_APBDMASK_SERCOM_Pos _U_(0) /**< (MCLK_APBDMASK Position) SERCOM4 APB Clock Enable */
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| 370 | #define MCLK_APBDMASK_SERCOM_Msk (_U_(0xF) << MCLK_APBDMASK_SERCOM_Pos) /**< (MCLK_APBDMASK Mask) SERCOM */
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| 371 | #define MCLK_APBDMASK_SERCOM(value) (MCLK_APBDMASK_SERCOM_Msk & ((value) << MCLK_APBDMASK_SERCOM_Pos))
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| 372 | #define MCLK_APBDMASK_TCC_Pos _U_(4) /**< (MCLK_APBDMASK Position) TCC4 APB Clock Enable */
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| 373 | #define MCLK_APBDMASK_TCC_Msk (_U_(0x1) << MCLK_APBDMASK_TCC_Pos) /**< (MCLK_APBDMASK Mask) TCC */
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| 374 | #define MCLK_APBDMASK_TCC(value) (MCLK_APBDMASK_TCC_Msk & ((value) << MCLK_APBDMASK_TCC_Pos))
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| 375 | #define MCLK_APBDMASK_TC_Pos _U_(5) /**< (MCLK_APBDMASK Position) TC6 APB Clock Enable */
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| 376 | #define MCLK_APBDMASK_TC_Msk (_U_(0x3) << MCLK_APBDMASK_TC_Pos) /**< (MCLK_APBDMASK Mask) TC */
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| 377 | #define MCLK_APBDMASK_TC(value) (MCLK_APBDMASK_TC_Msk & ((value) << MCLK_APBDMASK_TC_Pos))
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| 378 | #define MCLK_APBDMASK_ADC_Pos _U_(7) /**< (MCLK_APBDMASK Position) ADCx APB Clock Enable */
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| 379 | #define MCLK_APBDMASK_ADC_Msk (_U_(0x3) << MCLK_APBDMASK_ADC_Pos) /**< (MCLK_APBDMASK Mask) ADC */
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| 380 | #define MCLK_APBDMASK_ADC(value) (MCLK_APBDMASK_ADC_Msk & ((value) << MCLK_APBDMASK_ADC_Pos))
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| 381 |
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| 382 | /** \brief MCLK register offsets definitions */
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| 383 | #define MCLK_INTENCLR_REG_OFST (0x01) /**< (MCLK_INTENCLR) Interrupt Enable Clear Offset */
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| 384 | #define MCLK_INTENSET_REG_OFST (0x02) /**< (MCLK_INTENSET) Interrupt Enable Set Offset */
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| 385 | #define MCLK_INTFLAG_REG_OFST (0x03) /**< (MCLK_INTFLAG) Interrupt Flag Status and Clear Offset */
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| 386 | #define MCLK_HSDIV_REG_OFST (0x04) /**< (MCLK_HSDIV) HS Clock Division Offset */
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| 387 | #define MCLK_CPUDIV_REG_OFST (0x05) /**< (MCLK_CPUDIV) CPU Clock Division Offset */
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| 388 | #define MCLK_AHBMASK_REG_OFST (0x10) /**< (MCLK_AHBMASK) AHB Mask Offset */
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| 389 | #define MCLK_APBAMASK_REG_OFST (0x14) /**< (MCLK_APBAMASK) APBA Mask Offset */
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| 390 | #define MCLK_APBBMASK_REG_OFST (0x18) /**< (MCLK_APBBMASK) APBB Mask Offset */
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| 391 | #define MCLK_APBCMASK_REG_OFST (0x1C) /**< (MCLK_APBCMASK) APBC Mask Offset */
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| 392 | #define MCLK_APBDMASK_REG_OFST (0x20) /**< (MCLK_APBDMASK) APBD Mask Offset */
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| 393 |
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| 394 | #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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| 395 | /** \brief MCLK register API structure */
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| 396 | typedef struct
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| 397 | { /* Main Clock */
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| 398 | __I uint8_t Reserved1[0x01];
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| 399 | __IO uint8_t MCLK_INTENCLR; /**< Offset: 0x01 (R/W 8) Interrupt Enable Clear */
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| 400 | __IO uint8_t MCLK_INTENSET; /**< Offset: 0x02 (R/W 8) Interrupt Enable Set */
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| 401 | __IO uint8_t MCLK_INTFLAG; /**< Offset: 0x03 (R/W 8) Interrupt Flag Status and Clear */
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| 402 | __I uint8_t MCLK_HSDIV; /**< Offset: 0x04 (R/ 8) HS Clock Division */
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| 403 | __IO uint8_t MCLK_CPUDIV; /**< Offset: 0x05 (R/W 8) CPU Clock Division */
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| 404 | __I uint8_t Reserved2[0x0A];
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| 405 | __IO uint32_t MCLK_AHBMASK; /**< Offset: 0x10 (R/W 32) AHB Mask */
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| 406 | __IO uint32_t MCLK_APBAMASK; /**< Offset: 0x14 (R/W 32) APBA Mask */
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| 407 | __IO uint32_t MCLK_APBBMASK; /**< Offset: 0x18 (R/W 32) APBB Mask */
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| 408 | __IO uint32_t MCLK_APBCMASK; /**< Offset: 0x1C (R/W 32) APBC Mask */
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| 409 | __IO uint32_t MCLK_APBDMASK; /**< Offset: 0x20 (R/W 32) APBD Mask */
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| 410 | } mclk_registers_t;
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| 411 |
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| 412 |
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| 413 | #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 414 | #endif /* _SAMD51_MCLK_COMPONENT_H_ */
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