source: asp_wio_terminal/trunk/target/samd51_gcc/lib/gclk.h@ 460

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1/**
2 * \brief Component description for GCLK
3 *
4 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
5 *
6 * Subject to your compliance with these terms, you may use Microchip software and any derivatives
7 * exclusively with Microchip products. It is your responsibility to comply with third party license
8 * terms applicable to your use of third party software (including open source software) that may
9 * accompany Microchip software.
10 *
11 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
12 * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
13 * FITNESS FOR A PARTICULAR PURPOSE.
14 *
15 * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
16 * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
17 * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
18 * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
19 * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
20 *
21 */
22
23/* file generated from device description version 2020-03-12T17:26:00Z */
24#ifndef _SAMD51_GCLK_COMPONENT_H_
25#define _SAMD51_GCLK_COMPONENT_H_
26
27/* ************************************************************************** */
28/* SOFTWARE API DEFINITION FOR GCLK */
29/* ************************************************************************** */
30
31/* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */
32#define GCLK_CTRLA_RESETVALUE _U_(0x00) /**< (GCLK_CTRLA) Control Reset Value */
33
34#define GCLK_CTRLA_SWRST_Pos _U_(0) /**< (GCLK_CTRLA) Software Reset Position */
35#define GCLK_CTRLA_SWRST_Msk (_U_(0x1) << GCLK_CTRLA_SWRST_Pos) /**< (GCLK_CTRLA) Software Reset Mask */
36#define GCLK_CTRLA_SWRST(value) (GCLK_CTRLA_SWRST_Msk & ((value) << GCLK_CTRLA_SWRST_Pos))
37#define GCLK_CTRLA_Msk _U_(0x01) /**< (GCLK_CTRLA) Register Mask */
38
39
40/* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) ( R/ 32) Synchronization Busy -------- */
41#define GCLK_SYNCBUSY_RESETVALUE _U_(0x00) /**< (GCLK_SYNCBUSY) Synchronization Busy Reset Value */
42
43#define GCLK_SYNCBUSY_SWRST_Pos _U_(0) /**< (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit Position */
44#define GCLK_SYNCBUSY_SWRST_Msk (_U_(0x1) << GCLK_SYNCBUSY_SWRST_Pos) /**< (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit Mask */
45#define GCLK_SYNCBUSY_SWRST(value) (GCLK_SYNCBUSY_SWRST_Msk & ((value) << GCLK_SYNCBUSY_SWRST_Pos))
46#define GCLK_SYNCBUSY_GENCTRL_Pos _U_(2) /**< (GCLK_SYNCBUSY) Generic Clock Generator Control n Synchronization Busy bits Position */
47#define GCLK_SYNCBUSY_GENCTRL_Msk (_U_(0xFFF) << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic Clock Generator Control n Synchronization Busy bits Mask */
48#define GCLK_SYNCBUSY_GENCTRL(value) (GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos))
49#define GCLK_SYNCBUSY_GENCTRL_GCLK0_Val _U_(0x1) /**< (GCLK_SYNCBUSY) Generic clock generator 0 */
50#define GCLK_SYNCBUSY_GENCTRL_GCLK1_Val _U_(0x2) /**< (GCLK_SYNCBUSY) Generic clock generator 1 */
51#define GCLK_SYNCBUSY_GENCTRL_GCLK2_Val _U_(0x4) /**< (GCLK_SYNCBUSY) Generic clock generator 2 */
52#define GCLK_SYNCBUSY_GENCTRL_GCLK3_Val _U_(0x8) /**< (GCLK_SYNCBUSY) Generic clock generator 3 */
53#define GCLK_SYNCBUSY_GENCTRL_GCLK4_Val _U_(0x10) /**< (GCLK_SYNCBUSY) Generic clock generator 4 */
54#define GCLK_SYNCBUSY_GENCTRL_GCLK5_Val _U_(0x20) /**< (GCLK_SYNCBUSY) Generic clock generator 5 */
55#define GCLK_SYNCBUSY_GENCTRL_GCLK6_Val _U_(0x40) /**< (GCLK_SYNCBUSY) Generic clock generator 6 */
56#define GCLK_SYNCBUSY_GENCTRL_GCLK7_Val _U_(0x80) /**< (GCLK_SYNCBUSY) Generic clock generator 7 */
57#define GCLK_SYNCBUSY_GENCTRL_GCLK8_Val _U_(0x100) /**< (GCLK_SYNCBUSY) Generic clock generator 8 */
58#define GCLK_SYNCBUSY_GENCTRL_GCLK9_Val _U_(0x200) /**< (GCLK_SYNCBUSY) Generic clock generator 9 */
59#define GCLK_SYNCBUSY_GENCTRL_GCLK10_Val _U_(0x400) /**< (GCLK_SYNCBUSY) Generic clock generator 10 */
60#define GCLK_SYNCBUSY_GENCTRL_GCLK11_Val _U_(0x800) /**< (GCLK_SYNCBUSY) Generic clock generator 11 */
61#define GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 0 Position */
62#define GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 1 Position */
63#define GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 2 Position */
64#define GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 3 Position */
65#define GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 4 Position */
66#define GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 5 Position */
67#define GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 6 Position */
68#define GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 7 Position */
69#define GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 8 Position */
70#define GCLK_SYNCBUSY_GENCTRL_GCLK9 (GCLK_SYNCBUSY_GENCTRL_GCLK9_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 9 Position */
71#define GCLK_SYNCBUSY_GENCTRL_GCLK10 (GCLK_SYNCBUSY_GENCTRL_GCLK10_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 10 Position */
72#define GCLK_SYNCBUSY_GENCTRL_GCLK11 (GCLK_SYNCBUSY_GENCTRL_GCLK11_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 11 Position */
73#define GCLK_SYNCBUSY_Msk _U_(0x00003FFD) /**< (GCLK_SYNCBUSY) Register Mask */
74
75
76/* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */
77#define GCLK_GENCTRL_RESETVALUE _U_(0x00) /**< (GCLK_GENCTRL) Generic Clock Generator Control Reset Value */
78
79#define GCLK_GENCTRL_SRC_Pos _U_(0) /**< (GCLK_GENCTRL) Source Select Position */
80#define GCLK_GENCTRL_SRC_Msk (_U_(0xF) << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) Source Select Mask */
81#define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
82#define GCLK_GENCTRL_SRC_XOSC0_Val _U_(0x0) /**< (GCLK_GENCTRL) XOSC0 oscillator output */
83#define GCLK_GENCTRL_SRC_XOSC1_Val _U_(0x1) /**< (GCLK_GENCTRL) XOSC1 oscillator output */
84#define GCLK_GENCTRL_SRC_GCLKIN_Val _U_(0x2) /**< (GCLK_GENCTRL) Generator input pad */
85#define GCLK_GENCTRL_SRC_GCLKGEN1_Val _U_(0x3) /**< (GCLK_GENCTRL) Generic clock generator 1 output */
86#define GCLK_GENCTRL_SRC_OSCULP32K_Val _U_(0x4) /**< (GCLK_GENCTRL) OSCULP32K oscillator output */
87#define GCLK_GENCTRL_SRC_XOSC32K_Val _U_(0x5) /**< (GCLK_GENCTRL) XOSC32K oscillator output */
88#define GCLK_GENCTRL_SRC_DFLL_Val _U_(0x6) /**< (GCLK_GENCTRL) DFLL output */
89#define GCLK_GENCTRL_SRC_DPLL0_Val _U_(0x7) /**< (GCLK_GENCTRL) DPLL0 output */
90#define GCLK_GENCTRL_SRC_DPLL1_Val _U_(0x8) /**< (GCLK_GENCTRL) DPLL1 output */
91#define GCLK_GENCTRL_SRC_XOSC0 (GCLK_GENCTRL_SRC_XOSC0_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) XOSC0 oscillator output Position */
92#define GCLK_GENCTRL_SRC_XOSC1 (GCLK_GENCTRL_SRC_XOSC1_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) XOSC1 oscillator output Position */
93#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) Generator input pad Position */
94#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) Generic clock generator 1 output Position */
95#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) OSCULP32K oscillator output Position */
96#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) XOSC32K oscillator output Position */
97#define GCLK_GENCTRL_SRC_DFLL (GCLK_GENCTRL_SRC_DFLL_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) DFLL output Position */
98#define GCLK_GENCTRL_SRC_DPLL0 (GCLK_GENCTRL_SRC_DPLL0_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) DPLL0 output Position */
99#define GCLK_GENCTRL_SRC_DPLL1 (GCLK_GENCTRL_SRC_DPLL1_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) DPLL1 output Position */
100#define GCLK_GENCTRL_GENEN_Pos _U_(8) /**< (GCLK_GENCTRL) Generic Clock Generator Enable Position */
101#define GCLK_GENCTRL_GENEN_Msk (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos) /**< (GCLK_GENCTRL) Generic Clock Generator Enable Mask */
102#define GCLK_GENCTRL_GENEN(value) (GCLK_GENCTRL_GENEN_Msk & ((value) << GCLK_GENCTRL_GENEN_Pos))
103#define GCLK_GENCTRL_IDC_Pos _U_(9) /**< (GCLK_GENCTRL) Improve Duty Cycle Position */
104#define GCLK_GENCTRL_IDC_Msk (_U_(0x1) << GCLK_GENCTRL_IDC_Pos) /**< (GCLK_GENCTRL) Improve Duty Cycle Mask */
105#define GCLK_GENCTRL_IDC(value) (GCLK_GENCTRL_IDC_Msk & ((value) << GCLK_GENCTRL_IDC_Pos))
106#define GCLK_GENCTRL_OOV_Pos _U_(10) /**< (GCLK_GENCTRL) Output Off Value Position */
107#define GCLK_GENCTRL_OOV_Msk (_U_(0x1) << GCLK_GENCTRL_OOV_Pos) /**< (GCLK_GENCTRL) Output Off Value Mask */
108#define GCLK_GENCTRL_OOV(value) (GCLK_GENCTRL_OOV_Msk & ((value) << GCLK_GENCTRL_OOV_Pos))
109#define GCLK_GENCTRL_OE_Pos _U_(11) /**< (GCLK_GENCTRL) Output Enable Position */
110#define GCLK_GENCTRL_OE_Msk (_U_(0x1) << GCLK_GENCTRL_OE_Pos) /**< (GCLK_GENCTRL) Output Enable Mask */
111#define GCLK_GENCTRL_OE(value) (GCLK_GENCTRL_OE_Msk & ((value) << GCLK_GENCTRL_OE_Pos))
112#define GCLK_GENCTRL_DIVSEL_Pos _U_(12) /**< (GCLK_GENCTRL) Divide Selection Position */
113#define GCLK_GENCTRL_DIVSEL_Msk (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos) /**< (GCLK_GENCTRL) Divide Selection Mask */
114#define GCLK_GENCTRL_DIVSEL(value) (GCLK_GENCTRL_DIVSEL_Msk & ((value) << GCLK_GENCTRL_DIVSEL_Pos))
115#define GCLK_GENCTRL_DIVSEL_DIV1_Val _U_(0x0) /**< (GCLK_GENCTRL) Divide input directly by divider factor */
116#define GCLK_GENCTRL_DIVSEL_DIV2_Val _U_(0x1) /**< (GCLK_GENCTRL) Divide input by 2^(divider factor+ 1) */
117#define GCLK_GENCTRL_DIVSEL_DIV1 (GCLK_GENCTRL_DIVSEL_DIV1_Val << GCLK_GENCTRL_DIVSEL_Pos) /**< (GCLK_GENCTRL) Divide input directly by divider factor Position */
118#define GCLK_GENCTRL_DIVSEL_DIV2 (GCLK_GENCTRL_DIVSEL_DIV2_Val << GCLK_GENCTRL_DIVSEL_Pos) /**< (GCLK_GENCTRL) Divide input by 2^(divider factor+ 1) Position */
119#define GCLK_GENCTRL_RUNSTDBY_Pos _U_(13) /**< (GCLK_GENCTRL) Run in Standby Position */
120#define GCLK_GENCTRL_RUNSTDBY_Msk (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos) /**< (GCLK_GENCTRL) Run in Standby Mask */
121#define GCLK_GENCTRL_RUNSTDBY(value) (GCLK_GENCTRL_RUNSTDBY_Msk & ((value) << GCLK_GENCTRL_RUNSTDBY_Pos))
122#define GCLK_GENCTRL_DIV_Pos _U_(16) /**< (GCLK_GENCTRL) Division Factor Position */
123#define GCLK_GENCTRL_DIV_Msk (_U_(0xFFFF) << GCLK_GENCTRL_DIV_Pos) /**< (GCLK_GENCTRL) Division Factor Mask */
124#define GCLK_GENCTRL_DIV(value) (GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos))
125#define GCLK_GENCTRL_Msk _U_(0xFFFF3F0F) /**< (GCLK_GENCTRL) Register Mask */
126
127
128/* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */
129#define GCLK_PCHCTRL_RESETVALUE _U_(0x00) /**< (GCLK_PCHCTRL) Peripheral Clock Control Reset Value */
130
131#define GCLK_PCHCTRL_GEN_Pos _U_(0) /**< (GCLK_PCHCTRL) Generic Clock Generator Position */
132#define GCLK_PCHCTRL_GEN_Msk (_U_(0xF) << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic Clock Generator Mask */
133#define GCLK_PCHCTRL_GEN(value) (GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos))
134#define GCLK_PCHCTRL_GEN_GCLK0_Val _U_(0x0) /**< (GCLK_PCHCTRL) Generic clock generator 0 */
135#define GCLK_PCHCTRL_GEN_GCLK1_Val _U_(0x1) /**< (GCLK_PCHCTRL) Generic clock generator 1 */
136#define GCLK_PCHCTRL_GEN_GCLK2_Val _U_(0x2) /**< (GCLK_PCHCTRL) Generic clock generator 2 */
137#define GCLK_PCHCTRL_GEN_GCLK3_Val _U_(0x3) /**< (GCLK_PCHCTRL) Generic clock generator 3 */
138#define GCLK_PCHCTRL_GEN_GCLK4_Val _U_(0x4) /**< (GCLK_PCHCTRL) Generic clock generator 4 */
139#define GCLK_PCHCTRL_GEN_GCLK5_Val _U_(0x5) /**< (GCLK_PCHCTRL) Generic clock generator 5 */
140#define GCLK_PCHCTRL_GEN_GCLK6_Val _U_(0x6) /**< (GCLK_PCHCTRL) Generic clock generator 6 */
141#define GCLK_PCHCTRL_GEN_GCLK7_Val _U_(0x7) /**< (GCLK_PCHCTRL) Generic clock generator 7 */
142#define GCLK_PCHCTRL_GEN_GCLK8_Val _U_(0x8) /**< (GCLK_PCHCTRL) Generic clock generator 8 */
143#define GCLK_PCHCTRL_GEN_GCLK9_Val _U_(0x9) /**< (GCLK_PCHCTRL) Generic clock generator 9 */
144#define GCLK_PCHCTRL_GEN_GCLK10_Val _U_(0xA) /**< (GCLK_PCHCTRL) Generic clock generator 10 */
145#define GCLK_PCHCTRL_GEN_GCLK11_Val _U_(0xB) /**< (GCLK_PCHCTRL) Generic clock generator 11 */
146#define GCLK_PCHCTRL_GEN_GCLK0 (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 0 Position */
147#define GCLK_PCHCTRL_GEN_GCLK1 (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 1 Position */
148#define GCLK_PCHCTRL_GEN_GCLK2 (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 2 Position */
149#define GCLK_PCHCTRL_GEN_GCLK3 (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 3 Position */
150#define GCLK_PCHCTRL_GEN_GCLK4 (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 4 Position */
151#define GCLK_PCHCTRL_GEN_GCLK5 (GCLK_PCHCTRL_GEN_GCLK5_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 5 Position */
152#define GCLK_PCHCTRL_GEN_GCLK6 (GCLK_PCHCTRL_GEN_GCLK6_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 6 Position */
153#define GCLK_PCHCTRL_GEN_GCLK7 (GCLK_PCHCTRL_GEN_GCLK7_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 7 Position */
154#define GCLK_PCHCTRL_GEN_GCLK8 (GCLK_PCHCTRL_GEN_GCLK8_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 8 Position */
155#define GCLK_PCHCTRL_GEN_GCLK9 (GCLK_PCHCTRL_GEN_GCLK9_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 9 Position */
156#define GCLK_PCHCTRL_GEN_GCLK10 (GCLK_PCHCTRL_GEN_GCLK10_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 10 Position */
157#define GCLK_PCHCTRL_GEN_GCLK11 (GCLK_PCHCTRL_GEN_GCLK11_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 11 Position */
158#define GCLK_PCHCTRL_CHEN_Pos _U_(6) /**< (GCLK_PCHCTRL) Channel Enable Position */
159#define GCLK_PCHCTRL_CHEN_Msk (_U_(0x1) << GCLK_PCHCTRL_CHEN_Pos) /**< (GCLK_PCHCTRL) Channel Enable Mask */
160#define GCLK_PCHCTRL_CHEN(value) (GCLK_PCHCTRL_CHEN_Msk & ((value) << GCLK_PCHCTRL_CHEN_Pos))
161#define GCLK_PCHCTRL_WRTLOCK_Pos _U_(7) /**< (GCLK_PCHCTRL) Write Lock Position */
162#define GCLK_PCHCTRL_WRTLOCK_Msk (_U_(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos) /**< (GCLK_PCHCTRL) Write Lock Mask */
163#define GCLK_PCHCTRL_WRTLOCK(value) (GCLK_PCHCTRL_WRTLOCK_Msk & ((value) << GCLK_PCHCTRL_WRTLOCK_Pos))
164#define GCLK_PCHCTRL_Msk _U_(0x000000CF) /**< (GCLK_PCHCTRL) Register Mask */
165
166
167/** \brief GCLK register offsets definitions */
168#define GCLK_CTRLA_REG_OFST (0x00) /**< (GCLK_CTRLA) Control Offset */
169#define GCLK_SYNCBUSY_REG_OFST (0x04) /**< (GCLK_SYNCBUSY) Synchronization Busy Offset */
170#define GCLK_GENCTRL_REG_OFST (0x20) /**< (GCLK_GENCTRL) Generic Clock Generator Control Offset */
171#define GCLK_PCHCTRL_REG_OFST (0x80) /**< (GCLK_PCHCTRL) Peripheral Clock Control Offset */
172
173#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
174/** \brief GCLK register API structure */
175typedef struct
176{ /* Generic Clock Generator */
177 __IO uint8_t GCLK_CTRLA; /**< Offset: 0x00 (R/W 8) Control */
178 __I uint8_t Reserved1[0x03];
179 __I uint32_t GCLK_SYNCBUSY; /**< Offset: 0x04 (R/ 32) Synchronization Busy */
180 __I uint8_t Reserved2[0x18];
181 __IO uint32_t GCLK_GENCTRL[12]; /**< Offset: 0x20 (R/W 32) Generic Clock Generator Control */
182 __I uint8_t Reserved3[0x30];
183 __IO uint32_t GCLK_PCHCTRL[48]; /**< Offset: 0x80 (R/W 32) Peripheral Clock Control */
184} gclk_registers_t;
185
186
187#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
188#endif /* _SAMD51_GCLK_COMPONENT_H_ */
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