[460] | 1 | /**
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| 2 | * \brief Header file for ATSAMD51P19A
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| 3 | *
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| 4 | * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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| 5 | *
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| 6 | * Subject to your compliance with these terms, you may use Microchip software and any derivatives
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| 7 | * exclusively with Microchip products. It is your responsibility to comply with third party license
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| 8 | * terms applicable to your use of third party software (including open source software) that may
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| 9 | * accompany Microchip software.
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| 10 | *
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| 11 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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| 12 | * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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| 13 | * FITNESS FOR A PARTICULAR PURPOSE.
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| 14 | *
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| 15 | * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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| 16 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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| 17 | * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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| 18 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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| 19 | * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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| 20 | *
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| 21 | */
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| 22 |
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| 23 | /* file generated from device description version 2020-03-12T17:25:57Z */
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| 24 | #ifndef _SAMD51P19A_H_
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| 25 | #define _SAMD51P19A_H_
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| 26 |
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| 27 | // Header version uses Semantic Versioning 2.0.0 (https://semver.org/)
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| 28 | #define HEADER_FORMAT_VERSION "2.0.0"
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| 29 |
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| 30 | #define HEADER_FORMAT_VERSION_MAJOR (2)
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| 31 | #define HEADER_FORMAT_VERSION_MINOR (0)
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| 32 |
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| 33 | /** \addtogroup SAMD51P19A_definitions SAMD51P19A definitions
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| 34 | This file defines all structures and symbols for SAMD51P19A:
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| 35 | - registers and bitfields
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| 36 | - peripheral base address
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| 37 | - peripheral ID
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| 38 | - PIO definitions
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| 39 | * @{
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| 40 | */
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| 41 |
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| 42 | #ifdef __cplusplus
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| 43 | extern "C" {
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| 44 | #endif
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| 45 |
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| 46 | #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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| 47 | # include <stdint.h>
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| 48 | #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 49 |
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| 50 | #if !defined(SKIP_INTEGER_LITERALS)
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| 51 | # if defined(_U_) || defined(_L_) || defined(_UL_)
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| 52 | # error "Integer Literals macros already defined elsewhere"
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| 53 | # endif
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| 54 |
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| 55 | #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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| 56 | /* Macros that deal with adding suffixes to integer literal constants for C/C++ */
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| 57 | # define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */
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| 58 | # define _L_(x) (x ## L) /**< C code: Long integer literal constant value */
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| 59 | # define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */
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| 60 |
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| 61 | #else /* Assembler */
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| 62 |
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| 63 | # define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
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| 64 | # define _L_(x) x /**< Assembler: Long integer literal constant value */
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| 65 | # define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
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| 66 | #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 67 | #endif /* SKIP_INTEGER_LITERALS */
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| 68 | /** @} end of Atmel Global Defines */
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| 69 |
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| 70 | /* ************************************************************************** */
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| 71 | /* CMSIS DEFINITIONS FOR SAMD51P19A */
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| 72 | /* ************************************************************************** */
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| 73 | #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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| 74 | /** Interrupt Number Definition */
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| 75 | typedef enum IRQn
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| 76 | {
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| 77 | /****** CORTEX-M4 Processor Exceptions Numbers ******************************/
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| 78 | Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */
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| 79 | NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */
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| 80 | HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */
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| 81 | MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
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| 82 | BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
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| 83 | UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
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| 84 | SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */
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| 85 | DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */
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| 86 | PendSV_IRQn = -2, /**< -2 Pendable request for system service */
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| 87 | SysTick_IRQn = -1, /**< -1 System Tick Timer */
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| 88 | /****** SAMD51P19A specific Interrupt Numbers ***********************************/
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| 89 | PM_IRQn = 0, /**< 0 Power Manager (PM) */
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| 90 | MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */
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| 91 | OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */
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| 92 | OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */
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| 93 | OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */
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| 94 | OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */
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| 95 | OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */
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| 96 | OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */
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| 97 | SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */
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| 98 | SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */
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| 99 | WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */
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| 100 | RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */
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| 101 | EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */
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| 102 | EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */
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| 103 | EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */
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| 104 | EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */
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| 105 | EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */
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| 106 | EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */
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| 107 | EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */
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| 108 | EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */
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| 109 | EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */
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| 110 | EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */
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| 111 | EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */
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| 112 | EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */
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| 113 | EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */
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| 114 | EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */
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| 115 | EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */
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| 116 | EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */
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| 117 | FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */
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| 118 | NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */
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| 119 | NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */
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| 120 | DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */
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| 121 | DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */
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| 122 | DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */
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| 123 | DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */
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| 124 | DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */
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| 125 | EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */
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| 126 | EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */
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| 127 | EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */
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| 128 | EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */
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| 129 | EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */
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| 130 | PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */
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| 131 | RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */
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| 132 | SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */
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| 133 | SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */
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| 134 | SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */
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| 135 | SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */
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| 136 | SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */
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| 137 | SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */
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| 138 | SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */
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| 139 | SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */
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| 140 | SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */
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| 141 | SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */
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| 142 | SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */
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| 143 | SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */
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| 144 | SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */
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| 145 | SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */
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| 146 | SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */
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| 147 | SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */
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| 148 | SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */
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| 149 | SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */
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| 150 | SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */
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| 151 | SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */
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| 152 | SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */
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| 153 | SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */
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| 154 | SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */
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| 155 | SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */
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| 156 | SERCOM6_0_IRQn = 70, /**< 70 Serial Communication Interface (SERCOM6) */
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| 157 | SERCOM6_1_IRQn = 71, /**< 71 Serial Communication Interface (SERCOM6) */
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| 158 | SERCOM6_2_IRQn = 72, /**< 72 Serial Communication Interface (SERCOM6) */
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| 159 | SERCOM6_OTHER_IRQn = 73, /**< 73 Serial Communication Interface (SERCOM6) */
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| 160 | SERCOM7_0_IRQn = 74, /**< 74 Serial Communication Interface (SERCOM7) */
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| 161 | SERCOM7_1_IRQn = 75, /**< 75 Serial Communication Interface (SERCOM7) */
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| 162 | SERCOM7_2_IRQn = 76, /**< 76 Serial Communication Interface (SERCOM7) */
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| 163 | SERCOM7_OTHER_IRQn = 77, /**< 77 Serial Communication Interface (SERCOM7) */
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| 164 | USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */
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| 165 | USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */
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| 166 | USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */
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| 167 | USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */
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| 168 | TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */
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| 169 | TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */
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| 170 | TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */
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| 171 | TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */
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| 172 | TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */
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| 173 | TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */
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| 174 | TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */
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| 175 | TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */
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| 176 | TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */
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| 177 | TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */
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| 178 | TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */
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| 179 | TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */
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| 180 | TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */
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| 181 | TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */
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| 182 | TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */
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| 183 | TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */
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| 184 | TCC3_OTHER_IRQn = 101, /**< 101 Timer Counter Control (TCC3) */
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| 185 | TCC3_MC0_IRQn = 102, /**< 102 Timer Counter Control (TCC3) */
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| 186 | TCC3_MC1_IRQn = 103, /**< 103 Timer Counter Control (TCC3) */
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| 187 | TCC4_OTHER_IRQn = 104, /**< 104 Timer Counter Control (TCC4) */
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| 188 | TCC4_MC0_IRQn = 105, /**< 105 Timer Counter Control (TCC4) */
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| 189 | TCC4_MC1_IRQn = 106, /**< 106 Timer Counter Control (TCC4) */
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| 190 | TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */
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| 191 | TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */
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| 192 | TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */
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| 193 | TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */
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| 194 | TC4_IRQn = 111, /**< 111 Basic Timer Counter (TC4) */
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| 195 | TC5_IRQn = 112, /**< 112 Basic Timer Counter (TC5) */
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| 196 | TC6_IRQn = 113, /**< 113 Basic Timer Counter (TC6) */
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| 197 | TC7_IRQn = 114, /**< 114 Basic Timer Counter (TC7) */
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| 198 | PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */
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| 199 | PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */
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| 200 | PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */
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| 201 | ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */
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| 202 | ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */
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| 203 | ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */
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| 204 | ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */
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| 205 | AC_IRQn = 122, /**< 122 Analog Comparators (AC) */
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| 206 | DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */
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| 207 | DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */
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| 208 | DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */
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| 209 | DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */
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| 210 | DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */
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| 211 | I2S_IRQn = 128, /**< 128 Inter-IC Sound Interface (I2S) */
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| 212 | PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */
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| 213 | AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */
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| 214 | TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */
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| 215 | ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */
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| 216 | PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */
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| 217 | QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */
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| 218 | SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */
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| 219 | SDHC1_IRQn = 136, /**< 136 SD/MMC Host Controller (SDHC1) */
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| 220 |
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| 221 | PERIPH_MAX_IRQn = 136 /**< Max peripheral ID */
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| 222 | } IRQn_Type;
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| 223 | #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 224 |
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| 225 | #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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| 226 | typedef struct _DeviceVectors
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| 227 | {
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| 228 | /* Stack pointer */
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| 229 | void* pvStack;
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| 230 | /* Cortex-M handlers */
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| 231 | void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */
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| 232 | void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */
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| 233 | void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */
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| 234 | void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */
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| 235 | void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
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| 236 | void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
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| 237 | void* pvReservedC9;
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| 238 | void* pvReservedC8;
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| 239 | void* pvReservedC7;
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| 240 | void* pvReservedC6;
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| 241 | void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */
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| 242 | void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */
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| 243 | void* pvReservedC3;
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| 244 | void* pfnPendSV_Handler; /* -2 Pendable request for system service */
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| 245 | void* pfnSysTick_Handler; /* -1 System Tick Timer */
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| 246 |
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| 247 | /* Peripheral handlers */
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| 248 | void* pfnPM_Handler; /* 0 Power Manager (PM) */
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| 249 | void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */
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| 250 | void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */
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| 251 | void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */
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| 252 | void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */
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| 253 | void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */
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| 254 | void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */
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| 255 | void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */
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| 256 | void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */
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| 257 | void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */
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| 258 | void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */
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| 259 | void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */
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| 260 | void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */
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| 261 | void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */
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| 262 | void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */
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| 263 | void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */
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| 264 | void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */
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| 265 | void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */
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| 266 | void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */
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| 267 | void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */
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| 268 | void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */
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| 269 | void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */
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| 270 | void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */
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| 271 | void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */
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| 272 | void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */
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| 273 | void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */
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| 274 | void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */
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| 275 | void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */
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| 276 | void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */
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| 277 | void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */
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| 278 | void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */
|
---|
| 279 | void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */
|
---|
| 280 | void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */
|
---|
| 281 | void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */
|
---|
| 282 | void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */
|
---|
| 283 | void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */
|
---|
| 284 | void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */
|
---|
| 285 | void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */
|
---|
| 286 | void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */
|
---|
| 287 | void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */
|
---|
| 288 | void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */
|
---|
| 289 | void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */
|
---|
| 290 | void* pvReserved42;
|
---|
| 291 | void* pvReserved43;
|
---|
| 292 | void* pvReserved44;
|
---|
| 293 | void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */
|
---|
| 294 | void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */
|
---|
| 295 | void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */
|
---|
| 296 | void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */
|
---|
| 297 | void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */
|
---|
| 298 | void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */
|
---|
| 299 | void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */
|
---|
| 300 | void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */
|
---|
| 301 | void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */
|
---|
| 302 | void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */
|
---|
| 303 | void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */
|
---|
| 304 | void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */
|
---|
| 305 | void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */
|
---|
| 306 | void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */
|
---|
| 307 | void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */
|
---|
| 308 | void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */
|
---|
| 309 | void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */
|
---|
| 310 | void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */
|
---|
| 311 | void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */
|
---|
| 312 | void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */
|
---|
| 313 | void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */
|
---|
| 314 | void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */
|
---|
| 315 | void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */
|
---|
| 316 | void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */
|
---|
| 317 | void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */
|
---|
| 318 | void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface (SERCOM6) */
|
---|
| 319 | void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface (SERCOM6) */
|
---|
| 320 | void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface (SERCOM6) */
|
---|
| 321 | void* pfnSERCOM6_OTHER_Handler; /* 73 Serial Communication Interface (SERCOM6) */
|
---|
| 322 | void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface (SERCOM7) */
|
---|
| 323 | void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface (SERCOM7) */
|
---|
| 324 | void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface (SERCOM7) */
|
---|
| 325 | void* pfnSERCOM7_OTHER_Handler; /* 77 Serial Communication Interface (SERCOM7) */
|
---|
| 326 | void* pvReserved78;
|
---|
| 327 | void* pvReserved79;
|
---|
| 328 | void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */
|
---|
| 329 | void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */
|
---|
| 330 | void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */
|
---|
| 331 | void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */
|
---|
| 332 | void* pvReserved84;
|
---|
| 333 | void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */
|
---|
| 334 | void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */
|
---|
| 335 | void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */
|
---|
| 336 | void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */
|
---|
| 337 | void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */
|
---|
| 338 | void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */
|
---|
| 339 | void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */
|
---|
| 340 | void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */
|
---|
| 341 | void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */
|
---|
| 342 | void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */
|
---|
| 343 | void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */
|
---|
| 344 | void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */
|
---|
| 345 | void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */
|
---|
| 346 | void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */
|
---|
| 347 | void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */
|
---|
| 348 | void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */
|
---|
| 349 | void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */
|
---|
| 350 | void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */
|
---|
| 351 | void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */
|
---|
| 352 | void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */
|
---|
| 353 | void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */
|
---|
| 354 | void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */
|
---|
| 355 | void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */
|
---|
| 356 | void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */
|
---|
| 357 | void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */
|
---|
| 358 | void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */
|
---|
| 359 | void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */
|
---|
| 360 | void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */
|
---|
| 361 | void* pfnTC6_Handler; /* 113 Basic Timer Counter (TC6) */
|
---|
| 362 | void* pfnTC7_Handler; /* 114 Basic Timer Counter (TC7) */
|
---|
| 363 | void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */
|
---|
| 364 | void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */
|
---|
| 365 | void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */
|
---|
| 366 | void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */
|
---|
| 367 | void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */
|
---|
| 368 | void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */
|
---|
| 369 | void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */
|
---|
| 370 | void* pfnAC_Handler; /* 122 Analog Comparators (AC) */
|
---|
| 371 | void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */
|
---|
| 372 | void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */
|
---|
| 373 | void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */
|
---|
| 374 | void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */
|
---|
| 375 | void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */
|
---|
| 376 | void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */
|
---|
| 377 | void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */
|
---|
| 378 | void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */
|
---|
| 379 | void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */
|
---|
| 380 | void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */
|
---|
| 381 | void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */
|
---|
| 382 | void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */
|
---|
| 383 | void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */
|
---|
| 384 | void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller (SDHC1) */
|
---|
| 385 | } DeviceVectors;
|
---|
| 386 |
|
---|
| 387 | /* Defines for Deprecated Interrupt and Exceptions handler names */
|
---|
| 388 | #define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF*/
|
---|
| 389 | #define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF*/
|
---|
| 390 | #define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF*/
|
---|
| 391 | #define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF*/
|
---|
| 392 |
|
---|
| 393 | #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 394 |
|
---|
| 395 | #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 396 | #if !defined DONT_USE_PREDEFINED_CORE_HANDLERS
|
---|
| 397 | /* CORTEX-M4 exception handlers */
|
---|
| 398 | void Reset_Handler ( void );
|
---|
| 399 | void NonMaskableInt_Handler ( void );
|
---|
| 400 | void HardFault_Handler ( void );
|
---|
| 401 | void MemoryManagement_Handler ( void );
|
---|
| 402 | void BusFault_Handler ( void );
|
---|
| 403 | void UsageFault_Handler ( void );
|
---|
| 404 | void SVCall_Handler ( void );
|
---|
| 405 | void DebugMonitor_Handler ( void );
|
---|
| 406 | void PendSV_Handler ( void );
|
---|
| 407 | void SysTick_Handler ( void );
|
---|
| 408 | #endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */
|
---|
| 409 |
|
---|
| 410 | #if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
|
---|
| 411 | /* Peripherals interrupt handlers */
|
---|
| 412 | void PM_Handler ( void );
|
---|
| 413 | void MCLK_Handler ( void );
|
---|
| 414 | void OSCCTRL_XOSC0_Handler ( void );
|
---|
| 415 | void OSCCTRL_XOSC1_Handler ( void );
|
---|
| 416 | void OSCCTRL_DFLL_Handler ( void );
|
---|
| 417 | void OSCCTRL_DPLL0_Handler ( void );
|
---|
| 418 | void OSCCTRL_DPLL1_Handler ( void );
|
---|
| 419 | void OSC32KCTRL_Handler ( void );
|
---|
| 420 | void SUPC_OTHER_Handler ( void );
|
---|
| 421 | void SUPC_BODDET_Handler ( void );
|
---|
| 422 | void WDT_Handler ( void );
|
---|
| 423 | void RTC_Handler ( void );
|
---|
| 424 | void EIC_EXTINT_0_Handler ( void );
|
---|
| 425 | void EIC_EXTINT_1_Handler ( void );
|
---|
| 426 | void EIC_EXTINT_2_Handler ( void );
|
---|
| 427 | void EIC_EXTINT_3_Handler ( void );
|
---|
| 428 | void EIC_EXTINT_4_Handler ( void );
|
---|
| 429 | void EIC_EXTINT_5_Handler ( void );
|
---|
| 430 | void EIC_EXTINT_6_Handler ( void );
|
---|
| 431 | void EIC_EXTINT_7_Handler ( void );
|
---|
| 432 | void EIC_EXTINT_8_Handler ( void );
|
---|
| 433 | void EIC_EXTINT_9_Handler ( void );
|
---|
| 434 | void EIC_EXTINT_10_Handler ( void );
|
---|
| 435 | void EIC_EXTINT_11_Handler ( void );
|
---|
| 436 | void EIC_EXTINT_12_Handler ( void );
|
---|
| 437 | void EIC_EXTINT_13_Handler ( void );
|
---|
| 438 | void EIC_EXTINT_14_Handler ( void );
|
---|
| 439 | void EIC_EXTINT_15_Handler ( void );
|
---|
| 440 | void FREQM_Handler ( void );
|
---|
| 441 | void NVMCTRL_0_Handler ( void );
|
---|
| 442 | void NVMCTRL_1_Handler ( void );
|
---|
| 443 | void DMAC_0_Handler ( void );
|
---|
| 444 | void DMAC_1_Handler ( void );
|
---|
| 445 | void DMAC_2_Handler ( void );
|
---|
| 446 | void DMAC_3_Handler ( void );
|
---|
| 447 | void DMAC_OTHER_Handler ( void );
|
---|
| 448 | void EVSYS_0_Handler ( void );
|
---|
| 449 | void EVSYS_1_Handler ( void );
|
---|
| 450 | void EVSYS_2_Handler ( void );
|
---|
| 451 | void EVSYS_3_Handler ( void );
|
---|
| 452 | void EVSYS_OTHER_Handler ( void );
|
---|
| 453 | void PAC_Handler ( void );
|
---|
| 454 | void RAMECC_Handler ( void );
|
---|
| 455 | void SERCOM0_0_Handler ( void );
|
---|
| 456 | void SERCOM0_1_Handler ( void );
|
---|
| 457 | void SERCOM0_2_Handler ( void );
|
---|
| 458 | void SERCOM0_OTHER_Handler ( void );
|
---|
| 459 | void SERCOM1_0_Handler ( void );
|
---|
| 460 | void SERCOM1_1_Handler ( void );
|
---|
| 461 | void SERCOM1_2_Handler ( void );
|
---|
| 462 | void SERCOM1_OTHER_Handler ( void );
|
---|
| 463 | void SERCOM2_0_Handler ( void );
|
---|
| 464 | void SERCOM2_1_Handler ( void );
|
---|
| 465 | void SERCOM2_2_Handler ( void );
|
---|
| 466 | void SERCOM2_OTHER_Handler ( void );
|
---|
| 467 | void SERCOM3_0_Handler ( void );
|
---|
| 468 | void SERCOM3_1_Handler ( void );
|
---|
| 469 | void SERCOM3_2_Handler ( void );
|
---|
| 470 | void SERCOM3_OTHER_Handler ( void );
|
---|
| 471 | void SERCOM4_0_Handler ( void );
|
---|
| 472 | void SERCOM4_1_Handler ( void );
|
---|
| 473 | void SERCOM4_2_Handler ( void );
|
---|
| 474 | void SERCOM4_OTHER_Handler ( void );
|
---|
| 475 | void SERCOM5_0_Handler ( void );
|
---|
| 476 | void SERCOM5_1_Handler ( void );
|
---|
| 477 | void SERCOM5_2_Handler ( void );
|
---|
| 478 | void SERCOM5_OTHER_Handler ( void );
|
---|
| 479 | void SERCOM6_0_Handler ( void );
|
---|
| 480 | void SERCOM6_1_Handler ( void );
|
---|
| 481 | void SERCOM6_2_Handler ( void );
|
---|
| 482 | void SERCOM6_OTHER_Handler ( void );
|
---|
| 483 | void SERCOM7_0_Handler ( void );
|
---|
| 484 | void SERCOM7_1_Handler ( void );
|
---|
| 485 | void SERCOM7_2_Handler ( void );
|
---|
| 486 | void SERCOM7_OTHER_Handler ( void );
|
---|
| 487 | void USB_OTHER_Handler ( void );
|
---|
| 488 | void USB_SOF_HSOF_Handler ( void );
|
---|
| 489 | void USB_TRCPT0_Handler ( void );
|
---|
| 490 | void USB_TRCPT1_Handler ( void );
|
---|
| 491 | void TCC0_OTHER_Handler ( void );
|
---|
| 492 | void TCC0_MC0_Handler ( void );
|
---|
| 493 | void TCC0_MC1_Handler ( void );
|
---|
| 494 | void TCC0_MC2_Handler ( void );
|
---|
| 495 | void TCC0_MC3_Handler ( void );
|
---|
| 496 | void TCC0_MC4_Handler ( void );
|
---|
| 497 | void TCC0_MC5_Handler ( void );
|
---|
| 498 | void TCC1_OTHER_Handler ( void );
|
---|
| 499 | void TCC1_MC0_Handler ( void );
|
---|
| 500 | void TCC1_MC1_Handler ( void );
|
---|
| 501 | void TCC1_MC2_Handler ( void );
|
---|
| 502 | void TCC1_MC3_Handler ( void );
|
---|
| 503 | void TCC2_OTHER_Handler ( void );
|
---|
| 504 | void TCC2_MC0_Handler ( void );
|
---|
| 505 | void TCC2_MC1_Handler ( void );
|
---|
| 506 | void TCC2_MC2_Handler ( void );
|
---|
| 507 | void TCC3_OTHER_Handler ( void );
|
---|
| 508 | void TCC3_MC0_Handler ( void );
|
---|
| 509 | void TCC3_MC1_Handler ( void );
|
---|
| 510 | void TCC4_OTHER_Handler ( void );
|
---|
| 511 | void TCC4_MC0_Handler ( void );
|
---|
| 512 | void TCC4_MC1_Handler ( void );
|
---|
| 513 | void TC0_Handler ( void );
|
---|
| 514 | void TC1_Handler ( void );
|
---|
| 515 | void TC2_Handler ( void );
|
---|
| 516 | void TC3_Handler ( void );
|
---|
| 517 | void TC4_Handler ( void );
|
---|
| 518 | void TC5_Handler ( void );
|
---|
| 519 | void TC6_Handler ( void );
|
---|
| 520 | void TC7_Handler ( void );
|
---|
| 521 | void PDEC_OTHER_Handler ( void );
|
---|
| 522 | void PDEC_MC0_Handler ( void );
|
---|
| 523 | void PDEC_MC1_Handler ( void );
|
---|
| 524 | void ADC0_OTHER_Handler ( void );
|
---|
| 525 | void ADC0_RESRDY_Handler ( void );
|
---|
| 526 | void ADC1_OTHER_Handler ( void );
|
---|
| 527 | void ADC1_RESRDY_Handler ( void );
|
---|
| 528 | void AC_Handler ( void );
|
---|
| 529 | void DAC_OTHER_Handler ( void );
|
---|
| 530 | void DAC_EMPTY_0_Handler ( void );
|
---|
| 531 | void DAC_EMPTY_1_Handler ( void );
|
---|
| 532 | void DAC_RESRDY_0_Handler ( void );
|
---|
| 533 | void DAC_RESRDY_1_Handler ( void );
|
---|
| 534 | void I2S_Handler ( void );
|
---|
| 535 | void PCC_Handler ( void );
|
---|
| 536 | void AES_Handler ( void );
|
---|
| 537 | void TRNG_Handler ( void );
|
---|
| 538 | void ICM_Handler ( void );
|
---|
| 539 | void PUKCC_Handler ( void );
|
---|
| 540 | void QSPI_Handler ( void );
|
---|
| 541 | void SDHC0_Handler ( void );
|
---|
| 542 | void SDHC1_Handler ( void );
|
---|
| 543 | #endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */
|
---|
| 544 | /* Defines for Deprecated Interrupt and Exceptions handler names */
|
---|
| 545 | #define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility*/
|
---|
| 546 | #define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility*/
|
---|
| 547 | #define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility*/
|
---|
| 548 | #define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility*/
|
---|
| 549 |
|
---|
| 550 | #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 551 |
|
---|
| 552 | /*
|
---|
| 553 | * \brief Configuration of the CORTEX-M4 Processor and Core Peripherals
|
---|
| 554 | */
|
---|
| 555 | #define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */
|
---|
| 556 | #define __DEBUG_LVL 3 /**< Debug Level */
|
---|
| 557 | #define __FPU_PRESENT 1 /**< FPU present or not */
|
---|
| 558 | #define __MPU_PRESENT 1 /**< MPU present or not */
|
---|
| 559 | #define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */
|
---|
| 560 | #define __TRACE_LVL 2 /**< Trace Level */
|
---|
| 561 | #define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */
|
---|
| 562 | #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
|
---|
| 563 | #define __ARCH_ARM 1
|
---|
| 564 | #define __ARCH_ARM_CORTEX_M 1
|
---|
| 565 | #define __DEVICE_IS_SAM 1
|
---|
| 566 |
|
---|
| 567 | /*
|
---|
| 568 | * \brief CMSIS includes
|
---|
| 569 | */
|
---|
| 570 | //#include "core_cm4.h"
|
---|
| 571 | #if defined USE_CMSIS_INIT
|
---|
| 572 | //#include "system_samd51.h"
|
---|
| 573 | #endif /* USE_CMSIS_INIT */
|
---|
| 574 |
|
---|
| 575 | #ifdef __cplusplus
|
---|
| 576 | #define __I volatile /*!< Defines 'read only' permissions */
|
---|
| 577 | #else
|
---|
| 578 | #define __I volatile const /*!< Defines 'read only' permissions */
|
---|
| 579 | #endif
|
---|
| 580 | #define __O volatile /*!< Defines 'write only' permissions */
|
---|
| 581 | #define __IO volatile /*!< Defines 'read / write' permissions */
|
---|
| 582 |
|
---|
| 583 | /* following defines should be used for structure members */
|
---|
| 584 | #define __IM volatile const /*! Defines 'read only' structure member permissions */
|
---|
| 585 | #define __OM volatile /*! Defines 'write only' structure member permissions */
|
---|
| 586 | #define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
---|
| 587 |
|
---|
| 588 |
|
---|
| 589 | /** \defgroup SAMD51P19A_api Peripheral Software API
|
---|
| 590 | * @{
|
---|
| 591 | */
|
---|
| 592 |
|
---|
| 593 | /* ************************************************************************** */
|
---|
| 594 | /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51P19A */
|
---|
| 595 | /* ************************************************************************** */
|
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| 596 | //#include "ac.h"
|
---|
| 597 | //#include "adc.h"
|
---|
| 598 | //#include "aes.h"
|
---|
| 599 | //#include "ccl.h"
|
---|
| 600 | //#include "cmcc.h"
|
---|
| 601 | //#include "dac.h"
|
---|
| 602 | //#include "dmac.h"
|
---|
| 603 | //#include "dsu.h"
|
---|
| 604 | //#include "eic.h"
|
---|
| 605 | //#include "evsys.h"
|
---|
| 606 | //#include "freqm.h"
|
---|
| 607 | #include "gclk.h"
|
---|
| 608 | //#include "hmatrixb.h"
|
---|
| 609 | //#include "i2s.h"
|
---|
| 610 | //#include "icm.h"
|
---|
| 611 | #include "mclk.h"
|
---|
| 612 | //#include "nvmctrl.h"
|
---|
| 613 | #include "osc32kctrl.h"
|
---|
| 614 | #include "oscctrl.h"
|
---|
| 615 | //#include "pac.h"
|
---|
| 616 | //#include "pcc.h"
|
---|
| 617 | //#include "pdec.h"
|
---|
| 618 | //#include "pm.h"
|
---|
| 619 | #include "port.h"
|
---|
| 620 | //#include "pukcc.h"
|
---|
| 621 | //#include "qspi.h"
|
---|
| 622 | //#include "ramecc.h"
|
---|
| 623 | //#include "rstc.h"
|
---|
| 624 | //#include "rtc.h"
|
---|
| 625 | //#include "sdhc.h"
|
---|
| 626 | #include "sercom.h"
|
---|
| 627 | //#include "supc.h"
|
---|
| 628 | //#include "tc.h"
|
---|
| 629 | //#include "tcc.h"
|
---|
| 630 | //#include "trng.h"
|
---|
| 631 | //#include "usb.h"
|
---|
| 632 | //#include "wdt.h"
|
---|
| 633 | /** @} end of Peripheral Software API */
|
---|
| 634 |
|
---|
| 635 | /** \addtogroup SAMD51P19A_id Peripheral Ids Definitions
|
---|
| 636 | * @{
|
---|
| 637 | */
|
---|
| 638 |
|
---|
| 639 | /* ************************************************************************** */
|
---|
| 640 | /* PERIPHERAL ID DEFINITIONS FOR SAMD51P19A */
|
---|
| 641 | /* ************************************************************************** */
|
---|
| 642 | #define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */
|
---|
| 643 | #define ID_PM ( 1) /**< \brief Power Manager (PM) */
|
---|
| 644 | #define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */
|
---|
| 645 | #define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */
|
---|
| 646 | #define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */
|
---|
| 647 | #define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */
|
---|
| 648 | #define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */
|
---|
| 649 | #define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */
|
---|
| 650 | #define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */
|
---|
| 651 | #define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */
|
---|
| 652 | #define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */
|
---|
| 653 | #define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */
|
---|
| 654 | #define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */
|
---|
| 655 | #define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */
|
---|
| 656 | #define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */
|
---|
| 657 | #define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */
|
---|
| 658 | #define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */
|
---|
| 659 | #define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */
|
---|
| 660 | #define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
|
---|
| 661 | #define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */
|
---|
| 662 | #define ID_PORT ( 36) /**< \brief Port Module (PORT) */
|
---|
| 663 | #define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */
|
---|
| 664 | #define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */
|
---|
| 665 | #define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */
|
---|
| 666 | #define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */
|
---|
| 667 | #define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */
|
---|
| 668 | #define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */
|
---|
| 669 | #define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */
|
---|
| 670 | #define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */
|
---|
| 671 | #define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */
|
---|
| 672 | #define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */
|
---|
| 673 | #define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */
|
---|
| 674 | #define ID_TCC3 ( 68) /**< \brief Timer Counter Control (TCC3) */
|
---|
| 675 | #define ID_TC4 ( 69) /**< \brief Basic Timer Counter (TC4) */
|
---|
| 676 | #define ID_TC5 ( 70) /**< \brief Basic Timer Counter (TC5) */
|
---|
| 677 | #define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */
|
---|
| 678 | #define ID_AC ( 72) /**< \brief Analog Comparators (AC) */
|
---|
| 679 | #define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */
|
---|
| 680 | #define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */
|
---|
| 681 | #define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */
|
---|
| 682 | #define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */
|
---|
| 683 | #define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */
|
---|
| 684 | #define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */
|
---|
| 685 | #define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */
|
---|
| 686 | #define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */
|
---|
| 687 | #define ID_SERCOM6 ( 98) /**< \brief Serial Communication Interface (SERCOM6) */
|
---|
| 688 | #define ID_SERCOM7 ( 99) /**< \brief Serial Communication Interface (SERCOM7) */
|
---|
| 689 | #define ID_TCC4 (100) /**< \brief Timer Counter Control (TCC4) */
|
---|
| 690 | #define ID_TC6 (101) /**< \brief Basic Timer Counter (TC6) */
|
---|
| 691 | #define ID_TC7 (102) /**< \brief Basic Timer Counter (TC7) */
|
---|
| 692 | #define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */
|
---|
| 693 | #define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */
|
---|
| 694 | #define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */
|
---|
| 695 | #define ID_I2S (106) /**< \brief Inter-IC Sound Interface (I2S) */
|
---|
| 696 | #define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */
|
---|
| 697 |
|
---|
| 698 | #define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */
|
---|
| 699 | /** @} end of Peripheral Ids Definitions */
|
---|
| 700 |
|
---|
| 701 | /** \addtogroup SAMD51P19A_base Peripheral Base Address Definitions
|
---|
| 702 | * @{
|
---|
| 703 | */
|
---|
| 704 |
|
---|
| 705 | /* ************************************************************************** */
|
---|
| 706 | /* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAMD51P19A */
|
---|
| 707 | /* ************************************************************************** */
|
---|
| 708 | #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 709 | #define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */
|
---|
| 710 | #define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */
|
---|
| 711 | #define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */
|
---|
| 712 | #define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */
|
---|
| 713 | #define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */
|
---|
| 714 | #define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */
|
---|
| 715 | #define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */
|
---|
| 716 | #define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */
|
---|
| 717 | #define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */
|
---|
| 718 | #define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */
|
---|
| 719 | #define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */
|
---|
| 720 | #define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */
|
---|
| 721 | #define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */
|
---|
| 722 | #define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */
|
---|
| 723 | #define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */
|
---|
| 724 | #define I2S_REGS ((i2s_registers_t*)0x43002800) /**< \brief I2S Registers Address */
|
---|
| 725 | #define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */
|
---|
| 726 | #define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */
|
---|
| 727 | #define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */
|
---|
| 728 | #define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */
|
---|
| 729 | #define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */
|
---|
| 730 | #define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */
|
---|
| 731 | #define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */
|
---|
| 732 | #define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */
|
---|
| 733 | #define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */
|
---|
| 734 | #define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */
|
---|
| 735 | #define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */
|
---|
| 736 | #define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */
|
---|
| 737 | #define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */
|
---|
| 738 | #define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */
|
---|
| 739 | #define SDHC1_REGS ((sdhc_registers_t*)0x46000000) /**< \brief SDHC1 Registers Address */
|
---|
| 740 | #define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */
|
---|
| 741 | #define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */
|
---|
| 742 | #define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */
|
---|
| 743 | #define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */
|
---|
| 744 | #define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */
|
---|
| 745 | #define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */
|
---|
| 746 | #define SERCOM6_REGS ((sercom_registers_t*)0x43000800) /**< \brief SERCOM6 Registers Address */
|
---|
| 747 | #define SERCOM7_REGS ((sercom_registers_t*)0x43000c00) /**< \brief SERCOM7 Registers Address */
|
---|
| 748 | #define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */
|
---|
| 749 | #define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */
|
---|
| 750 | #define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */
|
---|
| 751 | #define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */
|
---|
| 752 | #define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */
|
---|
| 753 | #define TC4_REGS ((tc_registers_t*)0x42001400) /**< \brief TC4 Registers Address */
|
---|
| 754 | #define TC5_REGS ((tc_registers_t*)0x42001800) /**< \brief TC5 Registers Address */
|
---|
| 755 | #define TC6_REGS ((tc_registers_t*)0x43001400) /**< \brief TC6 Registers Address */
|
---|
| 756 | #define TC7_REGS ((tc_registers_t*)0x43001800) /**< \brief TC7 Registers Address */
|
---|
| 757 | #define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */
|
---|
| 758 | #define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */
|
---|
| 759 | #define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */
|
---|
| 760 | #define TCC3_REGS ((tcc_registers_t*)0x42001000) /**< \brief TCC3 Registers Address */
|
---|
| 761 | #define TCC4_REGS ((tcc_registers_t*)0x43001000) /**< \brief TCC4 Registers Address */
|
---|
| 762 | #define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */
|
---|
| 763 | #define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */
|
---|
| 764 | #define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */
|
---|
| 765 | #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 766 | /** @} end of Peripheral Base Address Definitions */
|
---|
| 767 |
|
---|
| 768 | /** \addtogroup SAMD51P19A_base Peripheral Base Address Definitions
|
---|
| 769 | * @{
|
---|
| 770 | */
|
---|
| 771 |
|
---|
| 772 | /* ************************************************************************** */
|
---|
| 773 | /* BASE ADDRESS DEFINITIONS FOR SAMD51P19A */
|
---|
| 774 | /* ************************************************************************** */
|
---|
| 775 | #define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */
|
---|
| 776 | #define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */
|
---|
| 777 | #define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */
|
---|
| 778 | #define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */
|
---|
| 779 | #define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */
|
---|
| 780 | #define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */
|
---|
| 781 | #define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */
|
---|
| 782 | #define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */
|
---|
| 783 | #define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */
|
---|
| 784 | #define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */
|
---|
| 785 | #define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */
|
---|
| 786 | #define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */
|
---|
| 787 | #define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */
|
---|
| 788 | #define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */
|
---|
| 789 | #define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */
|
---|
| 790 | #define I2S_BASE_ADDRESS _UL_(0x43002800) /**< \brief I2S Base Address */
|
---|
| 791 | #define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */
|
---|
| 792 | #define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */
|
---|
| 793 | #define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */
|
---|
| 794 | #define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */
|
---|
| 795 | #define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */
|
---|
| 796 | #define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */
|
---|
| 797 | #define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */
|
---|
| 798 | #define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */
|
---|
| 799 | #define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */
|
---|
| 800 | #define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */
|
---|
| 801 | #define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */
|
---|
| 802 | #define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */
|
---|
| 803 | #define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */
|
---|
| 804 | #define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */
|
---|
| 805 | #define SDHC1_BASE_ADDRESS _UL_(0x46000000) /**< \brief SDHC1 Base Address */
|
---|
| 806 | #define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */
|
---|
| 807 | #define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */
|
---|
| 808 | #define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */
|
---|
| 809 | #define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */
|
---|
| 810 | #define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */
|
---|
| 811 | #define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */
|
---|
| 812 | #define SERCOM6_BASE_ADDRESS _UL_(0x43000800) /**< \brief SERCOM6 Base Address */
|
---|
| 813 | #define SERCOM7_BASE_ADDRESS _UL_(0x43000c00) /**< \brief SERCOM7 Base Address */
|
---|
| 814 | #define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */
|
---|
| 815 | #define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */
|
---|
| 816 | #define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */
|
---|
| 817 | #define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */
|
---|
| 818 | #define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */
|
---|
| 819 | #define TC4_BASE_ADDRESS _UL_(0x42001400) /**< \brief TC4 Base Address */
|
---|
| 820 | #define TC5_BASE_ADDRESS _UL_(0x42001800) /**< \brief TC5 Base Address */
|
---|
| 821 | #define TC6_BASE_ADDRESS _UL_(0x43001400) /**< \brief TC6 Base Address */
|
---|
| 822 | #define TC7_BASE_ADDRESS _UL_(0x43001800) /**< \brief TC7 Base Address */
|
---|
| 823 | #define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */
|
---|
| 824 | #define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */
|
---|
| 825 | #define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */
|
---|
| 826 | #define TCC3_BASE_ADDRESS _UL_(0x42001000) /**< \brief TCC3 Base Address */
|
---|
| 827 | #define TCC4_BASE_ADDRESS _UL_(0x43001000) /**< \brief TCC4 Base Address */
|
---|
| 828 | #define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */
|
---|
| 829 | #define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */
|
---|
| 830 | #define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */
|
---|
| 831 | /** @} end of Peripheral Base Address Definitions */
|
---|
| 832 |
|
---|
| 833 | /** \addtogroup SAMD51P19A_pio Peripheral Pio Definitions
|
---|
| 834 | * @{
|
---|
| 835 | */
|
---|
| 836 |
|
---|
| 837 | /* ************************************************************************** */
|
---|
| 838 | /* PIO DEFINITIONS FOR SAMD51P19A */
|
---|
| 839 | /* ************************************************************************** */
|
---|
| 840 | //#include "pio/samd51p19a.h"
|
---|
| 841 | /** @} end of Peripheral Pio Definitions */
|
---|
| 842 |
|
---|
| 843 | /* ************************************************************************** */
|
---|
| 844 | /* MEMORY MAPPING DEFINITIONS FOR SAMD51P19A */
|
---|
| 845 | /* ************************************************************************** */
|
---|
| 846 |
|
---|
| 847 | #define FLASH_SIZE _UL_(0x00080000) /* 512kB Memory segment type: flash */
|
---|
| 848 | #define FLASH_PAGE_SIZE _UL_( 512)
|
---|
| 849 | #define FLASH_NB_OF_PAGES _UL_( 1024)
|
---|
| 850 |
|
---|
| 851 | #define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */
|
---|
| 852 | #define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */
|
---|
| 853 | #define TEMP_LOG_PAGE_SIZE _UL_( 512)
|
---|
| 854 | #define TEMP_LOG_NB_OF_PAGES _UL_( 1)
|
---|
| 855 |
|
---|
| 856 | #define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */
|
---|
| 857 | #define USER_PAGE_PAGE_SIZE _UL_( 512)
|
---|
| 858 | #define USER_PAGE_NB_OF_PAGES _UL_( 1)
|
---|
| 859 |
|
---|
| 860 | #define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */
|
---|
| 861 | #define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */
|
---|
| 862 | #define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */
|
---|
| 863 | #define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */
|
---|
| 864 | #define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */
|
---|
| 865 | #define HSRAM_SIZE _UL_(0x00030000) /* 192kB Memory segment type: ram */
|
---|
| 866 | #define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */
|
---|
| 867 | #define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */
|
---|
| 868 | #define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */
|
---|
| 869 | #define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */
|
---|
| 870 | #define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */
|
---|
| 871 | #define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */
|
---|
| 872 | #define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */
|
---|
| 873 | #define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */
|
---|
| 874 | #define SDHC1_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */
|
---|
| 875 | #define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */
|
---|
| 876 | #define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */
|
---|
| 877 | #define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */
|
---|
| 878 |
|
---|
| 879 | #define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/
|
---|
| 880 | #define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/
|
---|
| 881 | #define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/
|
---|
| 882 | #define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/
|
---|
| 883 | #define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/
|
---|
| 884 | #define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/
|
---|
| 885 | #define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/
|
---|
| 886 | #define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/
|
---|
| 887 | #define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/
|
---|
| 888 | #define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/
|
---|
| 889 | #define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/
|
---|
| 890 | #define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/
|
---|
| 891 | #define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/
|
---|
| 892 | #define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/
|
---|
| 893 | #define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/
|
---|
| 894 | #define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/
|
---|
| 895 | #define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/
|
---|
| 896 | #define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/
|
---|
| 897 | #define SDHC1_ADDR _UL_(0x46000000) /**< SDHC1 base address (type: io)*/
|
---|
| 898 | #define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/
|
---|
| 899 | #define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/
|
---|
| 900 | #define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/
|
---|
| 901 |
|
---|
| 902 | /* ************************************************************************** */
|
---|
| 903 | /** DEVICE SIGNATURES FOR SAMD51P19A */
|
---|
| 904 | /* ************************************************************************** */
|
---|
| 905 | #define CHIP_DSU_DID _UL_(0X60060301)
|
---|
| 906 |
|
---|
| 907 | /* ************************************************************************** */
|
---|
| 908 | /** ELECTRICAL DEFINITIONS FOR SAMD51P19A */
|
---|
| 909 | /* ************************************************************************** */
|
---|
| 910 |
|
---|
| 911 | /* ************************************************************************** */
|
---|
| 912 | /** Event Generator IDs for SAMD51P19A */
|
---|
| 913 | /* ************************************************************************** */
|
---|
| 914 | #define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */
|
---|
| 915 | #define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */
|
---|
| 916 | #define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */
|
---|
| 917 | #define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */
|
---|
| 918 | #define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */
|
---|
| 919 | #define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */
|
---|
| 920 | #define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */
|
---|
| 921 | #define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */
|
---|
| 922 | #define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */
|
---|
| 923 | #define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */
|
---|
| 924 | #define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */
|
---|
| 925 | #define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */
|
---|
| 926 | #define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */
|
---|
| 927 | #define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */
|
---|
| 928 | #define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */
|
---|
| 929 | #define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */
|
---|
| 930 | #define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */
|
---|
| 931 | #define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */
|
---|
| 932 | #define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */
|
---|
| 933 | #define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */
|
---|
| 934 | #define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */
|
---|
| 935 | #define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */
|
---|
| 936 | #define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */
|
---|
| 937 | #define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */
|
---|
| 938 | #define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */
|
---|
| 939 | #define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */
|
---|
| 940 | #define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */
|
---|
| 941 | #define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */
|
---|
| 942 | #define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */
|
---|
| 943 | #define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */
|
---|
| 944 | #define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */
|
---|
| 945 | #define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */
|
---|
| 946 | #define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */
|
---|
| 947 | #define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */
|
---|
| 948 | #define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */
|
---|
| 949 | #define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */
|
---|
| 950 | #define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */
|
---|
| 951 | #define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */
|
---|
| 952 | #define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */
|
---|
| 953 | #define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */
|
---|
| 954 | #define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */
|
---|
| 955 | #define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */
|
---|
| 956 | #define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */
|
---|
| 957 | #define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */
|
---|
| 958 | #define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */
|
---|
| 959 | #define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */
|
---|
| 960 | #define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */
|
---|
| 961 | #define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */
|
---|
| 962 | #define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */
|
---|
| 963 | #define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */
|
---|
| 964 | #define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */
|
---|
| 965 | #define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */
|
---|
| 966 | #define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */
|
---|
| 967 | #define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */
|
---|
| 968 | #define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */
|
---|
| 969 | #define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */
|
---|
| 970 | #define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */
|
---|
| 971 | #define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */
|
---|
| 972 | #define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */
|
---|
| 973 | #define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */
|
---|
| 974 | #define EVENT_ID_GEN_TCC3_OVF 63 /**< ID for TCC3 event generator OVF */
|
---|
| 975 | #define EVENT_ID_GEN_TCC3_TRG 64 /**< ID for TCC3 event generator TRG */
|
---|
| 976 | #define EVENT_ID_GEN_TCC3_CNT 65 /**< ID for TCC3 event generator CNT */
|
---|
| 977 | #define EVENT_ID_GEN_TCC3_MC_0 66 /**< ID for TCC3 event generator MC_0 */
|
---|
| 978 | #define EVENT_ID_GEN_TCC3_MC_1 67 /**< ID for TCC3 event generator MC_1 */
|
---|
| 979 | #define EVENT_ID_GEN_TCC4_OVF 68 /**< ID for TCC4 event generator OVF */
|
---|
| 980 | #define EVENT_ID_GEN_TCC4_TRG 69 /**< ID for TCC4 event generator TRG */
|
---|
| 981 | #define EVENT_ID_GEN_TCC4_CNT 70 /**< ID for TCC4 event generator CNT */
|
---|
| 982 | #define EVENT_ID_GEN_TCC4_MC_0 71 /**< ID for TCC4 event generator MC_0 */
|
---|
| 983 | #define EVENT_ID_GEN_TCC4_MC_1 72 /**< ID for TCC4 event generator MC_1 */
|
---|
| 984 | #define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */
|
---|
| 985 | #define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */
|
---|
| 986 | #define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */
|
---|
| 987 | #define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */
|
---|
| 988 | #define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */
|
---|
| 989 | #define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */
|
---|
| 990 | #define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */
|
---|
| 991 | #define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */
|
---|
| 992 | #define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */
|
---|
| 993 | #define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */
|
---|
| 994 | #define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */
|
---|
| 995 | #define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */
|
---|
| 996 | #define EVENT_ID_GEN_TC4_OVF 85 /**< ID for TC4 event generator OVF */
|
---|
| 997 | #define EVENT_ID_GEN_TC4_MC_0 86 /**< ID for TC4 event generator MC_0 */
|
---|
| 998 | #define EVENT_ID_GEN_TC4_MC_1 87 /**< ID for TC4 event generator MC_1 */
|
---|
| 999 | #define EVENT_ID_GEN_TC5_OVF 88 /**< ID for TC5 event generator OVF */
|
---|
| 1000 | #define EVENT_ID_GEN_TC5_MC_0 89 /**< ID for TC5 event generator MC_0 */
|
---|
| 1001 | #define EVENT_ID_GEN_TC5_MC_1 90 /**< ID for TC5 event generator MC_1 */
|
---|
| 1002 | #define EVENT_ID_GEN_TC6_OVF 91 /**< ID for TC6 event generator OVF */
|
---|
| 1003 | #define EVENT_ID_GEN_TC6_MC_0 92 /**< ID for TC6 event generator MC_0 */
|
---|
| 1004 | #define EVENT_ID_GEN_TC6_MC_1 93 /**< ID for TC6 event generator MC_1 */
|
---|
| 1005 | #define EVENT_ID_GEN_TC7_OVF 94 /**< ID for TC7 event generator OVF */
|
---|
| 1006 | #define EVENT_ID_GEN_TC7_MC_0 95 /**< ID for TC7 event generator MC_0 */
|
---|
| 1007 | #define EVENT_ID_GEN_TC7_MC_1 96 /**< ID for TC7 event generator MC_1 */
|
---|
| 1008 | #define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */
|
---|
| 1009 | #define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */
|
---|
| 1010 | #define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */
|
---|
| 1011 | #define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */
|
---|
| 1012 | #define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */
|
---|
| 1013 | #define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */
|
---|
| 1014 | #define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */
|
---|
| 1015 | #define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */
|
---|
| 1016 | #define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */
|
---|
| 1017 | #define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */
|
---|
| 1018 | #define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */
|
---|
| 1019 | #define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */
|
---|
| 1020 | #define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */
|
---|
| 1021 | #define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */
|
---|
| 1022 | #define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */
|
---|
| 1023 | #define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */
|
---|
| 1024 | #define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */
|
---|
| 1025 | #define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */
|
---|
| 1026 | #define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */
|
---|
| 1027 | #define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */
|
---|
| 1028 | #define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */
|
---|
| 1029 | #define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */
|
---|
| 1030 |
|
---|
| 1031 | /* ************************************************************************** */
|
---|
| 1032 | /** Event User IDs for SAMD51P19A */
|
---|
| 1033 | /* ************************************************************************** */
|
---|
| 1034 | #define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */
|
---|
| 1035 | #define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */
|
---|
| 1036 | #define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */
|
---|
| 1037 | #define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */
|
---|
| 1038 | #define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */
|
---|
| 1039 | #define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */
|
---|
| 1040 | #define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */
|
---|
| 1041 | #define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */
|
---|
| 1042 | #define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */
|
---|
| 1043 | #define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */
|
---|
| 1044 | #define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */
|
---|
| 1045 | #define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */
|
---|
| 1046 | #define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */
|
---|
| 1047 | #define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */
|
---|
| 1048 | #define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */
|
---|
| 1049 | #define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */
|
---|
| 1050 | #define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */
|
---|
| 1051 | #define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */
|
---|
| 1052 | #define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */
|
---|
| 1053 | #define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */
|
---|
| 1054 | #define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */
|
---|
| 1055 | #define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */
|
---|
| 1056 | #define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */
|
---|
| 1057 | #define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */
|
---|
| 1058 | #define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */
|
---|
| 1059 | #define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */
|
---|
| 1060 | #define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */
|
---|
| 1061 | #define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */
|
---|
| 1062 | #define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */
|
---|
| 1063 | #define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */
|
---|
| 1064 | #define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */
|
---|
| 1065 | #define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */
|
---|
| 1066 | #define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */
|
---|
| 1067 | #define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */
|
---|
| 1068 | #define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */
|
---|
| 1069 | #define EVENT_ID_USER_TCC3_EV_0 36 /**< ID for TCC3 event user EV_0 */
|
---|
| 1070 | #define EVENT_ID_USER_TCC3_EV_1 37 /**< ID for TCC3 event user EV_1 */
|
---|
| 1071 | #define EVENT_ID_USER_TCC3_MC_0 38 /**< ID for TCC3 event user MC_0 */
|
---|
| 1072 | #define EVENT_ID_USER_TCC3_MC_1 39 /**< ID for TCC3 event user MC_1 */
|
---|
| 1073 | #define EVENT_ID_USER_TCC4_EV_0 40 /**< ID for TCC4 event user EV_0 */
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| 1074 | #define EVENT_ID_USER_TCC4_EV_1 41 /**< ID for TCC4 event user EV_1 */
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| 1075 | #define EVENT_ID_USER_TCC4_MC_0 42 /**< ID for TCC4 event user MC_0 */
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| 1076 | #define EVENT_ID_USER_TCC4_MC_1 43 /**< ID for TCC4 event user MC_1 */
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| 1077 | #define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */
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| 1078 | #define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */
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| 1079 | #define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */
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| 1080 | #define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */
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| 1081 | #define EVENT_ID_USER_TC4_EVU 48 /**< ID for TC4 event user EVU */
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| 1082 | #define EVENT_ID_USER_TC5_EVU 49 /**< ID for TC5 event user EVU */
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| 1083 | #define EVENT_ID_USER_TC6_EVU 50 /**< ID for TC6 event user EVU */
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| 1084 | #define EVENT_ID_USER_TC7_EVU 51 /**< ID for TC7 event user EVU */
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| 1085 | #define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */
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| 1086 | #define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */
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| 1087 | #define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */
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| 1088 | #define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */
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| 1089 | #define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */
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| 1090 | #define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */
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| 1091 | #define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */
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| 1092 | #define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */
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| 1093 | #define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */
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| 1094 | #define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */
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| 1095 | #define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */
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| 1096 | #define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */
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| 1097 | #define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */
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| 1098 | #define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */
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| 1099 | #define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */
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| 1100 |
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| 1101 | #ifdef __cplusplus
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| 1102 | }
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| 1103 | #endif
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| 1104 |
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| 1105 | /** @} end of SAMD51P19A definitions */
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| 1106 |
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| 1107 |
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| 1108 | #endif /* _SAMD51P19A_H_ */
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| 1109 |
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