[1] | 1 | SYSTEM std_2s180
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| 2 | {
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| 3 | System_Wizard_Version = "6.10";
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| 4 | System_Wizard_Build = "201";
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| 5 | WIZARD_SCRIPT_ARGUMENTS
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| 6 | {
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| 7 | device_family = "STRATIXII";
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| 8 | clock_freq = "50000000";
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| 9 | generate_hdl = "1";
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| 10 | generate_sdk = "0";
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| 11 | do_build_sim = "0";
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| 12 | hdl_language = "vhdl";
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| 13 | view_master_columns = "1";
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| 14 | view_master_priorities = "0";
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| 15 | board_class = "altera_dsp_dev_board_stratix_2s180";
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| 16 | name_column_width = "253";
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| 17 | desc_column_width = "254";
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| 18 | bustype_column_width = "0";
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| 19 | base_column_width = "75";
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| 20 | end_column_width = "75";
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| 21 | view_frame_window = "140:131:1120:787";
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| 22 | do_log_history = "0";
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| 23 | device_family_id = "STRATIXII";
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| 24 | CLOCKS
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| 25 | {
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| 26 | CLOCK clk
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| 27 | {
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| 28 | frequency = "50000000";
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| 29 | source = "External";
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| 30 | Is_Clock_Source = "0";
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| 31 | display_name = "clk";
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| 32 | pipeline = "0";
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| 33 | }
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| 34 | }
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| 35 | clock_column_width = "75";
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| 36 | hardcopy_compatible = "0";
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| 37 | BOARD_INFO
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| 38 | {
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| 39 | CONFIGURATION factory
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| 40 | {
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| 41 | length = "";
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| 42 | menu_position = "1";
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| 43 | offset = "0x00200000";
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| 44 | reference_designator = "U17";
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| 45 | }
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| 46 | CONFIGURATION page0
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| 47 | {
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| 48 | length = "";
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| 49 | menu_position = "2";
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| 50 | offset = "0x00900000";
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| 51 | reference_designator = "U17";
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| 52 | }
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| 53 | JTAG_device_index = "1";
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| 54 | REFDES U17
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| 55 | {
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| 56 | base = "0x01000000";
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| 57 | }
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| 58 | altera_avalon_cfi_flash
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| 59 | {
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| 60 | reference_designators = "U17";
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| 61 | }
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| 62 | class = "altera_dsp_dev_board_stratix_2s180";
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| 63 | class_version = "1.0";
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| 64 | device_family = "STRATIXII";
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| 65 | quartus_pgm_file = "system/altera_dsp_dev_board_stratix_2s180.sof";
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| 66 | quartus_project_file = "system/altera_dsp_dev_board_stratix_2s180.qpf";
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| 67 | reference_designators = "U17";
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| 68 | sopc_system_file = "system/altera_dsp_dev_board_stratix_2s180.ptf";
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| 69 | }
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| 70 | }
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| 71 | MODULE cpu
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| 72 | {
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| 73 | class = "altera_nios2";
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| 74 | class_version = "6.05";
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| 75 | iss_model_name = "altera_nios2";
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| 76 | HDL_INFO
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| 77 | {
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| 78 | PLI_Files = "";
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| 79 | Precompiled_Simulation_Library_Files = "";
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| 80 | Simulation_HDL_Files = "";
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| 81 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_test_bench.vhd, __PROJECT_DIRECTORY__/cpu_mult_cell.vhd, __PROJECT_DIRECTORY__/cpu_jtag_debug_module.vhd, __PROJECT_DIRECTORY__/cpu_jtag_debug_module_wrapper.vhd, __PROJECT_DIRECTORY__/cpu.vhd";
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| 82 | Synthesis_Only_Files = "";
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| 83 | }
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| 84 | MASTER instruction_master
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| 85 | {
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| 86 | PORT_WIRING
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| 87 | {
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| 88 | PORT i_address
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| 89 | {
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| 90 | direction = "output";
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| 91 | type = "address";
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| 92 | width = "28";
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| 93 | Is_Enabled = "1";
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| 94 | }
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| 95 | PORT i_read
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| 96 | {
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| 97 | direction = "output";
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| 98 | type = "read";
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| 99 | width = "1";
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| 100 | Is_Enabled = "1";
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| 101 | }
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| 102 | PORT i_readdata
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| 103 | {
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| 104 | direction = "input";
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| 105 | type = "readdata";
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| 106 | width = "32";
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| 107 | Is_Enabled = "1";
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| 108 | }
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| 109 | PORT i_readdatavalid
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| 110 | {
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| 111 | direction = "input";
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| 112 | type = "readdatavalid";
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| 113 | width = "1";
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| 114 | Is_Enabled = "1";
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| 115 | }
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| 116 | PORT i_waitrequest
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| 117 | {
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| 118 | direction = "input";
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| 119 | type = "waitrequest";
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| 120 | width = "1";
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| 121 | Is_Enabled = "1";
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| 122 | }
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| 123 | }
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| 124 | SYSTEM_BUILDER_INFO
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| 125 | {
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| 126 | Bus_Type = "avalon";
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| 127 | Data_Width = "32";
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| 128 | Max_Address_Width = "31";
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| 129 | Address_Width = "8";
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| 130 | Is_Instruction_Master = "1";
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| 131 | Has_IRQ = "0";
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| 132 | Irq_Scheme = "individual_requests";
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| 133 | Interrupt_Range = "0-0";
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| 134 | Is_Enabled = "1";
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| 135 | Is_Readable = "1";
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| 136 | Is_Writeable = "0";
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| 137 | Address_Group = "0";
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| 138 | Maximum_Burst_Size = "1";
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| 139 | Burst_On_Burst_Boundaries_Only = "";
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| 140 | Linewrap_Bursts = "";
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| 141 | Interleave_Bursts = "";
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| 142 | Is_Big_Endian = "0";
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| 143 | }
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| 144 | }
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| 145 | MASTER data_master
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| 146 | {
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| 147 | PORT_WIRING
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| 148 | {
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| 149 | PORT clk
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| 150 | {
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| 151 | direction = "input";
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| 152 | type = "clk";
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| 153 | width = "1";
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| 154 | Is_Enabled = "0";
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| 155 | }
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| 156 | PORT d_address
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| 157 | {
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| 158 | direction = "output";
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| 159 | type = "address";
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| 160 | width = "28";
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| 161 | Is_Enabled = "1";
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| 162 | }
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| 163 | PORT d_byteenable
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| 164 | {
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| 165 | direction = "output";
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| 166 | type = "byteenable";
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| 167 | width = "4";
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| 168 | Is_Enabled = "1";
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| 169 | }
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| 170 | PORT d_irq
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| 171 | {
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| 172 | direction = "input";
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| 173 | type = "irq";
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| 174 | width = "32";
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| 175 | Is_Enabled = "1";
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| 176 | }
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| 177 | PORT d_read
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| 178 | {
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| 179 | direction = "output";
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| 180 | type = "read";
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| 181 | width = "1";
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| 182 | Is_Enabled = "1";
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| 183 | }
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| 184 | PORT d_readdata
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| 185 | {
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| 186 | direction = "input";
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| 187 | type = "readdata";
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| 188 | width = "32";
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| 189 | Is_Enabled = "1";
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| 190 | }
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| 191 | PORT d_waitrequest
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| 192 | {
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| 193 | direction = "input";
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| 194 | type = "waitrequest";
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| 195 | width = "1";
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| 196 | Is_Enabled = "1";
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| 197 | }
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| 198 | PORT d_write
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| 199 | {
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| 200 | direction = "output";
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| 201 | type = "write";
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| 202 | width = "1";
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| 203 | Is_Enabled = "1";
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| 204 | }
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| 205 | PORT d_writedata
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| 206 | {
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| 207 | direction = "output";
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| 208 | type = "writedata";
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| 209 | width = "32";
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| 210 | Is_Enabled = "1";
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| 211 | }
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| 212 | PORT jtag_debug_module_debugaccess_to_roms
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| 213 | {
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| 214 | direction = "output";
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| 215 | type = "debugaccess";
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| 216 | width = "1";
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| 217 | Is_Enabled = "1";
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| 218 | }
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| 219 | }
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| 220 | SYSTEM_BUILDER_INFO
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| 221 | {
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| 222 | Register_Incoming_Signals = "1";
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| 223 | Bus_Type = "avalon";
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| 224 | Data_Width = "32";
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| 225 | Max_Address_Width = "31";
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| 226 | Address_Width = "8";
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| 227 | Is_Data_Master = "1";
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| 228 | Has_IRQ = "1";
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| 229 | Irq_Scheme = "individual_requests";
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| 230 | Interrupt_Range = "0-31";
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| 231 | Is_Enabled = "1";
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| 232 | Address_Group = "0";
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| 233 | Is_Readable = "1";
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| 234 | Is_Writeable = "1";
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| 235 | Maximum_Burst_Size = "1";
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| 236 | Burst_On_Burst_Boundaries_Only = "";
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| 237 | Is_Big_Endian = "0";
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| 238 | }
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| 239 | }
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| 240 | SLAVE jtag_debug_module
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| 241 | {
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| 242 | PORT_WIRING
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| 243 | {
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| 244 | PORT jtag_debug_module_address
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| 245 | {
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| 246 | direction = "input";
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| 247 | type = "address";
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| 248 | width = "9";
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| 249 | Is_Enabled = "1";
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| 250 | }
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| 251 | PORT jtag_debug_module_begintransfer
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| 252 | {
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| 253 | direction = "input";
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| 254 | type = "begintransfer";
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| 255 | width = "1";
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| 256 | Is_Enabled = "1";
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| 257 | }
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| 258 | PORT jtag_debug_module_clk
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| 259 | {
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| 260 | direction = "input";
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| 261 | type = "clk";
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| 262 | width = "1";
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| 263 | Is_Enabled = "1";
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| 264 | }
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| 265 | PORT jtag_debug_module_debugaccess
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| 266 | {
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| 267 | direction = "input";
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| 268 | type = "debugaccess";
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| 269 | width = "1";
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| 270 | Is_Enabled = "1";
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| 271 | }
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| 272 | PORT jtag_debug_module_readdata
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| 273 | {
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| 274 | direction = "output";
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| 275 | type = "readdata";
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| 276 | width = "32";
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| 277 | Is_Enabled = "1";
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| 278 | }
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| 279 | PORT jtag_debug_module_reset
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| 280 | {
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| 281 | direction = "input";
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| 282 | type = "reset";
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| 283 | width = "1";
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| 284 | Is_Enabled = "1";
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| 285 | }
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| 286 | PORT jtag_debug_module_resetrequest
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| 287 | {
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| 288 | direction = "output";
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| 289 | type = "resetrequest";
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| 290 | width = "1";
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| 291 | Is_Enabled = "1";
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| 292 | }
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| 293 | PORT jtag_debug_module_select
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| 294 | {
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| 295 | direction = "input";
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| 296 | type = "chipselect";
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| 297 | width = "1";
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| 298 | Is_Enabled = "1";
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| 299 | }
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| 300 | PORT jtag_debug_module_write
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| 301 | {
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| 302 | direction = "input";
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| 303 | type = "write";
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| 304 | width = "1";
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| 305 | Is_Enabled = "1";
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| 306 | }
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| 307 | PORT jtag_debug_module_writedata
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| 308 | {
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| 309 | direction = "input";
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| 310 | type = "writedata";
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| 311 | width = "32";
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| 312 | Is_Enabled = "1";
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| 313 | }
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| 314 | PORT reset_n
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| 315 | {
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| 316 | direction = "input";
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| 317 | type = "reset_n";
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| 318 | width = "1";
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| 319 | Is_Enabled = "0";
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| 320 | }
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| 321 | PORT jtag_debug_module_byteenable
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| 322 | {
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| 323 | direction = "input";
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| 324 | type = "byteenable";
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| 325 | width = "4";
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| 326 | Is_Enabled = "1";
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| 327 | }
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| 328 | }
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| 329 | SYSTEM_BUILDER_INFO
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| 330 | {
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| 331 | Read_Wait_States = "1";
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| 332 | Write_Wait_States = "1";
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| 333 | Register_Incoming_Signals = "1";
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| 334 | Bus_Type = "avalon";
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| 335 | Data_Width = "32";
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| 336 | Address_Width = "9";
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| 337 | Accepts_Internal_Connections = "1";
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| 338 | Requires_Internal_Connections = "instruction_master,data_master";
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| 339 | Accepts_External_Connections = "0";
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| 340 | Is_Enabled = "1";
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| 341 | Address_Alignment = "dynamic";
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| 342 | Base_Address = "0x08010000";
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| 343 | Is_Memory_Device = "1";
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| 344 | Is_Printable_Device = "0";
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| 345 | Uses_Tri_State_Data_Bus = "0";
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| 346 | Has_IRQ = "0";
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| 347 | JTAG_Hub_Base_Id = "1118278";
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| 348 | JTAG_Hub_Instance_Id = "1";
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| 349 | MASTERED_BY cpu/instruction_master
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| 350 | {
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| 351 | priority = "1";
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| 352 | }
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| 353 | MASTERED_BY cpu/data_master
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| 354 | {
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| 355 | priority = "1";
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| 356 | }
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| 357 | IRQ_MASTER cpu/data_master
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| 358 | {
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| 359 | IRQ_Number = "NC";
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| 360 | }
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| 361 | Is_Readable = "1";
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| 362 | Is_Writeable = "1";
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| 363 | Is_Big_Endian = "0";
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| 364 | Address_Group = "0";
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| 365 | }
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| 366 | }
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| 367 | WIZARD_SCRIPT_ARGUMENTS
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| 368 | {
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| 369 | CPU_Architecture = "nios2";
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| 370 | do_generate = "1";
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| 371 | cpu_selection = "s";
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| 372 | CPU_Implementation = "small";
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| 373 | cache_has_dcache = "0";
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| 374 | cache_has_icache = "1";
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| 375 | cache_dcache_size = "2048";
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| 376 | cache_icache_size = "4096";
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| 377 | include_debug = "0";
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| 378 | include_trace = "0";
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| 379 | include_oci = "1";
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| 380 | debug_level = "2";
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| 381 | oci_offchip_trace = "0";
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| 382 | oci_onchip_trace = "0";
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| 383 | oci_data_trace = "0";
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| 384 | oci_trace_addr_width = "7";
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| 385 | oci_num_xbrk = "0";
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| 386 | oci_num_dbrk = "0";
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| 387 | oci_dbrk_trace = "0";
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| 388 | oci_dbrk_pairs = "0";
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| 389 | oci_num_pm = "0";
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| 390 | oci_pm_width = "40";
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| 391 | oci_debugreq_signals = "0";
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| 392 | oci_instance_number = "1";
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| 393 | hardware_multiply_present = "1";
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| 394 | hardware_divide_present = "0";
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| 395 | bht_ptr_sz = "8";
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| 396 | reset_slave = "ext_flash/s1";
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| 397 | reset_offset = "0x00000000";
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| 398 | exc_slave = "sdram/s1";
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| 399 | exc_offset = "0x00000020";
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| 400 | break_slave = "cpu/jtag_debug_module";
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| 401 | break_offset = "0x00000020";
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| 402 | altera_internal_test = "0";
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| 403 | full_waveform_signals = "0";
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| 404 | activate_model_checker = "0";
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| 405 | activate_monitors_and_trace = "0";
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| 406 | bit_31_bypass_dcache = "1";
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| 407 | always_bypass_dcache = "0";
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| 408 | always_encrypt = "1";
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| 409 | consistent_synthesis = "0";
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| 410 | ibuf_ptr_sz = "4";
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| 411 | jtb_ptr_sz = "5";
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| 412 | performance_counters_present = "0";
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| 413 | performance_counters_width = "32";
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| 414 | ras_ptr_sz = "4";
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| 415 | inst_decode_in_submodule = "0";
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| 416 | register_dependency_in_submodule = "0";
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| 417 | source_operands_in_submodule = "0";
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| 418 | alu_in_submodule = "0";
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| 419 | stdata_in_submodule = "0";
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| 420 | shift_rot_2N_in_submodule = "0";
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| 421 | control_regs_in_submodule = "0";
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| 422 | mult_cell_in_submodule = "0";
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| 423 | M_inst_result_mux_in_submodule = "0";
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| 424 | dcache_load_aligner_in_submodule = "0";
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| 425 | hardware_divide_in_submodule = "0";
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| 426 | mult_result_mux_in_submodule = "0";
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| 427 | shift_rotate_in_submodule = "0";
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| 428 | register_file_write_data_mux_in_submodule = "0";
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| 429 | avalon_imaster_in_submodule = "0";
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| 430 | avalon_dmaster_in_submodule = "0";
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| 431 | avalon_load_aligner_in_submodule = "0";
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| 432 | hbreak_test = "0";
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| 433 | iss_trace_on = "0";
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| 434 | iss_trace_warning = "1";
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| 435 | iss_trace_info = "1";
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| 436 | iss_trace_disassembly = "0";
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| 437 | iss_trace_registers = "0";
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| 438 | iss_trace_instr_count = "0";
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| 439 | iss_software_debug = "0";
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| 440 | iss_software_debug_port = "9996";
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| 441 | iss_memory_dump_start = "";
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| 442 | iss_memory_dump_end = "";
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| 443 | Boot_Copier = "boot_loader_cfi.srec";
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| 444 | Boot_Copier_EPCS = "boot_loader_epcs.srec";
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| 445 | CONSTANTS
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| 446 | {
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| 447 | CONSTANT __nios_catch_irqs__
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| 448 | {
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| 449 | value = "1";
|
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| 450 | comment = "Include panic handler for all irqs (needs uart)";
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| 451 | }
|
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| 452 | CONSTANT __nios_use_constructors__
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| 453 | {
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| 454 | value = "1";
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| 455 | comment = "Call c++ static constructors";
|
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| 456 | }
|
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| 457 | CONSTANT __nios_use_small_printf__
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| 458 | {
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| 459 | value = "1";
|
---|
| 460 | comment = "Smaller non-ANSI printf, with no floating point";
|
---|
| 461 | }
|
---|
| 462 | CONSTANT nasys_has_icache
|
---|
| 463 | {
|
---|
| 464 | value = "1";
|
---|
| 465 | comment = "True if instruction cache present";
|
---|
| 466 | }
|
---|
| 467 | CONSTANT nasys_icache_size
|
---|
| 468 | {
|
---|
| 469 | value = "4096";
|
---|
| 470 | comment = "Size in bytes of instruction cache";
|
---|
| 471 | }
|
---|
| 472 | CONSTANT nasys_icache_line_size
|
---|
| 473 | {
|
---|
| 474 | value = "32";
|
---|
| 475 | comment = "Size in bytes of each icache line";
|
---|
| 476 | }
|
---|
| 477 | CONSTANT nasys_icache_line_size_log2
|
---|
| 478 | {
|
---|
| 479 | value = "5";
|
---|
| 480 | comment = "Log2 size in bytes of each icache line";
|
---|
| 481 | }
|
---|
| 482 | CONSTANT nasys_has_dcache
|
---|
| 483 | {
|
---|
| 484 | value = "0";
|
---|
| 485 | comment = "True if instruction cache present";
|
---|
| 486 | }
|
---|
| 487 | CONSTANT nasys_dcache_size
|
---|
| 488 | {
|
---|
| 489 | value = "2048";
|
---|
| 490 | comment = "Size in bytes of data cache";
|
---|
| 491 | }
|
---|
| 492 | CONSTANT nasys_dcache_line_size
|
---|
| 493 | {
|
---|
| 494 | value = "4";
|
---|
| 495 | comment = "Size in bytes of each dcache line";
|
---|
| 496 | }
|
---|
| 497 | CONSTANT nasys_dcache_line_size_log2
|
---|
| 498 | {
|
---|
| 499 | value = "2";
|
---|
| 500 | comment = "Log2 size in bytes of each dcache line";
|
---|
| 501 | }
|
---|
| 502 | }
|
---|
| 503 | mainmem_slave = "sdram/s1";
|
---|
| 504 | datamem_slave = "sdram/s1";
|
---|
| 505 | maincomm_slave = "uart1/s1";
|
---|
| 506 | debugcomm_slave = "uart1/s1";
|
---|
| 507 | germs_monitor_id = "";
|
---|
| 508 | asp_debug = "0";
|
---|
| 509 | asp_core_debug = "0";
|
---|
| 510 | legacy_sdk_support = "0";
|
---|
| 511 | hdl_sim_caches_cleared = "1";
|
---|
| 512 | allow_full_address_range = "0";
|
---|
| 513 | break_slave_override = "";
|
---|
| 514 | break_offset_override = "0x20";
|
---|
| 515 | remove_hardware_multiplier = "0";
|
---|
| 516 | activate_trace = "1";
|
---|
| 517 | activate_monitors = "1";
|
---|
| 518 | activate_test_end_checker = "0";
|
---|
| 519 | clear_x_bits_ld_non_bypass = "1";
|
---|
| 520 | oci_trigger_arming = "1";
|
---|
| 521 | illegal_instructions_trap = "0";
|
---|
| 522 | include_third_party_debug_port = "0";
|
---|
| 523 | hardware_multiply_uses_les = "0";
|
---|
| 524 | hardware_multiply_omits_msw = "0";
|
---|
| 525 | hardware_multiply_implementation = "0";
|
---|
| 526 | hardware_multiply_implementation_dsp_blocks = "0";
|
---|
| 527 | hardware_multiply_implementation_embedded_mults = "1";
|
---|
| 528 | hardware_multiply_implementation_les = "2";
|
---|
| 529 | altera_show_unreleased_features = "0";
|
---|
| 530 | cache_omit_dcache = "0";
|
---|
| 531 | cache_omit_icache = "0";
|
---|
| 532 | omit_instruction_master = "0";
|
---|
| 533 | omit_data_master = "0";
|
---|
| 534 | num_data_channel_masters = "0";
|
---|
| 535 | num_instruction_channel_masters = "0";
|
---|
| 536 | gui_branch_prediction_type = "Automatic";
|
---|
| 537 | branch_prediction_type = "Static";
|
---|
| 538 | bht_index_pc_only = "0";
|
---|
| 539 | cpuid_sz = "1";
|
---|
| 540 | cpuid_value = "0";
|
---|
| 541 | gui_hardware_multiply_setting = "dsp_mul_dsp_shift";
|
---|
| 542 | hardware_multiply_impl = "dsp_mul";
|
---|
| 543 | num_tightly_coupled_data_masters = "0";
|
---|
| 544 | num_tightly_coupled_instruction_masters = "0";
|
---|
| 545 | shift_rot_impl = "dsp_shift";
|
---|
| 546 | gui_include_tightly_coupled_instruction_masters = "0";
|
---|
| 547 | gui_num_tightly_coupled_instruction_masters = "1";
|
---|
| 548 | gui_omit_avalon_data_master = "0";
|
---|
| 549 | gui_include_tightly_coupled_data_masters = "0";
|
---|
| 550 | gui_num_tightly_coupled_data_masters = "1";
|
---|
| 551 | cache_dcache_line_size = "4";
|
---|
| 552 | cache_icache_line_size = "32";
|
---|
| 553 | cache_dcache_bursts = "0";
|
---|
| 554 | cache_icache_burst_type = "none";
|
---|
| 555 | cache_dcache_ram_block_type = "AUTO";
|
---|
| 556 | cache_icache_ram_block_type = "AUTO";
|
---|
| 557 | oci_embedded_pll = "1";
|
---|
| 558 | gui_hardware_divide_setting = "0";
|
---|
| 559 | mmu_present = "0";
|
---|
| 560 | process_id_num_bits = "10";
|
---|
| 561 | dtlb_ptr_sz = "7";
|
---|
| 562 | dtlb_num_ways = "4";
|
---|
| 563 | udtlb_num_entries = "6";
|
---|
| 564 | itlb_ptr_sz = "7";
|
---|
| 565 | itlb_num_ways = "4";
|
---|
| 566 | uitlb_num_entries = "4";
|
---|
| 567 | fast_tlb_miss_exc_slave = "";
|
---|
| 568 | fast_tlb_miss_exc_offset = "0x0";
|
---|
| 569 | license_status = "encrypted";
|
---|
| 570 | cpu_reset = "0";
|
---|
| 571 | export_pcb = "0";
|
---|
| 572 | big_endian = "0";
|
---|
| 573 | altera_show_unpublished_features = "0";
|
---|
| 574 | alt_log_port_base = "";
|
---|
| 575 | alt_log_port_type = "";
|
---|
| 576 | gui_illegal_instructions_trap = "0";
|
---|
| 577 | gui_illegal_memory_access_detection = "0";
|
---|
| 578 | illegal_memory_access_detection = "0";
|
---|
| 579 | gui_mmu_present = "0";
|
---|
| 580 | debug_simgen = "0";
|
---|
| 581 | allow_legacy_sdk = "0";
|
---|
| 582 | Boot_Copier_EPCS_Stratix_II = "boot_loader_epcs_stratix_ii.srec";
|
---|
| 583 | Boot_Copier_BE = "boot_loader_cfi_be.srec";
|
---|
| 584 | Boot_Copier_EPCS_BE = "boot_loader_epcs_be.srec";
|
---|
| 585 | Boot_Copier_EPCS_Stratix_II_BE = "boot_loader_epcs_stratix_ii_be.srec";
|
---|
| 586 | dont_overwrite_cpuid = "0";
|
---|
| 587 | }
|
---|
| 588 | SYSTEM_BUILDER_INFO
|
---|
| 589 | {
|
---|
| 590 | Parameters_Signature = "";
|
---|
| 591 | Is_CPU = "1";
|
---|
| 592 | Is_Enabled = "1";
|
---|
| 593 | Instantiate_In_System_Module = "1";
|
---|
| 594 | Default_Module_Name = "cpu";
|
---|
| 595 | View
|
---|
| 596 | {
|
---|
| 597 | MESSAGES
|
---|
| 598 | {
|
---|
| 599 | }
|
---|
| 600 | Is_Collapsed = "0";
|
---|
| 601 | Settings_Summary = "Nios II/s
|
---|
| 602 | <br> 4-Kbyte Instruction Cache
|
---|
| 603 |
|
---|
| 604 | <br> JTAG Debug Module
|
---|
| 605 | ";
|
---|
| 606 | }
|
---|
| 607 | Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,STRATIXIII,CYCLONE,CYCLONEII";
|
---|
| 608 | Clock_Source = "clk";
|
---|
| 609 | Top_Level_Ports_Are_Enumerated = "1";
|
---|
| 610 | }
|
---|
| 611 | SOFTWARE_COMPONENT altera_hal
|
---|
| 612 | {
|
---|
| 613 | class = "altera_hal";
|
---|
| 614 | class_version = "1.0";
|
---|
| 615 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 616 | {
|
---|
| 617 | }
|
---|
| 618 | SYSTEM_BUILDER_INFO
|
---|
| 619 | {
|
---|
| 620 | Is_Enabled = "1";
|
---|
| 621 | }
|
---|
| 622 | }
|
---|
| 623 | SOFTWARE_COMPONENT altera_nios2_test
|
---|
| 624 | {
|
---|
| 625 | class = "altera_nios2_test";
|
---|
| 626 | class_version = "2.0";
|
---|
| 627 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 628 | {
|
---|
| 629 | CONSTANTS
|
---|
| 630 | {
|
---|
| 631 | CONSTANT debug_on
|
---|
| 632 | {
|
---|
| 633 | value = "0";
|
---|
| 634 | comment = "Enable debug features";
|
---|
| 635 | }
|
---|
| 636 | }
|
---|
| 637 | }
|
---|
| 638 | SYSTEM_BUILDER_INFO
|
---|
| 639 | {
|
---|
| 640 | Is_Enabled = "0";
|
---|
| 641 | }
|
---|
| 642 | }
|
---|
| 643 | SOFTWARE_COMPONENT altera_plugs_library
|
---|
| 644 | {
|
---|
| 645 | class = "altera_plugs_library";
|
---|
| 646 | class_version = "2.1";
|
---|
| 647 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 648 | {
|
---|
| 649 | CONSTANTS
|
---|
| 650 | {
|
---|
| 651 | CONSTANT PLUGS_PLUG_COUNT
|
---|
| 652 | {
|
---|
| 653 | value = "5";
|
---|
| 654 | comment = "Maximum number of plugs";
|
---|
| 655 | }
|
---|
| 656 | CONSTANT PLUGS_ADAPTER_COUNT
|
---|
| 657 | {
|
---|
| 658 | value = "2";
|
---|
| 659 | comment = "Maximum number of adapters";
|
---|
| 660 | }
|
---|
| 661 | CONSTANT PLUGS_DNS
|
---|
| 662 | {
|
---|
| 663 | value = "1";
|
---|
| 664 | comment = "Have routines for DNS lookups";
|
---|
| 665 | }
|
---|
| 666 | CONSTANT PLUGS_PING
|
---|
| 667 | {
|
---|
| 668 | value = "1";
|
---|
| 669 | comment = "Respond to icmp echo (ping) messages";
|
---|
| 670 | }
|
---|
| 671 | CONSTANT PLUGS_TCP
|
---|
| 672 | {
|
---|
| 673 | value = "1";
|
---|
| 674 | comment = "Support tcp in/out connections";
|
---|
| 675 | }
|
---|
| 676 | CONSTANT PLUGS_IRQ
|
---|
| 677 | {
|
---|
| 678 | value = "1";
|
---|
| 679 | comment = "Run at interrupte level";
|
---|
| 680 | }
|
---|
| 681 | CONSTANT PLUGS_DEBUG
|
---|
| 682 | {
|
---|
| 683 | value = "1";
|
---|
| 684 | comment = "Support debug routines";
|
---|
| 685 | }
|
---|
| 686 | }
|
---|
| 687 | }
|
---|
| 688 | SYSTEM_BUILDER_INFO
|
---|
| 689 | {
|
---|
| 690 | Is_Enabled = "1";
|
---|
| 691 | }
|
---|
| 692 | }
|
---|
| 693 | PORT_WIRING
|
---|
| 694 | {
|
---|
| 695 | PORT jtag_debug_trigout
|
---|
| 696 | {
|
---|
| 697 | width = "1";
|
---|
| 698 | direction = "output";
|
---|
| 699 | Is_Enabled = "0";
|
---|
| 700 | }
|
---|
| 701 | PORT jtag_debug_offchip_trace_clk
|
---|
| 702 | {
|
---|
| 703 | width = "1";
|
---|
| 704 | direction = "output";
|
---|
| 705 | Is_Enabled = "0";
|
---|
| 706 | }
|
---|
| 707 | PORT jtag_debug_offchip_trace_data
|
---|
| 708 | {
|
---|
| 709 | width = "18";
|
---|
| 710 | direction = "output";
|
---|
| 711 | Is_Enabled = "0";
|
---|
| 712 | }
|
---|
| 713 | PORT clkx2
|
---|
| 714 | {
|
---|
| 715 | width = "1";
|
---|
| 716 | direction = "input";
|
---|
| 717 | Is_Enabled = "0";
|
---|
| 718 | visible = "0";
|
---|
| 719 | }
|
---|
| 720 | }
|
---|
| 721 | SIMULATION
|
---|
| 722 | {
|
---|
| 723 | DISPLAY
|
---|
| 724 | {
|
---|
| 725 | SIGNAL aaa
|
---|
| 726 | {
|
---|
| 727 | format = "Logic";
|
---|
| 728 | name = "i_readdata";
|
---|
| 729 | radix = "hexadecimal";
|
---|
| 730 | }
|
---|
| 731 | SIGNAL aab
|
---|
| 732 | {
|
---|
| 733 | format = "Logic";
|
---|
| 734 | name = "i_readdatavalid";
|
---|
| 735 | radix = "hexadecimal";
|
---|
| 736 | }
|
---|
| 737 | SIGNAL aac
|
---|
| 738 | {
|
---|
| 739 | format = "Logic";
|
---|
| 740 | name = "i_waitrequest";
|
---|
| 741 | radix = "hexadecimal";
|
---|
| 742 | }
|
---|
| 743 | SIGNAL aad
|
---|
| 744 | {
|
---|
| 745 | format = "Logic";
|
---|
| 746 | name = "i_address";
|
---|
| 747 | radix = "hexadecimal";
|
---|
| 748 | }
|
---|
| 749 | SIGNAL aae
|
---|
| 750 | {
|
---|
| 751 | format = "Logic";
|
---|
| 752 | name = "i_read";
|
---|
| 753 | radix = "hexadecimal";
|
---|
| 754 | }
|
---|
| 755 | SIGNAL aaf
|
---|
| 756 | {
|
---|
| 757 | format = "Logic";
|
---|
| 758 | name = "E_ci_combo_dataa";
|
---|
| 759 | radix = "hexadecimal";
|
---|
| 760 | }
|
---|
| 761 | SIGNAL aag
|
---|
| 762 | {
|
---|
| 763 | format = "Logic";
|
---|
| 764 | name = "E_ci_combo_datab";
|
---|
| 765 | radix = "hexadecimal";
|
---|
| 766 | }
|
---|
| 767 | SIGNAL aah
|
---|
| 768 | {
|
---|
| 769 | format = "Logic";
|
---|
| 770 | name = "E_ci_combo_ipending";
|
---|
| 771 | radix = "hexadecimal";
|
---|
| 772 | }
|
---|
| 773 | SIGNAL aai
|
---|
| 774 | {
|
---|
| 775 | format = "Logic";
|
---|
| 776 | name = "E_ci_combo_status";
|
---|
| 777 | radix = "hexadecimal";
|
---|
| 778 | }
|
---|
| 779 | SIGNAL aaj
|
---|
| 780 | {
|
---|
| 781 | format = "Logic";
|
---|
| 782 | name = "E_ci_combo_estatus";
|
---|
| 783 | radix = "hexadecimal";
|
---|
| 784 | }
|
---|
| 785 | SIGNAL aak
|
---|
| 786 | {
|
---|
| 787 | format = "Logic";
|
---|
| 788 | name = "E_ci_combo_n";
|
---|
| 789 | radix = "hexadecimal";
|
---|
| 790 | }
|
---|
| 791 | SIGNAL aal
|
---|
| 792 | {
|
---|
| 793 | format = "Logic";
|
---|
| 794 | name = "E_ci_combo_a";
|
---|
| 795 | radix = "hexadecimal";
|
---|
| 796 | }
|
---|
| 797 | SIGNAL aam
|
---|
| 798 | {
|
---|
| 799 | format = "Logic";
|
---|
| 800 | name = "E_ci_combo_b";
|
---|
| 801 | radix = "hexadecimal";
|
---|
| 802 | }
|
---|
| 803 | SIGNAL aan
|
---|
| 804 | {
|
---|
| 805 | format = "Logic";
|
---|
| 806 | name = "E_ci_combo_c";
|
---|
| 807 | radix = "hexadecimal";
|
---|
| 808 | }
|
---|
| 809 | SIGNAL aao
|
---|
| 810 | {
|
---|
| 811 | format = "Logic";
|
---|
| 812 | name = "E_ci_combo_readra";
|
---|
| 813 | radix = "hexadecimal";
|
---|
| 814 | }
|
---|
| 815 | SIGNAL aap
|
---|
| 816 | {
|
---|
| 817 | format = "Logic";
|
---|
| 818 | name = "E_ci_combo_readrb";
|
---|
| 819 | radix = "hexadecimal";
|
---|
| 820 | }
|
---|
| 821 | SIGNAL aaq
|
---|
| 822 | {
|
---|
| 823 | format = "Logic";
|
---|
| 824 | name = "E_ci_combo_writerc";
|
---|
| 825 | radix = "hexadecimal";
|
---|
| 826 | }
|
---|
| 827 | SIGNAL aar
|
---|
| 828 | {
|
---|
| 829 | format = "Logic";
|
---|
| 830 | name = "E_ci_combo_result";
|
---|
| 831 | radix = "hexadecimal";
|
---|
| 832 | }
|
---|
| 833 | SIGNAL aas
|
---|
| 834 | {
|
---|
| 835 | format = "Logic";
|
---|
| 836 | name = "clk";
|
---|
| 837 | radix = "hexadecimal";
|
---|
| 838 | }
|
---|
| 839 | SIGNAL aat
|
---|
| 840 | {
|
---|
| 841 | format = "Logic";
|
---|
| 842 | name = "reset_n";
|
---|
| 843 | radix = "hexadecimal";
|
---|
| 844 | }
|
---|
| 845 | SIGNAL aau
|
---|
| 846 | {
|
---|
| 847 | format = "Logic";
|
---|
| 848 | name = "d_readdata";
|
---|
| 849 | radix = "hexadecimal";
|
---|
| 850 | }
|
---|
| 851 | SIGNAL aav
|
---|
| 852 | {
|
---|
| 853 | format = "Logic";
|
---|
| 854 | name = "d_waitrequest";
|
---|
| 855 | radix = "hexadecimal";
|
---|
| 856 | }
|
---|
| 857 | SIGNAL aaw
|
---|
| 858 | {
|
---|
| 859 | format = "Logic";
|
---|
| 860 | name = "d_irq";
|
---|
| 861 | radix = "hexadecimal";
|
---|
| 862 | }
|
---|
| 863 | SIGNAL aax
|
---|
| 864 | {
|
---|
| 865 | format = "Logic";
|
---|
| 866 | name = "d_address";
|
---|
| 867 | radix = "hexadecimal";
|
---|
| 868 | }
|
---|
| 869 | SIGNAL aay
|
---|
| 870 | {
|
---|
| 871 | format = "Logic";
|
---|
| 872 | name = "d_byteenable";
|
---|
| 873 | radix = "hexadecimal";
|
---|
| 874 | }
|
---|
| 875 | SIGNAL aaz
|
---|
| 876 | {
|
---|
| 877 | format = "Logic";
|
---|
| 878 | name = "d_read";
|
---|
| 879 | radix = "hexadecimal";
|
---|
| 880 | }
|
---|
| 881 | SIGNAL aba
|
---|
| 882 | {
|
---|
| 883 | format = "Logic";
|
---|
| 884 | name = "d_write";
|
---|
| 885 | radix = "hexadecimal";
|
---|
| 886 | }
|
---|
| 887 | SIGNAL abb
|
---|
| 888 | {
|
---|
| 889 | format = "Logic";
|
---|
| 890 | name = "d_writedata";
|
---|
| 891 | radix = "hexadecimal";
|
---|
| 892 | }
|
---|
| 893 | SIGNAL abc
|
---|
| 894 | {
|
---|
| 895 | format = "Divider";
|
---|
| 896 | name = "base pipeline";
|
---|
| 897 | radix = "";
|
---|
| 898 | }
|
---|
| 899 | SIGNAL abd
|
---|
| 900 | {
|
---|
| 901 | format = "Logic";
|
---|
| 902 | name = "clk";
|
---|
| 903 | radix = "hexadecimal";
|
---|
| 904 | }
|
---|
| 905 | SIGNAL abe
|
---|
| 906 | {
|
---|
| 907 | format = "Logic";
|
---|
| 908 | name = "reset_n";
|
---|
| 909 | radix = "hexadecimal";
|
---|
| 910 | }
|
---|
| 911 | SIGNAL abf
|
---|
| 912 | {
|
---|
| 913 | format = "Logic";
|
---|
| 914 | name = "M_stall";
|
---|
| 915 | radix = "hexadecimal";
|
---|
| 916 | }
|
---|
| 917 | SIGNAL abg
|
---|
| 918 | {
|
---|
| 919 | format = "Logic";
|
---|
| 920 | name = "F_pcb_nxt";
|
---|
| 921 | radix = "hexadecimal";
|
---|
| 922 | }
|
---|
| 923 | SIGNAL abh
|
---|
| 924 | {
|
---|
| 925 | format = "Logic";
|
---|
| 926 | name = "F_pcb";
|
---|
| 927 | radix = "hexadecimal";
|
---|
| 928 | }
|
---|
| 929 | SIGNAL abi
|
---|
| 930 | {
|
---|
| 931 | format = "Logic";
|
---|
| 932 | name = "D_pcb";
|
---|
| 933 | radix = "hexadecimal";
|
---|
| 934 | }
|
---|
| 935 | SIGNAL abj
|
---|
| 936 | {
|
---|
| 937 | format = "Logic";
|
---|
| 938 | name = "E_pcb";
|
---|
| 939 | radix = "hexadecimal";
|
---|
| 940 | }
|
---|
| 941 | SIGNAL abk
|
---|
| 942 | {
|
---|
| 943 | format = "Logic";
|
---|
| 944 | name = "M_pcb";
|
---|
| 945 | radix = "hexadecimal";
|
---|
| 946 | }
|
---|
| 947 | SIGNAL abl
|
---|
| 948 | {
|
---|
| 949 | format = "Logic";
|
---|
| 950 | name = "W_pcb";
|
---|
| 951 | radix = "hexadecimal";
|
---|
| 952 | }
|
---|
| 953 | SIGNAL abm
|
---|
| 954 | {
|
---|
| 955 | format = "Logic";
|
---|
| 956 | name = "F_vinst";
|
---|
| 957 | radix = "ascii";
|
---|
| 958 | }
|
---|
| 959 | SIGNAL abn
|
---|
| 960 | {
|
---|
| 961 | format = "Logic";
|
---|
| 962 | name = "D_vinst";
|
---|
| 963 | radix = "ascii";
|
---|
| 964 | }
|
---|
| 965 | SIGNAL abo
|
---|
| 966 | {
|
---|
| 967 | format = "Logic";
|
---|
| 968 | name = "E_vinst";
|
---|
| 969 | radix = "ascii";
|
---|
| 970 | }
|
---|
| 971 | SIGNAL abp
|
---|
| 972 | {
|
---|
| 973 | format = "Logic";
|
---|
| 974 | name = "M_vinst";
|
---|
| 975 | radix = "ascii";
|
---|
| 976 | }
|
---|
| 977 | SIGNAL abq
|
---|
| 978 | {
|
---|
| 979 | format = "Logic";
|
---|
| 980 | name = "W_vinst";
|
---|
| 981 | radix = "ascii";
|
---|
| 982 | }
|
---|
| 983 | SIGNAL abr
|
---|
| 984 | {
|
---|
| 985 | format = "Logic";
|
---|
| 986 | name = "F_inst_ram_hit";
|
---|
| 987 | radix = "hexadecimal";
|
---|
| 988 | }
|
---|
| 989 | SIGNAL abs
|
---|
| 990 | {
|
---|
| 991 | format = "Logic";
|
---|
| 992 | name = "F_issue";
|
---|
| 993 | radix = "hexadecimal";
|
---|
| 994 | }
|
---|
| 995 | SIGNAL abt
|
---|
| 996 | {
|
---|
| 997 | format = "Logic";
|
---|
| 998 | name = "F_kill";
|
---|
| 999 | radix = "hexadecimal";
|
---|
| 1000 | }
|
---|
| 1001 | SIGNAL abu
|
---|
| 1002 | {
|
---|
| 1003 | format = "Logic";
|
---|
| 1004 | name = "D_kill";
|
---|
| 1005 | radix = "hexadecimal";
|
---|
| 1006 | }
|
---|
| 1007 | SIGNAL abv
|
---|
| 1008 | {
|
---|
| 1009 | format = "Logic";
|
---|
| 1010 | name = "D_refetch";
|
---|
| 1011 | radix = "hexadecimal";
|
---|
| 1012 | }
|
---|
| 1013 | SIGNAL abw
|
---|
| 1014 | {
|
---|
| 1015 | format = "Logic";
|
---|
| 1016 | name = "D_issue";
|
---|
| 1017 | radix = "hexadecimal";
|
---|
| 1018 | }
|
---|
| 1019 | SIGNAL abx
|
---|
| 1020 | {
|
---|
| 1021 | format = "Logic";
|
---|
| 1022 | name = "D_valid";
|
---|
| 1023 | radix = "hexadecimal";
|
---|
| 1024 | }
|
---|
| 1025 | SIGNAL aby
|
---|
| 1026 | {
|
---|
| 1027 | format = "Logic";
|
---|
| 1028 | name = "E_valid";
|
---|
| 1029 | radix = "hexadecimal";
|
---|
| 1030 | }
|
---|
| 1031 | SIGNAL abz
|
---|
| 1032 | {
|
---|
| 1033 | format = "Logic";
|
---|
| 1034 | name = "M_valid";
|
---|
| 1035 | radix = "hexadecimal";
|
---|
| 1036 | }
|
---|
| 1037 | SIGNAL aca
|
---|
| 1038 | {
|
---|
| 1039 | format = "Logic";
|
---|
| 1040 | name = "W_valid";
|
---|
| 1041 | radix = "hexadecimal";
|
---|
| 1042 | }
|
---|
| 1043 | SIGNAL acb
|
---|
| 1044 | {
|
---|
| 1045 | format = "Logic";
|
---|
| 1046 | name = "W_wr_dst_reg";
|
---|
| 1047 | radix = "hexadecimal";
|
---|
| 1048 | }
|
---|
| 1049 | SIGNAL acc
|
---|
| 1050 | {
|
---|
| 1051 | format = "Logic";
|
---|
| 1052 | name = "W_dst_regnum";
|
---|
| 1053 | radix = "hexadecimal";
|
---|
| 1054 | }
|
---|
| 1055 | SIGNAL acd
|
---|
| 1056 | {
|
---|
| 1057 | format = "Logic";
|
---|
| 1058 | name = "W_wr_data";
|
---|
| 1059 | radix = "hexadecimal";
|
---|
| 1060 | }
|
---|
| 1061 | SIGNAL ace
|
---|
| 1062 | {
|
---|
| 1063 | format = "Logic";
|
---|
| 1064 | name = "F_en";
|
---|
| 1065 | radix = "hexadecimal";
|
---|
| 1066 | }
|
---|
| 1067 | SIGNAL acf
|
---|
| 1068 | {
|
---|
| 1069 | format = "Logic";
|
---|
| 1070 | name = "D_en";
|
---|
| 1071 | radix = "hexadecimal";
|
---|
| 1072 | }
|
---|
| 1073 | SIGNAL acg
|
---|
| 1074 | {
|
---|
| 1075 | format = "Logic";
|
---|
| 1076 | name = "E_en";
|
---|
| 1077 | radix = "hexadecimal";
|
---|
| 1078 | }
|
---|
| 1079 | SIGNAL ach
|
---|
| 1080 | {
|
---|
| 1081 | format = "Logic";
|
---|
| 1082 | name = "M_en";
|
---|
| 1083 | radix = "hexadecimal";
|
---|
| 1084 | }
|
---|
| 1085 | SIGNAL aci
|
---|
| 1086 | {
|
---|
| 1087 | format = "Logic";
|
---|
| 1088 | name = "F_iw";
|
---|
| 1089 | radix = "hexadecimal";
|
---|
| 1090 | }
|
---|
| 1091 | SIGNAL acj
|
---|
| 1092 | {
|
---|
| 1093 | format = "Logic";
|
---|
| 1094 | name = "D_iw";
|
---|
| 1095 | radix = "hexadecimal";
|
---|
| 1096 | }
|
---|
| 1097 | SIGNAL ack
|
---|
| 1098 | {
|
---|
| 1099 | format = "Logic";
|
---|
| 1100 | name = "E_iw";
|
---|
| 1101 | radix = "hexadecimal";
|
---|
| 1102 | }
|
---|
| 1103 | SIGNAL acl
|
---|
| 1104 | {
|
---|
| 1105 | format = "Logic";
|
---|
| 1106 | name = "E_valid_prior_to_hbreak";
|
---|
| 1107 | radix = "hexadecimal";
|
---|
| 1108 | }
|
---|
| 1109 | SIGNAL acm
|
---|
| 1110 | {
|
---|
| 1111 | format = "Logic";
|
---|
| 1112 | name = "M_pipe_flush_nxt";
|
---|
| 1113 | radix = "hexadecimal";
|
---|
| 1114 | }
|
---|
| 1115 | SIGNAL acn
|
---|
| 1116 | {
|
---|
| 1117 | format = "Logic";
|
---|
| 1118 | name = "M_pipe_flush_baddr_nxt";
|
---|
| 1119 | radix = "hexadecimal";
|
---|
| 1120 | }
|
---|
| 1121 | SIGNAL aco
|
---|
| 1122 | {
|
---|
| 1123 | format = "Logic";
|
---|
| 1124 | name = "M_status_reg_pie";
|
---|
| 1125 | radix = "hexadecimal";
|
---|
| 1126 | }
|
---|
| 1127 | SIGNAL acp
|
---|
| 1128 | {
|
---|
| 1129 | format = "Logic";
|
---|
| 1130 | name = "M_ienable_reg";
|
---|
| 1131 | radix = "hexadecimal";
|
---|
| 1132 | }
|
---|
| 1133 | SIGNAL acq
|
---|
| 1134 | {
|
---|
| 1135 | format = "Logic";
|
---|
| 1136 | name = "intr_req";
|
---|
| 1137 | radix = "hexadecimal";
|
---|
| 1138 | }
|
---|
| 1139 | SIGNAL acr
|
---|
| 1140 | {
|
---|
| 1141 | format = "Divider";
|
---|
| 1142 | name = "combinatorial_custom_instruction";
|
---|
| 1143 | radix = "";
|
---|
| 1144 | }
|
---|
| 1145 | SIGNAL acs
|
---|
| 1146 | {
|
---|
| 1147 | format = "Logic";
|
---|
| 1148 | name = "E_ctrl_custom_combo";
|
---|
| 1149 | radix = "hexadecimal";
|
---|
| 1150 | }
|
---|
| 1151 | SIGNAL act
|
---|
| 1152 | {
|
---|
| 1153 | format = "Logic";
|
---|
| 1154 | name = "E_ci_combo_dataa";
|
---|
| 1155 | radix = "hexadecimal";
|
---|
| 1156 | }
|
---|
| 1157 | SIGNAL acu
|
---|
| 1158 | {
|
---|
| 1159 | format = "Logic";
|
---|
| 1160 | name = "E_ci_combo_datab";
|
---|
| 1161 | radix = "hexadecimal";
|
---|
| 1162 | }
|
---|
| 1163 | SIGNAL acv
|
---|
| 1164 | {
|
---|
| 1165 | format = "Logic";
|
---|
| 1166 | name = "E_ci_combo_ipending";
|
---|
| 1167 | radix = "hexadecimal";
|
---|
| 1168 | }
|
---|
| 1169 | SIGNAL acw
|
---|
| 1170 | {
|
---|
| 1171 | format = "Logic";
|
---|
| 1172 | name = "E_ci_combo_status";
|
---|
| 1173 | radix = "hexadecimal";
|
---|
| 1174 | }
|
---|
| 1175 | SIGNAL acx
|
---|
| 1176 | {
|
---|
| 1177 | format = "Logic";
|
---|
| 1178 | name = "E_ci_combo_estatus";
|
---|
| 1179 | radix = "hexadecimal";
|
---|
| 1180 | }
|
---|
| 1181 | SIGNAL acy
|
---|
| 1182 | {
|
---|
| 1183 | format = "Logic";
|
---|
| 1184 | name = "E_ci_combo_n";
|
---|
| 1185 | radix = "hexadecimal";
|
---|
| 1186 | }
|
---|
| 1187 | SIGNAL acz
|
---|
| 1188 | {
|
---|
| 1189 | format = "Logic";
|
---|
| 1190 | name = "E_ci_combo_readra";
|
---|
| 1191 | radix = "hexadecimal";
|
---|
| 1192 | }
|
---|
| 1193 | SIGNAL ada
|
---|
| 1194 | {
|
---|
| 1195 | format = "Logic";
|
---|
| 1196 | name = "E_ci_combo_readrb";
|
---|
| 1197 | radix = "hexadecimal";
|
---|
| 1198 | }
|
---|
| 1199 | SIGNAL adb
|
---|
| 1200 | {
|
---|
| 1201 | format = "Logic";
|
---|
| 1202 | name = "E_ci_combo_writerc";
|
---|
| 1203 | radix = "hexadecimal";
|
---|
| 1204 | }
|
---|
| 1205 | SIGNAL adc
|
---|
| 1206 | {
|
---|
| 1207 | format = "Logic";
|
---|
| 1208 | name = "E_ci_combo_result";
|
---|
| 1209 | radix = "hexadecimal";
|
---|
| 1210 | }
|
---|
| 1211 | }
|
---|
| 1212 | }
|
---|
| 1213 | MASTER custom_instruction_master
|
---|
| 1214 | {
|
---|
| 1215 | PORT_WIRING
|
---|
| 1216 | {
|
---|
| 1217 | PORT E_ci_combo_a
|
---|
| 1218 | {
|
---|
| 1219 | Is_Enabled = "1";
|
---|
| 1220 | direction = "output";
|
---|
| 1221 | type = "combo_a";
|
---|
| 1222 | width = "5";
|
---|
| 1223 | }
|
---|
| 1224 | PORT E_ci_combo_b
|
---|
| 1225 | {
|
---|
| 1226 | Is_Enabled = "1";
|
---|
| 1227 | direction = "output";
|
---|
| 1228 | type = "combo_b";
|
---|
| 1229 | width = "5";
|
---|
| 1230 | }
|
---|
| 1231 | PORT E_ci_combo_c
|
---|
| 1232 | {
|
---|
| 1233 | Is_Enabled = "1";
|
---|
| 1234 | direction = "output";
|
---|
| 1235 | type = "combo_c";
|
---|
| 1236 | width = "5";
|
---|
| 1237 | }
|
---|
| 1238 | PORT E_ci_combo_dataa
|
---|
| 1239 | {
|
---|
| 1240 | Is_Enabled = "1";
|
---|
| 1241 | direction = "output";
|
---|
| 1242 | type = "combo_dataa";
|
---|
| 1243 | width = "32";
|
---|
| 1244 | }
|
---|
| 1245 | PORT E_ci_combo_datab
|
---|
| 1246 | {
|
---|
| 1247 | Is_Enabled = "1";
|
---|
| 1248 | direction = "output";
|
---|
| 1249 | type = "combo_datab";
|
---|
| 1250 | width = "32";
|
---|
| 1251 | }
|
---|
| 1252 | PORT E_ci_combo_estatus
|
---|
| 1253 | {
|
---|
| 1254 | Is_Enabled = "1";
|
---|
| 1255 | direction = "output";
|
---|
| 1256 | type = "combo_estatus";
|
---|
| 1257 | width = "1";
|
---|
| 1258 | }
|
---|
| 1259 | PORT E_ci_combo_ipending
|
---|
| 1260 | {
|
---|
| 1261 | Is_Enabled = "1";
|
---|
| 1262 | direction = "output";
|
---|
| 1263 | type = "combo_ipending";
|
---|
| 1264 | width = "32";
|
---|
| 1265 | }
|
---|
| 1266 | PORT E_ci_combo_n
|
---|
| 1267 | {
|
---|
| 1268 | Is_Enabled = "1";
|
---|
| 1269 | direction = "output";
|
---|
| 1270 | type = "combo_n";
|
---|
| 1271 | width = "8";
|
---|
| 1272 | }
|
---|
| 1273 | PORT E_ci_combo_readra
|
---|
| 1274 | {
|
---|
| 1275 | Is_Enabled = "1";
|
---|
| 1276 | direction = "output";
|
---|
| 1277 | type = "combo_readra";
|
---|
| 1278 | width = "1";
|
---|
| 1279 | }
|
---|
| 1280 | PORT E_ci_combo_readrb
|
---|
| 1281 | {
|
---|
| 1282 | Is_Enabled = "1";
|
---|
| 1283 | direction = "output";
|
---|
| 1284 | type = "combo_readrb";
|
---|
| 1285 | width = "1";
|
---|
| 1286 | }
|
---|
| 1287 | PORT E_ci_combo_result
|
---|
| 1288 | {
|
---|
| 1289 | Is_Enabled = "1";
|
---|
| 1290 | direction = "input";
|
---|
| 1291 | type = "combo_result";
|
---|
| 1292 | width = "32";
|
---|
| 1293 | }
|
---|
| 1294 | PORT E_ci_combo_status
|
---|
| 1295 | {
|
---|
| 1296 | Is_Enabled = "1";
|
---|
| 1297 | direction = "output";
|
---|
| 1298 | type = "combo_status";
|
---|
| 1299 | width = "1";
|
---|
| 1300 | }
|
---|
| 1301 | PORT E_ci_combo_writerc
|
---|
| 1302 | {
|
---|
| 1303 | Is_Enabled = "1";
|
---|
| 1304 | direction = "output";
|
---|
| 1305 | type = "combo_writerc";
|
---|
| 1306 | width = "1";
|
---|
| 1307 | }
|
---|
| 1308 | PORT clk
|
---|
| 1309 | {
|
---|
| 1310 | Is_Enabled = "1";
|
---|
| 1311 | direction = "input";
|
---|
| 1312 | type = "clk";
|
---|
| 1313 | width = "1";
|
---|
| 1314 | }
|
---|
| 1315 | PORT reset_n
|
---|
| 1316 | {
|
---|
| 1317 | Is_Enabled = "1";
|
---|
| 1318 | direction = "input";
|
---|
| 1319 | type = "reset_n";
|
---|
| 1320 | width = "1";
|
---|
| 1321 | }
|
---|
| 1322 | }
|
---|
| 1323 | SYSTEM_BUILDER_INFO
|
---|
| 1324 | {
|
---|
| 1325 | Bus_Type = "nios_custom_instruction";
|
---|
| 1326 | Data_Width = "32";
|
---|
| 1327 | Address_Width = "8";
|
---|
| 1328 | Max_Address_Width = "8";
|
---|
| 1329 | Base_Address = "N/A";
|
---|
| 1330 | Is_Visible = "0";
|
---|
| 1331 | Is_Custom_Instruction = "0";
|
---|
| 1332 | Is_Enabled = "1";
|
---|
| 1333 | }
|
---|
| 1334 | }
|
---|
| 1335 | MASTER data_master2
|
---|
| 1336 | {
|
---|
| 1337 | PORT_WIRING
|
---|
| 1338 | {
|
---|
| 1339 | }
|
---|
| 1340 | SYSTEM_BUILDER_INFO
|
---|
| 1341 | {
|
---|
| 1342 | Register_Incoming_Signals = "1";
|
---|
| 1343 | Bus_Type = "avalon";
|
---|
| 1344 | Data_Width = "32";
|
---|
| 1345 | Max_Address_Width = "31";
|
---|
| 1346 | Address_Width = "8";
|
---|
| 1347 | Is_Data_Master = "1";
|
---|
| 1348 | Has_IRQ = "0";
|
---|
| 1349 | Is_Enabled = "0";
|
---|
| 1350 | Address_Group = "0";
|
---|
| 1351 | Is_Readable = "1";
|
---|
| 1352 | Is_Writeable = "1";
|
---|
| 1353 | Is_Big_Endian = "0";
|
---|
| 1354 | }
|
---|
| 1355 | }
|
---|
| 1356 | MASTER data_channel_master_0
|
---|
| 1357 | {
|
---|
| 1358 | PORT_WIRING
|
---|
| 1359 | {
|
---|
| 1360 | }
|
---|
| 1361 | SYSTEM_BUILDER_INFO
|
---|
| 1362 | {
|
---|
| 1363 | Register_Incoming_Signals = "0";
|
---|
| 1364 | Bus_Type = "avalon";
|
---|
| 1365 | Data_Width = "32";
|
---|
| 1366 | Max_Address_Width = "31";
|
---|
| 1367 | Address_Width = "8";
|
---|
| 1368 | Is_Data_Master = "1";
|
---|
| 1369 | Has_IRQ = "0";
|
---|
| 1370 | Is_Enabled = "0";
|
---|
| 1371 | Connection_Limit = "1";
|
---|
| 1372 | Is_Channel = "1";
|
---|
| 1373 | }
|
---|
| 1374 | }
|
---|
| 1375 | MASTER data_channel_master_1
|
---|
| 1376 | {
|
---|
| 1377 | PORT_WIRING
|
---|
| 1378 | {
|
---|
| 1379 | }
|
---|
| 1380 | SYSTEM_BUILDER_INFO
|
---|
| 1381 | {
|
---|
| 1382 | Register_Incoming_Signals = "0";
|
---|
| 1383 | Bus_Type = "avalon";
|
---|
| 1384 | Data_Width = "32";
|
---|
| 1385 | Max_Address_Width = "31";
|
---|
| 1386 | Address_Width = "8";
|
---|
| 1387 | Is_Data_Master = "1";
|
---|
| 1388 | Has_IRQ = "0";
|
---|
| 1389 | Is_Enabled = "0";
|
---|
| 1390 | Connection_Limit = "1";
|
---|
| 1391 | Is_Channel = "1";
|
---|
| 1392 | }
|
---|
| 1393 | }
|
---|
| 1394 | MASTER data_channel_master_2
|
---|
| 1395 | {
|
---|
| 1396 | PORT_WIRING
|
---|
| 1397 | {
|
---|
| 1398 | }
|
---|
| 1399 | SYSTEM_BUILDER_INFO
|
---|
| 1400 | {
|
---|
| 1401 | Register_Incoming_Signals = "0";
|
---|
| 1402 | Bus_Type = "avalon";
|
---|
| 1403 | Data_Width = "32";
|
---|
| 1404 | Max_Address_Width = "31";
|
---|
| 1405 | Address_Width = "8";
|
---|
| 1406 | Is_Data_Master = "1";
|
---|
| 1407 | Has_IRQ = "0";
|
---|
| 1408 | Is_Enabled = "0";
|
---|
| 1409 | Connection_Limit = "1";
|
---|
| 1410 | Is_Channel = "1";
|
---|
| 1411 | }
|
---|
| 1412 | }
|
---|
| 1413 | MASTER data_channel_master_3
|
---|
| 1414 | {
|
---|
| 1415 | PORT_WIRING
|
---|
| 1416 | {
|
---|
| 1417 | }
|
---|
| 1418 | SYSTEM_BUILDER_INFO
|
---|
| 1419 | {
|
---|
| 1420 | Register_Incoming_Signals = "0";
|
---|
| 1421 | Bus_Type = "avalon";
|
---|
| 1422 | Data_Width = "32";
|
---|
| 1423 | Max_Address_Width = "31";
|
---|
| 1424 | Address_Width = "8";
|
---|
| 1425 | Is_Data_Master = "1";
|
---|
| 1426 | Has_IRQ = "0";
|
---|
| 1427 | Is_Enabled = "0";
|
---|
| 1428 | Connection_Limit = "1";
|
---|
| 1429 | Is_Channel = "1";
|
---|
| 1430 | }
|
---|
| 1431 | }
|
---|
| 1432 | MASTER instruction_channel_master_0
|
---|
| 1433 | {
|
---|
| 1434 | PORT_WIRING
|
---|
| 1435 | {
|
---|
| 1436 | }
|
---|
| 1437 | SYSTEM_BUILDER_INFO
|
---|
| 1438 | {
|
---|
| 1439 | Register_Incoming_Signals = "0";
|
---|
| 1440 | Bus_Type = "avalon";
|
---|
| 1441 | Data_Width = "32";
|
---|
| 1442 | Max_Address_Width = "31";
|
---|
| 1443 | Address_Width = "8";
|
---|
| 1444 | Is_Instruction_Master = "1";
|
---|
| 1445 | Has_IRQ = "0";
|
---|
| 1446 | Is_Enabled = "0";
|
---|
| 1447 | Connection_Limit = "1";
|
---|
| 1448 | Is_Channel = "1";
|
---|
| 1449 | }
|
---|
| 1450 | }
|
---|
| 1451 | MASTER tightly_coupled_data_master_0
|
---|
| 1452 | {
|
---|
| 1453 | PORT_WIRING
|
---|
| 1454 | {
|
---|
| 1455 | }
|
---|
| 1456 | SYSTEM_BUILDER_INFO
|
---|
| 1457 | {
|
---|
| 1458 | Register_Incoming_Signals = "0";
|
---|
| 1459 | Bus_Type = "avalon";
|
---|
| 1460 | Data_Width = "32";
|
---|
| 1461 | Max_Address_Width = "31";
|
---|
| 1462 | Address_Width = "8";
|
---|
| 1463 | Is_Data_Master = "1";
|
---|
| 1464 | Has_IRQ = "0";
|
---|
| 1465 | Is_Enabled = "0";
|
---|
| 1466 | Connection_Limit = "1";
|
---|
| 1467 | Is_Channel = "1";
|
---|
| 1468 | Address_Group = "0";
|
---|
| 1469 | Is_Readable = "1";
|
---|
| 1470 | Is_Writeable = "1";
|
---|
| 1471 | Is_Big_Endian = "0";
|
---|
| 1472 | }
|
---|
| 1473 | }
|
---|
| 1474 | MASTER tightly_coupled_data_master_1
|
---|
| 1475 | {
|
---|
| 1476 | PORT_WIRING
|
---|
| 1477 | {
|
---|
| 1478 | }
|
---|
| 1479 | SYSTEM_BUILDER_INFO
|
---|
| 1480 | {
|
---|
| 1481 | Register_Incoming_Signals = "0";
|
---|
| 1482 | Bus_Type = "avalon";
|
---|
| 1483 | Data_Width = "32";
|
---|
| 1484 | Max_Address_Width = "31";
|
---|
| 1485 | Address_Width = "8";
|
---|
| 1486 | Is_Data_Master = "1";
|
---|
| 1487 | Has_IRQ = "0";
|
---|
| 1488 | Is_Enabled = "0";
|
---|
| 1489 | Connection_Limit = "1";
|
---|
| 1490 | Is_Channel = "1";
|
---|
| 1491 | Address_Group = "0";
|
---|
| 1492 | Is_Readable = "1";
|
---|
| 1493 | Is_Writeable = "1";
|
---|
| 1494 | Is_Big_Endian = "0";
|
---|
| 1495 | }
|
---|
| 1496 | }
|
---|
| 1497 | MASTER tightly_coupled_data_master_2
|
---|
| 1498 | {
|
---|
| 1499 | PORT_WIRING
|
---|
| 1500 | {
|
---|
| 1501 | }
|
---|
| 1502 | SYSTEM_BUILDER_INFO
|
---|
| 1503 | {
|
---|
| 1504 | Register_Incoming_Signals = "0";
|
---|
| 1505 | Bus_Type = "avalon";
|
---|
| 1506 | Data_Width = "32";
|
---|
| 1507 | Max_Address_Width = "31";
|
---|
| 1508 | Address_Width = "8";
|
---|
| 1509 | Is_Data_Master = "1";
|
---|
| 1510 | Has_IRQ = "0";
|
---|
| 1511 | Is_Enabled = "0";
|
---|
| 1512 | Connection_Limit = "1";
|
---|
| 1513 | Is_Channel = "1";
|
---|
| 1514 | Address_Group = "0";
|
---|
| 1515 | Is_Readable = "1";
|
---|
| 1516 | Is_Writeable = "1";
|
---|
| 1517 | Is_Big_Endian = "0";
|
---|
| 1518 | }
|
---|
| 1519 | }
|
---|
| 1520 | MASTER tightly_coupled_data_master_3
|
---|
| 1521 | {
|
---|
| 1522 | PORT_WIRING
|
---|
| 1523 | {
|
---|
| 1524 | }
|
---|
| 1525 | SYSTEM_BUILDER_INFO
|
---|
| 1526 | {
|
---|
| 1527 | Register_Incoming_Signals = "0";
|
---|
| 1528 | Bus_Type = "avalon";
|
---|
| 1529 | Data_Width = "32";
|
---|
| 1530 | Max_Address_Width = "31";
|
---|
| 1531 | Address_Width = "8";
|
---|
| 1532 | Is_Data_Master = "1";
|
---|
| 1533 | Has_IRQ = "0";
|
---|
| 1534 | Is_Enabled = "0";
|
---|
| 1535 | Connection_Limit = "1";
|
---|
| 1536 | Is_Channel = "1";
|
---|
| 1537 | Address_Group = "0";
|
---|
| 1538 | Is_Readable = "1";
|
---|
| 1539 | Is_Writeable = "1";
|
---|
| 1540 | Is_Big_Endian = "0";
|
---|
| 1541 | }
|
---|
| 1542 | }
|
---|
| 1543 | MASTER tightly_coupled_instruction_master_0
|
---|
| 1544 | {
|
---|
| 1545 | PORT_WIRING
|
---|
| 1546 | {
|
---|
| 1547 | }
|
---|
| 1548 | SYSTEM_BUILDER_INFO
|
---|
| 1549 | {
|
---|
| 1550 | Register_Incoming_Signals = "0";
|
---|
| 1551 | Bus_Type = "avalon";
|
---|
| 1552 | Data_Width = "32";
|
---|
| 1553 | Max_Address_Width = "31";
|
---|
| 1554 | Address_Width = "8";
|
---|
| 1555 | Is_Instruction_Master = "1";
|
---|
| 1556 | Has_IRQ = "0";
|
---|
| 1557 | Is_Enabled = "0";
|
---|
| 1558 | Connection_Limit = "1";
|
---|
| 1559 | Is_Channel = "1";
|
---|
| 1560 | Is_Big_Endian = "0";
|
---|
| 1561 | }
|
---|
| 1562 | }
|
---|
| 1563 | MASTER tightly_coupled_instruction_master_1
|
---|
| 1564 | {
|
---|
| 1565 | PORT_WIRING
|
---|
| 1566 | {
|
---|
| 1567 | }
|
---|
| 1568 | SYSTEM_BUILDER_INFO
|
---|
| 1569 | {
|
---|
| 1570 | Register_Incoming_Signals = "0";
|
---|
| 1571 | Bus_Type = "avalon";
|
---|
| 1572 | Data_Width = "32";
|
---|
| 1573 | Max_Address_Width = "31";
|
---|
| 1574 | Address_Width = "8";
|
---|
| 1575 | Address_Group = "0";
|
---|
| 1576 | Is_Instruction_Master = "1";
|
---|
| 1577 | Is_Readable = "1";
|
---|
| 1578 | Is_Writeable = "0";
|
---|
| 1579 | Has_IRQ = "0";
|
---|
| 1580 | Is_Enabled = "0";
|
---|
| 1581 | Connection_Limit = "1";
|
---|
| 1582 | Is_Channel = "1";
|
---|
| 1583 | Is_Big_Endian = "0";
|
---|
| 1584 | }
|
---|
| 1585 | }
|
---|
| 1586 | MASTER tightly_coupled_instruction_master_2
|
---|
| 1587 | {
|
---|
| 1588 | PORT_WIRING
|
---|
| 1589 | {
|
---|
| 1590 | }
|
---|
| 1591 | SYSTEM_BUILDER_INFO
|
---|
| 1592 | {
|
---|
| 1593 | Register_Incoming_Signals = "0";
|
---|
| 1594 | Bus_Type = "avalon";
|
---|
| 1595 | Data_Width = "32";
|
---|
| 1596 | Max_Address_Width = "31";
|
---|
| 1597 | Address_Width = "8";
|
---|
| 1598 | Address_Group = "0";
|
---|
| 1599 | Is_Instruction_Master = "1";
|
---|
| 1600 | Is_Readable = "1";
|
---|
| 1601 | Is_Writeable = "0";
|
---|
| 1602 | Has_IRQ = "0";
|
---|
| 1603 | Is_Enabled = "0";
|
---|
| 1604 | Connection_Limit = "1";
|
---|
| 1605 | Is_Channel = "1";
|
---|
| 1606 | Is_Big_Endian = "0";
|
---|
| 1607 | }
|
---|
| 1608 | }
|
---|
| 1609 | MASTER tightly_coupled_instruction_master_3
|
---|
| 1610 | {
|
---|
| 1611 | PORT_WIRING
|
---|
| 1612 | {
|
---|
| 1613 | }
|
---|
| 1614 | SYSTEM_BUILDER_INFO
|
---|
| 1615 | {
|
---|
| 1616 | Register_Incoming_Signals = "0";
|
---|
| 1617 | Bus_Type = "avalon";
|
---|
| 1618 | Data_Width = "32";
|
---|
| 1619 | Max_Address_Width = "31";
|
---|
| 1620 | Address_Width = "8";
|
---|
| 1621 | Address_Group = "0";
|
---|
| 1622 | Is_Instruction_Master = "1";
|
---|
| 1623 | Is_Readable = "1";
|
---|
| 1624 | Is_Writeable = "0";
|
---|
| 1625 | Has_IRQ = "0";
|
---|
| 1626 | Is_Enabled = "0";
|
---|
| 1627 | Connection_Limit = "1";
|
---|
| 1628 | Is_Channel = "1";
|
---|
| 1629 | Is_Big_Endian = "0";
|
---|
| 1630 | }
|
---|
| 1631 | }
|
---|
| 1632 | }
|
---|
| 1633 | MODULE button_pio
|
---|
| 1634 | {
|
---|
| 1635 | class = "altera_avalon_pio";
|
---|
| 1636 | class_version = "6.05";
|
---|
| 1637 | HDL_INFO
|
---|
| 1638 | {
|
---|
| 1639 | Simulation_HDL_Files = "";
|
---|
| 1640 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/button_pio.vhd";
|
---|
| 1641 | Precompiled_Simulation_Library_Files = "";
|
---|
| 1642 | Synthesis_Only_Files = "";
|
---|
| 1643 | }
|
---|
| 1644 | PORT_WIRING
|
---|
| 1645 | {
|
---|
| 1646 | PORT in_port
|
---|
| 1647 | {
|
---|
| 1648 | direction = "input";
|
---|
| 1649 | width = "4";
|
---|
| 1650 | test_bench_value = "15";
|
---|
| 1651 | Is_Enabled = "1";
|
---|
| 1652 | }
|
---|
| 1653 | PORT out_port
|
---|
| 1654 | {
|
---|
| 1655 | direction = "output";
|
---|
| 1656 | Is_Enabled = "0";
|
---|
| 1657 | width = "4";
|
---|
| 1658 | }
|
---|
| 1659 | PORT bidir_port
|
---|
| 1660 | {
|
---|
| 1661 | direction = "inout";
|
---|
| 1662 | Is_Enabled = "0";
|
---|
| 1663 | width = "4";
|
---|
| 1664 | }
|
---|
| 1665 | }
|
---|
| 1666 | SLAVE s1
|
---|
| 1667 | {
|
---|
| 1668 | PORT_WIRING
|
---|
| 1669 | {
|
---|
| 1670 | PORT address
|
---|
| 1671 | {
|
---|
| 1672 | direction = "input";
|
---|
| 1673 | type = "address";
|
---|
| 1674 | width = "2";
|
---|
| 1675 | Is_Enabled = "1";
|
---|
| 1676 | }
|
---|
| 1677 | PORT chipselect
|
---|
| 1678 | {
|
---|
| 1679 | direction = "input";
|
---|
| 1680 | type = "chipselect";
|
---|
| 1681 | width = "1";
|
---|
| 1682 | Is_Enabled = "1";
|
---|
| 1683 | }
|
---|
| 1684 | PORT clk
|
---|
| 1685 | {
|
---|
| 1686 | direction = "input";
|
---|
| 1687 | type = "clk";
|
---|
| 1688 | width = "1";
|
---|
| 1689 | Is_Enabled = "1";
|
---|
| 1690 | }
|
---|
| 1691 | PORT irq
|
---|
| 1692 | {
|
---|
| 1693 | direction = "output";
|
---|
| 1694 | type = "irq";
|
---|
| 1695 | width = "1";
|
---|
| 1696 | Is_Enabled = "1";
|
---|
| 1697 | }
|
---|
| 1698 | PORT readdata
|
---|
| 1699 | {
|
---|
| 1700 | direction = "output";
|
---|
| 1701 | type = "readdata";
|
---|
| 1702 | width = "4";
|
---|
| 1703 | Is_Enabled = "1";
|
---|
| 1704 | }
|
---|
| 1705 | PORT reset_n
|
---|
| 1706 | {
|
---|
| 1707 | direction = "input";
|
---|
| 1708 | type = "reset_n";
|
---|
| 1709 | width = "1";
|
---|
| 1710 | Is_Enabled = "1";
|
---|
| 1711 | }
|
---|
| 1712 | PORT write_n
|
---|
| 1713 | {
|
---|
| 1714 | direction = "input";
|
---|
| 1715 | type = "write_n";
|
---|
| 1716 | width = "1";
|
---|
| 1717 | Is_Enabled = "1";
|
---|
| 1718 | }
|
---|
| 1719 | PORT writedata
|
---|
| 1720 | {
|
---|
| 1721 | direction = "input";
|
---|
| 1722 | type = "writedata";
|
---|
| 1723 | width = "4";
|
---|
| 1724 | Is_Enabled = "1";
|
---|
| 1725 | }
|
---|
| 1726 | }
|
---|
| 1727 | SYSTEM_BUILDER_INFO
|
---|
| 1728 | {
|
---|
| 1729 | Bus_Type = "avalon";
|
---|
| 1730 | Has_IRQ = "1";
|
---|
| 1731 | Address_Width = "2";
|
---|
| 1732 | Data_Width = "4";
|
---|
| 1733 | Base_Address = "0x08010830";
|
---|
| 1734 | Address_Alignment = "native";
|
---|
| 1735 | Read_Wait_States = "1";
|
---|
| 1736 | Write_Wait_States = "0";
|
---|
| 1737 | MASTERED_BY cpu/data_master
|
---|
| 1738 | {
|
---|
| 1739 | priority = "1";
|
---|
| 1740 | }
|
---|
| 1741 | IRQ_MASTER cpu/data_master
|
---|
| 1742 | {
|
---|
| 1743 | IRQ_Number = "5";
|
---|
| 1744 | }
|
---|
| 1745 | Address_Group = "0";
|
---|
| 1746 | }
|
---|
| 1747 | }
|
---|
| 1748 | SYSTEM_BUILDER_INFO
|
---|
| 1749 | {
|
---|
| 1750 | Date_Modified = "";
|
---|
| 1751 | Is_Enabled = "1";
|
---|
| 1752 | Instantiate_In_System_Module = "1";
|
---|
| 1753 | View
|
---|
| 1754 | {
|
---|
| 1755 | Settings_Summary = " 4-bit PIO using <br>
|
---|
| 1756 |
|
---|
| 1757 | input pins with edge type ANY and interrupt source EDGE
|
---|
| 1758 | ";
|
---|
| 1759 | MESSAGES
|
---|
| 1760 | {
|
---|
| 1761 | }
|
---|
| 1762 | Is_Collapsed = "1";
|
---|
| 1763 | }
|
---|
| 1764 | Wire_Test_Bench_Values = "1";
|
---|
| 1765 | Clock_Source = "clk";
|
---|
| 1766 | Top_Level_Ports_Are_Enumerated = "1";
|
---|
| 1767 | }
|
---|
| 1768 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 1769 | {
|
---|
| 1770 | has_tri = "0";
|
---|
| 1771 | has_out = "0";
|
---|
| 1772 | has_in = "1";
|
---|
| 1773 | capture = "1";
|
---|
| 1774 | edge_type = "ANY";
|
---|
| 1775 | irq_type = "EDGE";
|
---|
| 1776 | Do_Test_Bench_Wiring = "1";
|
---|
| 1777 | Driven_Sim_Value = "0x000F";
|
---|
| 1778 | }
|
---|
| 1779 | }
|
---|
| 1780 | MODULE ext_flash
|
---|
| 1781 | {
|
---|
| 1782 | class = "altera_avalon_cfi_flash";
|
---|
| 1783 | class_version = "6.05";
|
---|
| 1784 | iss_model_name = "altera_avalon_flash";
|
---|
| 1785 | HDL_INFO
|
---|
| 1786 | {
|
---|
| 1787 | }
|
---|
| 1788 | SLAVE s1
|
---|
| 1789 | {
|
---|
| 1790 | PORT_WIRING
|
---|
| 1791 | {
|
---|
| 1792 | PORT data
|
---|
| 1793 | {
|
---|
| 1794 | width = "8";
|
---|
| 1795 | is_shared = "1";
|
---|
| 1796 | direction = "inout";
|
---|
| 1797 | type = "data";
|
---|
| 1798 | }
|
---|
| 1799 | PORT address
|
---|
| 1800 | {
|
---|
| 1801 | width = "24";
|
---|
| 1802 | is_shared = "1";
|
---|
| 1803 | direction = "input";
|
---|
| 1804 | type = "address";
|
---|
| 1805 | }
|
---|
| 1806 | PORT read_n
|
---|
| 1807 | {
|
---|
| 1808 | width = "1";
|
---|
| 1809 | is_shared = "1";
|
---|
| 1810 | direction = "input";
|
---|
| 1811 | type = "read_n";
|
---|
| 1812 | }
|
---|
| 1813 | PORT write_n
|
---|
| 1814 | {
|
---|
| 1815 | width = "1";
|
---|
| 1816 | is_shared = "0";
|
---|
| 1817 | direction = "input";
|
---|
| 1818 | type = "write_n";
|
---|
| 1819 | }
|
---|
| 1820 | PORT select_n
|
---|
| 1821 | {
|
---|
| 1822 | width = "1";
|
---|
| 1823 | is_shared = "0";
|
---|
| 1824 | direction = "input";
|
---|
| 1825 | type = "chipselect_n";
|
---|
| 1826 | }
|
---|
| 1827 | }
|
---|
| 1828 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 1829 | {
|
---|
| 1830 | class = "altera_avalon_cfi_flash";
|
---|
| 1831 | flash_reference_designator = "U17";
|
---|
| 1832 | Supports_Flash_File_System = "1";
|
---|
| 1833 | }
|
---|
| 1834 | SYSTEM_BUILDER_INFO
|
---|
| 1835 | {
|
---|
| 1836 | Bus_Type = "avalon_tristate";
|
---|
| 1837 | Is_Memory_Device = "1";
|
---|
| 1838 | Address_Alignment = "dynamic";
|
---|
| 1839 | Has_IRQ = "0";
|
---|
| 1840 | Base_Address = "0x00000000";
|
---|
| 1841 | Data_Width = "8";
|
---|
| 1842 | Address_Width = "24";
|
---|
| 1843 | Write_Wait_States = "160ns";
|
---|
| 1844 | Read_Wait_States = "160ns";
|
---|
| 1845 | Setup_Time = "45ns";
|
---|
| 1846 | Hold_Time = "35ns";
|
---|
| 1847 | Is_Base_Locked = "1";
|
---|
| 1848 | Simulation_Num_Lanes = "1";
|
---|
| 1849 | Is_Nonvolatile_Storage = "1";
|
---|
| 1850 | Address_Span = "16777216";
|
---|
| 1851 | IRQ_MASTER cpu/data_master
|
---|
| 1852 | {
|
---|
| 1853 | IRQ_Number = "NC";
|
---|
| 1854 | }
|
---|
| 1855 | Convert_Xs_To_0 = "1";
|
---|
| 1856 | MASTERED_BY ext_flash_bus/tristate_master
|
---|
| 1857 | {
|
---|
| 1858 | priority = "1";
|
---|
| 1859 | }
|
---|
| 1860 | Address_Group = "0";
|
---|
| 1861 | }
|
---|
| 1862 | }
|
---|
| 1863 | SYSTEM_BUILDER_INFO
|
---|
| 1864 | {
|
---|
| 1865 | Is_Enabled = "1";
|
---|
| 1866 | Instantiate_In_System_Module = "0";
|
---|
| 1867 | View
|
---|
| 1868 | {
|
---|
| 1869 | MESSAGES
|
---|
| 1870 | {
|
---|
| 1871 | }
|
---|
| 1872 | Is_Collapsed = "1";
|
---|
| 1873 | }
|
---|
| 1874 | Make_Memory_Model = "1";
|
---|
| 1875 | Clock_Source = "clk";
|
---|
| 1876 | Top_Level_Ports_Are_Enumerated = "1";
|
---|
| 1877 | }
|
---|
| 1878 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 1879 | {
|
---|
| 1880 | Setup_Value = "45";
|
---|
| 1881 | Wait_Value = "160";
|
---|
| 1882 | Hold_Value = "35";
|
---|
| 1883 | Timing_Units = "ns";
|
---|
| 1884 | Unit_Multiplier = "1";
|
---|
| 1885 | Size = "16777216";
|
---|
| 1886 | MAKE
|
---|
| 1887 | {
|
---|
| 1888 | TARGET flashfiles
|
---|
| 1889 | {
|
---|
| 1890 | ext_flash
|
---|
| 1891 | {
|
---|
| 1892 | Command1 = "@echo Post-processing to create $(notdir $@)";
|
---|
| 1893 | Dependency = "$(ELF)";
|
---|
| 1894 | Target_File = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
|
---|
| 1895 | Command2 = "elf2flash --input=$(ELF) --flash=U17 --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER)$(DBL_QUOTE) --outfile=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0xFFFFFF --reset=$(CPU_RESET_ADDRESS) ";
|
---|
| 1896 | }
|
---|
| 1897 | }
|
---|
| 1898 | MACRO
|
---|
| 1899 | {
|
---|
| 1900 | EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(EXT_FLASH_FLASHTARGET_TMP1:0=)";
|
---|
| 1901 | EXT_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
|
---|
| 1902 | }
|
---|
| 1903 | MASTER cpu
|
---|
| 1904 | {
|
---|
| 1905 | MACRO
|
---|
| 1906 | {
|
---|
| 1907 | BOOT_COPIER = "boot_loader_cfi.srec";
|
---|
| 1908 | CPU_CLASS = "altera_nios2";
|
---|
| 1909 | CPU_RESET_ADDRESS = "0x0";
|
---|
| 1910 | }
|
---|
| 1911 | }
|
---|
| 1912 | TARGET delete_placeholder_warning
|
---|
| 1913 | {
|
---|
| 1914 | ext_flash
|
---|
| 1915 | {
|
---|
| 1916 | Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
|
---|
| 1917 | Is_Phony = "1";
|
---|
| 1918 | Target_File = "do_delete_placeholder_warning";
|
---|
| 1919 | }
|
---|
| 1920 | }
|
---|
| 1921 | TARGET sim
|
---|
| 1922 | {
|
---|
| 1923 | ext_flash
|
---|
| 1924 | {
|
---|
| 1925 | Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
|
---|
| 1926 | Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
|
---|
| 1927 | Command3 = "touch $(SIMDIR)/dummy_file";
|
---|
| 1928 | Dependency = "$(ELF)";
|
---|
| 1929 | Target_File = "$(SIMDIR)/dummy_file";
|
---|
| 1930 | }
|
---|
| 1931 | }
|
---|
| 1932 | }
|
---|
| 1933 | contents_info = "";
|
---|
| 1934 | }
|
---|
| 1935 | }
|
---|
| 1936 | MODULE ext_flash_bus
|
---|
| 1937 | {
|
---|
| 1938 | class = "altera_avalon_tri_state_bridge";
|
---|
| 1939 | class_version = "6.05";
|
---|
| 1940 | SLAVE avalon_slave
|
---|
| 1941 | {
|
---|
| 1942 | SYSTEM_BUILDER_INFO
|
---|
| 1943 | {
|
---|
| 1944 | Bus_Type = "avalon";
|
---|
| 1945 | Bridges_To = "tristate_master";
|
---|
| 1946 | Base_Address = "N/A";
|
---|
| 1947 | Has_IRQ = "0";
|
---|
| 1948 | IRQ = "N/A";
|
---|
| 1949 | Register_Outgoing_Signals = "1";
|
---|
| 1950 | Register_Incoming_Signals = "1";
|
---|
| 1951 | MASTERED_BY cpu/instruction_master
|
---|
| 1952 | {
|
---|
| 1953 | priority = "1";
|
---|
| 1954 | }
|
---|
| 1955 | MASTERED_BY cpu/data_master
|
---|
| 1956 | {
|
---|
| 1957 | priority = "1";
|
---|
| 1958 | }
|
---|
| 1959 | IRQ_MASTER cpu/data_master
|
---|
| 1960 | {
|
---|
| 1961 | IRQ_Number = "NC";
|
---|
| 1962 | }
|
---|
| 1963 | Address_Group = "0";
|
---|
| 1964 | }
|
---|
| 1965 | }
|
---|
| 1966 | MASTER tristate_master
|
---|
| 1967 | {
|
---|
| 1968 | SYSTEM_BUILDER_INFO
|
---|
| 1969 | {
|
---|
| 1970 | Bus_Type = "avalon_tristate";
|
---|
| 1971 | Bridges_To = "avalon_slave";
|
---|
| 1972 | }
|
---|
| 1973 | }
|
---|
| 1974 | SYSTEM_BUILDER_INFO
|
---|
| 1975 | {
|
---|
| 1976 | Instantiate_In_System_Module = "1";
|
---|
| 1977 | Is_Enabled = "1";
|
---|
| 1978 | Is_Bridge = "1";
|
---|
| 1979 | View
|
---|
| 1980 | {
|
---|
| 1981 | MESSAGES
|
---|
| 1982 | {
|
---|
| 1983 | }
|
---|
| 1984 | Is_Collapsed = "0";
|
---|
| 1985 | }
|
---|
| 1986 | Clock_Source = "clk";
|
---|
| 1987 | Top_Level_Ports_Are_Enumerated = "1";
|
---|
| 1988 | }
|
---|
| 1989 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 1990 | {
|
---|
| 1991 | }
|
---|
| 1992 | }
|
---|
| 1993 | MODULE ext_ram
|
---|
| 1994 | {
|
---|
| 1995 | class = "altera_nios_dev_kit_stratix_edition_sram2";
|
---|
| 1996 | class_version = "6.05";
|
---|
| 1997 | iss_model_name = "altera_memory";
|
---|
| 1998 | HDL_INFO
|
---|
| 1999 | {
|
---|
| 2000 | }
|
---|
| 2001 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 2002 | {
|
---|
| 2003 | sram_memory_size = "1024";
|
---|
| 2004 | sram_memory_units = "1024";
|
---|
| 2005 | sram_data_width = "32";
|
---|
| 2006 | MAKE
|
---|
| 2007 | {
|
---|
| 2008 | TARGET delete_placeholder_warning
|
---|
| 2009 | {
|
---|
| 2010 | ext_ram
|
---|
| 2011 | {
|
---|
| 2012 | Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
|
---|
| 2013 | Is_Phony = "1";
|
---|
| 2014 | Target_File = "do_delete_placeholder_warning";
|
---|
| 2015 | }
|
---|
| 2016 | }
|
---|
| 2017 | TARGET sim
|
---|
| 2018 | {
|
---|
| 2019 | ext_ram
|
---|
| 2020 | {
|
---|
| 2021 | Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
|
---|
| 2022 | Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
|
---|
| 2023 | Command3 = "touch $(SIMDIR)/dummy_file";
|
---|
| 2024 | Dependency = "$(ELF)";
|
---|
| 2025 | Target_File = "$(SIMDIR)/dummy_file";
|
---|
| 2026 | }
|
---|
| 2027 | }
|
---|
| 2028 | }
|
---|
| 2029 | contents_info = "";
|
---|
| 2030 | }
|
---|
| 2031 | SLAVE s1
|
---|
| 2032 | {
|
---|
| 2033 | PORT_WIRING
|
---|
| 2034 | {
|
---|
| 2035 | PORT data
|
---|
| 2036 | {
|
---|
| 2037 | width = "32";
|
---|
| 2038 | is_shared = "1";
|
---|
| 2039 | direction = "inout";
|
---|
| 2040 | type = "data";
|
---|
| 2041 | }
|
---|
| 2042 | PORT address
|
---|
| 2043 | {
|
---|
| 2044 | width = "18";
|
---|
| 2045 | is_shared = "1";
|
---|
| 2046 | direction = "input";
|
---|
| 2047 | type = "address";
|
---|
| 2048 | }
|
---|
| 2049 | PORT read_n
|
---|
| 2050 | {
|
---|
| 2051 | width = "1";
|
---|
| 2052 | is_shared = "0";
|
---|
| 2053 | direction = "input";
|
---|
| 2054 | type = "read_n";
|
---|
| 2055 | }
|
---|
| 2056 | PORT write_n
|
---|
| 2057 | {
|
---|
| 2058 | width = "1";
|
---|
| 2059 | is_shared = "0";
|
---|
| 2060 | direction = "input";
|
---|
| 2061 | type = "write_n";
|
---|
| 2062 | }
|
---|
| 2063 | PORT be_n
|
---|
| 2064 | {
|
---|
| 2065 | width = "4";
|
---|
| 2066 | is_shared = "0";
|
---|
| 2067 | direction = "input";
|
---|
| 2068 | type = "byteenable_n";
|
---|
| 2069 | }
|
---|
| 2070 | PORT select_n
|
---|
| 2071 | {
|
---|
| 2072 | width = "1";
|
---|
| 2073 | is_shared = "0";
|
---|
| 2074 | direction = "input";
|
---|
| 2075 | type = "chipselect_n";
|
---|
| 2076 | }
|
---|
| 2077 | }
|
---|
| 2078 | SYSTEM_BUILDER_INFO
|
---|
| 2079 | {
|
---|
| 2080 | Bus_Type = "avalon_tristate";
|
---|
| 2081 | Is_Memory_Device = "1";
|
---|
| 2082 | Address_Alignment = "dynamic";
|
---|
| 2083 | Data_Width = "32";
|
---|
| 2084 | Address_Width = "18";
|
---|
| 2085 | Has_IRQ = "0";
|
---|
| 2086 | Read_Wait_States = "0ns";
|
---|
| 2087 | Write_Wait_States = "0ns";
|
---|
| 2088 | Hold_Time = "half";
|
---|
| 2089 | Base_Address = "0x09000000";
|
---|
| 2090 | Address_Span = "1048576";
|
---|
| 2091 | MASTERED_BY ext_ram_bus/tristate_master
|
---|
| 2092 | {
|
---|
| 2093 | priority = "1";
|
---|
| 2094 | }
|
---|
| 2095 | Setup_Time = "0";
|
---|
| 2096 | IRQ_MASTER cpu/data_master
|
---|
| 2097 | {
|
---|
| 2098 | IRQ_Number = "NC";
|
---|
| 2099 | }
|
---|
| 2100 | Is_Base_Locked = "0";
|
---|
| 2101 | Address_Group = "0";
|
---|
| 2102 | }
|
---|
| 2103 | }
|
---|
| 2104 | SYSTEM_BUILDER_INFO
|
---|
| 2105 | {
|
---|
| 2106 | Is_Enabled = "1";
|
---|
| 2107 | Instantiate_In_System_Module = "0";
|
---|
| 2108 | Make_Memory_Model = "1";
|
---|
| 2109 | Default_Module_Name = "sram";
|
---|
| 2110 | View
|
---|
| 2111 | {
|
---|
| 2112 | MESSAGES
|
---|
| 2113 | {
|
---|
| 2114 | }
|
---|
| 2115 | Is_Collapsed = "1";
|
---|
| 2116 | }
|
---|
| 2117 | Clock_Source = "clk";
|
---|
| 2118 | Top_Level_Ports_Are_Enumerated = "1";
|
---|
| 2119 | }
|
---|
| 2120 | }
|
---|
| 2121 | MODULE ext_ram_bus
|
---|
| 2122 | {
|
---|
| 2123 | class = "altera_avalon_tri_state_bridge";
|
---|
| 2124 | class_version = "6.05";
|
---|
| 2125 | SLAVE avalon_slave
|
---|
| 2126 | {
|
---|
| 2127 | SYSTEM_BUILDER_INFO
|
---|
| 2128 | {
|
---|
| 2129 | Bus_Type = "avalon";
|
---|
| 2130 | Bridges_To = "tristate_master";
|
---|
| 2131 | Base_Address = "N/A";
|
---|
| 2132 | Has_IRQ = "0";
|
---|
| 2133 | IRQ = "N/A";
|
---|
| 2134 | Register_Outgoing_Signals = "1";
|
---|
| 2135 | Register_Incoming_Signals = "1";
|
---|
| 2136 | MASTERED_BY cpu/instruction_master
|
---|
| 2137 | {
|
---|
| 2138 | priority = "1";
|
---|
| 2139 | }
|
---|
| 2140 | MASTERED_BY cpu/data_master
|
---|
| 2141 | {
|
---|
| 2142 | priority = "1";
|
---|
| 2143 | }
|
---|
| 2144 | IRQ_MASTER cpu/data_master
|
---|
| 2145 | {
|
---|
| 2146 | IRQ_Number = "NC";
|
---|
| 2147 | }
|
---|
| 2148 | Address_Group = "0";
|
---|
| 2149 | MASTERED_BY vga_16_bit/image_dma_master
|
---|
| 2150 | {
|
---|
| 2151 | priority = "1";
|
---|
| 2152 | }
|
---|
| 2153 | }
|
---|
| 2154 | }
|
---|
| 2155 | MASTER tristate_master
|
---|
| 2156 | {
|
---|
| 2157 | SYSTEM_BUILDER_INFO
|
---|
| 2158 | {
|
---|
| 2159 | Bus_Type = "avalon_tristate";
|
---|
| 2160 | Bridges_To = "avalon_slave";
|
---|
| 2161 | }
|
---|
| 2162 | }
|
---|
| 2163 | SYSTEM_BUILDER_INFO
|
---|
| 2164 | {
|
---|
| 2165 | Instantiate_In_System_Module = "1";
|
---|
| 2166 | Is_Enabled = "1";
|
---|
| 2167 | Is_Bridge = "1";
|
---|
| 2168 | View
|
---|
| 2169 | {
|
---|
| 2170 | MESSAGES
|
---|
| 2171 | {
|
---|
| 2172 | }
|
---|
| 2173 | Is_Collapsed = "0";
|
---|
| 2174 | }
|
---|
| 2175 | Clock_Source = "clk";
|
---|
| 2176 | Top_Level_Ports_Are_Enumerated = "1";
|
---|
| 2177 | }
|
---|
| 2178 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 2179 | {
|
---|
| 2180 | }
|
---|
| 2181 | }
|
---|
| 2182 | MODULE high_res_timer
|
---|
| 2183 | {
|
---|
| 2184 | class = "altera_avalon_timer";
|
---|
| 2185 | class_version = "6.05";
|
---|
| 2186 | iss_model_name = "altera_avalon_timer";
|
---|
| 2187 | SLAVE s1
|
---|
| 2188 | {
|
---|
| 2189 | SYSTEM_BUILDER_INFO
|
---|
| 2190 | {
|
---|
| 2191 | Bus_Type = "avalon";
|
---|
| 2192 | Is_Printable_Device = "0";
|
---|
| 2193 | Address_Alignment = "native";
|
---|
| 2194 | Address_Width = "3";
|
---|
| 2195 | Data_Width = "16";
|
---|
| 2196 | Has_IRQ = "1";
|
---|
| 2197 | Read_Wait_States = "1";
|
---|
| 2198 | Write_Wait_States = "0";
|
---|
| 2199 | Base_Address = "0x08010860";
|
---|
| 2200 | MASTERED_BY cpu/data_master
|
---|
| 2201 | {
|
---|
| 2202 | priority = "1";
|
---|
| 2203 | }
|
---|
| 2204 | IRQ_MASTER cpu/data_master
|
---|
| 2205 | {
|
---|
| 2206 | IRQ_Number = "4";
|
---|
| 2207 | }
|
---|
| 2208 | Address_Group = "0";
|
---|
| 2209 | }
|
---|
| 2210 | PORT_WIRING
|
---|
| 2211 | {
|
---|
| 2212 | PORT address
|
---|
| 2213 | {
|
---|
| 2214 | direction = "input";
|
---|
| 2215 | type = "address";
|
---|
| 2216 | width = "3";
|
---|
| 2217 | Is_Enabled = "1";
|
---|
| 2218 | }
|
---|
| 2219 | PORT chipselect
|
---|
| 2220 | {
|
---|
| 2221 | direction = "input";
|
---|
| 2222 | type = "chipselect";
|
---|
| 2223 | width = "1";
|
---|
| 2224 | Is_Enabled = "1";
|
---|
| 2225 | }
|
---|
| 2226 | PORT clk
|
---|
| 2227 | {
|
---|
| 2228 | direction = "input";
|
---|
| 2229 | type = "clk";
|
---|
| 2230 | width = "1";
|
---|
| 2231 | Is_Enabled = "1";
|
---|
| 2232 | }
|
---|
| 2233 | PORT irq
|
---|
| 2234 | {
|
---|
| 2235 | direction = "output";
|
---|
| 2236 | type = "irq";
|
---|
| 2237 | width = "1";
|
---|
| 2238 | Is_Enabled = "1";
|
---|
| 2239 | }
|
---|
| 2240 | PORT readdata
|
---|
| 2241 | {
|
---|
| 2242 | direction = "output";
|
---|
| 2243 | type = "readdata";
|
---|
| 2244 | width = "16";
|
---|
| 2245 | Is_Enabled = "1";
|
---|
| 2246 | }
|
---|
| 2247 | PORT reset_n
|
---|
| 2248 | {
|
---|
| 2249 | direction = "input";
|
---|
| 2250 | type = "reset_n";
|
---|
| 2251 | width = "1";
|
---|
| 2252 | Is_Enabled = "1";
|
---|
| 2253 | }
|
---|
| 2254 | PORT write_n
|
---|
| 2255 | {
|
---|
| 2256 | direction = "input";
|
---|
| 2257 | type = "write_n";
|
---|
| 2258 | width = "1";
|
---|
| 2259 | Is_Enabled = "1";
|
---|
| 2260 | }
|
---|
| 2261 | PORT writedata
|
---|
| 2262 | {
|
---|
| 2263 | direction = "input";
|
---|
| 2264 | type = "writedata";
|
---|
| 2265 | width = "16";
|
---|
| 2266 | Is_Enabled = "1";
|
---|
| 2267 | }
|
---|
| 2268 | }
|
---|
| 2269 | }
|
---|
| 2270 | SYSTEM_BUILDER_INFO
|
---|
| 2271 | {
|
---|
| 2272 | Instantiate_In_System_Module = "1";
|
---|
| 2273 | Is_Enabled = "1";
|
---|
| 2274 | View
|
---|
| 2275 | {
|
---|
| 2276 | Settings_Summary = "Timer with 1 ms timeout period.";
|
---|
| 2277 | MESSAGES
|
---|
| 2278 | {
|
---|
| 2279 | }
|
---|
| 2280 | Is_Collapsed = "1";
|
---|
| 2281 | }
|
---|
| 2282 | Clock_Source = "clk";
|
---|
| 2283 | Top_Level_Ports_Are_Enumerated = "1";
|
---|
| 2284 | }
|
---|
| 2285 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 2286 | {
|
---|
| 2287 | always_run = "0";
|
---|
| 2288 | fixed_period = "0";
|
---|
| 2289 | snapshot = "1";
|
---|
| 2290 | period = "1";
|
---|
| 2291 | period_units = "ms";
|
---|
| 2292 | reset_output = "0";
|
---|
| 2293 | timeout_pulse_output = "0";
|
---|
| 2294 | mult = "0.001";
|
---|
| 2295 | }
|
---|
| 2296 | HDL_INFO
|
---|
| 2297 | {
|
---|
| 2298 | Simulation_HDL_Files = "";
|
---|
| 2299 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/high_res_timer.vhd";
|
---|
| 2300 | Precompiled_Simulation_Library_Files = "";
|
---|
| 2301 | Synthesis_Only_Files = "";
|
---|
| 2302 | }
|
---|
| 2303 | PORT_WIRING
|
---|
| 2304 | {
|
---|
| 2305 | }
|
---|
| 2306 | }
|
---|
| 2307 | MODULE jtag_uart
|
---|
| 2308 | {
|
---|
| 2309 | class = "altera_avalon_jtag_uart";
|
---|
| 2310 | class_version = "6.05";
|
---|
| 2311 | iss_model_name = "altera_avalon_jtag_uart";
|
---|
| 2312 | SLAVE avalon_jtag_slave
|
---|
| 2313 | {
|
---|
| 2314 | SYSTEM_BUILDER_INFO
|
---|
| 2315 | {
|
---|
| 2316 | Bus_Type = "avalon";
|
---|
| 2317 | Is_Printable_Device = "1";
|
---|
| 2318 | Address_Alignment = "native";
|
---|
| 2319 | Address_Width = "1";
|
---|
| 2320 | Data_Width = "32";
|
---|
| 2321 | Has_IRQ = "1";
|
---|
| 2322 | Read_Wait_States = "peripheral_controlled";
|
---|
| 2323 | Write_Wait_States = "peripheral_controlled";
|
---|
| 2324 | JTAG_Hub_Base_Id = "0x04006E";
|
---|
| 2325 | JTAG_Hub_Instance_Id = "1";
|
---|
| 2326 | Base_Address = "0x08010820";
|
---|
| 2327 | MASTERED_BY cpu/data_master
|
---|
| 2328 | {
|
---|
| 2329 | priority = "1";
|
---|
| 2330 | }
|
---|
| 2331 | IRQ_MASTER cpu/data_master
|
---|
| 2332 | {
|
---|
| 2333 | IRQ_Number = "2";
|
---|
| 2334 | }
|
---|
| 2335 | Connection_Limit = "1";
|
---|
| 2336 | Address_Group = "0";
|
---|
| 2337 | }
|
---|
| 2338 | PORT_WIRING
|
---|
| 2339 | {
|
---|
| 2340 | PORT clk
|
---|
| 2341 | {
|
---|
| 2342 | type = "clk";
|
---|
| 2343 | direction = "input";
|
---|
| 2344 | width = "1";
|
---|
| 2345 | Is_Enabled = "1";
|
---|
| 2346 | }
|
---|
| 2347 | PORT rst_n
|
---|
| 2348 | {
|
---|
| 2349 | type = "reset_n";
|
---|
| 2350 | direction = "input";
|
---|
| 2351 | width = "1";
|
---|
| 2352 | Is_Enabled = "1";
|
---|
| 2353 | }
|
---|
| 2354 | PORT av_chipselect
|
---|
| 2355 | {
|
---|
| 2356 | type = "chipselect";
|
---|
| 2357 | direction = "input";
|
---|
| 2358 | width = "1";
|
---|
| 2359 | Is_Enabled = "1";
|
---|
| 2360 | }
|
---|
| 2361 | PORT av_address
|
---|
| 2362 | {
|
---|
| 2363 | type = "address";
|
---|
| 2364 | direction = "input";
|
---|
| 2365 | width = "1";
|
---|
| 2366 | Is_Enabled = "1";
|
---|
| 2367 | }
|
---|
| 2368 | PORT av_read_n
|
---|
| 2369 | {
|
---|
| 2370 | type = "read_n";
|
---|
| 2371 | direction = "input";
|
---|
| 2372 | width = "1";
|
---|
| 2373 | Is_Enabled = "1";
|
---|
| 2374 | }
|
---|
| 2375 | PORT av_readdata
|
---|
| 2376 | {
|
---|
| 2377 | type = "readdata";
|
---|
| 2378 | direction = "output";
|
---|
| 2379 | width = "32";
|
---|
| 2380 | Is_Enabled = "1";
|
---|
| 2381 | }
|
---|
| 2382 | PORT av_write_n
|
---|
| 2383 | {
|
---|
| 2384 | type = "write_n";
|
---|
| 2385 | direction = "input";
|
---|
| 2386 | width = "1";
|
---|
| 2387 | Is_Enabled = "1";
|
---|
| 2388 | }
|
---|
| 2389 | PORT av_writedata
|
---|
| 2390 | {
|
---|
| 2391 | type = "writedata";
|
---|
| 2392 | direction = "input";
|
---|
| 2393 | width = "32";
|
---|
| 2394 | Is_Enabled = "1";
|
---|
| 2395 | }
|
---|
| 2396 | PORT av_waitrequest
|
---|
| 2397 | {
|
---|
| 2398 | type = "waitrequest";
|
---|
| 2399 | direction = "output";
|
---|
| 2400 | width = "1";
|
---|
| 2401 | Is_Enabled = "1";
|
---|
| 2402 | }
|
---|
| 2403 | PORT av_irq
|
---|
| 2404 | {
|
---|
| 2405 | type = "irq";
|
---|
| 2406 | direction = "output";
|
---|
| 2407 | width = "1";
|
---|
| 2408 | Is_Enabled = "1";
|
---|
| 2409 | }
|
---|
| 2410 | PORT dataavailable
|
---|
| 2411 | {
|
---|
| 2412 | direction = "output";
|
---|
| 2413 | type = "dataavailable";
|
---|
| 2414 | width = "1";
|
---|
| 2415 | Is_Enabled = "1";
|
---|
| 2416 | }
|
---|
| 2417 | PORT readyfordata
|
---|
| 2418 | {
|
---|
| 2419 | direction = "output";
|
---|
| 2420 | type = "readyfordata";
|
---|
| 2421 | width = "1";
|
---|
| 2422 | Is_Enabled = "1";
|
---|
| 2423 | }
|
---|
| 2424 | }
|
---|
| 2425 | }
|
---|
| 2426 | SYSTEM_BUILDER_INFO
|
---|
| 2427 | {
|
---|
| 2428 | Instantiate_In_System_Module = "1";
|
---|
| 2429 | Is_Enabled = "1";
|
---|
| 2430 | Iss_Launch_Telnet = "0";
|
---|
| 2431 | View
|
---|
| 2432 | {
|
---|
| 2433 | Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8
|
---|
| 2434 | <br>Read Depth: 64; Read IRQ Threshold: 8";
|
---|
| 2435 | MESSAGES
|
---|
| 2436 | {
|
---|
| 2437 | }
|
---|
| 2438 | Is_Collapsed = "1";
|
---|
| 2439 | }
|
---|
| 2440 | Clock_Source = "clk";
|
---|
| 2441 | Top_Level_Ports_Are_Enumerated = "1";
|
---|
| 2442 | }
|
---|
| 2443 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 2444 | {
|
---|
| 2445 | write_depth = "64";
|
---|
| 2446 | read_depth = "64";
|
---|
| 2447 | write_threshold = "8";
|
---|
| 2448 | read_threshold = "8";
|
---|
| 2449 | read_char_stream = "";
|
---|
| 2450 | showascii = "1";
|
---|
| 2451 | read_le = "0";
|
---|
| 2452 | write_le = "0";
|
---|
| 2453 | altera_show_unreleased_jtag_uart_features = "0";
|
---|
| 2454 | }
|
---|
| 2455 | SIMULATION
|
---|
| 2456 | {
|
---|
| 2457 | Fix_Me_Up = "";
|
---|
| 2458 | DISPLAY
|
---|
| 2459 | {
|
---|
| 2460 | SIGNAL av_chipselect
|
---|
| 2461 | {
|
---|
| 2462 | name = "av_chipselect";
|
---|
| 2463 | radix = "hexadecimal";
|
---|
| 2464 | }
|
---|
| 2465 | SIGNAL av_address
|
---|
| 2466 | {
|
---|
| 2467 | name = "av_address";
|
---|
| 2468 | radix = "hexadecimal";
|
---|
| 2469 | }
|
---|
| 2470 | SIGNAL av_read_n
|
---|
| 2471 | {
|
---|
| 2472 | name = "av_read_n";
|
---|
| 2473 | radix = "hexadecimal";
|
---|
| 2474 | }
|
---|
| 2475 | SIGNAL av_readdata
|
---|
| 2476 | {
|
---|
| 2477 | name = "av_readdata";
|
---|
| 2478 | radix = "hexadecimal";
|
---|
| 2479 | }
|
---|
| 2480 | SIGNAL av_write_n
|
---|
| 2481 | {
|
---|
| 2482 | name = "av_write_n";
|
---|
| 2483 | radix = "hexadecimal";
|
---|
| 2484 | }
|
---|
| 2485 | SIGNAL av_writedata
|
---|
| 2486 | {
|
---|
| 2487 | name = "av_writedata";
|
---|
| 2488 | radix = "hexadecimal";
|
---|
| 2489 | }
|
---|
| 2490 | SIGNAL av_waitrequest
|
---|
| 2491 | {
|
---|
| 2492 | name = "av_waitrequest";
|
---|
| 2493 | radix = "hexadecimal";
|
---|
| 2494 | }
|
---|
| 2495 | SIGNAL av_irq
|
---|
| 2496 | {
|
---|
| 2497 | name = "av_irq";
|
---|
| 2498 | radix = "hexadecimal";
|
---|
| 2499 | }
|
---|
| 2500 | SIGNAL dataavailable
|
---|
| 2501 | {
|
---|
| 2502 | name = "dataavailable";
|
---|
| 2503 | }
|
---|
| 2504 | SIGNAL readyfordata
|
---|
| 2505 | {
|
---|
| 2506 | name = "readyfordata";
|
---|
| 2507 | }
|
---|
| 2508 | }
|
---|
| 2509 | INTERACTIVE_IN drive
|
---|
| 2510 | {
|
---|
| 2511 | enable = "0";
|
---|
| 2512 | file = "_input_data_stream.dat";
|
---|
| 2513 | mutex = "_input_data_mutex.dat";
|
---|
| 2514 | log = "_in.log";
|
---|
| 2515 | rate = "100";
|
---|
| 2516 | signals = "temp,list";
|
---|
| 2517 | exe = "nios2-terminal";
|
---|
| 2518 | }
|
---|
| 2519 | INTERACTIVE_OUT log
|
---|
| 2520 | {
|
---|
| 2521 | enable = "1";
|
---|
| 2522 | exe = "perl -- atail-f.pl";
|
---|
| 2523 | file = "_output_stream.dat";
|
---|
| 2524 | radix = "ascii";
|
---|
| 2525 | signals = "temp,list";
|
---|
| 2526 | }
|
---|
| 2527 | }
|
---|
| 2528 | HDL_INFO
|
---|
| 2529 | {
|
---|
| 2530 | Simulation_HDL_Files = "";
|
---|
| 2531 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart.vhd";
|
---|
| 2532 | Precompiled_Simulation_Library_Files = "";
|
---|
| 2533 | Synthesis_Only_Files = "";
|
---|
| 2534 | }
|
---|
| 2535 | PORT_WIRING
|
---|
| 2536 | {
|
---|
| 2537 | }
|
---|
| 2538 | }
|
---|
| 2539 | MODULE lan91c111
|
---|
| 2540 | {
|
---|
| 2541 | class = "altera_avalon_lan91c111";
|
---|
| 2542 | class_version = "6.05";
|
---|
| 2543 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 2544 | {
|
---|
| 2545 | CONSTANTS
|
---|
| 2546 | {
|
---|
| 2547 | CONSTANT LAN91C111_REGISTERS_OFFSET
|
---|
| 2548 | {
|
---|
| 2549 | value = "0x0300";
|
---|
| 2550 | comment = "offset 0 or 0x300, depending on address bus wiring";
|
---|
| 2551 | }
|
---|
| 2552 | CONSTANT LAN91C111_DATA_BUS_WIDTH
|
---|
| 2553 | {
|
---|
| 2554 | value = "32";
|
---|
| 2555 | comment = "width 16 or 32, depending on data bus wiring";
|
---|
| 2556 | }
|
---|
| 2557 | }
|
---|
| 2558 | Is_Ethernet_Mac = "1";
|
---|
| 2559 | }
|
---|
| 2560 | SYSTEM_BUILDER_INFO
|
---|
| 2561 | {
|
---|
| 2562 | Instantiate_In_System_Module = "0";
|
---|
| 2563 | Wire_Test_Bench_Values = "1";
|
---|
| 2564 | Is_Enabled = "1";
|
---|
| 2565 | View
|
---|
| 2566 | {
|
---|
| 2567 | MESSAGES
|
---|
| 2568 | {
|
---|
| 2569 | }
|
---|
| 2570 | Is_Collapsed = "1";
|
---|
| 2571 | }
|
---|
| 2572 | Clock_Source = "clk";
|
---|
| 2573 | Top_Level_Ports_Are_Enumerated = "1";
|
---|
| 2574 | }
|
---|
| 2575 | SLAVE s1
|
---|
| 2576 | {
|
---|
| 2577 | SYSTEM_BUILDER_INFO
|
---|
| 2578 | {
|
---|
| 2579 | Instantiate_In_System_Module = "0";
|
---|
| 2580 | Is_Enabled = "1";
|
---|
| 2581 | Is_Bus_Master = "0";
|
---|
| 2582 | Bus_Type = "avalon_tristate";
|
---|
| 2583 | Uses_Tri_State_Data_Bus = "1";
|
---|
| 2584 | Address_Alignment = "native";
|
---|
| 2585 | Address_Width = "14";
|
---|
| 2586 | Data_Width = "32";
|
---|
| 2587 | Has_IRQ = "1";
|
---|
| 2588 | Read_Wait_States = "20ns";
|
---|
| 2589 | Write_Wait_States = "20ns";
|
---|
| 2590 | Setup_Time = "20ns";
|
---|
| 2591 | Hold_Time = "20ns";
|
---|
| 2592 | Is_Memory_Device = "0";
|
---|
| 2593 | Date_Modified = "2002.03.19.10:51:51";
|
---|
| 2594 | Base_Address = "0x08000000";
|
---|
| 2595 | Tri_State_Data_Bus = "--unknown--";
|
---|
| 2596 | MASTERED_BY ext_ram_bus/tristate_master
|
---|
| 2597 | {
|
---|
| 2598 | priority = "1";
|
---|
| 2599 | }
|
---|
| 2600 | IRQ_MASTER cpu/data_master
|
---|
| 2601 | {
|
---|
| 2602 | IRQ_Number = "0";
|
---|
| 2603 | }
|
---|
| 2604 | Address_Group = "0";
|
---|
| 2605 | }
|
---|
| 2606 | PORT_WIRING
|
---|
| 2607 | {
|
---|
| 2608 | PORT irq
|
---|
| 2609 | {
|
---|
| 2610 | direction = "output";
|
---|
| 2611 | width = "1";
|
---|
| 2612 | type = "irq";
|
---|
| 2613 | test_bench_value = "0";
|
---|
| 2614 | }
|
---|
| 2615 | PORT byteenablen
|
---|
| 2616 | {
|
---|
| 2617 | is_shared = "1";
|
---|
| 2618 | direction = "input";
|
---|
| 2619 | width = "4";
|
---|
| 2620 | type = "byteenable_n";
|
---|
| 2621 | }
|
---|
| 2622 | PORT address
|
---|
| 2623 | {
|
---|
| 2624 | is_shared = "1";
|
---|
| 2625 | direction = "input";
|
---|
| 2626 | width = "14";
|
---|
| 2627 | type = "address";
|
---|
| 2628 | }
|
---|
| 2629 | PORT data
|
---|
| 2630 | {
|
---|
| 2631 | is_shared = "1";
|
---|
| 2632 | direction = "inout";
|
---|
| 2633 | width = "32";
|
---|
| 2634 | type = "data";
|
---|
| 2635 | }
|
---|
| 2636 | PORT iow_n
|
---|
| 2637 | {
|
---|
| 2638 | direction = "input";
|
---|
| 2639 | width = "1";
|
---|
| 2640 | type = "write_n";
|
---|
| 2641 | }
|
---|
| 2642 | PORT ior_n
|
---|
| 2643 | {
|
---|
| 2644 | direction = "input";
|
---|
| 2645 | width = "1";
|
---|
| 2646 | type = "read_n";
|
---|
| 2647 | }
|
---|
| 2648 | PORT reset_n
|
---|
| 2649 | {
|
---|
| 2650 | direction = "input";
|
---|
| 2651 | width = "1";
|
---|
| 2652 | type = "reset_n";
|
---|
| 2653 | Is_Enabled = "0";
|
---|
| 2654 | }
|
---|
| 2655 | PORT reset
|
---|
| 2656 | {
|
---|
| 2657 | direction = "input";
|
---|
| 2658 | width = "1";
|
---|
| 2659 | type = "reset";
|
---|
| 2660 | }
|
---|
| 2661 | PORT ardy
|
---|
| 2662 | {
|
---|
| 2663 | direction = "output";
|
---|
| 2664 | width = "1";
|
---|
| 2665 | type = "inhibitrequest_n";
|
---|
| 2666 | Is_Enabled = "0";
|
---|
| 2667 | }
|
---|
| 2668 | }
|
---|
| 2669 | }
|
---|
| 2670 | }
|
---|
| 2671 | MODULE lcd_display
|
---|
| 2672 | {
|
---|
| 2673 | class = "altera_avalon_lcd_16207";
|
---|
| 2674 | class_version = "6.05";
|
---|
| 2675 | HDL_INFO
|
---|
| 2676 | {
|
---|
| 2677 | Simulation_HDL_Files = "";
|
---|
| 2678 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/lcd_display.vhd";
|
---|
| 2679 | Precompiled_Simulation_Library_Files = "";
|
---|
| 2680 | Synthesis_Only_Files = "";
|
---|
| 2681 | }
|
---|
| 2682 | PORT_WIRING
|
---|
| 2683 | {
|
---|
| 2684 | PORT LCD_E
|
---|
| 2685 | {
|
---|
| 2686 | direction = "output";
|
---|
| 2687 | width = "1";
|
---|
| 2688 | Is_Enabled = "1";
|
---|
| 2689 | }
|
---|
| 2690 | PORT LCD_RS
|
---|
| 2691 | {
|
---|
| 2692 | direction = "output";
|
---|
| 2693 | width = "1";
|
---|
| 2694 | Is_Enabled = "1";
|
---|
| 2695 | }
|
---|
| 2696 | PORT LCD_RW
|
---|
| 2697 | {
|
---|
| 2698 | direction = "output";
|
---|
| 2699 | width = "1";
|
---|
| 2700 | Is_Enabled = "1";
|
---|
| 2701 | }
|
---|
| 2702 | PORT LCD_data
|
---|
| 2703 | {
|
---|
| 2704 | direction = "inout";
|
---|
| 2705 | width = "8";
|
---|
| 2706 | Is_Enabled = "1";
|
---|
| 2707 | }
|
---|
| 2708 | }
|
---|
| 2709 | SLAVE control_slave
|
---|
| 2710 | {
|
---|
| 2711 | PORT_WIRING
|
---|
| 2712 | {
|
---|
| 2713 | PORT address
|
---|
| 2714 | {
|
---|
| 2715 | direction = "input";
|
---|
| 2716 | type = "address";
|
---|
| 2717 | width = "2";
|
---|
| 2718 | Is_Enabled = "1";
|
---|
| 2719 | }
|
---|
| 2720 | PORT begintransfer
|
---|
| 2721 | {
|
---|
| 2722 | direction = "input";
|
---|
| 2723 | type = "begintransfer";
|
---|
| 2724 | width = "1";
|
---|
| 2725 | Is_Enabled = "1";
|
---|
| 2726 | }
|
---|
| 2727 | PORT irq
|
---|
| 2728 | {
|
---|
| 2729 | direction = "output";
|
---|
| 2730 | type = "irq";
|
---|
| 2731 | width = "1";
|
---|
| 2732 | Is_Enabled = "1";
|
---|
| 2733 | }
|
---|
| 2734 | PORT read
|
---|
| 2735 | {
|
---|
| 2736 | direction = "input";
|
---|
| 2737 | type = "read";
|
---|
| 2738 | width = "1";
|
---|
| 2739 | Is_Enabled = "1";
|
---|
| 2740 | }
|
---|
| 2741 | PORT readdata
|
---|
| 2742 | {
|
---|
| 2743 | direction = "output";
|
---|
| 2744 | type = "readdata";
|
---|
| 2745 | width = "8";
|
---|
| 2746 | Is_Enabled = "1";
|
---|
| 2747 | }
|
---|
| 2748 | PORT write
|
---|
| 2749 | {
|
---|
| 2750 | direction = "input";
|
---|
| 2751 | type = "write";
|
---|
| 2752 | width = "1";
|
---|
| 2753 | Is_Enabled = "1";
|
---|
| 2754 | }
|
---|
| 2755 | PORT writedata
|
---|
| 2756 | {
|
---|
| 2757 | direction = "input";
|
---|
| 2758 | type = "writedata";
|
---|
| 2759 | width = "8";
|
---|
| 2760 | Is_Enabled = "1";
|
---|
| 2761 | }
|
---|
| 2762 | }
|
---|
| 2763 | SYSTEM_BUILDER_INFO
|
---|
| 2764 | {
|
---|
| 2765 | Bus_Type = "avalon";
|
---|
| 2766 | Has_IRQ = "0";
|
---|
| 2767 | Is_Printable_Device = "1";
|
---|
| 2768 | Address_Width = "2";
|
---|
| 2769 | Data_Width = "8";
|
---|
| 2770 | Base_Address = "0x080108B0";
|
---|
| 2771 | Address_Alignment = "native";
|
---|
| 2772 | Read_Wait_States = "250ns";
|
---|
| 2773 | Write_Wait_States = "250ns";
|
---|
| 2774 | Setup_Time = "250ns";
|
---|
| 2775 | Hold_Time = "250ns";
|
---|
| 2776 | Read_Latency = "0";
|
---|
| 2777 | MASTERED_BY cpu/data_master
|
---|
| 2778 | {
|
---|
| 2779 | priority = "1";
|
---|
| 2780 | }
|
---|
| 2781 | IRQ_MASTER cpu/data_master
|
---|
| 2782 | {
|
---|
| 2783 | IRQ_Number = "NC";
|
---|
| 2784 | }
|
---|
| 2785 | Address_Group = "0";
|
---|
| 2786 | }
|
---|
| 2787 | }
|
---|
| 2788 | SYSTEM_BUILDER_INFO
|
---|
| 2789 | {
|
---|
| 2790 | Date_Modified = "";
|
---|
| 2791 | Is_Enabled = "1";
|
---|
| 2792 | Instantiate_In_System_Module = "1";
|
---|
| 2793 | View
|
---|
| 2794 | {
|
---|
| 2795 | Is_Collapsed = "1";
|
---|
| 2796 | MESSAGES
|
---|
| 2797 | {
|
---|
| 2798 | }
|
---|
| 2799 | }
|
---|
| 2800 | Clock_Source = "clk";
|
---|
| 2801 | Top_Level_Ports_Are_Enumerated = "1";
|
---|
| 2802 | }
|
---|
| 2803 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 2804 | {
|
---|
| 2805 | }
|
---|
| 2806 | }
|
---|
| 2807 | MODULE led_pio
|
---|
| 2808 | {
|
---|
| 2809 | class = "altera_avalon_pio";
|
---|
| 2810 | class_version = "6.05";
|
---|
| 2811 | HDL_INFO
|
---|
| 2812 | {
|
---|
| 2813 | Simulation_HDL_Files = "";
|
---|
| 2814 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/led_pio.vhd";
|
---|
| 2815 | Precompiled_Simulation_Library_Files = "";
|
---|
| 2816 | Synthesis_Only_Files = "";
|
---|
| 2817 | }
|
---|
| 2818 | PORT_WIRING
|
---|
| 2819 | {
|
---|
| 2820 | PORT out_port
|
---|
| 2821 | {
|
---|
| 2822 | direction = "output";
|
---|
| 2823 | width = "8";
|
---|
| 2824 | Is_Enabled = "1";
|
---|
| 2825 | }
|
---|
| 2826 | PORT in_port
|
---|
| 2827 | {
|
---|
| 2828 | direction = "input";
|
---|
| 2829 | Is_Enabled = "0";
|
---|
| 2830 | width = "4";
|
---|
| 2831 | }
|
---|
| 2832 | PORT bidir_port
|
---|
| 2833 | {
|
---|
| 2834 | direction = "inout";
|
---|
| 2835 | Is_Enabled = "0";
|
---|
| 2836 | width = "4";
|
---|
| 2837 | }
|
---|
| 2838 | }
|
---|
| 2839 | SLAVE s1
|
---|
| 2840 | {
|
---|
| 2841 | PORT_WIRING
|
---|
| 2842 | {
|
---|
| 2843 | PORT address
|
---|
| 2844 | {
|
---|
| 2845 | direction = "input";
|
---|
| 2846 | type = "address";
|
---|
| 2847 | width = "2";
|
---|
| 2848 | Is_Enabled = "1";
|
---|
| 2849 | }
|
---|
| 2850 | PORT chipselect
|
---|
| 2851 | {
|
---|
| 2852 | direction = "input";
|
---|
| 2853 | type = "chipselect";
|
---|
| 2854 | width = "1";
|
---|
| 2855 | Is_Enabled = "1";
|
---|
| 2856 | }
|
---|
| 2857 | PORT clk
|
---|
| 2858 | {
|
---|
| 2859 | direction = "input";
|
---|
| 2860 | type = "clk";
|
---|
| 2861 | width = "1";
|
---|
| 2862 | Is_Enabled = "1";
|
---|
| 2863 | }
|
---|
| 2864 | PORT reset_n
|
---|
| 2865 | {
|
---|
| 2866 | direction = "input";
|
---|
| 2867 | type = "reset_n";
|
---|
| 2868 | width = "1";
|
---|
| 2869 | Is_Enabled = "1";
|
---|
| 2870 | }
|
---|
| 2871 | PORT write_n
|
---|
| 2872 | {
|
---|
| 2873 | direction = "input";
|
---|
| 2874 | type = "write_n";
|
---|
| 2875 | width = "1";
|
---|
| 2876 | Is_Enabled = "1";
|
---|
| 2877 | }
|
---|
| 2878 | PORT writedata
|
---|
| 2879 | {
|
---|
| 2880 | direction = "input";
|
---|
| 2881 | type = "writedata";
|
---|
| 2882 | width = "8";
|
---|
| 2883 | Is_Enabled = "1";
|
---|
| 2884 | }
|
---|
| 2885 | }
|
---|
| 2886 | SYSTEM_BUILDER_INFO
|
---|
| 2887 | {
|
---|
| 2888 | Bus_Type = "avalon";
|
---|
| 2889 | Has_IRQ = "0";
|
---|
| 2890 | Address_Width = "2";
|
---|
| 2891 | Data_Width = "8";
|
---|
| 2892 | Base_Address = "0x08010880";
|
---|
| 2893 | Address_Alignment = "native";
|
---|
| 2894 | Read_Wait_States = "1";
|
---|
| 2895 | Write_Wait_States = "0";
|
---|
| 2896 | MASTERED_BY cpu/data_master
|
---|
| 2897 | {
|
---|
| 2898 | priority = "1";
|
---|
| 2899 | }
|
---|
| 2900 | IRQ_MASTER cpu/data_master
|
---|
| 2901 | {
|
---|
| 2902 | IRQ_Number = "NC";
|
---|
| 2903 | }
|
---|
| 2904 | Address_Group = "0";
|
---|
| 2905 | }
|
---|
| 2906 | }
|
---|
| 2907 | SYSTEM_BUILDER_INFO
|
---|
| 2908 | {
|
---|
| 2909 | Date_Modified = "";
|
---|
| 2910 | Is_Enabled = "1";
|
---|
| 2911 | Instantiate_In_System_Module = "1";
|
---|
| 2912 | View
|
---|
| 2913 | {
|
---|
| 2914 | Settings_Summary = " 8-bit PIO using <br>
|
---|
| 2915 |
|
---|
| 2916 |
|
---|
| 2917 | output pins";
|
---|
| 2918 | MESSAGES
|
---|
| 2919 | {
|
---|
| 2920 | }
|
---|
| 2921 | Is_Collapsed = "1";
|
---|
| 2922 | }
|
---|
| 2923 | Wire_Test_Bench_Values = "1";
|
---|
| 2924 | Clock_Source = "clk";
|
---|
| 2925 | Top_Level_Ports_Are_Enumerated = "1";
|
---|
| 2926 | }
|
---|
| 2927 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 2928 | {
|
---|
| 2929 | has_tri = "0";
|
---|
| 2930 | has_out = "1";
|
---|
| 2931 | has_in = "0";
|
---|
| 2932 | capture = "0";
|
---|
| 2933 | edge_type = "NONE";
|
---|
| 2934 | irq_type = "NONE";
|
---|
| 2935 | Do_Test_Bench_Wiring = "0";
|
---|
| 2936 | Driven_Sim_Value = "0x0000";
|
---|
| 2937 | }
|
---|
| 2938 | }
|
---|
| 2939 | MODULE onchip_ram_64_kbytes
|
---|
| 2940 | {
|
---|
| 2941 | class = "altera_avalon_onchip_memory2";
|
---|
| 2942 | class_version = "6.05";
|
---|
| 2943 | iss_model_name = "altera_memory";
|
---|
| 2944 | HDL_INFO
|
---|
| 2945 | {
|
---|
| 2946 | Simulation_HDL_Files = "";
|
---|
| 2947 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/onchip_ram_64_kbytes.vhd";
|
---|
| 2948 | Precompiled_Simulation_Library_Files = "";
|
---|
| 2949 | Synthesis_Only_Files = "";
|
---|
| 2950 | }
|
---|
| 2951 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 2952 | {
|
---|
| 2953 | allow_mram_sim_contents_only_file = "0";
|
---|
| 2954 | ram_block_type = "M4K";
|
---|
| 2955 | gui_ram_block_type = "M4K";
|
---|
| 2956 | Writeable = "1";
|
---|
| 2957 | dual_port = "0";
|
---|
| 2958 | Size_Value = "64";
|
---|
| 2959 | Size_Multiple = "1024";
|
---|
| 2960 | contents_info = "QUARTUS_PROJECT_DIR/onchip_ram_64_kbytes.hex 1194955072 ";
|
---|
| 2961 | MAKE
|
---|
| 2962 | {
|
---|
| 2963 | TARGET delete_placeholder_warning
|
---|
| 2964 | {
|
---|
| 2965 | onchip_ram_64_kbytes
|
---|
| 2966 | {
|
---|
| 2967 | Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
|
---|
| 2968 | Is_Phony = "1";
|
---|
| 2969 | Target_File = "do_delete_placeholder_warning";
|
---|
| 2970 | }
|
---|
| 2971 | }
|
---|
| 2972 | TARGET hex
|
---|
| 2973 | {
|
---|
| 2974 | onchip_ram_64_kbytes
|
---|
| 2975 | {
|
---|
| 2976 | Command1 = "@echo Post-processing to create $(notdir $@)";
|
---|
| 2977 | Command2 = "elf2hex $(ELF) 0x02100000 0x210FFFF --width=32 $(QUARTUS_PROJECT_DIR)/onchip_ram_64_kbytes.hex --create-lanes=0 ";
|
---|
| 2978 | Dependency = "$(ELF)";
|
---|
| 2979 | Target_File = "$(QUARTUS_PROJECT_DIR)/onchip_ram_64_kbytes.hex";
|
---|
| 2980 | }
|
---|
| 2981 | }
|
---|
| 2982 | TARGET sim
|
---|
| 2983 | {
|
---|
| 2984 | onchip_ram_64_kbytes
|
---|
| 2985 | {
|
---|
| 2986 | Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
|
---|
| 2987 | Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
|
---|
| 2988 | Command3 = "touch $(SIMDIR)/dummy_file";
|
---|
| 2989 | Dependency = "$(ELF)";
|
---|
| 2990 | Target_File = "$(SIMDIR)/dummy_file";
|
---|
| 2991 | }
|
---|
| 2992 | }
|
---|
| 2993 | }
|
---|
| 2994 | init_contents_file = "onchip_ram_64_kbytes";
|
---|
| 2995 | non_default_init_file_enabled = "0";
|
---|
| 2996 | }
|
---|
| 2997 | SYSTEM_BUILDER_INFO
|
---|
| 2998 | {
|
---|
| 2999 | Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";
|
---|
| 3000 | Instantiate_In_System_Module = "1";
|
---|
| 3001 | Is_Enabled = "1";
|
---|
| 3002 | Default_Module_Name = "onchip_memory";
|
---|
| 3003 | View
|
---|
| 3004 | {
|
---|
| 3005 | MESSAGES
|
---|
| 3006 | {
|
---|
| 3007 | }
|
---|
| 3008 | Is_Collapsed = "1";
|
---|
| 3009 | }
|
---|
| 3010 | Clock_Source = "clk";
|
---|
| 3011 | Top_Level_Ports_Are_Enumerated = "1";
|
---|
| 3012 | }
|
---|
| 3013 | SLAVE s1
|
---|
| 3014 | {
|
---|
| 3015 | PORT_WIRING
|
---|
| 3016 | {
|
---|
| 3017 | PORT address
|
---|
| 3018 | {
|
---|
| 3019 | direction = "input";
|
---|
| 3020 | type = "address";
|
---|
| 3021 | width = "14";
|
---|
| 3022 | Is_Enabled = "1";
|
---|
| 3023 | }
|
---|
| 3024 | PORT byteenable
|
---|
| 3025 | {
|
---|
| 3026 | direction = "input";
|
---|
| 3027 | type = "byteenable";
|
---|
| 3028 | width = "4";
|
---|
| 3029 | Is_Enabled = "1";
|
---|
| 3030 | }
|
---|
| 3031 | PORT chipselect
|
---|
| 3032 | {
|
---|
| 3033 | direction = "input";
|
---|
| 3034 | type = "chipselect";
|
---|
| 3035 | width = "1";
|
---|
| 3036 | Is_Enabled = "1";
|
---|
| 3037 | }
|
---|
| 3038 | PORT clk
|
---|
| 3039 | {
|
---|
| 3040 | direction = "input";
|
---|
| 3041 | type = "clk";
|
---|
| 3042 | width = "1";
|
---|
| 3043 | Is_Enabled = "1";
|
---|
| 3044 | }
|
---|
| 3045 | PORT readdata
|
---|
| 3046 | {
|
---|
| 3047 | direction = "output";
|
---|
| 3048 | type = "readdata";
|
---|
| 3049 | width = "32";
|
---|
| 3050 | Is_Enabled = "1";
|
---|
| 3051 | }
|
---|
| 3052 | PORT write
|
---|
| 3053 | {
|
---|
| 3054 | direction = "input";
|
---|
| 3055 | type = "write";
|
---|
| 3056 | width = "1";
|
---|
| 3057 | Is_Enabled = "1";
|
---|
| 3058 | }
|
---|
| 3059 | PORT writedata
|
---|
| 3060 | {
|
---|
| 3061 | direction = "input";
|
---|
| 3062 | type = "writedata";
|
---|
| 3063 | width = "32";
|
---|
| 3064 | Is_Enabled = "1";
|
---|
| 3065 | }
|
---|
| 3066 | PORT clken
|
---|
| 3067 | {
|
---|
| 3068 | default_value = "1'b1";
|
---|
| 3069 | direction = "input";
|
---|
| 3070 | type = "clken";
|
---|
| 3071 | width = "1";
|
---|
| 3072 | Is_Enabled = "1";
|
---|
| 3073 | }
|
---|
| 3074 | }
|
---|
| 3075 | SYSTEM_BUILDER_INFO
|
---|
| 3076 | {
|
---|
| 3077 | Bus_Type = "avalon";
|
---|
| 3078 | Is_Memory_Device = "1";
|
---|
| 3079 | Address_Alignment = "dynamic";
|
---|
| 3080 | Address_Width = "14";
|
---|
| 3081 | Data_Width = "32";
|
---|
| 3082 | Has_IRQ = "0";
|
---|
| 3083 | Read_Wait_States = "0";
|
---|
| 3084 | Write_Wait_States = "0";
|
---|
| 3085 | Address_Span = "65536";
|
---|
| 3086 | Read_Latency = "1";
|
---|
| 3087 | Base_Address = "0x02100000";
|
---|
| 3088 | MASTERED_BY cpu/instruction_master
|
---|
| 3089 | {
|
---|
| 3090 | priority = "1";
|
---|
| 3091 | }
|
---|
| 3092 | MASTERED_BY cpu/data_master
|
---|
| 3093 | {
|
---|
| 3094 | priority = "1";
|
---|
| 3095 | }
|
---|
| 3096 | IRQ_MASTER cpu/data_master
|
---|
| 3097 | {
|
---|
| 3098 | IRQ_Number = "NC";
|
---|
| 3099 | }
|
---|
| 3100 | Is_Base_Locked = "1";
|
---|
| 3101 | Is_Channel = "1";
|
---|
| 3102 | Is_Writable = "1";
|
---|
| 3103 | Address_Group = "0";
|
---|
| 3104 | }
|
---|
| 3105 | }
|
---|
| 3106 | SLAVE s2
|
---|
| 3107 | {
|
---|
| 3108 | PORT_WIRING
|
---|
| 3109 | {
|
---|
| 3110 | }
|
---|
| 3111 | SYSTEM_BUILDER_INFO
|
---|
| 3112 | {
|
---|
| 3113 | Bus_Type = "avalon";
|
---|
| 3114 | Is_Memory_Device = "1";
|
---|
| 3115 | Address_Alignment = "dynamic";
|
---|
| 3116 | Address_Width = "14";
|
---|
| 3117 | Data_Width = "32";
|
---|
| 3118 | Has_IRQ = "0";
|
---|
| 3119 | Read_Wait_States = "0";
|
---|
| 3120 | Write_Wait_States = "0";
|
---|
| 3121 | Address_Span = "65536";
|
---|
| 3122 | Read_Latency = "1";
|
---|
| 3123 | Is_Enabled = "0";
|
---|
| 3124 | Is_Channel = "1";
|
---|
| 3125 | Is_Writable = "1";
|
---|
| 3126 | Address_Group = "0";
|
---|
| 3127 | }
|
---|
| 3128 | }
|
---|
| 3129 | SIMULATION
|
---|
| 3130 | {
|
---|
| 3131 | DISPLAY
|
---|
| 3132 | {
|
---|
| 3133 | SIGNAL a
|
---|
| 3134 | {
|
---|
| 3135 | name = "chipselect";
|
---|
| 3136 | conditional = "1";
|
---|
| 3137 | }
|
---|
| 3138 | SIGNAL b
|
---|
| 3139 | {
|
---|
| 3140 | name = "write";
|
---|
| 3141 | conditional = "1";
|
---|
| 3142 | }
|
---|
| 3143 | SIGNAL c
|
---|
| 3144 | {
|
---|
| 3145 | name = "address";
|
---|
| 3146 | radix = "hexadecimal";
|
---|
| 3147 | }
|
---|
| 3148 | SIGNAL d
|
---|
| 3149 | {
|
---|
| 3150 | name = "byteenable";
|
---|
| 3151 | radix = "binary";
|
---|
| 3152 | conditional = "1";
|
---|
| 3153 | }
|
---|
| 3154 | SIGNAL e
|
---|
| 3155 | {
|
---|
| 3156 | name = "readdata";
|
---|
| 3157 | radix = "hexadecimal";
|
---|
| 3158 | }
|
---|
| 3159 | SIGNAL f
|
---|
| 3160 | {
|
---|
| 3161 | name = "writedata";
|
---|
| 3162 | radix = "hexadecimal";
|
---|
| 3163 | conditional = "1";
|
---|
| 3164 | }
|
---|
| 3165 | }
|
---|
| 3166 | }
|
---|
| 3167 | PORT_WIRING
|
---|
| 3168 | {
|
---|
| 3169 | }
|
---|
| 3170 | }
|
---|
| 3171 | MODULE reconfig_request_pio
|
---|
| 3172 | {
|
---|
| 3173 | class = "altera_avalon_pio";
|
---|
| 3174 | class_version = "6.05";
|
---|
| 3175 | HDL_INFO
|
---|
| 3176 | {
|
---|
| 3177 | Simulation_HDL_Files = "";
|
---|
| 3178 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/reconfig_request_pio.vhd";
|
---|
| 3179 | Precompiled_Simulation_Library_Files = "";
|
---|
| 3180 | Synthesis_Only_Files = "";
|
---|
| 3181 | }
|
---|
| 3182 | PORT_WIRING
|
---|
| 3183 | {
|
---|
| 3184 | PORT bidir_port
|
---|
| 3185 | {
|
---|
| 3186 | direction = "inout";
|
---|
| 3187 | width = "1";
|
---|
| 3188 | Is_Enabled = "1";
|
---|
| 3189 | }
|
---|
| 3190 | PORT in_port
|
---|
| 3191 | {
|
---|
| 3192 | direction = "input";
|
---|
| 3193 | Is_Enabled = "0";
|
---|
| 3194 | width = "4";
|
---|
| 3195 | }
|
---|
| 3196 | PORT out_port
|
---|
| 3197 | {
|
---|
| 3198 | direction = "output";
|
---|
| 3199 | Is_Enabled = "0";
|
---|
| 3200 | width = "4";
|
---|
| 3201 | }
|
---|
| 3202 | }
|
---|
| 3203 | SLAVE s1
|
---|
| 3204 | {
|
---|
| 3205 | PORT_WIRING
|
---|
| 3206 | {
|
---|
| 3207 | PORT address
|
---|
| 3208 | {
|
---|
| 3209 | direction = "input";
|
---|
| 3210 | type = "address";
|
---|
| 3211 | width = "2";
|
---|
| 3212 | Is_Enabled = "1";
|
---|
| 3213 | }
|
---|
| 3214 | PORT chipselect
|
---|
| 3215 | {
|
---|
| 3216 | direction = "input";
|
---|
| 3217 | type = "chipselect";
|
---|
| 3218 | width = "1";
|
---|
| 3219 | Is_Enabled = "1";
|
---|
| 3220 | }
|
---|
| 3221 | PORT clk
|
---|
| 3222 | {
|
---|
| 3223 | direction = "input";
|
---|
| 3224 | type = "clk";
|
---|
| 3225 | width = "1";
|
---|
| 3226 | Is_Enabled = "1";
|
---|
| 3227 | }
|
---|
| 3228 | PORT readdata
|
---|
| 3229 | {
|
---|
| 3230 | direction = "output";
|
---|
| 3231 | type = "readdata";
|
---|
| 3232 | width = "1";
|
---|
| 3233 | Is_Enabled = "1";
|
---|
| 3234 | }
|
---|
| 3235 | PORT reset_n
|
---|
| 3236 | {
|
---|
| 3237 | direction = "input";
|
---|
| 3238 | type = "reset_n";
|
---|
| 3239 | width = "1";
|
---|
| 3240 | Is_Enabled = "1";
|
---|
| 3241 | }
|
---|
| 3242 | PORT write_n
|
---|
| 3243 | {
|
---|
| 3244 | direction = "input";
|
---|
| 3245 | type = "write_n";
|
---|
| 3246 | width = "1";
|
---|
| 3247 | Is_Enabled = "1";
|
---|
| 3248 | }
|
---|
| 3249 | PORT writedata
|
---|
| 3250 | {
|
---|
| 3251 | direction = "input";
|
---|
| 3252 | type = "writedata";
|
---|
| 3253 | width = "1";
|
---|
| 3254 | Is_Enabled = "1";
|
---|
| 3255 | }
|
---|
| 3256 | }
|
---|
| 3257 | SYSTEM_BUILDER_INFO
|
---|
| 3258 | {
|
---|
| 3259 | Bus_Type = "avalon";
|
---|
| 3260 | Has_IRQ = "0";
|
---|
| 3261 | Address_Width = "2";
|
---|
| 3262 | Data_Width = "1";
|
---|
| 3263 | Base_Address = "0x080108A0";
|
---|
| 3264 | Address_Alignment = "native";
|
---|
| 3265 | Read_Wait_States = "1";
|
---|
| 3266 | Write_Wait_States = "0";
|
---|
| 3267 | MASTERED_BY cpu/data_master
|
---|
| 3268 | {
|
---|
| 3269 | priority = "1";
|
---|
| 3270 | }
|
---|
| 3271 | IRQ_MASTER cpu/data_master
|
---|
| 3272 | {
|
---|
| 3273 | IRQ_Number = "NC";
|
---|
| 3274 | }
|
---|
| 3275 | Address_Group = "0";
|
---|
| 3276 | }
|
---|
| 3277 | }
|
---|
| 3278 | SYSTEM_BUILDER_INFO
|
---|
| 3279 | {
|
---|
| 3280 | Date_Modified = "";
|
---|
| 3281 | Is_Enabled = "1";
|
---|
| 3282 | Instantiate_In_System_Module = "1";
|
---|
| 3283 | View
|
---|
| 3284 | {
|
---|
| 3285 | Settings_Summary = " 1-bit PIO using <br>
|
---|
| 3286 | tri-state pins with edge type NONE and interrupt source NONE
|
---|
| 3287 |
|
---|
| 3288 | ";
|
---|
| 3289 | MESSAGES
|
---|
| 3290 | {
|
---|
| 3291 | }
|
---|
| 3292 | Is_Collapsed = "1";
|
---|
| 3293 | }
|
---|
| 3294 | Wire_Test_Bench_Values = "1";
|
---|
| 3295 | Clock_Source = "clk";
|
---|
| 3296 | Top_Level_Ports_Are_Enumerated = "1";
|
---|
| 3297 | }
|
---|
| 3298 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 3299 | {
|
---|
| 3300 | has_tri = "1";
|
---|
| 3301 | has_out = "0";
|
---|
| 3302 | has_in = "0";
|
---|
| 3303 | capture = "0";
|
---|
| 3304 | edge_type = "NONE";
|
---|
| 3305 | irq_type = "NONE";
|
---|
| 3306 | Do_Test_Bench_Wiring = "0";
|
---|
| 3307 | Driven_Sim_Value = "0x0000";
|
---|
| 3308 | }
|
---|
| 3309 | }
|
---|
| 3310 | MODULE sdram
|
---|
| 3311 | {
|
---|
| 3312 | class = "altera_avalon_new_sdram_controller";
|
---|
| 3313 | class_version = "6.05";
|
---|
| 3314 | iss_model_name = "altera_memory";
|
---|
| 3315 | SLAVE s1
|
---|
| 3316 | {
|
---|
| 3317 | SYSTEM_BUILDER_INFO
|
---|
| 3318 | {
|
---|
| 3319 | Bus_Type = "avalon";
|
---|
| 3320 | Address_Alignment = "dynamic";
|
---|
| 3321 | Has_IRQ = "0";
|
---|
| 3322 | Maximum_Pending_Read_Transactions = "6";
|
---|
| 3323 | Read_Wait_States = "peripheral_controlled";
|
---|
| 3324 | Write_Wait_States = "peripheral_controlled";
|
---|
| 3325 | Is_Memory_Device = "1";
|
---|
| 3326 | Address_Width = "22";
|
---|
| 3327 | Data_Width = "64";
|
---|
| 3328 | Simulation_Num_Lanes = "1";
|
---|
| 3329 | Base_Address = "0x0A000000";
|
---|
| 3330 | MASTERED_BY cpu/instruction_master
|
---|
| 3331 | {
|
---|
| 3332 | priority = "1";
|
---|
| 3333 | }
|
---|
| 3334 | MASTERED_BY cpu/data_master
|
---|
| 3335 | {
|
---|
| 3336 | priority = "1";
|
---|
| 3337 | }
|
---|
| 3338 | IRQ_MASTER cpu/data_master
|
---|
| 3339 | {
|
---|
| 3340 | IRQ_Number = "NC";
|
---|
| 3341 | }
|
---|
| 3342 | Is_Base_Locked = "0";
|
---|
| 3343 | Address_Group = "0";
|
---|
| 3344 | MASTERED_BY vga_16_bit/image_dma_master
|
---|
| 3345 | {
|
---|
| 3346 | priority = "1";
|
---|
| 3347 | }
|
---|
| 3348 | }
|
---|
| 3349 | PORT_WIRING
|
---|
| 3350 | {
|
---|
| 3351 | PORT az_addr
|
---|
| 3352 | {
|
---|
| 3353 | direction = "input";
|
---|
| 3354 | type = "address";
|
---|
| 3355 | width = "22";
|
---|
| 3356 | Is_Enabled = "1";
|
---|
| 3357 | }
|
---|
| 3358 | PORT az_be_n
|
---|
| 3359 | {
|
---|
| 3360 | direction = "input";
|
---|
| 3361 | type = "byteenable_n";
|
---|
| 3362 | width = "8";
|
---|
| 3363 | Is_Enabled = "1";
|
---|
| 3364 | }
|
---|
| 3365 | PORT az_cs
|
---|
| 3366 | {
|
---|
| 3367 | direction = "input";
|
---|
| 3368 | type = "chipselect";
|
---|
| 3369 | width = "1";
|
---|
| 3370 | Is_Enabled = "1";
|
---|
| 3371 | }
|
---|
| 3372 | PORT az_data
|
---|
| 3373 | {
|
---|
| 3374 | direction = "input";
|
---|
| 3375 | type = "writedata";
|
---|
| 3376 | width = "64";
|
---|
| 3377 | Is_Enabled = "1";
|
---|
| 3378 | }
|
---|
| 3379 | PORT az_rd_n
|
---|
| 3380 | {
|
---|
| 3381 | direction = "input";
|
---|
| 3382 | type = "read_n";
|
---|
| 3383 | width = "1";
|
---|
| 3384 | Is_Enabled = "1";
|
---|
| 3385 | }
|
---|
| 3386 | PORT az_wr_n
|
---|
| 3387 | {
|
---|
| 3388 | direction = "input";
|
---|
| 3389 | type = "write_n";
|
---|
| 3390 | width = "1";
|
---|
| 3391 | Is_Enabled = "1";
|
---|
| 3392 | }
|
---|
| 3393 | PORT clk
|
---|
| 3394 | {
|
---|
| 3395 | direction = "input";
|
---|
| 3396 | type = "clk";
|
---|
| 3397 | width = "1";
|
---|
| 3398 | Is_Enabled = "1";
|
---|
| 3399 | }
|
---|
| 3400 | PORT reset_n
|
---|
| 3401 | {
|
---|
| 3402 | direction = "input";
|
---|
| 3403 | type = "reset_n";
|
---|
| 3404 | width = "1";
|
---|
| 3405 | Is_Enabled = "1";
|
---|
| 3406 | }
|
---|
| 3407 | PORT za_data
|
---|
| 3408 | {
|
---|
| 3409 | direction = "output";
|
---|
| 3410 | type = "readdata";
|
---|
| 3411 | width = "64";
|
---|
| 3412 | Is_Enabled = "1";
|
---|
| 3413 | }
|
---|
| 3414 | PORT za_valid
|
---|
| 3415 | {
|
---|
| 3416 | direction = "output";
|
---|
| 3417 | type = "readdatavalid";
|
---|
| 3418 | width = "1";
|
---|
| 3419 | Is_Enabled = "1";
|
---|
| 3420 | }
|
---|
| 3421 | PORT za_waitrequest
|
---|
| 3422 | {
|
---|
| 3423 | direction = "output";
|
---|
| 3424 | type = "waitrequest";
|
---|
| 3425 | width = "1";
|
---|
| 3426 | Is_Enabled = "1";
|
---|
| 3427 | }
|
---|
| 3428 | PORT zs_addr
|
---|
| 3429 | {
|
---|
| 3430 | direction = "output";
|
---|
| 3431 | width = "12";
|
---|
| 3432 | Is_Enabled = "1";
|
---|
| 3433 | }
|
---|
| 3434 | PORT zs_ba
|
---|
| 3435 | {
|
---|
| 3436 | direction = "output";
|
---|
| 3437 | width = "2";
|
---|
| 3438 | Is_Enabled = "1";
|
---|
| 3439 | }
|
---|
| 3440 | PORT zs_cas_n
|
---|
| 3441 | {
|
---|
| 3442 | direction = "output";
|
---|
| 3443 | width = "1";
|
---|
| 3444 | Is_Enabled = "1";
|
---|
| 3445 | }
|
---|
| 3446 | PORT zs_cke
|
---|
| 3447 | {
|
---|
| 3448 | direction = "output";
|
---|
| 3449 | width = "1";
|
---|
| 3450 | Is_Enabled = "1";
|
---|
| 3451 | }
|
---|
| 3452 | PORT zs_cs_n
|
---|
| 3453 | {
|
---|
| 3454 | direction = "output";
|
---|
| 3455 | width = "1";
|
---|
| 3456 | Is_Enabled = "1";
|
---|
| 3457 | }
|
---|
| 3458 | PORT zs_dq
|
---|
| 3459 | {
|
---|
| 3460 | direction = "inout";
|
---|
| 3461 | width = "64";
|
---|
| 3462 | Is_Enabled = "1";
|
---|
| 3463 | }
|
---|
| 3464 | PORT zs_dqm
|
---|
| 3465 | {
|
---|
| 3466 | direction = "output";
|
---|
| 3467 | width = "8";
|
---|
| 3468 | Is_Enabled = "1";
|
---|
| 3469 | }
|
---|
| 3470 | PORT zs_ras_n
|
---|
| 3471 | {
|
---|
| 3472 | direction = "output";
|
---|
| 3473 | width = "1";
|
---|
| 3474 | Is_Enabled = "1";
|
---|
| 3475 | }
|
---|
| 3476 | PORT zs_we_n
|
---|
| 3477 | {
|
---|
| 3478 | direction = "output";
|
---|
| 3479 | width = "1";
|
---|
| 3480 | Is_Enabled = "1";
|
---|
| 3481 | }
|
---|
| 3482 | }
|
---|
| 3483 | }
|
---|
| 3484 | SYSTEM_BUILDER_INFO
|
---|
| 3485 | {
|
---|
| 3486 | Instantiate_In_System_Module = "1";
|
---|
| 3487 | Is_Enabled = "1";
|
---|
| 3488 | Default_Module_Name = "sdram";
|
---|
| 3489 | Disable_Simulation_Port_Wiring = "0";
|
---|
| 3490 | View
|
---|
| 3491 | {
|
---|
| 3492 | Settings_Summary = "4194304 x 64<br>
|
---|
| 3493 | Memory size: 32 MBytes<br>
|
---|
| 3494 | 256 MBits
|
---|
| 3495 | ";
|
---|
| 3496 | MESSAGES
|
---|
| 3497 | {
|
---|
| 3498 | }
|
---|
| 3499 | Is_Collapsed = "1";
|
---|
| 3500 | }
|
---|
| 3501 | Clock_Source = "clk";
|
---|
| 3502 | Top_Level_Ports_Are_Enumerated = "1";
|
---|
| 3503 | }
|
---|
| 3504 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 3505 | {
|
---|
| 3506 | register_data_in = "1";
|
---|
| 3507 | sim_model_base = "1";
|
---|
| 3508 | sdram_data_width = "64";
|
---|
| 3509 | sdram_addr_width = "12";
|
---|
| 3510 | sdram_row_width = "12";
|
---|
| 3511 | sdram_col_width = "8";
|
---|
| 3512 | sdram_num_chipselects = "1";
|
---|
| 3513 | sdram_num_banks = "4";
|
---|
| 3514 | refresh_period = "15.625";
|
---|
| 3515 | powerup_delay = "100";
|
---|
| 3516 | cas_latency = "2";
|
---|
| 3517 | t_rfc = "70";
|
---|
| 3518 | t_rp = "20";
|
---|
| 3519 | t_mrd = "3";
|
---|
| 3520 | t_rcd = "20";
|
---|
| 3521 | t_ac = "5.5";
|
---|
| 3522 | t_wr = "14";
|
---|
| 3523 | init_refresh_commands = "2";
|
---|
| 3524 | init_nop_delay = "0";
|
---|
| 3525 | shared_data = "0";
|
---|
| 3526 | starvation_indicator = "0";
|
---|
| 3527 | tristate_bridge_slave = "";
|
---|
| 3528 | is_initialized = "1";
|
---|
| 3529 | sdram_bank_width = "2";
|
---|
| 3530 | MAKE
|
---|
| 3531 | {
|
---|
| 3532 | TARGET delete_placeholder_warning
|
---|
| 3533 | {
|
---|
| 3534 | sdram
|
---|
| 3535 | {
|
---|
| 3536 | Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
|
---|
| 3537 | Is_Phony = "1";
|
---|
| 3538 | Target_File = "do_delete_placeholder_warning";
|
---|
| 3539 | }
|
---|
| 3540 | }
|
---|
| 3541 | TARGET sim
|
---|
| 3542 | {
|
---|
| 3543 | sdram
|
---|
| 3544 | {
|
---|
| 3545 | Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
|
---|
| 3546 | Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
|
---|
| 3547 | Command3 = "touch $(SIMDIR)/dummy_file";
|
---|
| 3548 | Dependency = "$(ELF)";
|
---|
| 3549 | Target_File = "$(SIMDIR)/dummy_file";
|
---|
| 3550 | }
|
---|
| 3551 | }
|
---|
| 3552 | }
|
---|
| 3553 | contents_info = "";
|
---|
| 3554 | }
|
---|
| 3555 | SIMULATION
|
---|
| 3556 | {
|
---|
| 3557 | Fix_Me_Up = "";
|
---|
| 3558 | DISPLAY
|
---|
| 3559 | {
|
---|
| 3560 | SIGNAL a
|
---|
| 3561 | {
|
---|
| 3562 | name = "az_addr";
|
---|
| 3563 | radix = "hexadecimal";
|
---|
| 3564 | }
|
---|
| 3565 | SIGNAL b
|
---|
| 3566 | {
|
---|
| 3567 | name = "az_be_n";
|
---|
| 3568 | radix = "hexadecimal";
|
---|
| 3569 | }
|
---|
| 3570 | SIGNAL c
|
---|
| 3571 | {
|
---|
| 3572 | name = "az_cs";
|
---|
| 3573 | }
|
---|
| 3574 | SIGNAL d
|
---|
| 3575 | {
|
---|
| 3576 | name = "az_data";
|
---|
| 3577 | radix = "hexadecimal";
|
---|
| 3578 | }
|
---|
| 3579 | SIGNAL e
|
---|
| 3580 | {
|
---|
| 3581 | name = "az_rd_n";
|
---|
| 3582 | }
|
---|
| 3583 | SIGNAL f
|
---|
| 3584 | {
|
---|
| 3585 | name = "az_wr_n";
|
---|
| 3586 | }
|
---|
| 3587 | SIGNAL g
|
---|
| 3588 | {
|
---|
| 3589 | name = "clk";
|
---|
| 3590 | }
|
---|
| 3591 | SIGNAL h
|
---|
| 3592 | {
|
---|
| 3593 | name = "za_data";
|
---|
| 3594 | radix = "hexadecimal";
|
---|
| 3595 | }
|
---|
| 3596 | SIGNAL i
|
---|
| 3597 | {
|
---|
| 3598 | name = "za_valid";
|
---|
| 3599 | }
|
---|
| 3600 | SIGNAL j
|
---|
| 3601 | {
|
---|
| 3602 | name = "za_waitrequest";
|
---|
| 3603 | }
|
---|
| 3604 | SIGNAL k
|
---|
| 3605 | {
|
---|
| 3606 | name = "za_cannotrefresh";
|
---|
| 3607 | suppress = "1";
|
---|
| 3608 | }
|
---|
| 3609 | SIGNAL l
|
---|
| 3610 | {
|
---|
| 3611 | name = "CODE";
|
---|
| 3612 | radix = "ascii";
|
---|
| 3613 | }
|
---|
| 3614 | SIGNAL m
|
---|
| 3615 | {
|
---|
| 3616 | name = "zs_addr";
|
---|
| 3617 | radix = "hexadecimal";
|
---|
| 3618 | suppress = "0";
|
---|
| 3619 | }
|
---|
| 3620 | SIGNAL n
|
---|
| 3621 | {
|
---|
| 3622 | name = "zs_ba";
|
---|
| 3623 | radix = "hexadecimal";
|
---|
| 3624 | suppress = "0";
|
---|
| 3625 | }
|
---|
| 3626 | SIGNAL o
|
---|
| 3627 | {
|
---|
| 3628 | name = "zs_cs_n";
|
---|
| 3629 | radix = "hexadecimal";
|
---|
| 3630 | suppress = "0";
|
---|
| 3631 | }
|
---|
| 3632 | SIGNAL p
|
---|
| 3633 | {
|
---|
| 3634 | name = "zs_ras_n";
|
---|
| 3635 | suppress = "0";
|
---|
| 3636 | }
|
---|
| 3637 | SIGNAL q
|
---|
| 3638 | {
|
---|
| 3639 | name = "zs_cas_n";
|
---|
| 3640 | suppress = "0";
|
---|
| 3641 | }
|
---|
| 3642 | SIGNAL r
|
---|
| 3643 | {
|
---|
| 3644 | name = "zs_we_n";
|
---|
| 3645 | suppress = "0";
|
---|
| 3646 | }
|
---|
| 3647 | SIGNAL s
|
---|
| 3648 | {
|
---|
| 3649 | name = "zs_dq";
|
---|
| 3650 | radix = "hexadecimal";
|
---|
| 3651 | suppress = "0";
|
---|
| 3652 | }
|
---|
| 3653 | SIGNAL t
|
---|
| 3654 | {
|
---|
| 3655 | name = "zs_dqm";
|
---|
| 3656 | radix = "hexadecimal";
|
---|
| 3657 | suppress = "0";
|
---|
| 3658 | }
|
---|
| 3659 | SIGNAL u
|
---|
| 3660 | {
|
---|
| 3661 | name = "zt_addr";
|
---|
| 3662 | radix = "hexadecimal";
|
---|
| 3663 | suppress = "1";
|
---|
| 3664 | }
|
---|
| 3665 | SIGNAL v
|
---|
| 3666 | {
|
---|
| 3667 | name = "zt_ba";
|
---|
| 3668 | radix = "hexadecimal";
|
---|
| 3669 | suppress = "1";
|
---|
| 3670 | }
|
---|
| 3671 | SIGNAL w
|
---|
| 3672 | {
|
---|
| 3673 | name = "zt_oe";
|
---|
| 3674 | suppress = "1";
|
---|
| 3675 | }
|
---|
| 3676 | SIGNAL x
|
---|
| 3677 | {
|
---|
| 3678 | name = "zt_cke";
|
---|
| 3679 | suppress = "1";
|
---|
| 3680 | }
|
---|
| 3681 | SIGNAL y
|
---|
| 3682 | {
|
---|
| 3683 | name = "zt_chipselect";
|
---|
| 3684 | suppress = "1";
|
---|
| 3685 | }
|
---|
| 3686 | SIGNAL z0
|
---|
| 3687 | {
|
---|
| 3688 | name = "zt_lock_n";
|
---|
| 3689 | suppress = "1";
|
---|
| 3690 | }
|
---|
| 3691 | SIGNAL z1
|
---|
| 3692 | {
|
---|
| 3693 | name = "zt_ras_n";
|
---|
| 3694 | suppress = "1";
|
---|
| 3695 | }
|
---|
| 3696 | SIGNAL z2
|
---|
| 3697 | {
|
---|
| 3698 | name = "zt_cas_n";
|
---|
| 3699 | suppress = "1";
|
---|
| 3700 | }
|
---|
| 3701 | SIGNAL z3
|
---|
| 3702 | {
|
---|
| 3703 | name = "zt_we_n";
|
---|
| 3704 | suppress = "1";
|
---|
| 3705 | }
|
---|
| 3706 | SIGNAL z4
|
---|
| 3707 | {
|
---|
| 3708 | name = "zt_cs_n";
|
---|
| 3709 | radix = "hexadecimal";
|
---|
| 3710 | suppress = "1";
|
---|
| 3711 | }
|
---|
| 3712 | SIGNAL z5
|
---|
| 3713 | {
|
---|
| 3714 | name = "zt_dqm";
|
---|
| 3715 | radix = "hexadecimal";
|
---|
| 3716 | suppress = "1";
|
---|
| 3717 | }
|
---|
| 3718 | SIGNAL z6
|
---|
| 3719 | {
|
---|
| 3720 | name = "zt_data";
|
---|
| 3721 | radix = "hexadecimal";
|
---|
| 3722 | suppress = "1";
|
---|
| 3723 | }
|
---|
| 3724 | SIGNAL z7
|
---|
| 3725 | {
|
---|
| 3726 | name = "tz_data";
|
---|
| 3727 | radix = "hexadecimal";
|
---|
| 3728 | suppress = "1";
|
---|
| 3729 | }
|
---|
| 3730 | SIGNAL z8
|
---|
| 3731 | {
|
---|
| 3732 | name = "tz_waitrequest";
|
---|
| 3733 | suppress = "1";
|
---|
| 3734 | }
|
---|
| 3735 | }
|
---|
| 3736 | PORT_WIRING
|
---|
| 3737 | {
|
---|
| 3738 | PORT clk
|
---|
| 3739 | {
|
---|
| 3740 | direction = "input";
|
---|
| 3741 | width = "1";
|
---|
| 3742 | Is_Enabled = "1";
|
---|
| 3743 | }
|
---|
| 3744 | PORT zs_addr
|
---|
| 3745 | {
|
---|
| 3746 | direction = "input";
|
---|
| 3747 | width = "12";
|
---|
| 3748 | Is_Enabled = "1";
|
---|
| 3749 | }
|
---|
| 3750 | PORT zs_ba
|
---|
| 3751 | {
|
---|
| 3752 | direction = "input";
|
---|
| 3753 | width = "2";
|
---|
| 3754 | Is_Enabled = "1";
|
---|
| 3755 | }
|
---|
| 3756 | PORT zs_cas_n
|
---|
| 3757 | {
|
---|
| 3758 | direction = "input";
|
---|
| 3759 | width = "1";
|
---|
| 3760 | Is_Enabled = "1";
|
---|
| 3761 | }
|
---|
| 3762 | PORT zs_cke
|
---|
| 3763 | {
|
---|
| 3764 | direction = "input";
|
---|
| 3765 | width = "1";
|
---|
| 3766 | Is_Enabled = "1";
|
---|
| 3767 | }
|
---|
| 3768 | PORT zs_cs_n
|
---|
| 3769 | {
|
---|
| 3770 | direction = "input";
|
---|
| 3771 | width = "1";
|
---|
| 3772 | Is_Enabled = "1";
|
---|
| 3773 | }
|
---|
| 3774 | PORT zs_dq
|
---|
| 3775 | {
|
---|
| 3776 | direction = "inout";
|
---|
| 3777 | width = "64";
|
---|
| 3778 | Is_Enabled = "1";
|
---|
| 3779 | }
|
---|
| 3780 | PORT zs_dqm
|
---|
| 3781 | {
|
---|
| 3782 | direction = "input";
|
---|
| 3783 | width = "8";
|
---|
| 3784 | Is_Enabled = "1";
|
---|
| 3785 | }
|
---|
| 3786 | PORT zs_ras_n
|
---|
| 3787 | {
|
---|
| 3788 | direction = "input";
|
---|
| 3789 | width = "1";
|
---|
| 3790 | Is_Enabled = "1";
|
---|
| 3791 | }
|
---|
| 3792 | PORT zs_we_n
|
---|
| 3793 | {
|
---|
| 3794 | direction = "input";
|
---|
| 3795 | width = "1";
|
---|
| 3796 | Is_Enabled = "1";
|
---|
| 3797 | }
|
---|
| 3798 | }
|
---|
| 3799 | }
|
---|
| 3800 | HDL_INFO
|
---|
| 3801 | {
|
---|
| 3802 | Simulation_HDL_Files = "";
|
---|
| 3803 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sdram.vhd, __PROJECT_DIRECTORY__/sdram_test_component.vhd";
|
---|
| 3804 | Precompiled_Simulation_Library_Files = "";
|
---|
| 3805 | Synthesis_Only_Files = "";
|
---|
| 3806 | }
|
---|
| 3807 | PORT_WIRING
|
---|
| 3808 | {
|
---|
| 3809 | }
|
---|
| 3810 | }
|
---|
| 3811 | MODULE seven_seg_pio
|
---|
| 3812 | {
|
---|
| 3813 | class = "altera_avalon_pio";
|
---|
| 3814 | class_version = "6.05";
|
---|
| 3815 | HDL_INFO
|
---|
| 3816 | {
|
---|
| 3817 | Simulation_HDL_Files = "";
|
---|
| 3818 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/seven_seg_pio.vhd";
|
---|
| 3819 | Precompiled_Simulation_Library_Files = "";
|
---|
| 3820 | Synthesis_Only_Files = "";
|
---|
| 3821 | }
|
---|
| 3822 | PORT_WIRING
|
---|
| 3823 | {
|
---|
| 3824 | PORT out_port
|
---|
| 3825 | {
|
---|
| 3826 | direction = "output";
|
---|
| 3827 | width = "16";
|
---|
| 3828 | Is_Enabled = "1";
|
---|
| 3829 | }
|
---|
| 3830 | PORT in_port
|
---|
| 3831 | {
|
---|
| 3832 | direction = "input";
|
---|
| 3833 | Is_Enabled = "0";
|
---|
| 3834 | width = "4";
|
---|
| 3835 | }
|
---|
| 3836 | PORT bidir_port
|
---|
| 3837 | {
|
---|
| 3838 | direction = "inout";
|
---|
| 3839 | Is_Enabled = "0";
|
---|
| 3840 | width = "4";
|
---|
| 3841 | }
|
---|
| 3842 | }
|
---|
| 3843 | SLAVE s1
|
---|
| 3844 | {
|
---|
| 3845 | PORT_WIRING
|
---|
| 3846 | {
|
---|
| 3847 | PORT address
|
---|
| 3848 | {
|
---|
| 3849 | direction = "input";
|
---|
| 3850 | type = "address";
|
---|
| 3851 | width = "2";
|
---|
| 3852 | Is_Enabled = "1";
|
---|
| 3853 | }
|
---|
| 3854 | PORT chipselect
|
---|
| 3855 | {
|
---|
| 3856 | direction = "input";
|
---|
| 3857 | type = "chipselect";
|
---|
| 3858 | width = "1";
|
---|
| 3859 | Is_Enabled = "1";
|
---|
| 3860 | }
|
---|
| 3861 | PORT clk
|
---|
| 3862 | {
|
---|
| 3863 | direction = "input";
|
---|
| 3864 | type = "clk";
|
---|
| 3865 | width = "1";
|
---|
| 3866 | Is_Enabled = "1";
|
---|
| 3867 | }
|
---|
| 3868 | PORT reset_n
|
---|
| 3869 | {
|
---|
| 3870 | direction = "input";
|
---|
| 3871 | type = "reset_n";
|
---|
| 3872 | width = "1";
|
---|
| 3873 | Is_Enabled = "1";
|
---|
| 3874 | }
|
---|
| 3875 | PORT write_n
|
---|
| 3876 | {
|
---|
| 3877 | direction = "input";
|
---|
| 3878 | type = "write_n";
|
---|
| 3879 | width = "1";
|
---|
| 3880 | Is_Enabled = "1";
|
---|
| 3881 | }
|
---|
| 3882 | PORT writedata
|
---|
| 3883 | {
|
---|
| 3884 | direction = "input";
|
---|
| 3885 | type = "writedata";
|
---|
| 3886 | width = "16";
|
---|
| 3887 | Is_Enabled = "1";
|
---|
| 3888 | }
|
---|
| 3889 | }
|
---|
| 3890 | SYSTEM_BUILDER_INFO
|
---|
| 3891 | {
|
---|
| 3892 | Bus_Type = "avalon";
|
---|
| 3893 | Has_IRQ = "0";
|
---|
| 3894 | Address_Width = "2";
|
---|
| 3895 | Data_Width = "16";
|
---|
| 3896 | Base_Address = "0x08010890";
|
---|
| 3897 | Address_Alignment = "native";
|
---|
| 3898 | Read_Wait_States = "1";
|
---|
| 3899 | Write_Wait_States = "0";
|
---|
| 3900 | MASTERED_BY cpu/data_master
|
---|
| 3901 | {
|
---|
| 3902 | priority = "1";
|
---|
| 3903 | }
|
---|
| 3904 | IRQ_MASTER cpu/data_master
|
---|
| 3905 | {
|
---|
| 3906 | IRQ_Number = "NC";
|
---|
| 3907 | }
|
---|
| 3908 | Address_Group = "0";
|
---|
| 3909 | }
|
---|
| 3910 | }
|
---|
| 3911 | SYSTEM_BUILDER_INFO
|
---|
| 3912 | {
|
---|
| 3913 | Date_Modified = "";
|
---|
| 3914 | Is_Enabled = "1";
|
---|
| 3915 | Instantiate_In_System_Module = "1";
|
---|
| 3916 | View
|
---|
| 3917 | {
|
---|
| 3918 | Settings_Summary = " 16-bit PIO using <br>
|
---|
| 3919 |
|
---|
| 3920 |
|
---|
| 3921 | output pins";
|
---|
| 3922 | MESSAGES
|
---|
| 3923 | {
|
---|
| 3924 | }
|
---|
| 3925 | Is_Collapsed = "1";
|
---|
| 3926 | }
|
---|
| 3927 | Wire_Test_Bench_Values = "1";
|
---|
| 3928 | Clock_Source = "clk";
|
---|
| 3929 | Top_Level_Ports_Are_Enumerated = "1";
|
---|
| 3930 | }
|
---|
| 3931 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 3932 | {
|
---|
| 3933 | has_tri = "0";
|
---|
| 3934 | has_out = "1";
|
---|
| 3935 | has_in = "0";
|
---|
| 3936 | capture = "0";
|
---|
| 3937 | edge_type = "NONE";
|
---|
| 3938 | irq_type = "NONE";
|
---|
| 3939 | Do_Test_Bench_Wiring = "0";
|
---|
| 3940 | Driven_Sim_Value = "0x0000";
|
---|
| 3941 | }
|
---|
| 3942 | }
|
---|
| 3943 | MODULE sys_clk_timer
|
---|
| 3944 | {
|
---|
| 3945 | class = "altera_avalon_timer";
|
---|
| 3946 | class_version = "6.05";
|
---|
| 3947 | iss_model_name = "altera_avalon_timer";
|
---|
| 3948 | SLAVE s1
|
---|
| 3949 | {
|
---|
| 3950 | SYSTEM_BUILDER_INFO
|
---|
| 3951 | {
|
---|
| 3952 | Bus_Type = "avalon";
|
---|
| 3953 | Is_Printable_Device = "0";
|
---|
| 3954 | Address_Alignment = "native";
|
---|
| 3955 | Address_Width = "3";
|
---|
| 3956 | Data_Width = "16";
|
---|
| 3957 | Has_IRQ = "1";
|
---|
| 3958 | Read_Wait_States = "1";
|
---|
| 3959 | Write_Wait_States = "0";
|
---|
| 3960 | Base_Address = "0x08010800";
|
---|
| 3961 | MASTERED_BY cpu/data_master
|
---|
| 3962 | {
|
---|
| 3963 | priority = "1";
|
---|
| 3964 | }
|
---|
| 3965 | IRQ_MASTER cpu/data_master
|
---|
| 3966 | {
|
---|
| 3967 | IRQ_Number = "1";
|
---|
| 3968 | }
|
---|
| 3969 | Address_Group = "0";
|
---|
| 3970 | }
|
---|
| 3971 | PORT_WIRING
|
---|
| 3972 | {
|
---|
| 3973 | PORT address
|
---|
| 3974 | {
|
---|
| 3975 | direction = "input";
|
---|
| 3976 | type = "address";
|
---|
| 3977 | width = "3";
|
---|
| 3978 | Is_Enabled = "1";
|
---|
| 3979 | }
|
---|
| 3980 | PORT chipselect
|
---|
| 3981 | {
|
---|
| 3982 | direction = "input";
|
---|
| 3983 | type = "chipselect";
|
---|
| 3984 | width = "1";
|
---|
| 3985 | Is_Enabled = "1";
|
---|
| 3986 | }
|
---|
| 3987 | PORT clk
|
---|
| 3988 | {
|
---|
| 3989 | direction = "input";
|
---|
| 3990 | type = "clk";
|
---|
| 3991 | width = "1";
|
---|
| 3992 | Is_Enabled = "1";
|
---|
| 3993 | }
|
---|
| 3994 | PORT irq
|
---|
| 3995 | {
|
---|
| 3996 | direction = "output";
|
---|
| 3997 | type = "irq";
|
---|
| 3998 | width = "1";
|
---|
| 3999 | Is_Enabled = "1";
|
---|
| 4000 | }
|
---|
| 4001 | PORT readdata
|
---|
| 4002 | {
|
---|
| 4003 | direction = "output";
|
---|
| 4004 | type = "readdata";
|
---|
| 4005 | width = "16";
|
---|
| 4006 | Is_Enabled = "1";
|
---|
| 4007 | }
|
---|
| 4008 | PORT reset_n
|
---|
| 4009 | {
|
---|
| 4010 | direction = "input";
|
---|
| 4011 | type = "reset_n";
|
---|
| 4012 | width = "1";
|
---|
| 4013 | Is_Enabled = "1";
|
---|
| 4014 | }
|
---|
| 4015 | PORT write_n
|
---|
| 4016 | {
|
---|
| 4017 | direction = "input";
|
---|
| 4018 | type = "write_n";
|
---|
| 4019 | width = "1";
|
---|
| 4020 | Is_Enabled = "1";
|
---|
| 4021 | }
|
---|
| 4022 | PORT writedata
|
---|
| 4023 | {
|
---|
| 4024 | direction = "input";
|
---|
| 4025 | type = "writedata";
|
---|
| 4026 | width = "16";
|
---|
| 4027 | Is_Enabled = "1";
|
---|
| 4028 | }
|
---|
| 4029 | }
|
---|
| 4030 | }
|
---|
| 4031 | SYSTEM_BUILDER_INFO
|
---|
| 4032 | {
|
---|
| 4033 | Instantiate_In_System_Module = "1";
|
---|
| 4034 | Is_Enabled = "1";
|
---|
| 4035 | View
|
---|
| 4036 | {
|
---|
| 4037 | Settings_Summary = "Timer with 1 ms timeout period.";
|
---|
| 4038 | MESSAGES
|
---|
| 4039 | {
|
---|
| 4040 | }
|
---|
| 4041 | Is_Collapsed = "1";
|
---|
| 4042 | }
|
---|
| 4043 | Clock_Source = "clk";
|
---|
| 4044 | Top_Level_Ports_Are_Enumerated = "1";
|
---|
| 4045 | }
|
---|
| 4046 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 4047 | {
|
---|
| 4048 | always_run = "0";
|
---|
| 4049 | fixed_period = "0";
|
---|
| 4050 | snapshot = "1";
|
---|
| 4051 | period = "1";
|
---|
| 4052 | period_units = "ms";
|
---|
| 4053 | reset_output = "0";
|
---|
| 4054 | timeout_pulse_output = "0";
|
---|
| 4055 | mult = "0.001";
|
---|
| 4056 | }
|
---|
| 4057 | HDL_INFO
|
---|
| 4058 | {
|
---|
| 4059 | Simulation_HDL_Files = "";
|
---|
| 4060 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sys_clk_timer.vhd";
|
---|
| 4061 | Precompiled_Simulation_Library_Files = "";
|
---|
| 4062 | Synthesis_Only_Files = "";
|
---|
| 4063 | }
|
---|
| 4064 | PORT_WIRING
|
---|
| 4065 | {
|
---|
| 4066 | }
|
---|
| 4067 | }
|
---|
| 4068 | MODULE sysid
|
---|
| 4069 | {
|
---|
| 4070 | class = "altera_avalon_sysid";
|
---|
| 4071 | class_version = "6.05";
|
---|
| 4072 | HDL_INFO
|
---|
| 4073 | {
|
---|
| 4074 | Simulation_HDL_Files = "";
|
---|
| 4075 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.vhd";
|
---|
| 4076 | Precompiled_Simulation_Library_Files = "";
|
---|
| 4077 | Synthesis_Only_Files = "";
|
---|
| 4078 | }
|
---|
| 4079 | PORT_WIRING
|
---|
| 4080 | {
|
---|
| 4081 | }
|
---|
| 4082 | SLAVE control_slave
|
---|
| 4083 | {
|
---|
| 4084 | PORT_WIRING
|
---|
| 4085 | {
|
---|
| 4086 | PORT address
|
---|
| 4087 | {
|
---|
| 4088 | direction = "input";
|
---|
| 4089 | type = "address";
|
---|
| 4090 | width = "1";
|
---|
| 4091 | Is_Enabled = "1";
|
---|
| 4092 | }
|
---|
| 4093 | PORT readdata
|
---|
| 4094 | {
|
---|
| 4095 | direction = "output";
|
---|
| 4096 | type = "readdata";
|
---|
| 4097 | width = "32";
|
---|
| 4098 | Is_Enabled = "1";
|
---|
| 4099 | }
|
---|
| 4100 | }
|
---|
| 4101 | SYSTEM_BUILDER_INFO
|
---|
| 4102 | {
|
---|
| 4103 | Bus_Type = "avalon";
|
---|
| 4104 | Has_IRQ = "0";
|
---|
| 4105 | Address_Width = "1";
|
---|
| 4106 | Data_Width = "32";
|
---|
| 4107 | Base_Address = "0x08010828";
|
---|
| 4108 | Address_Alignment = "native";
|
---|
| 4109 | Read_Wait_States = "1";
|
---|
| 4110 | Write_Wait_States = "0";
|
---|
| 4111 | Read_Latency = "0";
|
---|
| 4112 | MASTERED_BY cpu/data_master
|
---|
| 4113 | {
|
---|
| 4114 | priority = "1";
|
---|
| 4115 | }
|
---|
| 4116 | IRQ_MASTER cpu/data_master
|
---|
| 4117 | {
|
---|
| 4118 | IRQ_Number = "NC";
|
---|
| 4119 | }
|
---|
| 4120 | Address_Group = "0";
|
---|
| 4121 | }
|
---|
| 4122 | }
|
---|
| 4123 | SYSTEM_BUILDER_INFO
|
---|
| 4124 | {
|
---|
| 4125 | Date_Modified = "";
|
---|
| 4126 | Is_Enabled = "1";
|
---|
| 4127 | Instantiate_In_System_Module = "1";
|
---|
| 4128 | Fixed_Module_Name = "sysid";
|
---|
| 4129 | View
|
---|
| 4130 | {
|
---|
| 4131 | Settings_Summary = "System ID (at last Generate):<br> <b>A957D3F3</b> (unique ID tag) <br> <b>4739914A</b> (timestamp: Tue Nov 13, 2007 @8:58 PM)";
|
---|
| 4132 | Is_Collapsed = "1";
|
---|
| 4133 | MESSAGES
|
---|
| 4134 | {
|
---|
| 4135 | }
|
---|
| 4136 | }
|
---|
| 4137 | Clock_Source = "clk";
|
---|
| 4138 | Top_Level_Ports_Are_Enumerated = "1";
|
---|
| 4139 | }
|
---|
| 4140 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 4141 | {
|
---|
| 4142 | value0 = "3165772932u";
|
---|
| 4143 | value1 = "1077149968u";
|
---|
| 4144 | MAKE
|
---|
| 4145 | {
|
---|
| 4146 | TARGET verifysysid
|
---|
| 4147 | {
|
---|
| 4148 | verifysysid
|
---|
| 4149 | {
|
---|
| 4150 | All_Depends_On = "0";
|
---|
| 4151 | Command = "nios2-download $(JTAG_CABLE) --sidp=0x08010828 --id=2841105395 --timestamp=1194955082";
|
---|
| 4152 | Target_File = "dummy_verifysysid_file";
|
---|
| 4153 | Is_Phony = "1";
|
---|
| 4154 | }
|
---|
| 4155 | }
|
---|
| 4156 | }
|
---|
| 4157 | id = "2841105395u";
|
---|
| 4158 | timestamp = "1194955082u";
|
---|
| 4159 | }
|
---|
| 4160 | }
|
---|
| 4161 | MODULE uart1
|
---|
| 4162 | {
|
---|
| 4163 | class = "altera_avalon_uart";
|
---|
| 4164 | class_version = "6.05";
|
---|
| 4165 | iss_model_name = "altera_avalon_uart";
|
---|
| 4166 | SLAVE s1
|
---|
| 4167 | {
|
---|
| 4168 | SYSTEM_BUILDER_INFO
|
---|
| 4169 | {
|
---|
| 4170 | Bus_Type = "avalon";
|
---|
| 4171 | Is_Printable_Device = "1";
|
---|
| 4172 | Address_Alignment = "native";
|
---|
| 4173 | Address_Width = "3";
|
---|
| 4174 | Data_Width = "16";
|
---|
| 4175 | Has_IRQ = "1";
|
---|
| 4176 | Read_Wait_States = "1";
|
---|
| 4177 | Write_Wait_States = "1";
|
---|
| 4178 | Base_Address = "0x08010840";
|
---|
| 4179 | MASTERED_BY cpu/data_master
|
---|
| 4180 | {
|
---|
| 4181 | priority = "1";
|
---|
| 4182 | }
|
---|
| 4183 | IRQ_MASTER cpu/data_master
|
---|
| 4184 | {
|
---|
| 4185 | IRQ_Number = "3";
|
---|
| 4186 | }
|
---|
| 4187 | Address_Group = "0";
|
---|
| 4188 | }
|
---|
| 4189 | PORT_WIRING
|
---|
| 4190 | {
|
---|
| 4191 | PORT address
|
---|
| 4192 | {
|
---|
| 4193 | direction = "input";
|
---|
| 4194 | type = "address";
|
---|
| 4195 | width = "3";
|
---|
| 4196 | Is_Enabled = "1";
|
---|
| 4197 | }
|
---|
| 4198 | PORT begintransfer
|
---|
| 4199 | {
|
---|
| 4200 | direction = "input";
|
---|
| 4201 | type = "begintransfer";
|
---|
| 4202 | width = "1";
|
---|
| 4203 | Is_Enabled = "1";
|
---|
| 4204 | }
|
---|
| 4205 | PORT chipselect
|
---|
| 4206 | {
|
---|
| 4207 | direction = "input";
|
---|
| 4208 | type = "chipselect";
|
---|
| 4209 | width = "1";
|
---|
| 4210 | Is_Enabled = "1";
|
---|
| 4211 | }
|
---|
| 4212 | PORT clk
|
---|
| 4213 | {
|
---|
| 4214 | direction = "input";
|
---|
| 4215 | type = "clk";
|
---|
| 4216 | width = "1";
|
---|
| 4217 | Is_Enabled = "1";
|
---|
| 4218 | }
|
---|
| 4219 | PORT dataavailable
|
---|
| 4220 | {
|
---|
| 4221 | direction = "output";
|
---|
| 4222 | type = "dataavailable";
|
---|
| 4223 | width = "1";
|
---|
| 4224 | Is_Enabled = "1";
|
---|
| 4225 | }
|
---|
| 4226 | PORT irq
|
---|
| 4227 | {
|
---|
| 4228 | direction = "output";
|
---|
| 4229 | type = "irq";
|
---|
| 4230 | width = "1";
|
---|
| 4231 | Is_Enabled = "1";
|
---|
| 4232 | }
|
---|
| 4233 | PORT read_n
|
---|
| 4234 | {
|
---|
| 4235 | direction = "input";
|
---|
| 4236 | type = "read_n";
|
---|
| 4237 | width = "1";
|
---|
| 4238 | Is_Enabled = "1";
|
---|
| 4239 | }
|
---|
| 4240 | PORT readdata
|
---|
| 4241 | {
|
---|
| 4242 | direction = "output";
|
---|
| 4243 | type = "readdata";
|
---|
| 4244 | width = "16";
|
---|
| 4245 | Is_Enabled = "1";
|
---|
| 4246 | }
|
---|
| 4247 | PORT readyfordata
|
---|
| 4248 | {
|
---|
| 4249 | direction = "output";
|
---|
| 4250 | type = "readyfordata";
|
---|
| 4251 | width = "1";
|
---|
| 4252 | Is_Enabled = "1";
|
---|
| 4253 | }
|
---|
| 4254 | PORT reset_n
|
---|
| 4255 | {
|
---|
| 4256 | direction = "input";
|
---|
| 4257 | type = "reset_n";
|
---|
| 4258 | width = "1";
|
---|
| 4259 | Is_Enabled = "1";
|
---|
| 4260 | }
|
---|
| 4261 | PORT write_n
|
---|
| 4262 | {
|
---|
| 4263 | direction = "input";
|
---|
| 4264 | type = "write_n";
|
---|
| 4265 | width = "1";
|
---|
| 4266 | Is_Enabled = "1";
|
---|
| 4267 | }
|
---|
| 4268 | PORT writedata
|
---|
| 4269 | {
|
---|
| 4270 | direction = "input";
|
---|
| 4271 | type = "writedata";
|
---|
| 4272 | width = "16";
|
---|
| 4273 | Is_Enabled = "1";
|
---|
| 4274 | }
|
---|
| 4275 | }
|
---|
| 4276 | }
|
---|
| 4277 | SYSTEM_BUILDER_INFO
|
---|
| 4278 | {
|
---|
| 4279 | Instantiate_In_System_Module = "1";
|
---|
| 4280 | Is_Enabled = "1";
|
---|
| 4281 | Iss_Launch_Telnet = "0";
|
---|
| 4282 | View
|
---|
| 4283 | {
|
---|
| 4284 | Settings_Summary = "8-bit UART with 115200 baud, <br>
|
---|
| 4285 | 1 stop bits and N parity";
|
---|
| 4286 | MESSAGES
|
---|
| 4287 | {
|
---|
| 4288 | }
|
---|
| 4289 | Is_Collapsed = "1";
|
---|
| 4290 | }
|
---|
| 4291 | Clock_Source = "clk";
|
---|
| 4292 | Top_Level_Ports_Are_Enumerated = "1";
|
---|
| 4293 | }
|
---|
| 4294 | SIMULATION
|
---|
| 4295 | {
|
---|
| 4296 | DISPLAY
|
---|
| 4297 | {
|
---|
| 4298 | SIGNAL a
|
---|
| 4299 | {
|
---|
| 4300 | name = " Bus Interface";
|
---|
| 4301 | format = "Divider";
|
---|
| 4302 | }
|
---|
| 4303 | SIGNAL b
|
---|
| 4304 | {
|
---|
| 4305 | name = "chipselect";
|
---|
| 4306 | }
|
---|
| 4307 | SIGNAL c
|
---|
| 4308 | {
|
---|
| 4309 | name = "address";
|
---|
| 4310 | radix = "hexadecimal";
|
---|
| 4311 | }
|
---|
| 4312 | SIGNAL d
|
---|
| 4313 | {
|
---|
| 4314 | name = "writedata";
|
---|
| 4315 | radix = "hexadecimal";
|
---|
| 4316 | }
|
---|
| 4317 | SIGNAL e
|
---|
| 4318 | {
|
---|
| 4319 | name = "readdata";
|
---|
| 4320 | radix = "hexadecimal";
|
---|
| 4321 | }
|
---|
| 4322 | SIGNAL f
|
---|
| 4323 | {
|
---|
| 4324 | name = " Internals";
|
---|
| 4325 | format = "Divider";
|
---|
| 4326 | }
|
---|
| 4327 | SIGNAL g
|
---|
| 4328 | {
|
---|
| 4329 | name = "tx_ready";
|
---|
| 4330 | }
|
---|
| 4331 | SIGNAL h
|
---|
| 4332 | {
|
---|
| 4333 | name = "tx_data";
|
---|
| 4334 | radix = "ascii";
|
---|
| 4335 | }
|
---|
| 4336 | SIGNAL i
|
---|
| 4337 | {
|
---|
| 4338 | name = "rx_char_ready";
|
---|
| 4339 | }
|
---|
| 4340 | SIGNAL j
|
---|
| 4341 | {
|
---|
| 4342 | name = "rx_data";
|
---|
| 4343 | radix = "ascii";
|
---|
| 4344 | }
|
---|
| 4345 | }
|
---|
| 4346 | INTERACTIVE_OUT log
|
---|
| 4347 | {
|
---|
| 4348 | enable = "0";
|
---|
| 4349 | file = "_log_module.txt";
|
---|
| 4350 | radix = "ascii";
|
---|
| 4351 | signals = "temp,list";
|
---|
| 4352 | exe = "perl -- tail-f.pl";
|
---|
| 4353 | }
|
---|
| 4354 | INTERACTIVE_IN drive
|
---|
| 4355 | {
|
---|
| 4356 | enable = "0";
|
---|
| 4357 | file = "_input_data_stream.dat";
|
---|
| 4358 | mutex = "_input_data_mutex.dat";
|
---|
| 4359 | log = "_in.log";
|
---|
| 4360 | rate = "100";
|
---|
| 4361 | signals = "temp,list";
|
---|
| 4362 | exe = "perl -- uart.pl";
|
---|
| 4363 | }
|
---|
| 4364 | }
|
---|
| 4365 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 4366 | {
|
---|
| 4367 | baud = "115200";
|
---|
| 4368 | data_bits = "8";
|
---|
| 4369 | fixed_baud = "1";
|
---|
| 4370 | parity = "N";
|
---|
| 4371 | stop_bits = "1";
|
---|
| 4372 | use_cts_rts = "0";
|
---|
| 4373 | use_eop_register = "0";
|
---|
| 4374 | sim_true_baud = "0";
|
---|
| 4375 | sim_char_stream = "";
|
---|
| 4376 | }
|
---|
| 4377 | HDL_INFO
|
---|
| 4378 | {
|
---|
| 4379 | Simulation_HDL_Files = "";
|
---|
| 4380 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart1.vhd";
|
---|
| 4381 | Precompiled_Simulation_Library_Files = "";
|
---|
| 4382 | Synthesis_Only_Files = "";
|
---|
| 4383 | }
|
---|
| 4384 | PORT_WIRING
|
---|
| 4385 | {
|
---|
| 4386 | PORT rxd
|
---|
| 4387 | {
|
---|
| 4388 | direction = "input";
|
---|
| 4389 | width = "1";
|
---|
| 4390 | Is_Enabled = "1";
|
---|
| 4391 | }
|
---|
| 4392 | PORT txd
|
---|
| 4393 | {
|
---|
| 4394 | direction = "output";
|
---|
| 4395 | width = "1";
|
---|
| 4396 | Is_Enabled = "1";
|
---|
| 4397 | }
|
---|
| 4398 | PORT cts_n
|
---|
| 4399 | {
|
---|
| 4400 | direction = "input";
|
---|
| 4401 | width = "1";
|
---|
| 4402 | Is_Enabled = "0";
|
---|
| 4403 | }
|
---|
| 4404 | PORT rts_n
|
---|
| 4405 | {
|
---|
| 4406 | direction = "output";
|
---|
| 4407 | width = "1";
|
---|
| 4408 | Is_Enabled = "0";
|
---|
| 4409 | }
|
---|
| 4410 | }
|
---|
| 4411 | }
|
---|
| 4412 | MODULE vga_16_bit
|
---|
| 4413 | {
|
---|
| 4414 | class = "altera_avalon_16_bit_vga";
|
---|
| 4415 | class_version = "2.0";
|
---|
| 4416 | HDL_INFO
|
---|
| 4417 | {
|
---|
| 4418 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/image_package.vhd,__PROJECT_DIRECTORY__/vga_register_bank.vhd,__PROJECT_DIRECTORY__/line_buffer.vhd,__PROJECT_DIRECTORY__/image_dma.vhd,__PROJECT_DIRECTORY__/vga_driver.vhd,__PROJECT_DIRECTORY__/altera_avalon_16_bit_vga.vhd,__PROJECT_DIRECTORY__/vga_16_bit.vhd";
|
---|
| 4419 | Simulation_HDL_Files = "";
|
---|
| 4420 | Precompiled_Simulation_Library_Files = "";
|
---|
| 4421 | Synthesis_Only_Files = "";
|
---|
| 4422 | vhdl_Sim_Model_Files = "";
|
---|
| 4423 | }
|
---|
| 4424 | MASTER image_dma_master
|
---|
| 4425 | {
|
---|
| 4426 | SYSTEM_BUILDER_INFO
|
---|
| 4427 | {
|
---|
| 4428 | Bus_Type = "avalon";
|
---|
| 4429 | Address_Width = "32";
|
---|
| 4430 | Data_Width = "32";
|
---|
| 4431 | Is_Enabled = "1";
|
---|
| 4432 | Interrupts_Enabled = "0";
|
---|
| 4433 | }
|
---|
| 4434 | PORT_WIRING
|
---|
| 4435 | {
|
---|
| 4436 | PORT read_to_sram
|
---|
| 4437 | {
|
---|
| 4438 | type = "read";
|
---|
| 4439 | direction = "output";
|
---|
| 4440 | width = "1";
|
---|
| 4441 | }
|
---|
| 4442 | PORT address_to_sram
|
---|
| 4443 | {
|
---|
| 4444 | type = "address";
|
---|
| 4445 | direction = "output";
|
---|
| 4446 | width = "32";
|
---|
| 4447 | }
|
---|
| 4448 | PORT data_from_sram
|
---|
| 4449 | {
|
---|
| 4450 | type = "readdata";
|
---|
| 4451 | direction = "input";
|
---|
| 4452 | width = "32";
|
---|
| 4453 | }
|
---|
| 4454 | PORT waitrequest
|
---|
| 4455 | {
|
---|
| 4456 | type = "waitrequest";
|
---|
| 4457 | direction = "input";
|
---|
| 4458 | width = "1";
|
---|
| 4459 | }
|
---|
| 4460 | PORT readdatavalid
|
---|
| 4461 | {
|
---|
| 4462 | type = "readdatavalid";
|
---|
| 4463 | direction = "input";
|
---|
| 4464 | width = "1";
|
---|
| 4465 | }
|
---|
| 4466 | }
|
---|
| 4467 | }
|
---|
| 4468 | SLAVE config_slave
|
---|
| 4469 | {
|
---|
| 4470 | SYSTEM_BUILDER_INFO
|
---|
| 4471 | {
|
---|
| 4472 | Bus_Type = "avalon";
|
---|
| 4473 | Address_Width = "3";
|
---|
| 4474 | Data_Width = "32";
|
---|
| 4475 | Has_IRQ = "1";
|
---|
| 4476 | Address_Alignment = "dynamic";
|
---|
| 4477 | Read_Wait_States = "1";
|
---|
| 4478 | Write_Wait_States = "0";
|
---|
| 4479 | MASTERED_BY cpu/data_master
|
---|
| 4480 | {
|
---|
| 4481 | priority = "1";
|
---|
| 4482 | }
|
---|
| 4483 | IRQ_MASTER cpu/data_master
|
---|
| 4484 | {
|
---|
| 4485 | IRQ_Number = "6";
|
---|
| 4486 | }
|
---|
| 4487 | Base_Address = "0x080108C0";
|
---|
| 4488 | Address_Group = "0";
|
---|
| 4489 | }
|
---|
| 4490 | PORT_WIRING
|
---|
| 4491 | {
|
---|
| 4492 | PORT clk
|
---|
| 4493 | {
|
---|
| 4494 | width = "1";
|
---|
| 4495 | direction = "input";
|
---|
| 4496 | type = "clk";
|
---|
| 4497 | }
|
---|
| 4498 | PORT chipselect_config
|
---|
| 4499 | {
|
---|
| 4500 | direction = "input";
|
---|
| 4501 | type = "chipselect";
|
---|
| 4502 | width = "1";
|
---|
| 4503 | }
|
---|
| 4504 | PORT address_config
|
---|
| 4505 | {
|
---|
| 4506 | direction = "input";
|
---|
| 4507 | is_shared = "1";
|
---|
| 4508 | type = "address";
|
---|
| 4509 | width = "3";
|
---|
| 4510 | }
|
---|
| 4511 | PORT read_config
|
---|
| 4512 | {
|
---|
| 4513 | type = "read";
|
---|
| 4514 | direction = "input";
|
---|
| 4515 | width = "1";
|
---|
| 4516 | }
|
---|
| 4517 | PORT readdata_config
|
---|
| 4518 | {
|
---|
| 4519 | type = "readdata";
|
---|
| 4520 | direction = "output";
|
---|
| 4521 | width = "32";
|
---|
| 4522 | }
|
---|
| 4523 | PORT write_config
|
---|
| 4524 | {
|
---|
| 4525 | type = "write";
|
---|
| 4526 | direction = "input";
|
---|
| 4527 | width = "1";
|
---|
| 4528 | }
|
---|
| 4529 | PORT writedata_config
|
---|
| 4530 | {
|
---|
| 4531 | type = "writedata";
|
---|
| 4532 | direction = "input";
|
---|
| 4533 | width = "32";
|
---|
| 4534 | }
|
---|
| 4535 | PORT irq
|
---|
| 4536 | {
|
---|
| 4537 | type = "irq";
|
---|
| 4538 | direction = "output";
|
---|
| 4539 | width = "1";
|
---|
| 4540 | }
|
---|
| 4541 | }
|
---|
| 4542 | }
|
---|
| 4543 | SYSTEM_BUILDER_INFO
|
---|
| 4544 | {
|
---|
| 4545 | Instantiate_In_System_Module = "1";
|
---|
| 4546 | Is_Enabled = "1";
|
---|
| 4547 | View
|
---|
| 4548 | {
|
---|
| 4549 | Is_Collapsed = "0";
|
---|
| 4550 | MESSAGES
|
---|
| 4551 | {
|
---|
| 4552 | }
|
---|
| 4553 | }
|
---|
| 4554 | Clock_Source = "clk";
|
---|
| 4555 | }
|
---|
| 4556 | SIMULATION
|
---|
| 4557 | {
|
---|
| 4558 | }
|
---|
| 4559 | PORT_WIRING
|
---|
| 4560 | {
|
---|
| 4561 | PORT vga_clk
|
---|
| 4562 | {
|
---|
| 4563 | direction = "input";
|
---|
| 4564 | width = "1";
|
---|
| 4565 | }
|
---|
| 4566 | PORT clock25
|
---|
| 4567 | {
|
---|
| 4568 | direction = "input";
|
---|
| 4569 | width = "1";
|
---|
| 4570 | }
|
---|
| 4571 | PORT resetn
|
---|
| 4572 | {
|
---|
| 4573 | direction = "input";
|
---|
| 4574 | width = "1";
|
---|
| 4575 | }
|
---|
| 4576 | PORT vga_clock_external
|
---|
| 4577 | {
|
---|
| 4578 | direction = "output";
|
---|
| 4579 | width = "1";
|
---|
| 4580 | }
|
---|
| 4581 | PORT hsync
|
---|
| 4582 | {
|
---|
| 4583 | direction = "output";
|
---|
| 4584 | width = "1";
|
---|
| 4585 | }
|
---|
| 4586 | PORT vsync
|
---|
| 4587 | {
|
---|
| 4588 | direction = "output";
|
---|
| 4589 | width = "1";
|
---|
| 4590 | }
|
---|
| 4591 | PORT M1
|
---|
| 4592 | {
|
---|
| 4593 | direction = "output";
|
---|
| 4594 | width = "1";
|
---|
| 4595 | }
|
---|
| 4596 | PORT M2
|
---|
| 4597 | {
|
---|
| 4598 | direction = "output";
|
---|
| 4599 | width = "1";
|
---|
| 4600 | }
|
---|
| 4601 | PORT sync_n
|
---|
| 4602 | {
|
---|
| 4603 | direction = "output";
|
---|
| 4604 | width = "1";
|
---|
| 4605 | }
|
---|
| 4606 | PORT sync_t
|
---|
| 4607 | {
|
---|
| 4608 | direction = "output";
|
---|
| 4609 | width = "1";
|
---|
| 4610 | }
|
---|
| 4611 | PORT blank_n
|
---|
| 4612 | {
|
---|
| 4613 | direction = "output";
|
---|
| 4614 | width = "1";
|
---|
| 4615 | }
|
---|
| 4616 | PORT R
|
---|
| 4617 | {
|
---|
| 4618 | direction = "output";
|
---|
| 4619 | width = "8";
|
---|
| 4620 | }
|
---|
| 4621 | PORT G
|
---|
| 4622 | {
|
---|
| 4623 | direction = "output";
|
---|
| 4624 | width = "8";
|
---|
| 4625 | }
|
---|
| 4626 | PORT B
|
---|
| 4627 | {
|
---|
| 4628 | direction = "output";
|
---|
| 4629 | width = "8";
|
---|
| 4630 | }
|
---|
| 4631 | }
|
---|
| 4632 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 4633 | {
|
---|
| 4634 | }
|
---|
| 4635 | }
|
---|
| 4636 | MODULE interruptvector_cpu
|
---|
| 4637 | {
|
---|
| 4638 | class = "altera_nios_custom_instr_interrupt_vector";
|
---|
| 4639 | class_version = "6.05";
|
---|
| 4640 | iss_model_name = "nios2_custom_instruction";
|
---|
| 4641 | HDL_INFO
|
---|
| 4642 | {
|
---|
| 4643 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/interruptvector_cpu.vhd";
|
---|
| 4644 | Precompiled_Simulation_Library_Files = "";
|
---|
| 4645 | Simulation_HDL_Files = "";
|
---|
| 4646 | Synthesis_Only_Files = "";
|
---|
| 4647 | }
|
---|
| 4648 | SLAVE interrupt_vector
|
---|
| 4649 | {
|
---|
| 4650 | PORT_WIRING
|
---|
| 4651 | {
|
---|
| 4652 | PORT estatus
|
---|
| 4653 | {
|
---|
| 4654 | Is_Enabled = "1";
|
---|
| 4655 | direction = "input";
|
---|
| 4656 | type = "estatus";
|
---|
| 4657 | width = "1";
|
---|
| 4658 | }
|
---|
| 4659 | PORT ipending
|
---|
| 4660 | {
|
---|
| 4661 | Is_Enabled = "1";
|
---|
| 4662 | direction = "input";
|
---|
| 4663 | type = "ipending";
|
---|
| 4664 | width = "32";
|
---|
| 4665 | }
|
---|
| 4666 | PORT result
|
---|
| 4667 | {
|
---|
| 4668 | Is_Enabled = "1";
|
---|
| 4669 | direction = "output";
|
---|
| 4670 | type = "result";
|
---|
| 4671 | width = "32";
|
---|
| 4672 | }
|
---|
| 4673 | }
|
---|
| 4674 | SYSTEM_BUILDER_INFO
|
---|
| 4675 | {
|
---|
| 4676 | Bus_Type = "nios_custom_instruction";
|
---|
| 4677 | Data_Width = "32";
|
---|
| 4678 | Address_Width = "0";
|
---|
| 4679 | Is_Custom_Instruction = "1";
|
---|
| 4680 | Is_Visible = "0";
|
---|
| 4681 | Is_Enabled = "1";
|
---|
| 4682 | ci_macro_name = "interrupt_vector";
|
---|
| 4683 | required_ci_macro_name = "interrupt_vector";
|
---|
| 4684 | ci_inst_type = "combinatorial";
|
---|
| 4685 | ci_operands = "0";
|
---|
| 4686 | MASTERED_BY cpu/custom_instruction_master
|
---|
| 4687 | {
|
---|
| 4688 | priority = "1";
|
---|
| 4689 | }
|
---|
| 4690 | Base_Address = "0x00000000";
|
---|
| 4691 | Address_Group = "0";
|
---|
| 4692 | IRQ_MASTER cpu/custom_instruction_master
|
---|
| 4693 | {
|
---|
| 4694 | IRQ_Number = "NC";
|
---|
| 4695 | }
|
---|
| 4696 | }
|
---|
| 4697 | }
|
---|
| 4698 | SYSTEM_BUILDER_INFO
|
---|
| 4699 | {
|
---|
| 4700 | Date_Modified = "";
|
---|
| 4701 | Is_Enabled = "1";
|
---|
| 4702 | Is_Visible = "0";
|
---|
| 4703 | Instantiate_In_System_Module = "1";
|
---|
| 4704 | Is_Custom_Instruction = "1";
|
---|
| 4705 | Clock_Source = "clk";
|
---|
| 4706 | View
|
---|
| 4707 | {
|
---|
| 4708 | MESSAGES
|
---|
| 4709 | {
|
---|
| 4710 | }
|
---|
| 4711 | }
|
---|
| 4712 | }
|
---|
| 4713 | WIZARD_SCRIPT_ARGUMENTS
|
---|
| 4714 | {
|
---|
| 4715 | Module_Name = "interrupt_vector";
|
---|
| 4716 | Synthesize_Imported_HDL = "1";
|
---|
| 4717 | }
|
---|
| 4718 | PORT_WIRING
|
---|
| 4719 | {
|
---|
| 4720 | }
|
---|
| 4721 | }
|
---|
| 4722 | }
|
---|