[61] | 1 | /*
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| 2 | * TOPPERS Software
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems
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| 4 | *
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| 5 | * Copyright (C) 2007-2009 by Embedded and Real-Time Systems Laboratory
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| 6 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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| 7 | *
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| 8 | * ãLì ÒÍCȺÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
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| 9 | * Ai{\tgEFAðüϵ½àÌðÜÞDȺ¯¶jðgpE¡»Eü
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| 10 | * ÏEÄzziȺCpÆÄÔj·é±Æð³Åø·éD
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| 11 | * (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
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| 12 | * \¦C±Ìpð¨æѺL̳ÛØKèªC»ÌÜÜÌ`Å\[
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| 13 | * XR[hÉÜÜêÄ¢é±ÆD
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| 14 | * (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJÉg
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| 15 | * pÅ«é`ÅÄzz·éêÉÍCÄzzɺ¤hL
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| 16 | gip
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| 17 | * Ò}j
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| 18 | AÈÇjÉCãLÌì \¦C±Ìpð¨æѺL
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| 19 | * ̳ÛØKèðfÚ·é±ÆD
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| 20 | * (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJÉg
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| 21 | * pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
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| 22 | * ÆD
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| 23 | * (a) Äzzɺ¤hL
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| 24 | gipÒ}j
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| 25 | AÈÇjÉCãLÌ
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| 26 | * ì \¦C±Ìpð¨æѺL̳ÛØKèðfÚ·é±ÆD
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| 27 | * (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
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| 28 | * ñ·é±ÆD
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| 29 | * (4) {\tgEFAÌpÉæè¼ÚIܽÍÔÚIɶ¶é¢©Èé¹
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| 30 | * Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
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| 31 | * ܽC{\tgEFAÌ[UܽÍGh[U©çÌ¢©Èé
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| 32 | * RÉîÿ©çàCãLì Ò¨æÑTOPPERSvWFNgð
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| 33 | * ÆÓ·é±ÆD
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| 34 | *
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| 35 | * {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
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| 36 | * æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
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| 37 | * ÉηéK«àÜßÄC¢©ÈéÛØàsíÈ¢DܽC{\tgEF
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| 38 | * AÌpÉæè¼ÚIܽÍÔÚIɶ¶½¢©Èé¹QÉÖµÄàC»
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| 39 | * ÌÓCðíÈ¢D
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| 40 | *
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| 41 | * @(#) $Id: test_cpuexc11.c 2005 2010-12-31 04:20:08Z ertl-hiro $
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| 42 | */
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| 43 |
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| 44 | /*
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| 45 | * CPUáOÌeXg(11)
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| 46 | *
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| 47 | * yeXgÌÚIz
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| 48 | *
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| 49 | * ÝDæx}XNTIPM_ENAALLCfBXpb`ÂóÔC^XNáO
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| 50 | * ÂóÔŶµ½CPUáOɨ¯éVXeóÔÌeXgD^XNØ·¦É
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| 51 | * æèJo[Å«é±ÆàeXg·éD
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| 52 | *
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| 53 | * yeXgÚz
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| 54 | *
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| 55 | * ¢¸êàCÝDæx}XNTIPM_ENAALLCfBXpb`ÂóÔC^
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| 56 | * XNáOÂóÔŶµ½CPUáOɨ¢ÄC
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| 57 | *
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| 58 | * (A) CPUáOnhÀsJnÉCPUbNtOªÏ»µÈ¢±Æ
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| 59 | * (B) CPUáOnhÀsJnÉÝDæx}XNªÏ»µÈ¢±Æ
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| 60 | * ICPUáOnhÅÝDæx}XNðÇßÈ¢½ßCeXgÅ
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| 61 | * «È¢D
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| 62 | * (C) CPUáOnhÀsJnÉfBXpb`Ö~tOªÏ»µÈ¢±Æ
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| 63 | * (D) CPUáOnhÀsJnÉ^XNáOÖ~tOªÏ»µÈ¢±Æ
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| 64 | * (E) CPUáOnh^[ÉCPUbNtOª³Éßé±Æ
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| 65 | * (F) CPUáOnh^[ÉÝDæx}XNª³Éßé±Æ
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| 66 | * (G) CPUáOnh^[ÉfBXpb`Ö~tOªÏ»µÈ¢±Æ
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| 67 | * (H) CPUáOnh^[É^XNáOÖ~tOªÏ»µÈ¢±Æ
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| 68 | * (I) xsns_xpnªfalseðÔ·±Æ
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| 69 | * (J) xsns_dpnªfalseðÔ·±Æ
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| 70 | * (K) ^XNØ·¦ÉæéJo[ªÅ«é±Æ
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| 71 | * (L) ^XNáOÉæéJo[ªÅ«é±Æ
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| 72 | *
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| 73 | * ygp\[Xz
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| 74 | *
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| 75 | * TASK1: TA_ACTCDæxC^XNáO[`o^
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| 76 | * TASK2: TA_NULLCDæx
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| 77 | * CPUEXC1: TA_NULL
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| 78 | *
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| 79 | * yeXgV[PXz
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| 80 | *
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| 81 | * == TASK1iDæxC1ñÚj==
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| 82 | * 1: óÔÌ`FbN
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| 83 | * ena_tex()
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| 84 | * 2: óÔÌ`FbN
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| 85 | * RAISE_CPU_EXCEPTION
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| 86 | * == CPUEXC1i1ñÚj==
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| 87 | * 3: óÔÌ`FbN ... (A)(C)(D)
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| 88 | * xsns_xpn() == false ... (I)
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| 89 | * xsns_dpn() == false ... (J)
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| 90 | * 4: iact_tsk(TASK2)
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| 91 | * iloc_cpu()
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| 92 | * ^[
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| 93 | * == TASK2iDæxj==
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| 94 | * 5: óÔÌ`FbN ... (E)(F)(G)(H)
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| 95 | * 6: ter_tsk(TASK1) ... (K)
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| 96 | * 7: act_tsk(TASK1) ... (K)
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| 97 | * 8: ext_tsk()
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| 98 | * == TASK1iDæxC2ñÚj==
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| 99 | * 9: óÔÌ`FbN ... (K)
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| 100 | * ena_tex()
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| 101 | * 10: óÔÌ`FbN
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| 102 | * RAISE_CPU_EXCEPTION
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| 103 | * == CPUEXC1i2ñÚj==
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| 104 | * 11: óÔÌ`FbN ... (A)(C)(D)
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| 105 | * xsns_xpn() == false ... (I)
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| 106 | * xsns_dpn() == false ... (J)
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| 107 | * 12: iras_tex(TASK1, 1U)
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| 108 | * iloc_cpu()
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| 109 | * ^[
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| 110 | * == TASK1Ì^XNáO[` ==
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| 111 | * 13: óÔÌ`FbN ... (E)(F)(G)(H)
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| 112 | * 14: act_tsk(TASK1) ... (L)
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| 113 | * 15: ext_tsk() ... (L)
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| 114 | * == TASK1iDæxC3ñÚj==
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| 115 | * 16: óÔÌ`FbN ... (L)
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| 116 | * 17: eXgI¹
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| 117 | */
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| 118 |
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| 119 | #include <kernel.h>
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| 120 | #include <test_lib.h>
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| 121 | #include <t_syslog.h>
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| 122 | #include "kernel_cfg.h"
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| 123 | #include "test_cpuexc.h"
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| 124 |
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| 125 | int_t task1_count = 0;
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| 126 |
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| 127 | void
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| 128 | task1(intptr_t exinf)
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| 129 | {
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| 130 | ER ercd;
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| 131 |
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| 132 | switch (++task1_count) {
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| 133 | case 1:
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| 134 | check_point(1);
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| 135 | check_state(false, false, TIPM_ENAALL, false, false, true);
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| 136 | ercd = ena_tex();
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| 137 | check_ercd(ercd, E_OK);
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| 138 |
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| 139 | check_point(2);
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| 140 | check_state(false, false, TIPM_ENAALL, false, false, false);
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| 141 | RAISE_CPU_EXCEPTION;
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| 142 |
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| 143 | check_point(0);
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| 144 | break;
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| 145 |
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| 146 | case 2:
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| 147 | check_point(9);
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| 148 | check_state(false, false, TIPM_ENAALL, false, false, true);
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| 149 | ercd = ena_tex();
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| 150 | check_ercd(ercd, E_OK);
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| 151 |
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| 152 | check_point(10);
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| 153 | check_state(false, false, TIPM_ENAALL, false, false, false);
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| 154 | RAISE_CPU_EXCEPTION;
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| 155 |
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| 156 | check_point(0);
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| 157 | break;
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| 158 |
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| 159 | case 3:
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| 160 | check_point(16);
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| 161 | check_state(false, false, TIPM_ENAALL, false, false, true);
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| 162 |
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| 163 | check_finish(17);
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| 164 | break;
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| 165 |
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| 166 | default:
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| 167 | check_point(0);
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| 168 | break;
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| 169 | }
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| 170 | }
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| 171 |
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| 172 | void
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| 173 | tex_task1(TEXPTN texptn, intptr_t exinf)
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| 174 | {
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| 175 | ER ercd;
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| 176 |
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| 177 | check_point(13);
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| 178 | check_state(false, false, TIPM_ENAALL, false, false, true);
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| 179 |
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| 180 | check_point(14);
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| 181 | ercd = act_tsk(TASK1);
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| 182 | check_ercd(ercd, E_OK);
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| 183 |
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| 184 | check_point(15);
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| 185 | ercd = ext_tsk();
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| 186 | check_ercd(ercd, E_OK);
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| 187 |
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| 188 | check_point(0);
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| 189 | }
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| 190 |
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| 191 | void
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| 192 | task2(intptr_t exinf)
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| 193 | {
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| 194 | ER ercd;
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| 195 |
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| 196 | check_point(5);
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| 197 | check_state(false, false, TIPM_ENAALL, false, false, true);
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| 198 |
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| 199 | check_point(6);
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| 200 | ercd = ter_tsk(TASK1);
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| 201 | check_ercd(ercd, E_OK);
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| 202 |
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| 203 | check_point(7);
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| 204 | ercd = act_tsk(TASK1);
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| 205 | check_ercd(ercd, E_OK);
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| 206 |
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| 207 | check_point(8);
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| 208 | ercd = ext_tsk();
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| 209 | check_ercd(ercd, E_OK);
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| 210 |
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| 211 | check_point(0);
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| 212 | }
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| 213 |
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| 214 | void
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| 215 | alarm1_handler(intptr_t exinf)
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| 216 | {
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| 217 | check_point(0);
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| 218 | }
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| 219 |
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| 220 | int_t cpuexc_count = 0;
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| 221 |
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| 222 | void
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| 223 | cpuexc_handler(void *p_excinf)
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| 224 | {
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| 225 | ER ercd;
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| 226 |
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| 227 | switch (++cpuexc_count) {
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| 228 | case 1:
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| 229 | check_point(3);
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| 230 | check_state_i(true, false, false, true, false);
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| 231 | check_assert(xsns_xpn(p_excinf) == false);
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| 232 | check_assert(xsns_dpn(p_excinf) == false);
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| 233 |
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| 234 | check_point(4);
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| 235 | ercd = iact_tsk(TASK2);
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| 236 | check_ercd(ercd, E_OK);
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| 237 | ercd = iloc_cpu();
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| 238 | check_ercd(ercd, E_OK);
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| 239 | break;
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| 240 |
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| 241 | case 2:
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| 242 | check_point(11);
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| 243 | check_state_i(true, false, false, true, false);
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| 244 | check_assert(xsns_xpn(p_excinf) == false);
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| 245 | check_assert(xsns_dpn(p_excinf) == false);
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| 246 |
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| 247 | check_point(12);
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| 248 | ercd = iras_tex(TASK1, 1U);
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| 249 | check_ercd(ercd, E_OK);
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| 250 | ercd = iloc_cpu();
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| 251 | check_ercd(ercd, E_OK);
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| 252 | break;
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| 253 |
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| 254 | default:
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| 255 | check_point(0);
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| 256 | break;
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| 257 | }
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| 258 | }
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