source: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32fcube/system_stm32f4xx.c@ 303

Last change on this file since 303 was 303, checked in by ertl-honda, 7 years ago

nucleo_f401re依存部の追加
File size: 9.4 KB
Line 
1/**
2 ******************************************************************************
3 * @file system_stm32f4xx.c
4 * @author MCD Application Team
5 * @version V1.2.1
6 * @date 09-October-2015
7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
8 *
9 * This file provides two functions and one global variable to be called from
10 * user application:
11 * - SystemInit(): This function is called at startup just after reset and
12 * before branch to main program. This call is made inside
13 * the "startup_stm32f4xx.s" file.
14 *
15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
16 * by the user application to setup the SysTick
17 * timer or configure other parameters.
18 *
19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
20 * be called whenever the core clock is changed
21 * during program execution.
22 *
23 *
24 ******************************************************************************
25 * @attention
26 *
27 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
28 *
29 * Redistribution and use in source and binary forms, with or without modification,
30 * are permitted provided that the following conditions are met:
31 * 1. Redistributions of source code must retain the above copyright notice,
32 * this list of conditions and the following disclaimer.
33 * 2. Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following disclaimer in the documentation
35 * and/or other materials provided with the distribution.
36 * 3. Neither the name of STMicroelectronics nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
39 *
40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
41 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
43 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
46 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
47 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
49 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
50 *
51 ******************************************************************************
52 */
53
54/** @addtogroup CMSIS
55 * @{
56 */
57
58/** @addtogroup stm32f4xx_system
59 * @{
60 */
61
62/** @addtogroup STM32F4xx_System_Private_Includes
63 * @{
64 */
65
66#include "stm32f4xx.h"
67
68#if !defined (HSE_VALUE)
69 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
70#endif /* HSE_VALUE */
71
72#if !defined (HSI_VALUE)
73 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
74#endif /* HSI_VALUE */
75
76/**
77 * @}
78 */
79
80/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
81 * @{
82 */
83
84/**
85 * @}
86 */
87
88/** @addtogroup STM32F4xx_System_Private_Defines
89 * @{
90 */
91
92/************************* Miscellaneous Configuration ************************/
93
94/*!< Uncomment the following line if you need to relocate your vector Table in
95 Internal SRAM. */
96/* #define VECT_TAB_SRAM */
97#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
98 This value must be a multiple of 0x200. */
99/******************************************************************************/
100
101/**
102 * @}
103 */
104
105/** @addtogroup STM32F4xx_System_Private_Macros
106 * @{
107 */
108
109/**
110 * @}
111 */
112
113/** @addtogroup STM32F4xx_System_Private_Variables
114 * @{
115 */
116 /* This variable is updated in three ways:
117 1) by calling CMSIS function SystemCoreClockUpdate()
118 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
119 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
120 Note: If you use this function to configure the system clock; then there
121 is no need to call the 2 first functions listed above, since SystemCoreClock
122 variable is updated automatically.
123 */
124 uint32_t SystemCoreClock = 16000000;
125 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
126
127/**
128 * @}
129 */
130
131/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
132 * @{
133 */
134
135/**
136 * @}
137 */
138
139/** @addtogroup STM32F4xx_System_Private_Functions
140 * @{
141 */
142
143/**
144 * @brief Setup the microcontroller system
145 * Initialize the FPU setting, vector table location and External memory
146 * configuration.
147 * @param None
148 * @retval None
149 */
150void SystemInit(void)
151{
152 /* FPU settings ------------------------------------------------------------*/
153 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
154// SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
155 #endif
156 /* Reset the RCC clock configuration to the default reset state ------------*/
157 /* Set HSION bit */
158 RCC->CR |= (uint32_t)0x00000001;
159
160 /* Reset CFGR register */
161 RCC->CFGR = 0x00000000;
162
163 /* Reset HSEON, CSSON and PLLON bits */
164 RCC->CR &= (uint32_t)0xFEF6FFFF;
165
166 /* Reset PLLCFGR register */
167 RCC->PLLCFGR = 0x24003010;
168
169 /* Reset HSEBYP bit */
170 RCC->CR &= (uint32_t)0xFFFBFFFF;
171
172 /* Disable all interrupts */
173 RCC->CIR = 0x00000000;
174
175 /* Configure the Vector Table location add offset address ------------------*/
176#ifdef VECT_TAB_SRAM
177 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
178#else
179 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
180#endif
181}
182
183/**
184 * @brief Update SystemCoreClock variable according to Clock Register Values.
185 * The SystemCoreClock variable contains the core clock (HCLK), it can
186 * be used by the user application to setup the SysTick timer or configure
187 * other parameters.
188 *
189 * @note Each time the core clock (HCLK) changes, this function must be called
190 * to update SystemCoreClock variable value. Otherwise, any configuration
191 * based on this variable will be incorrect.
192 *
193 * @note - The system frequency computed by this function is not the real
194 * frequency in the chip. It is calculated based on the predefined
195 * constant and the selected clock source:
196 *
197 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
198 *
199 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
200 *
201 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
202 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
203 *
204 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
205 * 16 MHz) but the real value may vary depending on the variations
206 * in voltage and temperature.
207 *
208 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
209 * depends on the application requirements), user has to ensure that HSE_VALUE
210 * is same as the real frequency of the crystal used. Otherwise, this function
211 * may have wrong result.
212 *
213 * - The result of this function could be not correct when using fractional
214 * value for HSE crystal.
215 *
216 * @param None
217 * @retval None
218 */
219void SystemCoreClockUpdate(void)
220{
221 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
222
223 /* Get SYSCLK source -------------------------------------------------------*/
224 tmp = RCC->CFGR & RCC_CFGR_SWS;
225
226 switch (tmp)
227 {
228 case 0x00: /* HSI used as system clock source */
229 SystemCoreClock = HSI_VALUE;
230 break;
231 case 0x04: /* HSE used as system clock source */
232 SystemCoreClock = HSE_VALUE;
233 break;
234 case 0x08: /* PLL used as system clock source */
235
236 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
237 SYSCLK = PLL_VCO / PLL_P
238 */
239 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
240 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
241
242 if (pllsource != 0)
243 {
244 /* HSE used as PLL clock source */
245 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
246 }
247 else
248 {
249 /* HSI used as PLL clock source */
250 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
251 }
252
253 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
254 SystemCoreClock = pllvco/pllp;
255 break;
256 default:
257 SystemCoreClock = HSI_VALUE;
258 break;
259 }
260 /* Compute HCLK frequency --------------------------------------------------*/
261 /* Get HCLK prescaler */
262 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
263 /* HCLK frequency */
264 SystemCoreClock >>= tmp;
265}
266
267/**
268 * @}
269 */
270
271/**
272 * @}
273 */
274
275/**
276 * @}
277 */
278/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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