[302] | 1 | /*
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| 2 | * TOPPERS Software
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems
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| 4 | *
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| 5 | * Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
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| 6 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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| 7 | *
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| 8 | * ä¸è¨èä½æ¨©è
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| 9 | ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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| 10 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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| 11 | * å¤ã»åé
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| 12 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 13 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 14 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 15 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 16 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 17 | * ç¨ã§ããå½¢ã§åé
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| 18 | å¸ããå ´åã«ã¯ï¼åé
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| 19 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 20 | * è
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| 21 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 22 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 23 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 24 | * ç¨ã§ããªãå½¢ã§åé
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| 25 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 26 | * ã¨ï¼
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| 27 | * (a) åé
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| 28 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 29 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 30 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 31 | * (b) åé
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| 32 | å¸ã®å½¢æ
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| 33 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 34 | * å ±åãããã¨ï¼
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| 35 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 36 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 37 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 38 | 責ãããã¨ï¼
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| 39 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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| 40 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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| 41 | ããã³TOPPERSããã¸ã§ã¯ãã
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| 42 | * å
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| 43 | 責ãããã¨ï¼
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| 44 | *
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| 45 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 46 | ã
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| 47 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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| 48 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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| 49 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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| 50 | * ã®è²¬ä»»ãè² ããªãï¼
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| 51 | *
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| 52 | * $Id: ct11mpcore.h 478 2016-01-02 02:08:26Z ertl-hiro $
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| 53 | */
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| 54 |
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| 55 | /*
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| 56 | * CT11MPcore with RealView Emulation Baseboard ãµãã¼ãã¢ã¸ã¥ã¼ã«
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| 57 | */
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| 58 |
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| 59 | #ifndef TOPPERS_CT11MPCORE_H
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| 60 | #define TOPPERS_CT11MPCORE_H
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| 61 |
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| 62 | /*
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| 63 | * å²è¾¼ã¿ã®æ°
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| 64 | */
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| 65 | #define DIC_TNUM_INTNO UINT_C(64)
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| 66 |
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| 67 | /*
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| 68 | * å²è¾¼ã¿çªå·
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| 69 | */
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| 70 | #define EB_IRQNO_TIMER01 33U
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| 71 | #define EB_IRQNO_TIMER23 34U
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| 72 | #define EB_IRQNO_UART0 36U
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| 73 | #define EB_IRQNO_UART1 37U
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| 74 | #define EB_IRQNO_UART2 44U /* è¦æ¤è¨ */
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| 75 | #define EB_IRQNO_UART3 45U /* è¦æ¤è¨ */
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| 76 |
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| 77 | /*
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| 78 | * MPCore Private Memory Regionã®å
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| 79 | é çªå°
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| 80 | *
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| 81 | * ARM11 MPCoreã®å¶å¾¡ã¬ã¸ã¹ã¿ã«ã¯ï¼MPCore Private Memory Regionã¨å¼ã°
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| 82 | * ããã¡ã¢ãªé åã«ããã¢ã¯ã»ã¹ããï¼ãã®é åã®å
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| 83 | é çªå°ã¯ï¼ã³ã¢å¤é¨ã
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| 84 | * ãè¨å®å¯è½ã¨ãªã£ã¦ããï¼CT11MPCoreã§ã¯ï¼ãã¼ãã§è¨å®ã§ããããã«ãªã£
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| 85 | * ã¦ããï¼ããã©ã«ãã§ã¯ï¼0x1f000000ã«ãªã£ã¦ããï¼
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| 86 | *
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| 87 | * QEMUã§ã¯ï¼ãã®é åã®å
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| 88 | é çªå°ã¯ï¼0x10100000ã«è¨å®ããã¦ãã
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| 89 | * ï¼qemu-2.1.0/hw/arm/realview.cï¼ï¼
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| 90 | */
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| 91 | #ifdef TOPPERS_USE_QEMU
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| 92 | #define MPCORE_PMR_BASE 0x10100000
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| 93 | #endif /* TOPPERS_USE_QEMU */
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| 94 |
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| 95 | #ifndef MPCORE_PMR_BASE
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| 96 | #define MPCORE_PMR_BASE 0x1f000000
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| 97 | #endif /* MPCORE_PMR_BASE */
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| 98 |
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| 99 | /*
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| 100 | * MPCoreå
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| 101 | èµã®ã¿ã¤ãã¨ã¦ã©ããããã°ã1MHzã§åä½ãããããã®ããªã¹ã±ã¼
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| 102 | * ã©ã®è¨å®å¤ï¼ã³ã¢ã®ã¯ããã¯ã200MHzã®å ´åï¼
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| 103 | */
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| 104 | #define MPCORE_TMR_PS_1MHZ 99
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| 105 | #define MPCORE_WDG_PS_1MHZ 99
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| 106 |
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| 107 | /*
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| 108 | * Emulation Boardä¸ã®ãªã½ã¼ã¹
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| 109 | */
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| 110 | #define EB_SYS_BASE 0x10000000
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| 111 | #define EB_SYS_LOCK ((uint32_t *)(EB_SYS_BASE + 0x0020U))
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| 112 | #define EB_SYS_PLD_CTRL1 ((uint32_t *)(EB_SYS_BASE + 0x0074U))
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| 113 | #define EB_SYS_PLD_CTRL2 ((uint32_t *)(EB_SYS_BASE + 0x0078U))
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| 114 |
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| 115 | /*
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| 116 | * ããã¯ã¬ã¸ã¹ã¿ï¼EB_SYS_LOCKï¼ã®è¨å®å¤
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| 117 | */
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| 118 | #define EB_SYS_LOCK_LOCK UINT_C(0x0000)
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| 119 | #define EB_SYS_LOCK_UNLOCK UINT_C(0xa05f)
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| 120 |
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| 121 | /*
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| 122 | * ã·ã¹ãã å¶å¾¡ã¬ã¸ã¹ã¿1ï¼EB_SYS_PLD_CTRL1ï¼ã®è¨å®å¤
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| 123 | */
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| 124 | #define EB_SYS_PLD_CTRL1_INTMODE_LEGACY UINT_C(0x00000000)
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| 125 | #define EB_SYS_PLD_CTRL1_INTMODE_NEW_DCC UINT_C(0x00400000)
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| 126 | #define EB_SYS_PLD_CTRL1_INTMODE_NEW_NODCC UINT_C(0x00800000)
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| 127 | #define EB_SYS_PLD_CTRL1_INTMODE_EN_FIQ UINT_C(0x01000000)
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| 128 | #define EB_SYS_PLD_CTRL1_INTMODE_MASK UINT_C(0x01c00000)
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| 129 |
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| 130 | /*
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| 131 | * UARTé¢é£ã®å®ç¾©
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| 132 | */
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| 133 |
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| 134 | /*
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| 135 | * UARTã¬ã¸ã¹ã¿ã®ãã¼ã¹ã¢ãã¬ã¹
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| 136 | */
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| 137 | #define EB_UART0_BASE (EB_SYS_BASE + 0x9000U)
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| 138 | #define EB_UART1_BASE (EB_SYS_BASE + 0xa000U)
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| 139 | #define EB_UART2_BASE (EB_SYS_BASE + 0xb000U)
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| 140 | #define EB_UART3_BASE (EB_SYS_BASE + 0xc000U)
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| 141 |
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| 142 | /*
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| 143 | * ãã¼ã¬ã¼ãè¨å®ï¼38400bpsï¼
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| 144 | */
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| 145 | #define EB_UART_IBRD_38400 0x27U
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| 146 | #define EB_UART_FBRD_38400 0x04U
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| 147 |
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| 148 | /*
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| 149 | * ã¿ã¤ãé¢é£ã®å®ç¾©
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| 150 | */
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| 151 |
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| 152 | /*
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| 153 | * ã¿ã¤ãã¬ã¸ã¹ã¿ã®ãã¼ã¹ã¢ãã¬ã¹
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| 154 | */
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| 155 | #define EB_TIMER0_BASE (EB_SYS_BASE + 0x11000U)
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| 156 | #define EB_TIMER1_BASE (EB_SYS_BASE + 0x11020U)
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| 157 | #define EB_TIMER2_BASE (EB_SYS_BASE + 0x12000U)
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| 158 | #define EB_TIMER3_BASE (EB_SYS_BASE + 0x12020U)
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| 159 |
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| 160 | #endif /* TOPPERS_CT11MPCORE_H */
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