1 | /**
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2 | ******************************************************************************
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3 | * @file stm32f4xx_ll_usb.c
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4 | * @author MCD Application Team
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5 | * @version V1.4.1
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6 | * @date 09-October-2015
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7 | * @brief USB Low Layer HAL module driver.
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8 | *
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9 | * This file provides firmware functions to manage the following
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10 | * functionalities of the USB Peripheral Controller:
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11 | * + Initialization/de-initialization functions
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12 | * + I/O operation functions
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13 | * + Peripheral Control functions
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14 | * + Peripheral State functions
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15 | *
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16 | @verbatim
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17 | ==============================================================================
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18 | ##### How to use this driver #####
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19 | ==============================================================================
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20 | [..]
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21 | (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
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22 |
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23 | (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
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24 |
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25 | (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
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26 |
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27 | @endverbatim
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28 | ******************************************************************************
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29 | * @attention
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30 | *
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31 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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32 | *
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33 | * Redistribution and use in source and binary forms, with or without modification,
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34 | * are permitted provided that the following conditions are met:
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35 | * 1. Redistributions of source code must retain the above copyright notice,
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36 | * this list of conditions and the following disclaimer.
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37 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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38 | * this list of conditions and the following disclaimer in the documentation
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39 | * and/or other materials provided with the distribution.
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40 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
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41 | * may be used to endorse or promote products derived from this software
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42 | * without specific prior written permission.
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43 | *
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44 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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45 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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46 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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47 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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48 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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49 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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50 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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51 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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52 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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53 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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54 | *
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55 | ******************************************************************************
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56 | */
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57 |
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58 | /* Includes ------------------------------------------------------------------*/
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59 | #include "stm32f4xx_hal.h"
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60 |
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61 | /** @addtogroup STM32F4xx_LL_USB_DRIVER
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62 | * @{
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63 | */
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64 |
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65 | #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED)
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66 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
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67 | defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
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68 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
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69 | defined(STM32F469xx) || defined(STM32F479xx)
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70 | /* Private typedef -----------------------------------------------------------*/
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71 | /* Private define ------------------------------------------------------------*/
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72 | /* Private macro -------------------------------------------------------------*/
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73 | /* Private variables ---------------------------------------------------------*/
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74 | /* Private function prototypes -----------------------------------------------*/
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75 | /* Private functions ---------------------------------------------------------*/
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76 | static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
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77 |
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78 | /* Exported functions --------------------------------------------------------*/
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79 |
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80 | /** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions
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81 | * @{
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82 | */
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83 |
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84 | /** @defgroup LL_USB_Group1 Initialization/de-initialization functions
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85 | * @brief Initialization and Configuration functions
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86 | *
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87 | @verbatim
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88 | ===============================================================================
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89 | ##### Initialization/de-initialization functions #####
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90 | ===============================================================================
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91 | [..] This section provides functions allowing to:
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92 |
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93 | @endverbatim
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94 | * @{
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95 | */
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96 |
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97 | /**
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98 | * @brief Initializes the USB Core
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99 | * @param USBx: USB Instance
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100 | * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
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101 | * the configuration information for the specified USBx peripheral.
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102 | * @retval HAL status
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103 | */
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104 | HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
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105 | {
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106 | if (cfg.phy_itface == USB_OTG_ULPI_PHY)
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107 | {
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108 |
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109 | USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
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110 |
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111 | /* Init The ULPI Interface */
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112 | USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
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113 |
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114 | /* Select vbus source */
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115 | USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
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116 | if(cfg.use_external_vbus == 1)
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117 | {
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118 | USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
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119 | }
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120 | /* Reset after a PHY select */
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121 | USB_CoreReset(USBx);
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122 | }
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123 | else /* FS interface (embedded Phy) */
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124 | {
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125 | /* Select FS Embedded PHY */
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126 | USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
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127 |
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128 | /* Reset after a PHY select and set Host mode */
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129 | USB_CoreReset(USBx);
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130 |
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131 | /* Deactivate the power down*/
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132 | USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
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133 | }
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134 |
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135 | if(cfg.dma_enable == ENABLE)
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136 | {
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137 | USBx->GAHBCFG |= (USB_OTG_GAHBCFG_HBSTLEN_1 | USB_OTG_GAHBCFG_HBSTLEN_2);
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138 | USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
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139 | }
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140 |
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141 | return HAL_OK;
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142 | }
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143 |
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144 | /**
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145 | * @brief USB_EnableGlobalInt
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146 | * Enables the controller's Global Int in the AHB Config reg
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147 | * @param USBx : Selected device
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148 | * @retval HAL status
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149 | */
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150 | HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
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151 | {
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152 | USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
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153 | return HAL_OK;
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154 | }
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155 |
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156 |
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157 | /**
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158 | * @brief USB_DisableGlobalInt
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159 | * Disable the controller's Global Int in the AHB Config reg
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160 | * @param USBx : Selected device
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161 | * @retval HAL status
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162 | */
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163 | HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
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164 | {
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165 | USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
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166 | return HAL_OK;
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167 | }
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168 |
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169 | /**
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170 | * @brief USB_SetCurrentMode : Set functional mode
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171 | * @param USBx : Selected device
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172 | * @param mode : current core mode
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173 | * This parameter can be one of these values:
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174 | * @arg USB_OTG_DEVICE_MODE: Peripheral mode
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175 | * @arg USB_OTG_HOST_MODE: Host mode
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176 | * @arg USB_OTG_DRD_MODE: Dual Role Device mode
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177 | * @retval HAL status
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178 | */
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179 | HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)
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180 | {
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181 | USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
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182 |
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183 | if ( mode == USB_OTG_HOST_MODE)
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184 | {
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185 | USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
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186 | }
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187 | else if ( mode == USB_OTG_DEVICE_MODE)
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188 | {
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189 | USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
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190 | }
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191 | HAL_Delay(50);
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192 |
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193 | return HAL_OK;
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194 | }
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195 |
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196 | /**
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197 | * @brief USB_DevInit : Initializes the USB_OTG controller registers
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198 | * for device mode
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199 | * @param USBx : Selected device
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200 | * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
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201 | * the configuration information for the specified USBx peripheral.
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202 | * @retval HAL status
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203 | */
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204 | HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
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205 | {
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206 | uint32_t i = 0;
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207 |
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208 | /*Activate VBUS Sensing B */
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209 | #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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210 | USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
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211 |
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212 | if (cfg.vbus_sensing_enable == 0)
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213 | {
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214 | /* Deactivate VBUS Sensing B */
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215 | USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
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216 |
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217 | /* B-peripheral session valid override enable*/
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218 | USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
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219 | USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
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220 | }
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221 | #else
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222 | USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
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223 |
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224 | if (cfg.vbus_sensing_enable == 0)
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225 | {
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226 | USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
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227 | }
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228 | #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
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229 |
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230 | /* Restart the Phy Clock */
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231 | USBx_PCGCCTL = 0;
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232 |
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233 | /* Device mode configuration */
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234 | USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
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235 |
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236 | if(cfg.phy_itface == USB_OTG_ULPI_PHY)
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237 | {
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238 | if(cfg.speed == USB_OTG_SPEED_HIGH)
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239 | {
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240 | /* Set High speed phy */
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241 | USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);
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242 | }
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243 | else
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244 | {
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245 | /* set High speed phy in Full speed mode */
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246 | USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);
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247 | }
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248 | }
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249 | else
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250 | {
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251 | /* Set Full speed phy */
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252 | USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);
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253 | }
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254 |
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255 | /* Flush the FIFOs */
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256 | USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */
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257 | USB_FlushRxFifo(USBx);
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258 |
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259 | /* Clear all pending Device Interrupts */
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260 | USBx_DEVICE->DIEPMSK = 0;
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261 | USBx_DEVICE->DOEPMSK = 0;
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262 | USBx_DEVICE->DAINT = 0xFFFFFFFF;
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263 | USBx_DEVICE->DAINTMSK = 0;
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264 |
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265 | for (i = 0; i < cfg.dev_endpoints; i++)
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266 | {
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267 | if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
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268 | {
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269 | USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK);
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270 | }
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271 | else
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272 | {
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273 | USBx_INEP(i)->DIEPCTL = 0;
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274 | }
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275 |
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276 | USBx_INEP(i)->DIEPTSIZ = 0;
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277 | USBx_INEP(i)->DIEPINT = 0xFF;
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278 | }
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279 |
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280 | for (i = 0; i < cfg.dev_endpoints; i++)
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281 | {
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282 | if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
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283 | {
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284 | USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK);
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285 | }
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286 | else
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287 | {
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288 | USBx_OUTEP(i)->DOEPCTL = 0;
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289 | }
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290 |
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291 | USBx_OUTEP(i)->DOEPTSIZ = 0;
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292 | USBx_OUTEP(i)->DOEPINT = 0xFF;
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293 | }
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294 |
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295 | USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
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296 |
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297 | if (cfg.dma_enable == 1)
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298 | {
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299 | /*Set threshold parameters */
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300 | USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6);
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301 | USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN);
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302 |
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303 | i= USBx_DEVICE->DTHRCTL;
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304 | }
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305 |
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306 | /* Disable all interrupts. */
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307 | USBx->GINTMSK = 0;
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308 |
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309 | /* Clear any pending interrupts */
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310 | USBx->GINTSTS = 0xBFFFFFFF;
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311 |
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312 | /* Enable the common interrupts */
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313 | if (cfg.dma_enable == DISABLE)
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314 | {
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315 | USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
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316 | }
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317 |
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318 | /* Enable interrupts matching to the Device mode ONLY */
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319 | USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\
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320 | USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\
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321 | USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\
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322 | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
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323 |
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324 | if(cfg.Sof_enable)
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325 | {
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326 | USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
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327 | }
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328 |
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329 | if (cfg.vbus_sensing_enable == ENABLE)
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330 | {
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331 | USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
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332 | }
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333 |
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334 | return HAL_OK;
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335 | }
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336 |
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337 |
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338 | /**
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339 | * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
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340 | * @param USBx : Selected device
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341 | * @param num : FIFO number
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342 | * This parameter can be a value from 1 to 15
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343 | 15 means Flush all Tx FIFOs
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344 | * @retval HAL status
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345 | */
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346 | HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
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347 | {
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348 | uint32_t count = 0;
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349 |
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350 | USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6));
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351 |
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352 | do
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353 | {
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354 | if (++count > 200000)
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355 | {
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356 | return HAL_TIMEOUT;
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357 | }
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358 | }
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359 | while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
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360 |
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361 | return HAL_OK;
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362 | }
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363 |
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364 |
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365 | /**
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366 | * @brief USB_FlushRxFifo : Flush Rx FIFO
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367 | * @param USBx : Selected device
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368 | * @retval HAL status
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369 | */
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370 | HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
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371 | {
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372 | uint32_t count = 0;
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373 |
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374 | USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
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375 |
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376 | do
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377 | {
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378 | if (++count > 200000)
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379 | {
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380 | return HAL_TIMEOUT;
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381 | }
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382 | }
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383 | while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
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384 |
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385 | return HAL_OK;
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386 | }
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387 |
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388 | /**
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389 | * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register
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390 | * depending the PHY type and the enumeration speed of the device.
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391 | * @param USBx : Selected device
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392 | * @param speed : device speed
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393 | * This parameter can be one of these values:
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394 | * @arg USB_OTG_SPEED_HIGH: High speed mode
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395 | * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
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396 | * @arg USB_OTG_SPEED_FULL: Full speed mode
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397 | * @arg USB_OTG_SPEED_LOW: Low speed mode
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398 | * @retval Hal status
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399 | */
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400 | HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
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401 | {
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402 | USBx_DEVICE->DCFG |= speed;
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403 | return HAL_OK;
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404 | }
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405 |
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406 | /**
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407 | * @brief USB_GetDevSpeed :Return the Dev Speed
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408 | * @param USBx : Selected device
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409 | * @retval speed : device speed
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410 | * This parameter can be one of these values:
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411 | * @arg USB_OTG_SPEED_HIGH: High speed mode
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412 | * @arg USB_OTG_SPEED_FULL: Full speed mode
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413 | * @arg USB_OTG_SPEED_LOW: Low speed mode
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414 | */
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415 | uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
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416 | {
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417 | uint8_t speed = 0;
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418 |
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419 | if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
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420 | {
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421 | speed = USB_OTG_SPEED_HIGH;
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422 | }
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423 | else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||
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424 | ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))
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425 | {
|
---|
426 | speed = USB_OTG_SPEED_FULL;
|
---|
427 | }
|
---|
428 | else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
|
---|
429 | {
|
---|
430 | speed = USB_OTG_SPEED_LOW;
|
---|
431 | }
|
---|
432 |
|
---|
433 | return speed;
|
---|
434 | }
|
---|
435 |
|
---|
436 | /**
|
---|
437 | * @brief Activate and configure an endpoint
|
---|
438 | * @param USBx : Selected device
|
---|
439 | * @param ep: pointer to endpoint structure
|
---|
440 | * @retval HAL status
|
---|
441 | */
|
---|
442 | HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
|
---|
443 | {
|
---|
444 | if (ep->is_in == 1)
|
---|
445 | {
|
---|
446 | USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
|
---|
447 |
|
---|
448 | if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
|
---|
449 | {
|
---|
450 | USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
|
---|
451 | ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
|
---|
452 | }
|
---|
453 |
|
---|
454 | }
|
---|
455 | else
|
---|
456 | {
|
---|
457 | USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
|
---|
458 |
|
---|
459 | if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
|
---|
460 | {
|
---|
461 | USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
|
---|
462 | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));
|
---|
463 | }
|
---|
464 | }
|
---|
465 | return HAL_OK;
|
---|
466 | }
|
---|
467 | /**
|
---|
468 | * @brief Activate and configure a dedicated endpoint
|
---|
469 | * @param USBx : Selected device
|
---|
470 | * @param ep: pointer to endpoint structure
|
---|
471 | * @retval HAL status
|
---|
472 | */
|
---|
473 | HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
|
---|
474 | {
|
---|
475 | static __IO uint32_t debug = 0;
|
---|
476 |
|
---|
477 | /* Read DEPCTLn register */
|
---|
478 | if (ep->is_in == 1)
|
---|
479 | {
|
---|
480 | if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
|
---|
481 | {
|
---|
482 | USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
|
---|
483 | ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
|
---|
484 | }
|
---|
485 |
|
---|
486 |
|
---|
487 | debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
|
---|
488 | ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
|
---|
489 |
|
---|
490 | USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
|
---|
491 | }
|
---|
492 | else
|
---|
493 | {
|
---|
494 | if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
|
---|
495 | {
|
---|
496 | USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
|
---|
497 | ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));
|
---|
498 |
|
---|
499 | debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE);
|
---|
500 | debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;
|
---|
501 | debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
|
---|
502 | ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));
|
---|
503 | }
|
---|
504 |
|
---|
505 | USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
|
---|
506 | }
|
---|
507 |
|
---|
508 | return HAL_OK;
|
---|
509 | }
|
---|
510 | /**
|
---|
511 | * @brief De-activate and de-initialize an endpoint
|
---|
512 | * @param USBx : Selected device
|
---|
513 | * @param ep: pointer to endpoint structure
|
---|
514 | * @retval HAL status
|
---|
515 | */
|
---|
516 | HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
|
---|
517 | {
|
---|
518 | /* Read DEPCTLn register */
|
---|
519 | if (ep->is_in == 1)
|
---|
520 | {
|
---|
521 | USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
|
---|
522 | USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
|
---|
523 | USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
|
---|
524 | }
|
---|
525 | else
|
---|
526 | {
|
---|
527 | USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
|
---|
528 | USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
|
---|
529 | USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
|
---|
530 | }
|
---|
531 | return HAL_OK;
|
---|
532 | }
|
---|
533 |
|
---|
534 | /**
|
---|
535 | * @brief De-activate and de-initialize a dedicated endpoint
|
---|
536 | * @param USBx : Selected device
|
---|
537 | * @param ep: pointer to endpoint structure
|
---|
538 | * @retval HAL status
|
---|
539 | */
|
---|
540 | HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
|
---|
541 | {
|
---|
542 | /* Read DEPCTLn register */
|
---|
543 | if (ep->is_in == 1)
|
---|
544 | {
|
---|
545 | USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
|
---|
546 | USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
|
---|
547 | }
|
---|
548 | else
|
---|
549 | {
|
---|
550 | USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
|
---|
551 | USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
|
---|
552 | }
|
---|
553 | return HAL_OK;
|
---|
554 | }
|
---|
555 |
|
---|
556 | /**
|
---|
557 | * @brief USB_EPStartXfer : setup and starts a transfer over an EP
|
---|
558 | * @param USBx : Selected device
|
---|
559 | * @param ep: pointer to endpoint structure
|
---|
560 | * @param dma: USB dma enabled or disabled
|
---|
561 | * This parameter can be one of these values:
|
---|
562 | * 0 : DMA feature not used
|
---|
563 | * 1 : DMA feature used
|
---|
564 | * @retval HAL status
|
---|
565 | */
|
---|
566 | HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
|
---|
567 | {
|
---|
568 | uint16_t pktcnt = 0;
|
---|
569 |
|
---|
570 | /* IN endpoint */
|
---|
571 | if (ep->is_in == 1)
|
---|
572 | {
|
---|
573 | /* Zero Length Packet? */
|
---|
574 | if (ep->xfer_len == 0)
|
---|
575 | {
|
---|
576 | USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
|
---|
577 | USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
|
---|
578 | USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
|
---|
579 | }
|
---|
580 | else
|
---|
581 | {
|
---|
582 | /* Program the transfer size and packet count
|
---|
583 | * as follows: xfersize = N * maxpacket +
|
---|
584 | * short_packet pktcnt = N + (short_packet
|
---|
585 | * exist ? 1 : 0)
|
---|
586 | */
|
---|
587 | USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
|
---|
588 | USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
|
---|
589 | USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ;
|
---|
590 | USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
|
---|
591 |
|
---|
592 | if (ep->type == EP_TYPE_ISOC)
|
---|
593 | {
|
---|
594 | USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
|
---|
595 | USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29));
|
---|
596 | }
|
---|
597 | }
|
---|
598 |
|
---|
599 | if (dma == 1)
|
---|
600 | {
|
---|
601 | USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
|
---|
602 | }
|
---|
603 | else
|
---|
604 | {
|
---|
605 | if (ep->type != EP_TYPE_ISOC)
|
---|
606 | {
|
---|
607 | /* Enable the Tx FIFO Empty Interrupt for this EP */
|
---|
608 | if (ep->xfer_len > 0)
|
---|
609 | {
|
---|
610 | USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num;
|
---|
611 | }
|
---|
612 | }
|
---|
613 | }
|
---|
614 |
|
---|
615 | if (ep->type == EP_TYPE_ISOC)
|
---|
616 | {
|
---|
617 | if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
|
---|
618 | {
|
---|
619 | USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
|
---|
620 | }
|
---|
621 | else
|
---|
622 | {
|
---|
623 | USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
|
---|
624 | }
|
---|
625 | }
|
---|
626 |
|
---|
627 | /* EP enable, IN data in FIFO */
|
---|
628 | USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
|
---|
629 |
|
---|
630 | if (ep->type == EP_TYPE_ISOC)
|
---|
631 | {
|
---|
632 | USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma);
|
---|
633 | }
|
---|
634 | }
|
---|
635 | else /* OUT endpoint */
|
---|
636 | {
|
---|
637 | /* Program the transfer size and packet count as follows:
|
---|
638 | * pktcnt = N
|
---|
639 | * xfersize = N * maxpacket
|
---|
640 | */
|
---|
641 | USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
|
---|
642 | USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
|
---|
643 |
|
---|
644 | if (ep->xfer_len == 0)
|
---|
645 | {
|
---|
646 | USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
|
---|
647 | USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
|
---|
648 | }
|
---|
649 | else
|
---|
650 | {
|
---|
651 | pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket;
|
---|
652 | USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); ;
|
---|
653 | USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt));
|
---|
654 | }
|
---|
655 |
|
---|
656 | if (dma == 1)
|
---|
657 | {
|
---|
658 | USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;
|
---|
659 | }
|
---|
660 |
|
---|
661 | if (ep->type == EP_TYPE_ISOC)
|
---|
662 | {
|
---|
663 | if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
|
---|
664 | {
|
---|
665 | USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
|
---|
666 | }
|
---|
667 | else
|
---|
668 | {
|
---|
669 | USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
|
---|
670 | }
|
---|
671 | }
|
---|
672 | /* EP enable */
|
---|
673 | USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
|
---|
674 | }
|
---|
675 | return HAL_OK;
|
---|
676 | }
|
---|
677 |
|
---|
678 | /**
|
---|
679 | * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0
|
---|
680 | * @param USBx : Selected device
|
---|
681 | * @param ep: pointer to endpoint structure
|
---|
682 | * @param dma: USB dma enabled or disabled
|
---|
683 | * This parameter can be one of these values:
|
---|
684 | * 0 : DMA feature not used
|
---|
685 | * 1 : DMA feature used
|
---|
686 | * @retval HAL status
|
---|
687 | */
|
---|
688 | HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
|
---|
689 | {
|
---|
690 | /* IN endpoint */
|
---|
691 | if (ep->is_in == 1)
|
---|
692 | {
|
---|
693 | /* Zero Length Packet? */
|
---|
694 | if (ep->xfer_len == 0)
|
---|
695 | {
|
---|
696 | USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
|
---|
697 | USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
|
---|
698 | USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
|
---|
699 | }
|
---|
700 | else
|
---|
701 | {
|
---|
702 | /* Program the transfer size and packet count
|
---|
703 | * as follows: xfersize = N * maxpacket +
|
---|
704 | * short_packet pktcnt = N + (short_packet
|
---|
705 | * exist ? 1 : 0)
|
---|
706 | */
|
---|
707 | USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
|
---|
708 | USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
|
---|
709 |
|
---|
710 | if(ep->xfer_len > ep->maxpacket)
|
---|
711 | {
|
---|
712 | ep->xfer_len = ep->maxpacket;
|
---|
713 | }
|
---|
714 | USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
|
---|
715 | USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
|
---|
716 |
|
---|
717 | }
|
---|
718 |
|
---|
719 | if (dma == 1)
|
---|
720 | {
|
---|
721 | USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
|
---|
722 | }
|
---|
723 | else
|
---|
724 | {
|
---|
725 | /* Enable the Tx FIFO Empty Interrupt for this EP */
|
---|
726 | if (ep->xfer_len > 0)
|
---|
727 | {
|
---|
728 | USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num);
|
---|
729 | }
|
---|
730 | }
|
---|
731 |
|
---|
732 | /* EP enable, IN data in FIFO */
|
---|
733 | USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
|
---|
734 | }
|
---|
735 | else /* OUT endpoint */
|
---|
736 | {
|
---|
737 | /* Program the transfer size and packet count as follows:
|
---|
738 | * pktcnt = N
|
---|
739 | * xfersize = N * maxpacket
|
---|
740 | */
|
---|
741 | USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
|
---|
742 | USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
|
---|
743 |
|
---|
744 | if (ep->xfer_len > 0)
|
---|
745 | {
|
---|
746 | ep->xfer_len = ep->maxpacket;
|
---|
747 | }
|
---|
748 |
|
---|
749 | USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));
|
---|
750 | USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
|
---|
751 |
|
---|
752 |
|
---|
753 | if (dma == 1)
|
---|
754 | {
|
---|
755 | USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);
|
---|
756 | }
|
---|
757 |
|
---|
758 | /* EP enable */
|
---|
759 | USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
|
---|
760 | }
|
---|
761 | return HAL_OK;
|
---|
762 | }
|
---|
763 |
|
---|
764 | /**
|
---|
765 | * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
|
---|
766 | * with the EP/channel
|
---|
767 | * @param USBx : Selected device
|
---|
768 | * @param src : pointer to source buffer
|
---|
769 | * @param ch_ep_num : endpoint or host channel number
|
---|
770 | * @param len : Number of bytes to write
|
---|
771 | * @param dma: USB dma enabled or disabled
|
---|
772 | * This parameter can be one of these values:
|
---|
773 | * 0 : DMA feature not used
|
---|
774 | * 1 : DMA feature used
|
---|
775 | * @retval HAL status
|
---|
776 | */
|
---|
777 | HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
|
---|
778 | {
|
---|
779 | uint32_t count32b= 0 , i= 0;
|
---|
780 |
|
---|
781 | if (dma == 0)
|
---|
782 | {
|
---|
783 | count32b = (len + 3) / 4;
|
---|
784 | for (i = 0; i < count32b; i++, src += 4)
|
---|
785 | {
|
---|
786 | USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src);
|
---|
787 | }
|
---|
788 | }
|
---|
789 | return HAL_OK;
|
---|
790 | }
|
---|
791 |
|
---|
792 | /**
|
---|
793 | * @brief USB_ReadPacket : read a packet from the Tx FIFO associated
|
---|
794 | * with the EP/channel
|
---|
795 | * @param USBx : Selected device
|
---|
796 | * @param src : source pointer
|
---|
797 | * @param ch_ep_num : endpoint or host channel number
|
---|
798 | * @param len : Number of bytes to read
|
---|
799 | * @param dma: USB dma enabled or disabled
|
---|
800 | * This parameter can be one of these values:
|
---|
801 | * 0 : DMA feature not used
|
---|
802 | * 1 : DMA feature used
|
---|
803 | * @retval pointer to destination buffer
|
---|
804 | */
|
---|
805 | void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
|
---|
806 | {
|
---|
807 | uint32_t i=0;
|
---|
808 | uint32_t count32b = (len + 3) / 4;
|
---|
809 |
|
---|
810 | for ( i = 0; i < count32b; i++, dest += 4 )
|
---|
811 | {
|
---|
812 | *(__packed uint32_t *)dest = USBx_DFIFO(0);
|
---|
813 |
|
---|
814 | }
|
---|
815 | return ((void *)dest);
|
---|
816 | }
|
---|
817 |
|
---|
818 | /**
|
---|
819 | * @brief USB_EPSetStall : set a stall condition over an EP
|
---|
820 | * @param USBx : Selected device
|
---|
821 | * @param ep: pointer to endpoint structure
|
---|
822 | * @retval HAL status
|
---|
823 | */
|
---|
824 | HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
|
---|
825 | {
|
---|
826 | if (ep->is_in == 1)
|
---|
827 | {
|
---|
828 | if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0)
|
---|
829 | {
|
---|
830 | USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
|
---|
831 | }
|
---|
832 | USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
|
---|
833 | }
|
---|
834 | else
|
---|
835 | {
|
---|
836 | if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0)
|
---|
837 | {
|
---|
838 | USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
|
---|
839 | }
|
---|
840 | USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
|
---|
841 | }
|
---|
842 | return HAL_OK;
|
---|
843 | }
|
---|
844 |
|
---|
845 |
|
---|
846 | /**
|
---|
847 | * @brief USB_EPClearStall : Clear a stall condition over an EP
|
---|
848 | * @param USBx : Selected device
|
---|
849 | * @param ep: pointer to endpoint structure
|
---|
850 | * @retval HAL status
|
---|
851 | */
|
---|
852 | HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
|
---|
853 | {
|
---|
854 | if (ep->is_in == 1)
|
---|
855 | {
|
---|
856 | USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
|
---|
857 | if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
|
---|
858 | {
|
---|
859 | USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
|
---|
860 | }
|
---|
861 | }
|
---|
862 | else
|
---|
863 | {
|
---|
864 | USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
|
---|
865 | if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
|
---|
866 | {
|
---|
867 | USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
|
---|
868 | }
|
---|
869 | }
|
---|
870 | return HAL_OK;
|
---|
871 | }
|
---|
872 |
|
---|
873 | /**
|
---|
874 | * @brief USB_StopDevice : Stop the usb device mode
|
---|
875 | * @param USBx : Selected device
|
---|
876 | * @retval HAL status
|
---|
877 | */
|
---|
878 | HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
|
---|
879 | {
|
---|
880 | uint32_t i;
|
---|
881 |
|
---|
882 | /* Clear Pending interrupt */
|
---|
883 | for (i = 0; i < 15 ; i++)
|
---|
884 | {
|
---|
885 | USBx_INEP(i)->DIEPINT = 0xFF;
|
---|
886 | USBx_OUTEP(i)->DOEPINT = 0xFF;
|
---|
887 | }
|
---|
888 | USBx_DEVICE->DAINT = 0xFFFFFFFF;
|
---|
889 |
|
---|
890 | /* Clear interrupt masks */
|
---|
891 | USBx_DEVICE->DIEPMSK = 0;
|
---|
892 | USBx_DEVICE->DOEPMSK = 0;
|
---|
893 | USBx_DEVICE->DAINTMSK = 0;
|
---|
894 |
|
---|
895 | /* Flush the FIFO */
|
---|
896 | USB_FlushRxFifo(USBx);
|
---|
897 | USB_FlushTxFifo(USBx , 0x10 );
|
---|
898 |
|
---|
899 | return HAL_OK;
|
---|
900 | }
|
---|
901 |
|
---|
902 | /**
|
---|
903 | * @brief USB_SetDevAddress : Stop the usb device mode
|
---|
904 | * @param USBx : Selected device
|
---|
905 | * @param address : new device address to be assigned
|
---|
906 | * This parameter can be a value from 0 to 255
|
---|
907 | * @retval HAL status
|
---|
908 | */
|
---|
909 | HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)
|
---|
910 | {
|
---|
911 | USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
|
---|
912 | USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ;
|
---|
913 |
|
---|
914 | return HAL_OK;
|
---|
915 | }
|
---|
916 |
|
---|
917 | /**
|
---|
918 | * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
|
---|
919 | * @param USBx : Selected device
|
---|
920 | * @retval HAL status
|
---|
921 | */
|
---|
922 | HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
|
---|
923 | {
|
---|
924 | USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;
|
---|
925 | HAL_Delay(3);
|
---|
926 |
|
---|
927 | return HAL_OK;
|
---|
928 | }
|
---|
929 |
|
---|
930 | /**
|
---|
931 | * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
|
---|
932 | * @param USBx : Selected device
|
---|
933 | * @retval HAL status
|
---|
934 | */
|
---|
935 | HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
|
---|
936 | {
|
---|
937 | USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ;
|
---|
938 | HAL_Delay(3);
|
---|
939 |
|
---|
940 | return HAL_OK;
|
---|
941 | }
|
---|
942 |
|
---|
943 | /**
|
---|
944 | * @brief USB_ReadInterrupts: return the global USB interrupt status
|
---|
945 | * @param USBx : Selected device
|
---|
946 | * @retval HAL status
|
---|
947 | */
|
---|
948 | uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
|
---|
949 | {
|
---|
950 | uint32_t v = 0;
|
---|
951 |
|
---|
952 | v = USBx->GINTSTS;
|
---|
953 | v &= USBx->GINTMSK;
|
---|
954 | return v;
|
---|
955 | }
|
---|
956 |
|
---|
957 | /**
|
---|
958 | * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
|
---|
959 | * @param USBx : Selected device
|
---|
960 | * @retval HAL status
|
---|
961 | */
|
---|
962 | uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
|
---|
963 | {
|
---|
964 | uint32_t v;
|
---|
965 | v = USBx_DEVICE->DAINT;
|
---|
966 | v &= USBx_DEVICE->DAINTMSK;
|
---|
967 | return ((v & 0xffff0000) >> 16);
|
---|
968 | }
|
---|
969 |
|
---|
970 | /**
|
---|
971 | * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
|
---|
972 | * @param USBx : Selected device
|
---|
973 | * @retval HAL status
|
---|
974 | */
|
---|
975 | uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
|
---|
976 | {
|
---|
977 | uint32_t v;
|
---|
978 | v = USBx_DEVICE->DAINT;
|
---|
979 | v &= USBx_DEVICE->DAINTMSK;
|
---|
980 | return ((v & 0xFFFF));
|
---|
981 | }
|
---|
982 |
|
---|
983 | /**
|
---|
984 | * @brief Returns Device OUT EP Interrupt register
|
---|
985 | * @param USBx : Selected device
|
---|
986 | * @param epnum : endpoint number
|
---|
987 | * This parameter can be a value from 0 to 15
|
---|
988 | * @retval Device OUT EP Interrupt register
|
---|
989 | */
|
---|
990 | uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
|
---|
991 | {
|
---|
992 | uint32_t v;
|
---|
993 | v = USBx_OUTEP(epnum)->DOEPINT;
|
---|
994 | v &= USBx_DEVICE->DOEPMSK;
|
---|
995 | return v;
|
---|
996 | }
|
---|
997 |
|
---|
998 | /**
|
---|
999 | * @brief Returns Device IN EP Interrupt register
|
---|
1000 | * @param USBx : Selected device
|
---|
1001 | * @param epnum : endpoint number
|
---|
1002 | * This parameter can be a value from 0 to 15
|
---|
1003 | * @retval Device IN EP Interrupt register
|
---|
1004 | */
|
---|
1005 | uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
|
---|
1006 | {
|
---|
1007 | uint32_t v, msk, emp;
|
---|
1008 |
|
---|
1009 | msk = USBx_DEVICE->DIEPMSK;
|
---|
1010 | emp = USBx_DEVICE->DIEPEMPMSK;
|
---|
1011 | msk |= ((emp >> epnum) & 0x1) << 7;
|
---|
1012 | v = USBx_INEP(epnum)->DIEPINT & msk;
|
---|
1013 | return v;
|
---|
1014 | }
|
---|
1015 |
|
---|
1016 | /**
|
---|
1017 | * @brief USB_ClearInterrupts: clear a USB interrupt
|
---|
1018 | * @param USBx : Selected device
|
---|
1019 | * @param interrupt : interrupt flag
|
---|
1020 | * @retval None
|
---|
1021 | */
|
---|
1022 | void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
|
---|
1023 | {
|
---|
1024 | USBx->GINTSTS |= interrupt;
|
---|
1025 | }
|
---|
1026 |
|
---|
1027 | /**
|
---|
1028 | * @brief Returns USB core mode
|
---|
1029 | * @param USBx : Selected device
|
---|
1030 | * @retval return core mode : Host or Device
|
---|
1031 | * This parameter can be one of these values:
|
---|
1032 | * 0 : Host
|
---|
1033 | * 1 : Device
|
---|
1034 | */
|
---|
1035 | uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
|
---|
1036 | {
|
---|
1037 | return ((USBx->GINTSTS ) & 0x1);
|
---|
1038 | }
|
---|
1039 |
|
---|
1040 |
|
---|
1041 | /**
|
---|
1042 | * @brief Activate EP0 for Setup transactions
|
---|
1043 | * @param USBx : Selected device
|
---|
1044 | * @retval HAL status
|
---|
1045 | */
|
---|
1046 | HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
|
---|
1047 | {
|
---|
1048 | /* Set the MPS of the IN EP based on the enumeration speed */
|
---|
1049 | USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
|
---|
1050 |
|
---|
1051 | if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
|
---|
1052 | {
|
---|
1053 | USBx_INEP(0)->DIEPCTL |= 3;
|
---|
1054 | }
|
---|
1055 | USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
|
---|
1056 |
|
---|
1057 | return HAL_OK;
|
---|
1058 | }
|
---|
1059 |
|
---|
1060 |
|
---|
1061 | /**
|
---|
1062 | * @brief Prepare the EP0 to start the first control setup
|
---|
1063 | * @param USBx : Selected device
|
---|
1064 | * @param dma: USB dma enabled or disabled
|
---|
1065 | * This parameter can be one of these values:
|
---|
1066 | * 0 : DMA feature not used
|
---|
1067 | * 1 : DMA feature used
|
---|
1068 | * @param psetup : pointer to setup packet
|
---|
1069 | * @retval HAL status
|
---|
1070 | */
|
---|
1071 | HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
|
---|
1072 | {
|
---|
1073 | USBx_OUTEP(0)->DOEPTSIZ = 0;
|
---|
1074 | USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
|
---|
1075 | USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8);
|
---|
1076 | USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
|
---|
1077 |
|
---|
1078 | if (dma == 1)
|
---|
1079 | {
|
---|
1080 | USBx_OUTEP(0)->DOEPDMA = (uint32_t)psetup;
|
---|
1081 | /* EP enable */
|
---|
1082 | USBx_OUTEP(0)->DOEPCTL = 0x80008000;
|
---|
1083 | }
|
---|
1084 |
|
---|
1085 | return HAL_OK;
|
---|
1086 | }
|
---|
1087 |
|
---|
1088 |
|
---|
1089 | /**
|
---|
1090 | * @brief Reset the USB Core (needed after USB clock settings change)
|
---|
1091 | * @param USBx : Selected device
|
---|
1092 | * @retval HAL status
|
---|
1093 | */
|
---|
1094 | static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
|
---|
1095 | {
|
---|
1096 | uint32_t count = 0;
|
---|
1097 |
|
---|
1098 | /* Wait for AHB master IDLE state. */
|
---|
1099 | do
|
---|
1100 | {
|
---|
1101 | if (++count > 200000)
|
---|
1102 | {
|
---|
1103 | return HAL_TIMEOUT;
|
---|
1104 | }
|
---|
1105 | }
|
---|
1106 | while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);
|
---|
1107 |
|
---|
1108 | /* Core Soft Reset */
|
---|
1109 | count = 0;
|
---|
1110 | USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
|
---|
1111 |
|
---|
1112 | do
|
---|
1113 | {
|
---|
1114 | if (++count > 200000)
|
---|
1115 | {
|
---|
1116 | return HAL_TIMEOUT;
|
---|
1117 | }
|
---|
1118 | }
|
---|
1119 | while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
|
---|
1120 |
|
---|
1121 | return HAL_OK;
|
---|
1122 | }
|
---|
1123 |
|
---|
1124 |
|
---|
1125 | /**
|
---|
1126 | * @brief USB_HostInit : Initializes the USB OTG controller registers
|
---|
1127 | * for Host mode
|
---|
1128 | * @param USBx : Selected device
|
---|
1129 | * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
|
---|
1130 | * the configuration information for the specified USBx peripheral.
|
---|
1131 | * @retval HAL status
|
---|
1132 | */
|
---|
1133 | HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
|
---|
1134 | {
|
---|
1135 | uint32_t i;
|
---|
1136 |
|
---|
1137 | /* Restart the Phy Clock */
|
---|
1138 | USBx_PCGCCTL = 0;
|
---|
1139 |
|
---|
1140 | /* Activate VBUS Sensing B */
|
---|
1141 | #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
---|
1142 | USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
|
---|
1143 | #else
|
---|
1144 | USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSASEN);
|
---|
1145 | USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSBSEN);
|
---|
1146 | USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
|
---|
1147 | #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
|
---|
1148 |
|
---|
1149 | /* Disable the FS/LS support mode only */
|
---|
1150 | if((cfg.speed == USB_OTG_SPEED_FULL)&&
|
---|
1151 | (USBx != USB_OTG_FS))
|
---|
1152 | {
|
---|
1153 | USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
|
---|
1154 | }
|
---|
1155 | else
|
---|
1156 | {
|
---|
1157 | USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
|
---|
1158 | }
|
---|
1159 |
|
---|
1160 | /* Make sure the FIFOs are flushed. */
|
---|
1161 | USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */
|
---|
1162 | USB_FlushRxFifo(USBx);
|
---|
1163 |
|
---|
1164 | /* Clear all pending HC Interrupts */
|
---|
1165 | for (i = 0; i < cfg.Host_channels; i++)
|
---|
1166 | {
|
---|
1167 | USBx_HC(i)->HCINT = 0xFFFFFFFF;
|
---|
1168 | USBx_HC(i)->HCINTMSK = 0;
|
---|
1169 | }
|
---|
1170 |
|
---|
1171 | /* Enable VBUS driving */
|
---|
1172 | USB_DriveVbus(USBx, 1);
|
---|
1173 |
|
---|
1174 | HAL_Delay(200);
|
---|
1175 |
|
---|
1176 | /* Disable all interrupts. */
|
---|
1177 | USBx->GINTMSK = 0;
|
---|
1178 |
|
---|
1179 | /* Clear any pending interrupts */
|
---|
1180 | USBx->GINTSTS = 0xFFFFFFFF;
|
---|
1181 |
|
---|
1182 | if(USBx == USB_OTG_FS)
|
---|
1183 | {
|
---|
1184 | /* set Rx FIFO size */
|
---|
1185 | USBx->GRXFSIZ = (uint32_t )0x80;
|
---|
1186 | USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);
|
---|
1187 | USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);
|
---|
1188 | }
|
---|
1189 | else
|
---|
1190 | {
|
---|
1191 | /* set Rx FIFO size */
|
---|
1192 | USBx->GRXFSIZ = (uint32_t )0x200;
|
---|
1193 | USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100 << 16)& USB_OTG_NPTXFD) | 0x200);
|
---|
1194 | USBx->HPTXFSIZ = (uint32_t )(((0xE0 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300);
|
---|
1195 | }
|
---|
1196 |
|
---|
1197 | /* Enable the common interrupts */
|
---|
1198 | if (cfg.dma_enable == DISABLE)
|
---|
1199 | {
|
---|
1200 | USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
|
---|
1201 | }
|
---|
1202 |
|
---|
1203 | /* Enable interrupts matching to the Host mode ONLY */
|
---|
1204 | USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\
|
---|
1205 | USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\
|
---|
1206 | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
|
---|
1207 |
|
---|
1208 | return HAL_OK;
|
---|
1209 | }
|
---|
1210 |
|
---|
1211 | /**
|
---|
1212 | * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
|
---|
1213 | * HCFG register on the PHY type and set the right frame interval
|
---|
1214 | * @param USBx : Selected device
|
---|
1215 | * @param freq : clock frequency
|
---|
1216 | * This parameter can be one of these values:
|
---|
1217 | * HCFG_48_MHZ : Full Speed 48 MHz Clock
|
---|
1218 | * HCFG_6_MHZ : Low Speed 6 MHz Clock
|
---|
1219 | * @retval HAL status
|
---|
1220 | */
|
---|
1221 | HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
|
---|
1222 | {
|
---|
1223 | USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
|
---|
1224 | USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);
|
---|
1225 |
|
---|
1226 | if (freq == HCFG_48_MHZ)
|
---|
1227 | {
|
---|
1228 | USBx_HOST->HFIR = (uint32_t)48000;
|
---|
1229 | }
|
---|
1230 | else if (freq == HCFG_6_MHZ)
|
---|
1231 | {
|
---|
1232 | USBx_HOST->HFIR = (uint32_t)6000;
|
---|
1233 | }
|
---|
1234 | return HAL_OK;
|
---|
1235 | }
|
---|
1236 |
|
---|
1237 | /**
|
---|
1238 | * @brief USB_OTG_ResetPort : Reset Host Port
|
---|
1239 | * @param USBx : Selected device
|
---|
1240 | * @retval HAL status
|
---|
1241 | * @note (1)The application must wait at least 10 ms
|
---|
1242 | * before clearing the reset bit.
|
---|
1243 | */
|
---|
1244 | HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
|
---|
1245 | {
|
---|
1246 | __IO uint32_t hprt0;
|
---|
1247 |
|
---|
1248 | hprt0 = USBx_HPRT0;
|
---|
1249 |
|
---|
1250 | hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
|
---|
1251 | USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
|
---|
1252 |
|
---|
1253 | USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
|
---|
1254 | HAL_Delay (10); /* See Note #1 */
|
---|
1255 | USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
|
---|
1256 | return HAL_OK;
|
---|
1257 | }
|
---|
1258 |
|
---|
1259 | /**
|
---|
1260 | * @brief USB_DriveVbus : activate or de-activate vbus
|
---|
1261 | * @param state : VBUS state
|
---|
1262 | * This parameter can be one of these values:
|
---|
1263 | * 0 : VBUS Active
|
---|
1264 | * 1 : VBUS Inactive
|
---|
1265 | * @retval HAL status
|
---|
1266 | */
|
---|
1267 | HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
|
---|
1268 | {
|
---|
1269 | __IO uint32_t hprt0;
|
---|
1270 |
|
---|
1271 | hprt0 = USBx_HPRT0;
|
---|
1272 | hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
|
---|
1273 | USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
|
---|
1274 |
|
---|
1275 | if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))
|
---|
1276 | {
|
---|
1277 | USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
|
---|
1278 | }
|
---|
1279 | if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 ))
|
---|
1280 | {
|
---|
1281 | USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
|
---|
1282 | }
|
---|
1283 | return HAL_OK;
|
---|
1284 | }
|
---|
1285 |
|
---|
1286 | /**
|
---|
1287 | * @brief Return Host Core speed
|
---|
1288 | * @param USBx : Selected device
|
---|
1289 | * @retval speed : Host speed
|
---|
1290 | * This parameter can be one of these values:
|
---|
1291 | * @arg USB_OTG_SPEED_HIGH: High speed mode
|
---|
1292 | * @arg USB_OTG_SPEED_FULL: Full speed mode
|
---|
1293 | * @arg USB_OTG_SPEED_LOW: Low speed mode
|
---|
1294 | */
|
---|
1295 | uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
|
---|
1296 | {
|
---|
1297 | __IO uint32_t hprt0;
|
---|
1298 |
|
---|
1299 | hprt0 = USBx_HPRT0;
|
---|
1300 | return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
|
---|
1301 | }
|
---|
1302 |
|
---|
1303 | /**
|
---|
1304 | * @brief Return Host Current Frame number
|
---|
1305 | * @param USBx : Selected device
|
---|
1306 | * @retval current frame number
|
---|
1307 | */
|
---|
1308 | uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
|
---|
1309 | {
|
---|
1310 | return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
|
---|
1311 | }
|
---|
1312 |
|
---|
1313 | /**
|
---|
1314 | * @brief Initialize a host channel
|
---|
1315 | * @param USBx : Selected device
|
---|
1316 | * @param ch_num : Channel number
|
---|
1317 | * This parameter can be a value from 1 to 15
|
---|
1318 | * @param epnum : Endpoint number
|
---|
1319 | * This parameter can be a value from 1 to 15
|
---|
1320 | * @param dev_address : Current device address
|
---|
1321 | * This parameter can be a value from 0 to 255
|
---|
1322 | * @param speed : Current device speed
|
---|
1323 | * This parameter can be one of these values:
|
---|
1324 | * @arg USB_OTG_SPEED_HIGH: High speed mode
|
---|
1325 | * @arg USB_OTG_SPEED_FULL: Full speed mode
|
---|
1326 | * @arg USB_OTG_SPEED_LOW: Low speed mode
|
---|
1327 | * @param ep_type : Endpoint Type
|
---|
1328 | * This parameter can be one of these values:
|
---|
1329 | * @arg EP_TYPE_CTRL: Control type
|
---|
1330 | * @arg EP_TYPE_ISOC: Isochronous type
|
---|
1331 | * @arg EP_TYPE_BULK: Bulk type
|
---|
1332 | * @arg EP_TYPE_INTR: Interrupt type
|
---|
1333 | * @param mps : Max Packet Size
|
---|
1334 | * This parameter can be a value from 0 to32K
|
---|
1335 | * @retval HAL state
|
---|
1336 | */
|
---|
1337 | HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
|
---|
1338 | uint8_t ch_num,
|
---|
1339 | uint8_t epnum,
|
---|
1340 | uint8_t dev_address,
|
---|
1341 | uint8_t speed,
|
---|
1342 | uint8_t ep_type,
|
---|
1343 | uint16_t mps)
|
---|
1344 | {
|
---|
1345 |
|
---|
1346 | /* Clear old interrupt conditions for this host channel. */
|
---|
1347 | USBx_HC(ch_num)->HCINT = 0xFFFFFFFF;
|
---|
1348 |
|
---|
1349 | /* Enable channel interrupts required for this transfer. */
|
---|
1350 | switch (ep_type)
|
---|
1351 | {
|
---|
1352 | case EP_TYPE_CTRL:
|
---|
1353 | case EP_TYPE_BULK:
|
---|
1354 |
|
---|
1355 | USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
|
---|
1356 | USB_OTG_HCINTMSK_STALLM |\
|
---|
1357 | USB_OTG_HCINTMSK_TXERRM |\
|
---|
1358 | USB_OTG_HCINTMSK_DTERRM |\
|
---|
1359 | USB_OTG_HCINTMSK_AHBERR |\
|
---|
1360 | USB_OTG_HCINTMSK_NAKM ;
|
---|
1361 |
|
---|
1362 | if (epnum & 0x80)
|
---|
1363 | {
|
---|
1364 | USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
|
---|
1365 | }
|
---|
1366 | else
|
---|
1367 | {
|
---|
1368 | if(USBx != USB_OTG_FS)
|
---|
1369 | {
|
---|
1370 | USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
|
---|
1371 | }
|
---|
1372 | }
|
---|
1373 | break;
|
---|
1374 |
|
---|
1375 | case EP_TYPE_INTR:
|
---|
1376 |
|
---|
1377 | USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
|
---|
1378 | USB_OTG_HCINTMSK_STALLM |\
|
---|
1379 | USB_OTG_HCINTMSK_TXERRM |\
|
---|
1380 | USB_OTG_HCINTMSK_DTERRM |\
|
---|
1381 | USB_OTG_HCINTMSK_NAKM |\
|
---|
1382 | USB_OTG_HCINTMSK_AHBERR |\
|
---|
1383 | USB_OTG_HCINTMSK_FRMORM ;
|
---|
1384 |
|
---|
1385 | if (epnum & 0x80)
|
---|
1386 | {
|
---|
1387 | USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
|
---|
1388 | }
|
---|
1389 |
|
---|
1390 | break;
|
---|
1391 | case EP_TYPE_ISOC:
|
---|
1392 |
|
---|
1393 | USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
|
---|
1394 | USB_OTG_HCINTMSK_ACKM |\
|
---|
1395 | USB_OTG_HCINTMSK_AHBERR |\
|
---|
1396 | USB_OTG_HCINTMSK_FRMORM ;
|
---|
1397 |
|
---|
1398 | if (epnum & 0x80)
|
---|
1399 | {
|
---|
1400 | USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
|
---|
1401 | }
|
---|
1402 | break;
|
---|
1403 | }
|
---|
1404 |
|
---|
1405 | /* Enable the top level host channel interrupt. */
|
---|
1406 | USBx_HOST->HAINTMSK |= (1 << ch_num);
|
---|
1407 |
|
---|
1408 | /* Make sure host channel interrupts are enabled. */
|
---|
1409 | USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
|
---|
1410 |
|
---|
1411 | /* Program the HCCHAR register */
|
---|
1412 | USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\
|
---|
1413 | (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\
|
---|
1414 | ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\
|
---|
1415 | (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\
|
---|
1416 | ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\
|
---|
1417 | (mps & USB_OTG_HCCHAR_MPSIZ));
|
---|
1418 |
|
---|
1419 | if (ep_type == EP_TYPE_INTR)
|
---|
1420 | {
|
---|
1421 | USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
|
---|
1422 | }
|
---|
1423 |
|
---|
1424 | return HAL_OK;
|
---|
1425 | }
|
---|
1426 |
|
---|
1427 | /**
|
---|
1428 | * @brief Start a transfer over a host channel
|
---|
1429 | * @param USBx : Selected device
|
---|
1430 | * @param hc : pointer to host channel structure
|
---|
1431 | * @param dma: USB dma enabled or disabled
|
---|
1432 | * This parameter can be one of these values:
|
---|
1433 | * 0 : DMA feature not used
|
---|
1434 | * 1 : DMA feature used
|
---|
1435 | * @retval HAL state
|
---|
1436 | */
|
---|
1437 | #if defined (__CC_ARM) /*!< ARM Compiler */
|
---|
1438 | #pragma O0
|
---|
1439 | #elif defined (__GNUC__) /*!< GNU Compiler */
|
---|
1440 | #pragma GCC optimize ("O0")
|
---|
1441 | #endif /* __CC_ARM */
|
---|
1442 | HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
|
---|
1443 | {
|
---|
1444 | uint8_t is_oddframe = 0;
|
---|
1445 | uint16_t len_words = 0;
|
---|
1446 | uint16_t num_packets = 0;
|
---|
1447 | uint16_t max_hc_pkt_count = 256;
|
---|
1448 | uint32_t tmpreg = 0;
|
---|
1449 |
|
---|
1450 | if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))
|
---|
1451 | {
|
---|
1452 | if((dma == 0) && (hc->do_ping == 1))
|
---|
1453 | {
|
---|
1454 | USB_DoPing(USBx, hc->ch_num);
|
---|
1455 | return HAL_OK;
|
---|
1456 | }
|
---|
1457 | else if(dma == 1)
|
---|
1458 | {
|
---|
1459 | USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
|
---|
1460 | hc->do_ping = 0;
|
---|
1461 | }
|
---|
1462 | }
|
---|
1463 |
|
---|
1464 | /* Compute the expected number of packets associated to the transfer */
|
---|
1465 | if (hc->xfer_len > 0)
|
---|
1466 | {
|
---|
1467 | num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;
|
---|
1468 |
|
---|
1469 | if (num_packets > max_hc_pkt_count)
|
---|
1470 | {
|
---|
1471 | num_packets = max_hc_pkt_count;
|
---|
1472 | hc->xfer_len = num_packets * hc->max_packet;
|
---|
1473 | }
|
---|
1474 | }
|
---|
1475 | else
|
---|
1476 | {
|
---|
1477 | num_packets = 1;
|
---|
1478 | }
|
---|
1479 | if (hc->ep_is_in)
|
---|
1480 | {
|
---|
1481 | hc->xfer_len = num_packets * hc->max_packet;
|
---|
1482 | }
|
---|
1483 |
|
---|
1484 | /* Initialize the HCTSIZn register */
|
---|
1485 | USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
|
---|
1486 | ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
|
---|
1487 | (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);
|
---|
1488 |
|
---|
1489 | if (dma)
|
---|
1490 | {
|
---|
1491 | /* xfer_buff MUST be 32-bits aligned */
|
---|
1492 | USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
|
---|
1493 | }
|
---|
1494 |
|
---|
1495 | is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;
|
---|
1496 | USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
|
---|
1497 | USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);
|
---|
1498 |
|
---|
1499 | /* Set host channel enable */
|
---|
1500 | tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
|
---|
1501 | tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
---|
1502 | tmpreg |= USB_OTG_HCCHAR_CHENA;
|
---|
1503 | USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
|
---|
1504 |
|
---|
1505 | if (dma == 0) /* Slave mode */
|
---|
1506 | {
|
---|
1507 | if((hc->ep_is_in == 0) && (hc->xfer_len > 0))
|
---|
1508 | {
|
---|
1509 | switch(hc->ep_type)
|
---|
1510 | {
|
---|
1511 | /* Non periodic transfer */
|
---|
1512 | case EP_TYPE_CTRL:
|
---|
1513 | case EP_TYPE_BULK:
|
---|
1514 |
|
---|
1515 | len_words = (hc->xfer_len + 3) / 4;
|
---|
1516 |
|
---|
1517 | /* check if there is enough space in FIFO space */
|
---|
1518 | if(len_words > (USBx->HNPTXSTS & 0xFFFF))
|
---|
1519 | {
|
---|
1520 | /* need to process data in nptxfempty interrupt */
|
---|
1521 | USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
|
---|
1522 | }
|
---|
1523 | break;
|
---|
1524 | /* Periodic transfer */
|
---|
1525 | case EP_TYPE_INTR:
|
---|
1526 | case EP_TYPE_ISOC:
|
---|
1527 | len_words = (hc->xfer_len + 3) / 4;
|
---|
1528 | /* check if there is enough space in FIFO space */
|
---|
1529 | if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */
|
---|
1530 | {
|
---|
1531 | /* need to process data in ptxfempty interrupt */
|
---|
1532 | USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
|
---|
1533 | }
|
---|
1534 | break;
|
---|
1535 |
|
---|
1536 | default:
|
---|
1537 | break;
|
---|
1538 | }
|
---|
1539 |
|
---|
1540 | /* Write packet into the Tx FIFO. */
|
---|
1541 | USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);
|
---|
1542 | }
|
---|
1543 | }
|
---|
1544 |
|
---|
1545 | return HAL_OK;
|
---|
1546 | }
|
---|
1547 |
|
---|
1548 | /**
|
---|
1549 | * @brief Read all host channel interrupts status
|
---|
1550 | * @param USBx : Selected device
|
---|
1551 | * @retval HAL state
|
---|
1552 | */
|
---|
1553 | uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
|
---|
1554 | {
|
---|
1555 | return ((USBx_HOST->HAINT) & 0xFFFF);
|
---|
1556 | }
|
---|
1557 |
|
---|
1558 | /**
|
---|
1559 | * @brief Halt a host channel
|
---|
1560 | * @param USBx : Selected device
|
---|
1561 | * @param hc_num : Host Channel number
|
---|
1562 | * This parameter can be a value from 1 to 15
|
---|
1563 | * @retval HAL state
|
---|
1564 | */
|
---|
1565 | HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
|
---|
1566 | {
|
---|
1567 | uint32_t count = 0;
|
---|
1568 |
|
---|
1569 | /* Check for space in the request queue to issue the halt. */
|
---|
1570 | if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18)))
|
---|
1571 | {
|
---|
1572 | USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
|
---|
1573 |
|
---|
1574 | if ((USBx->HNPTXSTS & 0xFFFF) == 0)
|
---|
1575 | {
|
---|
1576 | USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
|
---|
1577 | USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
|
---|
1578 | USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
|
---|
1579 | do
|
---|
1580 | {
|
---|
1581 | if (++count > 1000)
|
---|
1582 | {
|
---|
1583 | break;
|
---|
1584 | }
|
---|
1585 | }
|
---|
1586 | while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
|
---|
1587 | }
|
---|
1588 | else
|
---|
1589 | {
|
---|
1590 | USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
|
---|
1591 | }
|
---|
1592 | }
|
---|
1593 | else
|
---|
1594 | {
|
---|
1595 | USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
|
---|
1596 |
|
---|
1597 | if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0)
|
---|
1598 | {
|
---|
1599 | USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
|
---|
1600 | USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
|
---|
1601 | USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
|
---|
1602 | do
|
---|
1603 | {
|
---|
1604 | if (++count > 1000)
|
---|
1605 | {
|
---|
1606 | break;
|
---|
1607 | }
|
---|
1608 | }
|
---|
1609 | while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
|
---|
1610 | }
|
---|
1611 | else
|
---|
1612 | {
|
---|
1613 | USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
|
---|
1614 | }
|
---|
1615 | }
|
---|
1616 |
|
---|
1617 | return HAL_OK;
|
---|
1618 | }
|
---|
1619 |
|
---|
1620 | /**
|
---|
1621 | * @brief Initiate Do Ping protocol
|
---|
1622 | * @param USBx : Selected device
|
---|
1623 | * @param hc_num : Host Channel number
|
---|
1624 | * This parameter can be a value from 1 to 15
|
---|
1625 | * @retval HAL state
|
---|
1626 | */
|
---|
1627 | HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
|
---|
1628 | {
|
---|
1629 | uint8_t num_packets = 1;
|
---|
1630 | uint32_t tmpreg = 0;
|
---|
1631 |
|
---|
1632 | USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
|
---|
1633 | USB_OTG_HCTSIZ_DOPING;
|
---|
1634 |
|
---|
1635 | /* Set host channel enable */
|
---|
1636 | tmpreg = USBx_HC(ch_num)->HCCHAR;
|
---|
1637 | tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
---|
1638 | tmpreg |= USB_OTG_HCCHAR_CHENA;
|
---|
1639 | USBx_HC(ch_num)->HCCHAR = tmpreg;
|
---|
1640 |
|
---|
1641 | return HAL_OK;
|
---|
1642 | }
|
---|
1643 |
|
---|
1644 | /**
|
---|
1645 | * @brief Stop Host Core
|
---|
1646 | * @param USBx : Selected device
|
---|
1647 | * @retval HAL state
|
---|
1648 | */
|
---|
1649 | HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
|
---|
1650 | {
|
---|
1651 | uint8_t i;
|
---|
1652 | uint32_t count = 0;
|
---|
1653 | uint32_t value;
|
---|
1654 |
|
---|
1655 | USB_DisableGlobalInt(USBx);
|
---|
1656 |
|
---|
1657 | /* Flush FIFO */
|
---|
1658 | USB_FlushTxFifo(USBx, 0x10);
|
---|
1659 | USB_FlushRxFifo(USBx);
|
---|
1660 |
|
---|
1661 | /* Flush out any leftover queued requests. */
|
---|
1662 | for (i = 0; i <= 15; i++)
|
---|
1663 | {
|
---|
1664 |
|
---|
1665 | value = USBx_HC(i)->HCCHAR ;
|
---|
1666 | value |= USB_OTG_HCCHAR_CHDIS;
|
---|
1667 | value &= ~USB_OTG_HCCHAR_CHENA;
|
---|
1668 | value &= ~USB_OTG_HCCHAR_EPDIR;
|
---|
1669 | USBx_HC(i)->HCCHAR = value;
|
---|
1670 | }
|
---|
1671 |
|
---|
1672 | /* Halt all channels to put them into a known state. */
|
---|
1673 | for (i = 0; i <= 15; i++)
|
---|
1674 | {
|
---|
1675 | value = USBx_HC(i)->HCCHAR ;
|
---|
1676 |
|
---|
1677 | value |= USB_OTG_HCCHAR_CHDIS;
|
---|
1678 | value |= USB_OTG_HCCHAR_CHENA;
|
---|
1679 | value &= ~USB_OTG_HCCHAR_EPDIR;
|
---|
1680 |
|
---|
1681 | USBx_HC(i)->HCCHAR = value;
|
---|
1682 | do
|
---|
1683 | {
|
---|
1684 | if (++count > 1000)
|
---|
1685 | {
|
---|
1686 | break;
|
---|
1687 | }
|
---|
1688 | }
|
---|
1689 | while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
|
---|
1690 | }
|
---|
1691 |
|
---|
1692 | /* Clear any pending Host interrupts */
|
---|
1693 | USBx_HOST->HAINT = 0xFFFFFFFF;
|
---|
1694 | USBx->GINTSTS = 0xFFFFFFFF;
|
---|
1695 | USB_EnableGlobalInt(USBx);
|
---|
1696 | return HAL_OK;
|
---|
1697 | }
|
---|
1698 | /**
|
---|
1699 | * @}
|
---|
1700 | */
|
---|
1701 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
|
---|
1702 | STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
|
---|
1703 | #endif /* defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) */
|
---|
1704 |
|
---|
1705 | /**
|
---|
1706 | * @}
|
---|
1707 | */
|
---|
1708 |
|
---|
1709 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
---|