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source: asp3_wo_tecs/trunk/arch/arm_m_gcc/stm32f4xx_stm32cube/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c@ 303

Last change on this file since 303 was 303, checked in by ertl-honda, 7 years ago
nucleo_f401re依存部の追加
File size: 60.7 KB

Line
1	/**
2	******************************************************************************
3	* @file stm32f4xx_ll_fmc.c
4	* @author MCD Application Team
5	* @version V1.4.1
6	* @date 09-October-2015
7	* @brief FMC Low Layer HAL module driver.
8	*
9	* This file provides firmware functions to manage the following
10	* functionalities of the Flexible Memory Controller (FMC) peripheral memories:
11	* + Initialization/de-initialization functions
12	* + Peripheral Control functions
13	* + Peripheral State functions
14	*
15	@verbatim
16	==============================================================================
17	##### FMC peripheral features #####
18	==============================================================================
19	[..] The Flexible memory controller (FMC) includes three memory controllers:
20	(+) The NOR/PSRAM memory controller
21	(+) The NAND/PC Card memory controller
22	(+) The Synchronous DRAM (SDRAM) controller
23
24	[..] The FMC functional block makes the interface with synchronous and asynchronous static
25	memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
26	(+) to translate AHB transactions into the appropriate external device protocol
27	(+) to meet the access time requirements of the external memory devices
28
29	[..] All external memories share the addresses, data and control signals with the controller.
30	Each external device is accessed by means of a unique Chip Select. The FMC performs
31	only one access at a time to an external device.
32	The main features of the FMC controller are the following:
33	(+) Interface with static-memory mapped devices including:
34	(++) Static random access memory (SRAM)
35	(++) Read-only memory (ROM)
36	(++) NOR Flash memory/OneNAND Flash memory
37	(++) PSRAM (4 memory banks)
38	(++) 16-bit PC Card compatible devices
39	(++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
40	data
41	(+) Interface with synchronous DRAM (SDRAM) memories
42	(+) Independent Chip Select control for each memory bank
43	(+) Independent configuration for each memory bank
44
45	@endverbatim
46	******************************************************************************
47	* @attention
48	*
49	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
50	*
51	* Redistribution and use in source and binary forms, with or without modification,
52	* are permitted provided that the following conditions are met:
53	* 1. Redistributions of source code must retain the above copyright notice,
54	* this list of conditions and the following disclaimer.
55	* 2. Redistributions in binary form must reproduce the above copyright notice,
56	* this list of conditions and the following disclaimer in the documentation
57	* and/or other materials provided with the distribution.
58	* 3. Neither the name of STMicroelectronics nor the names of its contributors
59	* may be used to endorse or promote products derived from this software
60	* without specific prior written permission.
61	*
62	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
63	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
64	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
65	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
66	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
67	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
68	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
69	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
70	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
71	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
72	*
73	******************************************************************************
74	*/
75
76	/* Includes ------------------------------------------------------------------*/
77	#include "stm32f4xx_hal.h"
78
79	/** @addtogroup STM32F4xx_HAL_Driver
80	* @{
81	*/
82
83	/** @defgroup FMC_LL FMC Low Layer
84	* @brief FMC driver modules
85	* @{
86	*/
87
88	#if defined (HAL_SRAM_MODULE_ENABLED) \|\| defined(HAL_NOR_MODULE_ENABLED) \|\| defined(HAL_NAND_MODULE_ENABLED) \|\| defined(HAL_PCCARD_MODULE_ENABLED) \|\| defined(HAL_SDRAM_MODULE_ENABLED)
89
90	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
91
92	/* Private typedef -----------------------------------------------------------*/
93	/* Private define ------------------------------------------------------------*/
94	/* Private macro -------------------------------------------------------------*/
95	/* Private variables ---------------------------------------------------------*/
96	/* Private function prototypes -----------------------------------------------*/
97	/* Private functions ---------------------------------------------------------*/
98	/** @addtogroup FMC_LL_Private_Functions
99	* @{
100	*/
101
102	/** @addtogroup FMC_LL_NORSRAM
103	* @brief NORSRAM Controller functions
104	*
105	@verbatim
106	==============================================================================
107	##### How to use NORSRAM device driver #####
108	==============================================================================
109
110	[..]
111	This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
112	to run the NORSRAM external devices.
113
114	(+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
115	(+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
116	(+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
117	(+) FMC NORSRAM bank extended timing configuration using the function
118	FMC_NORSRAM_Extended_Timing_Init()
119	(+) FMC NORSRAM bank enable/disable write operation using the functions
120	FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
121
122
123	@endverbatim
124	* @{
125	*/
126
127	/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group1
128	* @brief Initialization and Configuration functions
129	*
130	@verbatim
131	==============================================================================
132	##### Initialization and de_initialization functions #####
133	==============================================================================
134	[..]
135	This section provides functions allowing to:
136	(+) Initialize and configure the FMC NORSRAM interface
137	(+) De-initialize the FMC NORSRAM interface
138	(+) Configure the FMC clock and associated GPIOs
139
140	@endverbatim
141	* @{
142	*/
143
144	/**
145	* @brief Initialize the FMC_NORSRAM device according to the specified
146	* control parameters in the FMC_NORSRAM_InitTypeDef
147	* @param Device: Pointer to NORSRAM device instance
148	* @param Init: Pointer to NORSRAM Initialization structure
149	* @retval HAL status
150	*/
151	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init)
152	{
153	uint32_t tmpr = 0;
154
155	/* Check the parameters */
156	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
157	assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
158	assert_param(IS_FMC_MUX(Init->DataAddressMux));
159	assert_param(IS_FMC_MEMORY(Init->MemoryType));
160	assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
161	assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
162	assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
163	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
164	assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
165	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
166	assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
167	assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
168	assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
169	assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
170	assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
171	assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
172	assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
173	#if defined (STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
174	assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
175	assert_param(IS_FMC_PAGESIZE(Init->PageSize));
176	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
177
178	/* Get the BTCR register value */
179	tmpr = Device->BTCR[Init->NSBank];
180
181	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
182	/* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
183	WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
184	tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN \| FMC_BCR1_MUXEN \| FMC_BCR1_MTYP \| \
185	FMC_BCR1_MWID \| FMC_BCR1_FACCEN \| FMC_BCR1_BURSTEN \| \
186	FMC_BCR1_WAITPOL \| FMC_BCR1_WRAPMOD \| FMC_BCR1_WAITCFG \| \
187	FMC_BCR1_WREN \| FMC_BCR1_WAITEN \| FMC_BCR1_EXTMOD \| \
188	FMC_BCR1_ASYNCWAIT \| FMC_BCR1_CBURSTRW \| FMC_BCR1_CCLKEN));
189
190	/* Set NORSRAM device control parameters */
191	tmpr \|= (uint32_t)(Init->DataAddressMux \|\
192	Init->MemoryType \|\
193	Init->MemoryDataWidth \|\
194	Init->BurstAccessMode \|\
195	Init->WaitSignalPolarity \|\
196	Init->WrapMode \|\
197	Init->WaitSignalActive \|\
198	Init->WriteOperation \|\
199	Init->WaitSignal \|\
200	Init->ExtendedMode \|\
201	Init->AsynchronousWait \|\
202	Init->WriteBurst \|\
203	Init->ContinuousClock);
204	#else /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
205	/* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, CPSIZE, WAITCFG, WREN,
206	WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW, CCLKEN and WFDIS bits */
207	tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN \| FMC_BCR1_MUXEN \| FMC_BCR1_MTYP \| \
208	FMC_BCR1_MWID \| FMC_BCR1_FACCEN \| FMC_BCR1_BURSTEN \| \
209	FMC_BCR1_WAITPOL \| FMC_BCR1_WAITCFG \| FMC_BCR1_CPSIZE \| \
210	FMC_BCR1_WREN \| FMC_BCR1_WAITEN \| FMC_BCR1_EXTMOD \| \
211	FMC_BCR1_ASYNCWAIT \| FMC_BCR1_CBURSTRW \| FMC_BCR1_CCLKEN \| \
212	FMC_BCR1_WFDIS));
213
214	/* Set NORSRAM device control parameters */
215	tmpr \|= (uint32_t)(Init->DataAddressMux \|\
216	Init->MemoryType \|\
217	Init->MemoryDataWidth \|\
218	Init->BurstAccessMode \|\
219	Init->WaitSignalPolarity \|\
220	Init->WaitSignalActive \|\
221	Init->WriteOperation \|\
222	Init->WaitSignal \|\
223	Init->ExtendedMode \|\
224	Init->AsynchronousWait \|\
225	Init->WriteBurst \|\
226	Init->ContinuousClock \|\
227	Init->PageSize \|\
228	Init->WriteFifo);
229	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
230
231	if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
232	{
233	tmpr \|= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
234	}
235
236	Device->BTCR[Init->NSBank] = tmpr;
237
238	/* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
239	if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
240	{
241	Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE;
242	Device->BTCR[FMC_NORSRAM_BANK1] \|= (uint32_t)(Init->BurstAccessMode \|\
243	Init->ContinuousClock);
244	}
245
246	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
247	if(Init->NSBank != FMC_NORSRAM_BANK1)
248	{
249	Device->BTCR[FMC_NORSRAM_BANK1] \|= (uint32_t)(Init->WriteFifo);
250	}
251	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
252
253	return HAL_OK;
254	}
255
256	/**
257	* @brief DeInitialize the FMC_NORSRAM peripheral
258	* @param Device: Pointer to NORSRAM device instance
259	* @param ExDevice: Pointer to NORSRAM extended mode device instance
260	* @param Bank: NORSRAM bank number
261	* @retval HAL status
262	*/
263	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank)
264	{
265	/* Check the parameters */
266	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
267	assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
268	assert_param(IS_FMC_NORSRAM_BANK(Bank));
269
270	/* Disable the FMC_NORSRAM device */
271	__FMC_NORSRAM_DISABLE(Device, Bank);
272
273	/* De-initialize the FMC_NORSRAM device */
274	/* FMC_NORSRAM_BANK1 */
275	if(Bank == FMC_NORSRAM_BANK1)
276	{
277	Device->BTCR[Bank] = 0x000030DB;
278	}
279	/* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
280	else
281	{
282	Device->BTCR[Bank] = 0x000030D2;
283	}
284
285	Device->BTCR[Bank + 1] = 0x0FFFFFFF;
286	ExDevice->BWTR[Bank] = 0x0FFFFFFF;
287
288	return HAL_OK;
289	}
290
291	/**
292	* @brief Initialize the FMC_NORSRAM Timing according to the specified
293	* parameters in the FMC_NORSRAM_TimingTypeDef
294	* @param Device: Pointer to NORSRAM device instance
295	* @param Timing: Pointer to NORSRAM Timing structure
296	* @param Bank: NORSRAM bank number
297	* @retval HAL status
298	*/
299	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank)
300	{
301	uint32_t tmpr = 0;
302
303	/* Check the parameters */
304	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
305	assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
306	assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
307	assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
308	assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
309	assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
310	assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
311	assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
312	assert_param(IS_FMC_NORSRAM_BANK(Bank));
313
314	/* Get the BTCR register value */
315	tmpr = Device->BTCR[Bank + 1];
316
317	/* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
318	tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET \| FMC_BTR1_ADDHLD \| FMC_BTR1_DATAST \| \
319	FMC_BTR1_BUSTURN \| FMC_BTR1_CLKDIV \| FMC_BTR1_DATLAT \| \
320	FMC_BTR1_ACCMOD));
321
322	/* Set FMC_NORSRAM device timing parameters */
323	tmpr \|= (uint32_t)(Timing->AddressSetupTime \|\
324	((Timing->AddressHoldTime) << 4) \|\
325	((Timing->DataSetupTime) << 8) \|\
326	((Timing->BusTurnAroundDuration) << 16) \|\
327	(((Timing->CLKDivision)-1) << 20) \|\
328	(((Timing->DataLatency)-2) << 24) \|\
329	(Timing->AccessMode));
330
331	Device->BTCR[Bank + 1] = tmpr;
332
333	/* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
334	if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
335	{
336	tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20));
337	tmpr \|= (uint32_t)(((Timing->CLKDivision)-1) << 20);
338	Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
339	}
340
341	return HAL_OK;
342	}
343
344	/**
345	* @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
346	* parameters in the FMC_NORSRAM_TimingTypeDef
347	* @param Device: Pointer to NORSRAM device instance
348	* @param Timing: Pointer to NORSRAM Timing structure
349	* @param Bank: NORSRAM bank number
350	* @retval HAL status
351	*/
352	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode)
353	{
354	uint32_t tmpr = 0;
355
356	/* Check the parameters */
357	assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
358
359	/* Set NORSRAM device timing register for write configuration, if extended mode is used */
360	if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
361	{
362	/* Check the parameters */
363	assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
364	assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
365	assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
366	assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
367	assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
368	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
369	assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
370	assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
371	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
372	assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
373	assert_param(IS_FMC_NORSRAM_BANK(Bank));
374
375	/* Get the BWTR register value */
376	tmpr = Device->BWTR[Bank];
377
378	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
379	/* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
380	tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET \| FMC_BWTR1_ADDHLD \| FMC_BWTR1_DATAST \| \
381	FMC_BWTR1_BUSTURN \| FMC_BWTR1_CLKDIV \| FMC_BWTR1_DATLAT \| \
382	FMC_BWTR1_ACCMOD));
383
384	tmpr \|= (uint32_t)(Timing->AddressSetupTime \|\
385	((Timing->AddressHoldTime) << 4) \|\
386	((Timing->DataSetupTime) << 8) \|\
387	((Timing->BusTurnAroundDuration) << 16) \|\
388	(((Timing->CLKDivision)-1) << 20) \|\
389	(((Timing->DataLatency)-2) << 24) \|\
390	(Timing->AccessMode));
391	#else /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
392	/* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
393	tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET \| FMC_BWTR1_ADDHLD \| FMC_BWTR1_DATAST \| \
394	FMC_BWTR1_BUSTURN \| FMC_BWTR1_ACCMOD));
395
396	tmpr \|= (uint32_t)(Timing->AddressSetupTime \|\
397	((Timing->AddressHoldTime) << 4) \|\
398	((Timing->DataSetupTime) << 8) \|\
399	((Timing->BusTurnAroundDuration) << 16) \|\
400	(Timing->AccessMode));
401	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
402
403	Device->BWTR[Bank] = tmpr;
404	}
405	else
406	{
407	Device->BWTR[Bank] = 0x0FFFFFFF;
408	}
409
410	return HAL_OK;
411	}
412	/**
413	* @}
414	*/
415
416	/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
417	* @brief management functions
418	*
419	@verbatim
420	==============================================================================
421	##### FMC_NORSRAM Control functions #####
422	==============================================================================
423	[..]
424	This subsection provides a set of functions allowing to control dynamically
425	the FMC NORSRAM interface.
426
427	@endverbatim
428	* @{
429	*/
430	/**
431	* @brief Enables dynamically FMC_NORSRAM write operation.
432	* @param Device: Pointer to NORSRAM device instance
433	* @param Bank: NORSRAM bank number
434	* @retval HAL status
435	*/
436	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
437	{
438	/* Check the parameters */
439	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
440	assert_param(IS_FMC_NORSRAM_BANK(Bank));
441
442	/* Enable write operation */
443	Device->BTCR[Bank] \|= FMC_WRITE_OPERATION_ENABLE;
444
445	return HAL_OK;
446	}
447
448	/**
449	* @brief Disables dynamically FMC_NORSRAM write operation.
450	* @param Device: Pointer to NORSRAM device instance
451	* @param Bank: NORSRAM bank number
452	* @retval HAL status
453	*/
454	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
455	{
456	/* Check the parameters */
457	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
458	assert_param(IS_FMC_NORSRAM_BANK(Bank));
459
460	/* Disable write operation */
461	Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
462
463	return HAL_OK;
464	}
465
466	/**
467	* @}
468	*/
469
470	/**
471	* @}
472	*/
473
474	/** @addtogroup FMC_LL_NAND
475	* @brief NAND Controller functions
476	*
477	@verbatim
478	==============================================================================
479	##### How to use NAND device driver #####
480	==============================================================================
481	[..]
482	This driver contains a set of APIs to interface with the FMC NAND banks in order
483	to run the NAND external devices.
484
485	(+) FMC NAND bank reset using the function FMC_NAND_DeInit()
486	(+) FMC NAND bank control configuration using the function FMC_NAND_Init()
487	(+) FMC NAND bank common space timing configuration using the function
488	FMC_NAND_CommonSpace_Timing_Init()
489	(+) FMC NAND bank attribute space timing configuration using the function
490	FMC_NAND_AttributeSpace_Timing_Init()
491	(+) FMC NAND bank enable/disable ECC correction feature using the functions
492	FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
493	(+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
494
495	@endverbatim
496	* @{
497	*/
498
499	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
500	/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
501	* @brief Initialization and Configuration functions
502	*
503	@verbatim
504	==============================================================================
505	##### Initialization and de_initialization functions #####
506	==============================================================================
507	[..]
508	This section provides functions allowing to:
509	(+) Initialize and configure the FMC NAND interface
510	(+) De-initialize the FMC NAND interface
511	(+) Configure the FMC clock and associated GPIOs
512
513	@endverbatim
514	* @{
515	*/
516
517	/**
518	* @brief Initializes the FMC_NAND device according to the specified
519	* control parameters in the FMC_NAND_HandleTypeDef
520	* @param Device: Pointer to NAND device instance
521	* @param Init: Pointer to NAND Initialization structure
522	* @retval HAL status
523	*/
524	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init)
525	{
526	uint32_t tmpr = 0;
527
528	/* Check the parameters */
529	assert_param(IS_FMC_NAND_DEVICE(Device));
530	assert_param(IS_FMC_NAND_BANK(Init->NandBank));
531	assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
532	assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
533	assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
534	assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
535	assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
536	assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
537
538	/* Get the NAND bank register value */
539	tmpr = Device->PCR;
540
541	/* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
542	tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN \| FMC_PCR_PBKEN \| FMC_PCR_PTYP \| \
543	FMC_PCR_PWID \| FMC_PCR_ECCEN \| FMC_PCR_TCLR \| \
544	FMC_PCR_TAR \| FMC_PCR_ECCPS));
545
546	/* Set NAND device control parameters */
547	tmpr \|= (uint32_t)(Init->Waitfeature \|\
548	FMC_PCR_MEMORY_TYPE_NAND \|\
549	Init->MemoryDataWidth \|\
550	Init->EccComputation \|\
551	Init->ECCPageSize \|\
552	((Init->TCLRSetupTime) << 9) \|\
553	((Init->TARSetupTime) << 13));
554
555	/* NAND bank registers configuration */
556	Device->PCR = tmpr;
557
558	return HAL_OK;
559	}
560
561	/**
562	* @brief Initializes the FMC_NAND Common space Timing according to the specified
563	* parameters in the FMC_NAND_PCC_TimingTypeDef
564	* @param Device: Pointer to NAND device instance
565	* @param Timing: Pointer to NAND timing structure
566	* @param Bank: NAND bank number
567	* @retval HAL status
568	*/
569	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank)
570	{
571	uint32_t tmpr = 0;
572
573	/* Check the parameters */
574	assert_param(IS_FMC_NAND_DEVICE(Device));
575	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
576	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
577	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
578	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
579	assert_param(IS_FMC_NAND_BANK(Bank));
580
581	/* Get the NAND bank 2 register value */
582	tmpr = Device->PMEM;
583
584
585	/* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
586	tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET2 \| FMC_PMEM_MEMWAIT2 \| FMC_PMEM_MEMHOLD2 \| \
587	FMC_PMEM_MEMHIZ2));
588
589	/* Set FMC_NAND device timing parameters */
590	tmpr \|= (uint32_t)(Timing->SetupTime \|\
591	((Timing->WaitSetupTime) << 8) \|\
592	((Timing->HoldSetupTime) << 16) \|\
593	((Timing->HiZSetupTime) << 24)
594	);
595
596	/* NAND bank registers configuration */
597	Device->PMEM = tmpr;
598
599	return HAL_OK;
600	}
601
602	/**
603	* @brief Initializes the FMC_NAND Attribute space Timing according to the specified
604	* parameters in the FMC_NAND_PCC_TimingTypeDef
605	* @param Device: Pointer to NAND device instance
606	* @param Timing: Pointer to NAND timing structure
607	* @param Bank: NAND bank number
608	* @retval HAL status
609	*/
610	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank)
611	{
612	uint32_t tmpr = 0;
613
614	/* Check the parameters */
615	assert_param(IS_FMC_NAND_DEVICE(Device));
616	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
617	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
618	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
619	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
620	assert_param(IS_FMC_NAND_BANK(Bank));
621
622	/* Get the NAND bank register value */
623	tmpr = Device->PATT;
624
625	/* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
626	tmpr &= ((uint32_t)~(FMC_PATT_ATTSET2 \| FMC_PATT_ATTWAIT2 \| FMC_PATT_ATTHOLD2 \| \
627	FMC_PATT_ATTHIZ2));
628
629	/* Set FMC_NAND device timing parameters */
630	tmpr \|= (uint32_t)(Timing->SetupTime \|\
631	((Timing->WaitSetupTime) << 8) \|\
632	((Timing->HoldSetupTime) << 16) \|\
633	((Timing->HiZSetupTime) << 24));
634
635	/* NAND bank registers configuration */
636	Device->PATT = tmpr;
637
638	return HAL_OK;
639	}
640
641
642	/**
643	* @brief DeInitializes the FMC_NAND device
644	* @param Device: Pointer to NAND device instance
645	* @param Bank: NAND bank number
646	* @retval HAL status
647	*/
648	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
649	{
650	/* Check the parameters */
651	assert_param(IS_FMC_NAND_DEVICE(Device));
652	assert_param(IS_FMC_NAND_BANK(Bank));
653
654	/* Disable the NAND Bank */
655	__FMC_NAND_DISABLE(Device, Bank);
656
657	/* De-initialize the NAND Bank */
658	/* Set the FMC_NAND_BANK registers to their reset values */
659	Device->PCR = 0x00000018;
660	Device->SR = 0x00000040;
661	Device->PMEM = 0xFCFCFCFC;
662	Device->PATT = 0xFCFCFCFC;
663
664	return HAL_OK;
665	}
666
667	/**
668	* @}
669	*/
670
671
672	/** @defgroup HAL_FMC_NAND_Group2 Control functions
673	* @brief management functions
674	*
675	@verbatim
676	==============================================================================
677	##### FMC_NAND Control functions #####
678	==============================================================================
679	[..]
680	This subsection provides a set of functions allowing to control dynamically
681	the FMC NAND interface.
682
683	@endverbatim
684	* @{
685	*/
686
687
688	/**
689	* @brief Enables dynamically FMC_NAND ECC feature.
690	* @param Device: Pointer to NAND device instance
691	* @param Bank: NAND bank number
692	* @retval HAL status
693	*/
694	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
695	{
696	/* Check the parameters */
697	assert_param(IS_FMC_NAND_DEVICE(Device));
698	assert_param(IS_FMC_NAND_BANK(Bank));
699
700	/* Enable ECC feature */
701	Device->PCR \|= FMC_PCR_ECCEN;
702
703	return HAL_OK;
704	}
705
706
707	/**
708	* @brief Disables dynamically FMC_NAND ECC feature.
709	* @param Device: Pointer to NAND device instance
710	* @param Bank: NAND bank number
711	* @retval HAL status
712	*/
713	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
714	{
715	/* Check the parameters */
716	assert_param(IS_FMC_NAND_DEVICE(Device));
717	assert_param(IS_FMC_NAND_BANK(Bank));
718
719	/* Disable ECC feature */
720	Device->PCR &= ~FMC_PCR_ECCEN;
721
722	return HAL_OK;
723	}
724
725	/**
726	* @brief Disables dynamically FMC_NAND ECC feature.
727	* @param Device: Pointer to NAND device instance
728	* @param ECCval: Pointer to ECC value
729	* @param Bank: NAND bank number
730	* @param Timeout: Timeout wait value
731	* @retval HAL status
732	*/
733	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout)
734	{
735	uint32_t tickstart = 0;
736
737	/* Check the parameters */
738	assert_param(IS_FMC_NAND_DEVICE(Device));
739	assert_param(IS_FMC_NAND_BANK(Bank));
740
741	/* Get tick */
742	tickstart = HAL_GetTick();
743
744	/* Wait until FIFO is empty */
745	while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
746	{
747	/* Check for the Timeout */
748	if(Timeout != HAL_MAX_DELAY)
749	{
750	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
751	{
752	return HAL_TIMEOUT;
753	}
754	}
755	}
756
757	/* Get the ECCR register value */
758	*ECCval = (uint32_t)Device->ECCR;
759
760	return HAL_OK;
761	}
762
763	/**
764	* @}
765	*/
766
767	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
768	/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
769	* @brief Initialization and Configuration functions
770	*
771	@verbatim
772	==============================================================================
773	##### Initialization and de_initialization functions #####
774	==============================================================================
775	[..]
776	This section provides functions allowing to:
777	(+) Initialize and configure the FMC NAND interface
778	(+) De-initialize the FMC NAND interface
779	(+) Configure the FMC clock and associated GPIOs
780
781	@endverbatim
782	* @{
783	*/
784	/**
785	* @brief Initializes the FMC_NAND device according to the specified
786	* control parameters in the FMC_NAND_HandleTypeDef
787	* @param Device: Pointer to NAND device instance
788	* @param Init: Pointer to NAND Initialization structure
789	* @retval HAL status
790	*/
791	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init)
792	{
793	uint32_t tmpr = 0;
794
795	/* Check the parameters */
796	assert_param(IS_FMC_NAND_DEVICE(Device));
797	assert_param(IS_FMC_NAND_BANK(Init->NandBank));
798	assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
799	assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
800	assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
801	assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
802	assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
803	assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
804
805	if(Init->NandBank == FMC_NAND_BANK2)
806	{
807	/* Get the NAND bank 2 register value */
808	tmpr = Device->PCR2;
809	}
810	else
811	{
812	/* Get the NAND bank 3 register value */
813	tmpr = Device->PCR3;
814	}
815
816	/* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
817	tmpr &= ((uint32_t)~(FMC_PCR2_PWAITEN \| FMC_PCR2_PBKEN \| FMC_PCR2_PTYP \| \
818	FMC_PCR2_PWID \| FMC_PCR2_ECCEN \| FMC_PCR2_TCLR \| \
819	FMC_PCR2_TAR \| FMC_PCR2_ECCPS));
820
821	/* Set NAND device control parameters */
822	tmpr \|= (uint32_t)(Init->Waitfeature \|\
823	FMC_PCR_MEMORY_TYPE_NAND \|\
824	Init->MemoryDataWidth \|\
825	Init->EccComputation \|\
826	Init->ECCPageSize \|\
827	((Init->TCLRSetupTime) << 9) \|\
828	((Init->TARSetupTime) << 13));
829
830	if(Init->NandBank == FMC_NAND_BANK2)
831	{
832	/* NAND bank 2 registers configuration */
833	Device->PCR2 = tmpr;
834	}
835	else
836	{
837	/* NAND bank 3 registers configuration */
838	Device->PCR3 = tmpr;
839	}
840
841	return HAL_OK;
842
843	}
844
845	/**
846	* @brief Initializes the FMC_NAND Common space Timing according to the specified
847	* parameters in the FMC_NAND_PCC_TimingTypeDef
848	* @param Device: Pointer to NAND device instance
849	* @param Timing: Pointer to NAND timing structure
850	* @param Bank: NAND bank number
851	* @retval HAL status
852	*/
853	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank)
854	{
855	uint32_t tmpr = 0;
856
857	/* Check the parameters */
858	assert_param(IS_FMC_NAND_DEVICE(Device));
859	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
860	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
861	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
862	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
863	assert_param(IS_FMC_NAND_BANK(Bank));
864
865	if(Bank == FMC_NAND_BANK2)
866	{
867	/* Get the NAND bank 2 register value */
868	tmpr = Device->PMEM2;
869	}
870	else
871	{
872	/* Get the NAND bank 3 register value */
873	tmpr = Device->PMEM3;
874	}
875
876	/* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
877	tmpr &= ((uint32_t)~(FMC_PMEM2_MEMSET2 \| FMC_PMEM2_MEMWAIT2 \| FMC_PMEM2_MEMHOLD2 \| \
878	FMC_PMEM2_MEMHIZ2));
879
880	/* Set FMC_NAND device timing parameters */
881	tmpr \|= (uint32_t)(Timing->SetupTime \|\
882	((Timing->WaitSetupTime) << 8) \|\
883	((Timing->HoldSetupTime) << 16) \|\
884	((Timing->HiZSetupTime) << 24)
885	);
886
887	if(Bank == FMC_NAND_BANK2)
888	{
889	/* NAND bank 2 registers configuration */
890	Device->PMEM2 = tmpr;
891	}
892	else
893	{
894	/* NAND bank 3 registers configuration */
895	Device->PMEM3 = tmpr;
896	}
897
898	return HAL_OK;
899	}
900
901	/**
902	* @brief Initializes the FMC_NAND Attribute space Timing according to the specified
903	* parameters in the FMC_NAND_PCC_TimingTypeDef
904	* @param Device: Pointer to NAND device instance
905	* @param Timing: Pointer to NAND timing structure
906	* @param Bank: NAND bank number
907	* @retval HAL status
908	*/
909	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank)
910	{
911	uint32_t tmpr = 0;
912
913	/* Check the parameters */
914	assert_param(IS_FMC_NAND_DEVICE(Device));
915	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
916	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
917	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
918	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
919	assert_param(IS_FMC_NAND_BANK(Bank));
920
921	if(Bank == FMC_NAND_BANK2)
922	{
923	/* Get the NAND bank 2 register value */
924	tmpr = Device->PATT2;
925	}
926	else
927	{
928	/* Get the NAND bank 3 register value */
929	tmpr = Device->PATT3;
930	}
931
932	/* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
933	tmpr &= ((uint32_t)~(FMC_PATT2_ATTSET2 \| FMC_PATT2_ATTWAIT2 \| FMC_PATT2_ATTHOLD2 \| \
934	FMC_PATT2_ATTHIZ2));
935
936	/* Set FMC_NAND device timing parameters */
937	tmpr \|= (uint32_t)(Timing->SetupTime \|\
938	((Timing->WaitSetupTime) << 8) \|\
939	((Timing->HoldSetupTime) << 16) \|\
940	((Timing->HiZSetupTime) << 24));
941
942	if(Bank == FMC_NAND_BANK2)
943	{
944	/* NAND bank 2 registers configuration */
945	Device->PATT2 = tmpr;
946	}
947	else
948	{
949	/* NAND bank 3 registers configuration */
950	Device->PATT3 = tmpr;
951	}
952
953	return HAL_OK;
954	}
955
956	/**
957	* @brief DeInitializes the FMC_NAND device
958	* @param Device: Pointer to NAND device instance
959	* @param Bank: NAND bank number
960	* @retval HAL status
961	*/
962	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
963	{
964	/* Check the parameters */
965	assert_param(IS_FMC_NAND_DEVICE(Device));
966	assert_param(IS_FMC_NAND_BANK(Bank));
967
968	/* Disable the NAND Bank */
969	__FMC_NAND_DISABLE(Device, Bank);
970
971	/* De-initialize the NAND Bank */
972	if(Bank == FMC_NAND_BANK2)
973	{
974	/* Set the FMC_NAND_BANK2 registers to their reset values */
975	Device->PCR2 = 0x00000018;
976	Device->SR2 = 0x00000040;
977	Device->PMEM2 = 0xFCFCFCFC;
978	Device->PATT2 = 0xFCFCFCFC;
979	}
980	/* FMC_Bank3_NAND */
981	else
982	{
983	/* Set the FMC_NAND_BANK3 registers to their reset values */
984	Device->PCR3 = 0x00000018;
985	Device->SR3 = 0x00000040;
986	Device->PMEM3 = 0xFCFCFCFC;
987	Device->PATT3 = 0xFCFCFCFC;
988	}
989
990	return HAL_OK;
991	}
992
993	/**
994	* @}
995	*/
996
997	/** @addtogroup FMC_LL_NAND_Private_Functions_Group2
998	* @brief management functions
999	*
1000	@verbatim
1001	==============================================================================
1002	##### FMC_NAND Control functions #####
1003	==============================================================================
1004	[..]
1005	This subsection provides a set of functions allowing to control dynamically
1006	the FMC NAND interface.
1007
1008	@endverbatim
1009	* @{
1010	*/
1011	/**
1012	* @brief Enables dynamically FMC_NAND ECC feature.
1013	* @param Device: Pointer to NAND device instance
1014	* @param Bank: NAND bank number
1015	* @retval HAL status
1016	*/
1017	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
1018	{
1019	/* Check the parameters */
1020	assert_param(IS_FMC_NAND_DEVICE(Device));
1021	assert_param(IS_FMC_NAND_BANK(Bank));
1022
1023	/* Enable ECC feature */
1024	if(Bank == FMC_NAND_BANK2)
1025	{
1026	Device->PCR2 \|= FMC_PCR2_ECCEN;
1027	}
1028	else
1029	{
1030	Device->PCR3 \|= FMC_PCR3_ECCEN;
1031	}
1032
1033	return HAL_OK;
1034	}
1035
1036	/**
1037	* @brief Disables dynamically FMC_NAND ECC feature.
1038	* @param Device: Pointer to NAND device instance
1039	* @param Bank: NAND bank number
1040	* @retval HAL status
1041	*/
1042	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
1043	{
1044	/* Check the parameters */
1045	assert_param(IS_FMC_NAND_DEVICE(Device));
1046	assert_param(IS_FMC_NAND_BANK(Bank));
1047
1048	/* Disable ECC feature */
1049	if(Bank == FMC_NAND_BANK2)
1050	{
1051	Device->PCR2 &= ~FMC_PCR2_ECCEN;
1052	}
1053	else
1054	{
1055	Device->PCR3 &= ~FMC_PCR3_ECCEN;
1056	}
1057
1058	return HAL_OK;
1059	}
1060
1061	/**
1062	* @brief Disables dynamically FMC_NAND ECC feature.
1063	* @param Device: Pointer to NAND device instance
1064	* @param ECCval: Pointer to ECC value
1065	* @param Bank: NAND bank number
1066	* @param Timeout: Timeout wait value
1067	* @retval HAL status
1068	*/
1069	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout)
1070	{
1071	uint32_t tickstart = 0;
1072
1073	/* Check the parameters */
1074	assert_param(IS_FMC_NAND_DEVICE(Device));
1075	assert_param(IS_FMC_NAND_BANK(Bank));
1076
1077	/* Get tick */
1078	tickstart = HAL_GetTick();
1079
1080	/* Wait until FIFO is empty */
1081	while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
1082	{
1083	/* Check for the Timeout */
1084	if(Timeout != HAL_MAX_DELAY)
1085	{
1086	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
1087	{
1088	return HAL_TIMEOUT;
1089	}
1090	}
1091	}
1092
1093	if(Bank == FMC_NAND_BANK2)
1094	{
1095	/* Get the ECCR2 register value */
1096	*ECCval = (uint32_t)Device->ECCR2;
1097	}
1098	else
1099	{
1100	/* Get the ECCR3 register value */
1101	*ECCval = (uint32_t)Device->ECCR3;
1102	}
1103
1104	return HAL_OK;
1105	}
1106
1107	/**
1108	* @}
1109	*/
1110
1111	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
1112	/**
1113	* @}
1114	*/
1115
1116	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
1117	/** @addtogroup FMC_LL_PCCARD
1118	* @brief PCCARD Controller functions
1119	*
1120	@verbatim
1121	==============================================================================
1122	##### How to use PCCARD device driver #####
1123	==============================================================================
1124	[..]
1125	This driver contains a set of APIs to interface with the FMC PCCARD bank in order
1126	to run the PCCARD/compact flash external devices.
1127
1128	(+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
1129	(+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
1130	(+) FMC PCCARD bank common space timing configuration using the function
1131	FMC_PCCARD_CommonSpace_Timing_Init()
1132	(+) FMC PCCARD bank attribute space timing configuration using the function
1133	FMC_PCCARD_AttributeSpace_Timing_Init()
1134	(+) FMC PCCARD bank IO space timing configuration using the function
1135	FMC_PCCARD_IOSpace_Timing_Init()
1136	@endverbatim
1137	* @{
1138	*/
1139
1140	/** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1
1141	* @brief Initialization and Configuration functions
1142	*
1143	@verbatim
1144	==============================================================================
1145	##### Initialization and de_initialization functions #####
1146	==============================================================================
1147	[..]
1148	This section provides functions allowing to:
1149	(+) Initialize and configure the FMC PCCARD interface
1150	(+) De-initialize the FMC PCCARD interface
1151	(+) Configure the FMC clock and associated GPIOs
1152
1153	@endverbatim
1154	* @{
1155	*/
1156
1157	/**
1158	* @brief Initializes the FMC_PCCARD device according to the specified
1159	* control parameters in the FMC_PCCARD_HandleTypeDef
1160	* @param Device: Pointer to PCCARD device instance
1161	* @param Init: Pointer to PCCARD Initialization structure
1162	* @retval HAL status
1163	*/
1164	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init)
1165	{
1166	uint32_t tmpr = 0;
1167
1168	/* Check the parameters */
1169	assert_param(IS_FMC_PCCARD_DEVICE(Device));
1170	assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
1171	assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
1172	assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
1173
1174	/* Get PCCARD control register value */
1175	tmpr = Device->PCR4;
1176
1177	/* Clear TAR, TCLR, PWAITEN and PWID bits */
1178	tmpr &= ((uint32_t)~(FMC_PCR4_TAR \| FMC_PCR4_TCLR \| FMC_PCR4_PWAITEN \| \
1179	FMC_PCR4_PWID));
1180
1181	/* Set FMC_PCCARD device control parameters */
1182	tmpr \|= (uint32_t)(Init->Waitfeature \|\
1183	FMC_NAND_PCC_MEM_BUS_WIDTH_16 \|\
1184	(Init->TCLRSetupTime << 9) \|\
1185	(Init->TARSetupTime << 13));
1186
1187	Device->PCR4 = tmpr;
1188
1189	return HAL_OK;
1190	}
1191
1192	/**
1193	* @brief Initializes the FMC_PCCARD Common space Timing according to the specified
1194	* parameters in the FMC_NAND_PCC_TimingTypeDef
1195	* @param Device: Pointer to PCCARD device instance
1196	* @param Timing: Pointer to PCCARD timing structure
1197	* @retval HAL status
1198	*/
1199	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing)
1200	{
1201	uint32_t tmpr = 0;
1202
1203	/* Check the parameters */
1204	assert_param(IS_FMC_PCCARD_DEVICE(Device));
1205	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
1206	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
1207	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
1208	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
1209
1210	/* Get PCCARD common space timing register value */
1211	tmpr = Device->PMEM4;
1212
1213	/* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
1214	tmpr &= ((uint32_t)~(FMC_PMEM4_MEMSET4 \| FMC_PMEM4_MEMWAIT4 \| FMC_PMEM4_MEMHOLD4 \| \
1215	FMC_PMEM4_MEMHIZ4));
1216	/* Set PCCARD timing parameters */
1217	tmpr \|= (uint32_t)(Timing->SetupTime \|\
1218	((Timing->WaitSetupTime) << 8) \|\
1219	((Timing->HoldSetupTime) << 16) \|\
1220	((Timing->HiZSetupTime) << 24));
1221
1222	Device->PMEM4 = tmpr;
1223
1224	return HAL_OK;
1225	}
1226
1227	/**
1228	* @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
1229	* parameters in the FMC_NAND_PCC_TimingTypeDef
1230	* @param Device: Pointer to PCCARD device instance
1231	* @param Timing: Pointer to PCCARD timing structure
1232	* @retval HAL status
1233	*/
1234	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing)
1235	{
1236	uint32_t tmpr = 0;
1237
1238	/* Check the parameters */
1239	assert_param(IS_FMC_PCCARD_DEVICE(Device));
1240	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
1241	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
1242	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
1243	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
1244
1245	/* Get PCCARD timing parameters */
1246	tmpr = Device->PATT4;
1247
1248	/* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
1249	tmpr &= ((uint32_t)~(FMC_PATT4_ATTSET4 \| FMC_PATT4_ATTWAIT4 \| FMC_PATT4_ATTHOLD4 \| \
1250	FMC_PATT4_ATTHIZ4));
1251
1252	/* Set PCCARD timing parameters */
1253	tmpr \|= (uint32_t)(Timing->SetupTime \|\
1254	((Timing->WaitSetupTime) << 8) \|\
1255	((Timing->HoldSetupTime) << 16) \|\
1256	((Timing->HiZSetupTime) << 24));
1257	Device->PATT4 = tmpr;
1258
1259	return HAL_OK;
1260	}
1261
1262	/**
1263	* @brief Initializes the FMC_PCCARD IO space Timing according to the specified
1264	* parameters in the FMC_NAND_PCC_TimingTypeDef
1265	* @param Device: Pointer to PCCARD device instance
1266	* @param Timing: Pointer to PCCARD timing structure
1267	* @retval HAL status
1268	*/
1269	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing)
1270	{
1271	uint32_t tmpr = 0;
1272
1273	/* Check the parameters */
1274	assert_param(IS_FMC_PCCARD_DEVICE(Device));
1275	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
1276	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
1277	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
1278	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
1279
1280	/* Get FMC_PCCARD device timing parameters */
1281	tmpr = Device->PIO4;
1282
1283	/* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
1284	tmpr &= ((uint32_t)~(FMC_PIO4_IOSET4 \| FMC_PIO4_IOWAIT4 \| FMC_PIO4_IOHOLD4 \| \
1285	FMC_PIO4_IOHIZ4));
1286
1287	/* Set FMC_PCCARD device timing parameters */
1288	tmpr \|= (uint32_t)(Timing->SetupTime \|\
1289	((Timing->WaitSetupTime) << 8) \|\
1290	((Timing->HoldSetupTime) << 16) \|\
1291	((Timing->HiZSetupTime) << 24));
1292
1293	Device->PIO4 = tmpr;
1294
1295	return HAL_OK;
1296	}
1297
1298	/**
1299	* @brief DeInitializes the FMC_PCCARD device
1300	* @param Device: Pointer to PCCARD device instance
1301	* @retval HAL status
1302	*/
1303	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
1304	{
1305	/* Check the parameters */
1306	assert_param(IS_FMC_PCCARD_DEVICE(Device));
1307
1308	/* Disable the FMC_PCCARD device */
1309	__FMC_PCCARD_DISABLE(Device);
1310
1311	/* De-initialize the FMC_PCCARD device */
1312	Device->PCR4 = 0x00000018;
1313	Device->SR4 = 0x00000000;
1314	Device->PMEM4 = 0xFCFCFCFC;
1315	Device->PATT4 = 0xFCFCFCFC;
1316	Device->PIO4 = 0xFCFCFCFC;
1317
1318	return HAL_OK;
1319	}
1320
1321	/**
1322	* @}
1323	*/
1324	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
1325
1326
1327	/** @addtogroup FMC_LL_SDRAM
1328	* @brief SDRAM Controller functions
1329	*
1330	@verbatim
1331	==============================================================================
1332	##### How to use SDRAM device driver #####
1333	==============================================================================
1334	[..]
1335	This driver contains a set of APIs to interface with the FMC SDRAM banks in order
1336	to run the SDRAM external devices.
1337
1338	(+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
1339	(+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
1340	(+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
1341	(+) FMC SDRAM bank enable/disable write operation using the functions
1342	FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
1343	(+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
1344
1345	@endverbatim
1346	* @{
1347	*/
1348
1349	/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
1350	* @brief Initialization and Configuration functions
1351	*
1352	@verbatim
1353	==============================================================================
1354	##### Initialization and de_initialization functions #####
1355	==============================================================================
1356	[..]
1357	This section provides functions allowing to:
1358	(+) Initialize and configure the FMC SDRAM interface
1359	(+) De-initialize the FMC SDRAM interface
1360	(+) Configure the FMC clock and associated GPIOs
1361
1362	@endverbatim
1363	* @{
1364	*/
1365
1366	/**
1367	* @brief Initializes the FMC_SDRAM device according to the specified
1368	* control parameters in the FMC_SDRAM_InitTypeDef
1369	* @param Device: Pointer to SDRAM device instance
1370	* @param Init: Pointer to SDRAM Initialization structure
1371	* @retval HAL status
1372	*/
1373	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init)
1374	{
1375	uint32_t tmpr1 = 0;
1376	uint32_t tmpr2 = 0;
1377
1378	/* Check the parameters */
1379	assert_param(IS_FMC_SDRAM_DEVICE(Device));
1380	assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
1381	assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
1382	assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
1383	assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
1384	assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
1385	assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
1386	assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
1387	assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
1388	assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
1389	assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
1390
1391	/* Set SDRAM bank configuration parameters */
1392	if (Init->SDBank != FMC_SDRAM_BANK2)
1393	{
1394	tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
1395
1396	/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
1397	tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC \| FMC_SDCR1_NR \| FMC_SDCR1_MWID \| \
1398	FMC_SDCR1_NB \| FMC_SDCR1_CAS \| FMC_SDCR1_WP \| \
1399	FMC_SDCR1_SDCLK \| FMC_SDCR1_RBURST \| FMC_SDCR1_RPIPE));
1400
1401
1402	tmpr1 \|= (uint32_t)(Init->ColumnBitsNumber \|\
1403	Init->RowBitsNumber \|\
1404	Init->MemoryDataWidth \|\
1405	Init->InternalBankNumber \|\
1406	Init->CASLatency \|\
1407	Init->WriteProtection \|\
1408	Init->SDClockPeriod \|\
1409	Init->ReadBurst \|\
1410	Init->ReadPipeDelay
1411	);
1412	Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
1413	}
1414	else /* FMC_Bank2_SDRAM */
1415	{
1416	tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
1417
1418	/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
1419	tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC \| FMC_SDCR1_NR \| FMC_SDCR1_MWID \| \
1420	FMC_SDCR1_NB \| FMC_SDCR1_CAS \| FMC_SDCR1_WP \| \
1421	FMC_SDCR1_SDCLK \| FMC_SDCR1_RBURST \| FMC_SDCR1_RPIPE));
1422
1423	tmpr1 \|= (uint32_t)(Init->SDClockPeriod \|\
1424	Init->ReadBurst \|\
1425	Init->ReadPipeDelay);
1426
1427	tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
1428
1429	/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
1430	tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC \| FMC_SDCR1_NR \| FMC_SDCR1_MWID \| \
1431	FMC_SDCR1_NB \| FMC_SDCR1_CAS \| FMC_SDCR1_WP \| \
1432	FMC_SDCR1_SDCLK \| FMC_SDCR1_RBURST \| FMC_SDCR1_RPIPE));
1433
1434	tmpr2 \|= (uint32_t)(Init->ColumnBitsNumber \|\
1435	Init->RowBitsNumber \|\
1436	Init->MemoryDataWidth \|\
1437	Init->InternalBankNumber \|\
1438	Init->CASLatency \|\
1439	Init->WriteProtection);
1440
1441	Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
1442	Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
1443	}
1444
1445	return HAL_OK;
1446	}
1447
1448	/**
1449	* @brief Initializes the FMC_SDRAM device timing according to the specified
1450	* parameters in the FMC_SDRAM_TimingTypeDef
1451	* @param Device: Pointer to SDRAM device instance
1452	* @param Timing: Pointer to SDRAM Timing structure
1453	* @param Bank: SDRAM bank number
1454	* @retval HAL status
1455	*/
1456	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank)
1457	{
1458	uint32_t tmpr1 = 0;
1459	uint32_t tmpr2 = 0;
1460
1461	/* Check the parameters */
1462	assert_param(IS_FMC_SDRAM_DEVICE(Device));
1463	assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
1464	assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
1465	assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
1466	assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
1467	assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
1468	assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
1469	assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
1470	assert_param(IS_FMC_SDRAM_BANK(Bank));
1471
1472	/* Set SDRAM device timing parameters */
1473	if (Bank != FMC_SDRAM_BANK2)
1474	{
1475	tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
1476
1477	/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
1478	tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD \| FMC_SDTR1_TXSR \| FMC_SDTR1_TRAS \| \
1479	FMC_SDTR1_TRC \| FMC_SDTR1_TWR \| FMC_SDTR1_TRP \| \
1480	FMC_SDTR1_TRCD));
1481
1482	tmpr1 \|= (uint32_t)(((Timing->LoadToActiveDelay)-1) \|\
1483	(((Timing->ExitSelfRefreshDelay)-1) << 4) \|\
1484	(((Timing->SelfRefreshTime)-1) << 8) \|\
1485	(((Timing->RowCycleDelay)-1) << 12) \|\
1486	(((Timing->WriteRecoveryTime)-1) <<16) \|\
1487	(((Timing->RPDelay)-1) << 20) \|\
1488	(((Timing->RCDDelay)-1) << 24));
1489	Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
1490	}
1491	else /* FMC_Bank2_SDRAM */
1492	{
1493	tmpr1 = Device->SDTR[FMC_SDRAM_BANK2];
1494
1495	/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
1496	tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD \| FMC_SDTR1_TXSR \| FMC_SDTR1_TRAS \| \
1497	FMC_SDTR1_TRC \| FMC_SDTR1_TWR \| FMC_SDTR1_TRP \| \
1498	FMC_SDTR1_TRCD));
1499
1500	tmpr1 \|= (uint32_t)(((Timing->LoadToActiveDelay)-1) \|\
1501	(((Timing->ExitSelfRefreshDelay)-1) << 4) \|\
1502	(((Timing->SelfRefreshTime)-1) << 8) \|\
1503	(((Timing->WriteRecoveryTime)-1) <<16) \|\
1504	(((Timing->RCDDelay)-1) << 24));
1505
1506	tmpr2 = Device->SDTR[FMC_SDRAM_BANK1];
1507
1508	/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
1509	tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD \| FMC_SDTR1_TXSR \| FMC_SDTR1_TRAS \| \
1510	FMC_SDTR1_TRC \| FMC_SDTR1_TWR \| FMC_SDTR1_TRP \| \
1511	FMC_SDTR1_TRCD));
1512	tmpr2 \|= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) \|\
1513	(((Timing->RPDelay)-1) << 20));
1514
1515	Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
1516	Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;
1517	}
1518
1519	return HAL_OK;
1520	}
1521
1522	/**
1523	* @brief DeInitializes the FMC_SDRAM peripheral
1524	* @param Device: Pointer to SDRAM device instance
1525	* @retval HAL status
1526	*/
1527	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1528	{
1529	/* Check the parameters */
1530	assert_param(IS_FMC_SDRAM_DEVICE(Device));
1531	assert_param(IS_FMC_SDRAM_BANK(Bank));
1532
1533	/* De-initialize the SDRAM device */
1534	Device->SDCR[Bank] = 0x000002D0;
1535	Device->SDTR[Bank] = 0x0FFFFFFF;
1536	Device->SDCMR = 0x00000000;
1537	Device->SDRTR = 0x00000000;
1538	Device->SDSR = 0x00000000;
1539
1540	return HAL_OK;
1541	}
1542
1543	/**
1544	* @}
1545	*/
1546
1547	/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
1548	* @brief management functions
1549	*
1550	@verbatim
1551	==============================================================================
1552	##### FMC_SDRAM Control functions #####
1553	==============================================================================
1554	[..]
1555	This subsection provides a set of functions allowing to control dynamically
1556	the FMC SDRAM interface.
1557
1558	@endverbatim
1559	* @{
1560	*/
1561	/**
1562	* @brief Enables dynamically FMC_SDRAM write protection.
1563	* @param Device: Pointer to SDRAM device instance
1564	* @param Bank: SDRAM bank number
1565	* @retval HAL status
1566	*/
1567	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1568	{
1569	/* Check the parameters */
1570	assert_param(IS_FMC_SDRAM_DEVICE(Device));
1571	assert_param(IS_FMC_SDRAM_BANK(Bank));
1572
1573	/* Enable write protection */
1574	Device->SDCR[Bank] \|= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
1575
1576	return HAL_OK;
1577	}
1578
1579	/**
1580	* @brief Disables dynamically FMC_SDRAM write protection.
1581	* @param hsdram: FMC_SDRAM handle
1582	* @retval HAL status
1583	*/
1584	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1585	{
1586	/* Check the parameters */
1587	assert_param(IS_FMC_SDRAM_DEVICE(Device));
1588	assert_param(IS_FMC_SDRAM_BANK(Bank));
1589
1590	/* Disable write protection */
1591	Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
1592
1593	return HAL_OK;
1594	}
1595
1596	/**
1597	* @brief Send Command to the FMC SDRAM bank
1598	* @param Device: Pointer to SDRAM device instance
1599	* @param Command: Pointer to SDRAM command structure
1600	* @param Timing: Pointer to SDRAM Timing structure
1601	* @param Timeout: Timeout wait value
1602	* @retval HAL state
1603	*/
1604	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout)
1605	{
1606	__IO uint32_t tmpr = 0;
1607	uint32_t tickstart = 0;
1608
1609	/* Check the parameters */
1610	assert_param(IS_FMC_SDRAM_DEVICE(Device));
1611	assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
1612	assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
1613	assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
1614	assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
1615
1616	/* Set command register */
1617	tmpr = (uint32_t)((Command->CommandMode) \|\
1618	(Command->CommandTarget) \|\
1619	(((Command->AutoRefreshNumber)-1) << 5) \|\
1620	((Command->ModeRegisterDefinition) << 9)
1621	);
1622
1623	Device->SDCMR = tmpr;
1624
1625	/* Get tick */
1626	tickstart = HAL_GetTick();
1627
1628	/* Wait until command is send */
1629	while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
1630	{
1631	/* Check for the Timeout */
1632	if(Timeout != HAL_MAX_DELAY)
1633	{
1634	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
1635	{
1636	return HAL_TIMEOUT;
1637	}
1638	}
1639	}
1640
1641	return HAL_OK;
1642	}
1643
1644	/**
1645	* @brief Program the SDRAM Memory Refresh rate.
1646	* @param Device: Pointer to SDRAM device instance
1647	* @param RefreshRate: The SDRAM refresh rate value.
1648	* @retval HAL state
1649	*/
1650	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
1651	{
1652	/* Check the parameters */
1653	assert_param(IS_FMC_SDRAM_DEVICE(Device));
1654	assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
1655
1656	/* Set the refresh rate in command register */
1657	Device->SDRTR \|= (RefreshRate<<1);
1658
1659	return HAL_OK;
1660	}
1661
1662	/**
1663	* @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
1664	* @param Device: Pointer to SDRAM device instance
1665	* @param AutoRefreshNumber: Specifies the auto Refresh number.
1666	* @retval None
1667	*/
1668	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
1669	{
1670	/* Check the parameters */
1671	assert_param(IS_FMC_SDRAM_DEVICE(Device));
1672	assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
1673
1674	/* Set the Auto-refresh number in command register */
1675	Device->SDCMR \|= (AutoRefreshNumber << 5);
1676
1677	return HAL_OK;
1678	}
1679
1680	/**
1681	* @brief Returns the indicated FMC SDRAM bank mode status.
1682	* @param Device: Pointer to SDRAM device instance
1683	* @param Bank: Defines the FMC SDRAM bank. This parameter can be
1684	* FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
1685	* @retval The FMC SDRAM bank mode status, could be on of the following values:
1686	* FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
1687	* FMC_SDRAM_POWER_DOWN_MODE.
1688	*/
1689	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1690	{
1691	uint32_t tmpreg = 0;
1692
1693	/* Check the parameters */
1694	assert_param(IS_FMC_SDRAM_DEVICE(Device));
1695	assert_param(IS_FMC_SDRAM_BANK(Bank));
1696
1697	/* Get the corresponding bank mode */
1698	if(Bank == FMC_SDRAM_BANK1)
1699	{
1700	tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
1701	}
1702	else
1703	{
1704	tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);
1705	}
1706
1707	/* Return the mode status */
1708	return tmpreg;
1709	}
1710
1711	/**
1712	* @}
1713	*/
1714
1715	/**
1716	* @}
1717	*/
1718
1719	/**
1720	* @}
1721	*/
1722	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
1723	#endif /* HAL_SRAM_MODULE_ENABLED \|\| HAL_NOR_MODULE_ENABLED \|\| HAL_NAND_MODULE_ENABLED \|\| HAL_PCCARD_MODULE_ENABLED \|\| HAL_SDRAM_MODULE_ENABLED */
1724
1725	/**
1726	* @}
1727	*/
1728
1729	/**
1730	* @}
1731	*/
1732
1733	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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