1 | /**
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2 | ******************************************************************************
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3 | * @file stm32f4xx_hal_tim.c
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4 | * @author MCD Application Team
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5 | * @version V1.4.1
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6 | * @date 09-October-2015
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7 | * @brief TIM HAL module driver.
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8 | * This file provides firmware functions to manage the following
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9 | * functionalities of the Timer (TIM) peripheral:
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10 | * + Time Base Initialization
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11 | * + Time Base Start
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12 | * + Time Base Start Interruption
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13 | * + Time Base Start DMA
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14 | * + Time Output Compare/PWM Initialization
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15 | * + Time Output Compare/PWM Channel Configuration
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16 | * + Time Output Compare/PWM Start
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17 | * + Time Output Compare/PWM Start Interruption
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18 | * + Time Output Compare/PWM Start DMA
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19 | * + Time Input Capture Initialization
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20 | * + Time Input Capture Channel Configuration
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21 | * + Time Input Capture Start
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22 | * + Time Input Capture Start Interruption
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23 | * + Time Input Capture Start DMA
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24 | * + Time One Pulse Initialization
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25 | * + Time One Pulse Channel Configuration
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26 | * + Time One Pulse Start
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27 | * + Time Encoder Interface Initialization
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28 | * + Time Encoder Interface Start
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29 | * + Time Encoder Interface Start Interruption
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30 | * + Time Encoder Interface Start DMA
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31 | * + Commutation Event configuration with Interruption and DMA
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32 | * + Time OCRef clear configuration
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33 | * + Time External Clock configuration
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34 | @verbatim
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35 | ==============================================================================
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36 | ##### TIMER Generic features #####
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37 | ==============================================================================
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38 | [..] The Timer features include:
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39 | (#) 16-bit up, down, up/down auto-reload counter.
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40 | (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
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41 | counter clock frequency either by any factor between 1 and 65536.
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42 | (#) Up to 4 independent channels for:
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43 | (++) Input Capture
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44 | (++) Output Compare
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45 | (++) PWM generation (Edge and Center-aligned Mode)
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46 | (++) One-pulse mode output
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47 |
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48 | ##### How to use this driver #####
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49 | ==============================================================================
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50 | [..]
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51 | (#) Initialize the TIM low level resources by implementing the following functions
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52 | depending from feature used :
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53 | (++) Time Base : HAL_TIM_Base_MspInit()
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54 | (++) Input Capture : HAL_TIM_IC_MspInit()
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55 | (++) Output Compare : HAL_TIM_OC_MspInit()
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56 | (++) PWM generation : HAL_TIM_PWM_MspInit()
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57 | (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
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58 | (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
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59 |
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60 | (#) Initialize the TIM low level resources :
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61 | (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
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62 | (##) TIM pins configuration
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63 | (+++) Enable the clock for the TIM GPIOs using the following function:
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64 | __GPIOx_CLK_ENABLE();
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65 | (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
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66 |
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67 | (#) The external Clock can be configured, if needed (the default clock is the
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68 | internal clock from the APBx), using the following function:
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69 | HAL_TIM_ConfigClockSource, the clock configuration should be done before
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70 | any start function.
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71 |
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72 | (#) Configure the TIM in the desired functioning mode using one of the
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73 | initialization function of this driver:
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74 | (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
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75 | (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
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76 | Output Compare signal.
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77 | (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
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78 | PWM signal.
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79 | (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
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80 | external signal.
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81 | (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
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82 | in One Pulse Mode.
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83 | (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
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84 |
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85 | (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
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86 | (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
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87 | (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
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88 | (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
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89 | (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
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90 | (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
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91 | (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
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92 |
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93 | (#) The DMA Burst is managed with the two following functions:
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94 | HAL_TIM_DMABurst_WriteStart()
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95 | HAL_TIM_DMABurst_ReadStart()
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96 |
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97 | @endverbatim
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98 | ******************************************************************************
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99 | * @attention
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100 | *
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101 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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102 | *
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103 | * Redistribution and use in source and binary forms, with or without modification,
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104 | * are permitted provided that the following conditions are met:
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105 | * 1. Redistributions of source code must retain the above copyright notice,
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106 | * this list of conditions and the following disclaimer.
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107 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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108 | * this list of conditions and the following disclaimer in the documentation
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109 | * and/or other materials provided with the distribution.
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110 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
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111 | * may be used to endorse or promote products derived from this software
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112 | * without specific prior written permission.
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113 | *
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114 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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115 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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116 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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117 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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118 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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119 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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120 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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121 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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122 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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123 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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124 | *
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125 | ******************************************************************************
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126 | */
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127 |
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128 | /* Includes ------------------------------------------------------------------*/
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129 | #include "stm32f4xx_hal.h"
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130 |
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131 | /** @addtogroup STM32F4xx_HAL_Driver
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132 | * @{
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133 | */
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134 |
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135 | /** @defgroup TIM TIM
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136 | * @brief TIM HAL module driver
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137 | * @{
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138 | */
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139 |
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140 | #ifdef HAL_TIM_MODULE_ENABLED
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141 |
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142 | /* Private typedef -----------------------------------------------------------*/
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143 | /* Private define ------------------------------------------------------------*/
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144 | /* Private macro -------------------------------------------------------------*/
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145 | /* Private variables ---------------------------------------------------------*/
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146 | /** @addtogroup TIM_Private_Functions
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147 | * @{
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148 | */
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149 | /* Private function prototypes -----------------------------------------------*/
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150 | static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
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151 | static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
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152 | static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
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153 |
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154 | static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
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155 | static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
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156 | uint32_t TIM_ICFilter);
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157 | static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
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158 | static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
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159 | uint32_t TIM_ICFilter);
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160 | static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
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161 | uint32_t TIM_ICFilter);
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162 |
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163 | static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
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164 | uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
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165 |
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166 | static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
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167 | static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
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168 | static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
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169 | static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
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170 | TIM_SlaveConfigTypeDef * sSlaveConfig);
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171 | /**
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172 | * @}
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173 | */
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174 |
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175 | /* Exported functions --------------------------------------------------------*/
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176 | /** @defgroup TIM_Exported_Functions TIM Exported Functions
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177 | * @{
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178 | */
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179 |
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180 | /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
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181 | * @brief Time Base functions
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182 | *
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183 | @verbatim
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184 | ==============================================================================
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185 | ##### Time Base functions #####
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186 | ==============================================================================
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187 | [..]
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188 | This section provides functions allowing to:
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189 | (+) Initialize and configure the TIM base.
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190 | (+) De-initialize the TIM base.
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191 | (+) Start the Time Base.
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192 | (+) Stop the Time Base.
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193 | (+) Start the Time Base and enable interrupt.
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194 | (+) Stop the Time Base and disable interrupt.
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195 | (+) Start the Time Base and enable DMA transfer.
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196 | (+) Stop the Time Base and disable DMA transfer.
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197 |
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198 | @endverbatim
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199 | * @{
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200 | */
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201 | /**
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202 | * @brief Initializes the TIM Time base Unit according to the specified
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203 | * parameters in the TIM_HandleTypeDef and create the associated handle.
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204 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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205 | * the configuration information for TIM module.
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206 | * @retval HAL status
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207 | */
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208 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
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209 | {
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210 | /* Check the TIM handle allocation */
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211 | if(htim == NULL)
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212 | {
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213 | return HAL_ERROR;
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214 | }
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215 |
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216 | /* Check the parameters */
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217 | assert_param(IS_TIM_INSTANCE(htim->Instance));
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218 | assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
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219 | assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
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220 |
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221 | if(htim->State == HAL_TIM_STATE_RESET)
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222 | {
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223 | /* Allocate lock resource and initialize it */
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224 | htim->Lock = HAL_UNLOCKED;
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225 | /* Init the low level hardware : GPIO, CLOCK, NVIC */
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226 | HAL_TIM_Base_MspInit(htim);
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227 | }
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228 |
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229 | /* Set the TIM state */
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230 | htim->State= HAL_TIM_STATE_BUSY;
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231 |
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232 | /* Set the Time Base configuration */
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233 | TIM_Base_SetConfig(htim->Instance, &htim->Init);
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234 |
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235 | /* Initialize the TIM state*/
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236 | htim->State= HAL_TIM_STATE_READY;
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237 |
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238 | return HAL_OK;
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239 | }
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240 |
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241 | /**
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242 | * @brief DeInitializes the TIM Base peripheral
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243 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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244 | * the configuration information for TIM module.
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245 | * @retval HAL status
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246 | */
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247 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
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248 | {
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249 | /* Check the parameters */
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250 | assert_param(IS_TIM_INSTANCE(htim->Instance));
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251 |
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252 | htim->State = HAL_TIM_STATE_BUSY;
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253 |
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254 | /* Disable the TIM Peripheral Clock */
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255 | __HAL_TIM_DISABLE(htim);
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256 |
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257 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
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258 | HAL_TIM_Base_MspDeInit(htim);
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259 |
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260 | /* Change TIM state */
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261 | htim->State = HAL_TIM_STATE_RESET;
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262 |
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263 | /* Release Lock */
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264 | __HAL_UNLOCK(htim);
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265 |
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266 | return HAL_OK;
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267 | }
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268 |
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269 | /**
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270 | * @brief Initializes the TIM Base MSP.
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271 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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272 | * the configuration information for TIM module.
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273 | * @retval None
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274 | */
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275 | __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
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276 | {
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277 | /* NOTE : This function Should not be modified, when the callback is needed,
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278 | the HAL_TIM_Base_MspInit could be implemented in the user file
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279 | */
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280 | }
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281 |
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282 | /**
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283 | * @brief DeInitializes TIM Base MSP.
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284 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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285 | * the configuration information for TIM module.
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286 | * @retval None
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287 | */
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288 | __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
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289 | {
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290 | /* NOTE : This function Should not be modified, when the callback is needed,
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291 | the HAL_TIM_Base_MspDeInit could be implemented in the user file
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292 | */
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293 | }
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294 |
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295 | /**
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296 | * @brief Starts the TIM Base generation.
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297 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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298 | * the configuration information for TIM module.
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299 | * @retval HAL status
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300 | */
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301 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
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302 | {
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303 | /* Check the parameters */
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304 | assert_param(IS_TIM_INSTANCE(htim->Instance));
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305 |
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306 | /* Set the TIM state */
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307 | htim->State= HAL_TIM_STATE_BUSY;
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308 |
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309 | /* Enable the Peripheral */
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310 | __HAL_TIM_ENABLE(htim);
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311 |
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312 | /* Change the TIM state*/
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313 | htim->State= HAL_TIM_STATE_READY;
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314 |
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315 | /* Return function status */
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316 | return HAL_OK;
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317 | }
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318 |
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319 | /**
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320 | * @brief Stops the TIM Base generation.
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321 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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322 | * the configuration information for TIM module.
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323 | * @retval HAL status
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324 | */
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325 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
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326 | {
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327 | /* Check the parameters */
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328 | assert_param(IS_TIM_INSTANCE(htim->Instance));
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329 |
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330 | /* Set the TIM state */
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331 | htim->State= HAL_TIM_STATE_BUSY;
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332 |
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333 | /* Disable the Peripheral */
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334 | __HAL_TIM_DISABLE(htim);
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335 |
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336 | /* Change the TIM state*/
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337 | htim->State= HAL_TIM_STATE_READY;
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338 |
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339 | /* Return function status */
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340 | return HAL_OK;
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341 | }
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342 |
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343 | /**
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344 | * @brief Starts the TIM Base generation in interrupt mode.
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345 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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346 | * the configuration information for TIM module.
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347 | * @retval HAL status
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348 | */
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349 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
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350 | {
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351 | /* Check the parameters */
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352 | assert_param(IS_TIM_INSTANCE(htim->Instance));
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353 |
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354 | /* Enable the TIM Update interrupt */
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355 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
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356 |
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357 | /* Enable the Peripheral */
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358 | __HAL_TIM_ENABLE(htim);
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359 |
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360 | /* Return function status */
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361 | return HAL_OK;
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362 | }
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363 |
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364 | /**
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365 | * @brief Stops the TIM Base generation in interrupt mode.
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366 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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367 | * the configuration information for TIM module.
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368 | * @retval HAL status
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369 | */
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370 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
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371 | {
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372 | /* Check the parameters */
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373 | assert_param(IS_TIM_INSTANCE(htim->Instance));
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374 | /* Disable the TIM Update interrupt */
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375 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
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376 |
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377 | /* Disable the Peripheral */
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378 | __HAL_TIM_DISABLE(htim);
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379 |
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380 | /* Return function status */
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381 | return HAL_OK;
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382 | }
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383 |
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384 | /**
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385 | * @brief Starts the TIM Base generation in DMA mode.
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386 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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387 | * the configuration information for TIM module.
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388 | * @param pData: The source Buffer address.
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389 | * @param Length: The length of data to be transferred from memory to peripheral.
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390 | * @retval HAL status
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391 | */
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392 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
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393 | {
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394 | /* Check the parameters */
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395 | assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
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396 |
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397 | if((htim->State == HAL_TIM_STATE_BUSY))
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398 | {
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399 | return HAL_BUSY;
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400 | }
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401 | else if((htim->State == HAL_TIM_STATE_READY))
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402 | {
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403 | if((pData == 0 ) && (Length > 0))
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404 | {
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405 | return HAL_ERROR;
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406 | }
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407 | else
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408 | {
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409 | htim->State = HAL_TIM_STATE_BUSY;
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410 | }
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411 | }
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412 | /* Set the DMA Period elapsed callback */
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413 | htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
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414 |
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415 | /* Set the DMA error callback */
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416 | htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
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417 |
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418 | /* Enable the DMA Stream */
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419 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
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420 |
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421 | /* Enable the TIM Update DMA request */
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422 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
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423 |
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424 | /* Enable the Peripheral */
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425 | __HAL_TIM_ENABLE(htim);
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426 |
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427 | /* Return function status */
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428 | return HAL_OK;
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429 | }
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430 |
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431 | /**
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432 | * @brief Stops the TIM Base generation in DMA mode.
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433 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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434 | * the configuration information for TIM module.
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435 | * @retval HAL status
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436 | */
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437 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
|
---|
438 | {
|
---|
439 | /* Check the parameters */
|
---|
440 | assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
|
---|
441 |
|
---|
442 | /* Disable the TIM Update DMA request */
|
---|
443 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
|
---|
444 |
|
---|
445 | /* Disable the Peripheral */
|
---|
446 | __HAL_TIM_DISABLE(htim);
|
---|
447 |
|
---|
448 | /* Change the htim state */
|
---|
449 | htim->State = HAL_TIM_STATE_READY;
|
---|
450 |
|
---|
451 | /* Return function status */
|
---|
452 | return HAL_OK;
|
---|
453 | }
|
---|
454 | /**
|
---|
455 | * @}
|
---|
456 | */
|
---|
457 |
|
---|
458 | /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
|
---|
459 | * @brief Time Output Compare functions
|
---|
460 | *
|
---|
461 | @verbatim
|
---|
462 | ==============================================================================
|
---|
463 | ##### Time Output Compare functions #####
|
---|
464 | ==============================================================================
|
---|
465 | [..]
|
---|
466 | This section provides functions allowing to:
|
---|
467 | (+) Initialize and configure the TIM Output Compare.
|
---|
468 | (+) De-initialize the TIM Output Compare.
|
---|
469 | (+) Start the Time Output Compare.
|
---|
470 | (+) Stop the Time Output Compare.
|
---|
471 | (+) Start the Time Output Compare and enable interrupt.
|
---|
472 | (+) Stop the Time Output Compare and disable interrupt.
|
---|
473 | (+) Start the Time Output Compare and enable DMA transfer.
|
---|
474 | (+) Stop the Time Output Compare and disable DMA transfer.
|
---|
475 |
|
---|
476 | @endverbatim
|
---|
477 | * @{
|
---|
478 | */
|
---|
479 | /**
|
---|
480 | * @brief Initializes the TIM Output Compare according to the specified
|
---|
481 | * parameters in the TIM_HandleTypeDef and create the associated handle.
|
---|
482 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
483 | * the configuration information for TIM module.
|
---|
484 | * @retval HAL status
|
---|
485 | */
|
---|
486 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
|
---|
487 | {
|
---|
488 | /* Check the TIM handle allocation */
|
---|
489 | if(htim == NULL)
|
---|
490 | {
|
---|
491 | return HAL_ERROR;
|
---|
492 | }
|
---|
493 |
|
---|
494 | /* Check the parameters */
|
---|
495 | assert_param(IS_TIM_INSTANCE(htim->Instance));
|
---|
496 | assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
---|
497 | assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
---|
498 |
|
---|
499 | if(htim->State == HAL_TIM_STATE_RESET)
|
---|
500 | {
|
---|
501 | /* Allocate lock resource and initialize it */
|
---|
502 | htim->Lock = HAL_UNLOCKED;
|
---|
503 | /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
---|
504 | HAL_TIM_OC_MspInit(htim);
|
---|
505 | }
|
---|
506 |
|
---|
507 | /* Set the TIM state */
|
---|
508 | htim->State= HAL_TIM_STATE_BUSY;
|
---|
509 |
|
---|
510 | /* Init the base time for the Output Compare */
|
---|
511 | TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
---|
512 |
|
---|
513 | /* Initialize the TIM state*/
|
---|
514 | htim->State= HAL_TIM_STATE_READY;
|
---|
515 |
|
---|
516 | return HAL_OK;
|
---|
517 | }
|
---|
518 |
|
---|
519 | /**
|
---|
520 | * @brief DeInitializes the TIM peripheral
|
---|
521 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
522 | * the configuration information for TIM module.
|
---|
523 | * @retval HAL status
|
---|
524 | */
|
---|
525 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
|
---|
526 | {
|
---|
527 | /* Check the parameters */
|
---|
528 | assert_param(IS_TIM_INSTANCE(htim->Instance));
|
---|
529 |
|
---|
530 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
531 |
|
---|
532 | /* Disable the TIM Peripheral Clock */
|
---|
533 | __HAL_TIM_DISABLE(htim);
|
---|
534 |
|
---|
535 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
|
---|
536 | HAL_TIM_OC_MspDeInit(htim);
|
---|
537 |
|
---|
538 | /* Change TIM state */
|
---|
539 | htim->State = HAL_TIM_STATE_RESET;
|
---|
540 |
|
---|
541 | /* Release Lock */
|
---|
542 | __HAL_UNLOCK(htim);
|
---|
543 |
|
---|
544 | return HAL_OK;
|
---|
545 | }
|
---|
546 |
|
---|
547 | /**
|
---|
548 | * @brief Initializes the TIM Output Compare MSP.
|
---|
549 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
550 | * the configuration information for TIM module.
|
---|
551 | * @retval None
|
---|
552 | */
|
---|
553 | __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
|
---|
554 | {
|
---|
555 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
556 | the HAL_TIM_OC_MspInit could be implemented in the user file
|
---|
557 | */
|
---|
558 | }
|
---|
559 |
|
---|
560 | /**
|
---|
561 | * @brief DeInitializes TIM Output Compare MSP.
|
---|
562 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
563 | * the configuration information for TIM module.
|
---|
564 | * @retval None
|
---|
565 | */
|
---|
566 | __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
|
---|
567 | {
|
---|
568 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
569 | the HAL_TIM_OC_MspDeInit could be implemented in the user file
|
---|
570 | */
|
---|
571 | }
|
---|
572 |
|
---|
573 | /**
|
---|
574 | * @brief Starts the TIM Output Compare signal generation.
|
---|
575 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
576 | * the configuration information for TIM module.
|
---|
577 | * @param Channel: TIM Channel to be enabled.
|
---|
578 | * This parameter can be one of the following values:
|
---|
579 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
580 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
581 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
582 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
583 | * @retval HAL status
|
---|
584 | */
|
---|
585 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
586 | {
|
---|
587 | /* Check the parameters */
|
---|
588 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
---|
589 |
|
---|
590 | /* Enable the Output compare channel */
|
---|
591 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
---|
592 |
|
---|
593 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
|
---|
594 | {
|
---|
595 | /* Enable the main output */
|
---|
596 | __HAL_TIM_MOE_ENABLE(htim);
|
---|
597 | }
|
---|
598 |
|
---|
599 | /* Enable the Peripheral */
|
---|
600 | __HAL_TIM_ENABLE(htim);
|
---|
601 |
|
---|
602 | /* Return function status */
|
---|
603 | return HAL_OK;
|
---|
604 | }
|
---|
605 |
|
---|
606 | /**
|
---|
607 | * @brief Stops the TIM Output Compare signal generation.
|
---|
608 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
609 | * the configuration information for TIM module.
|
---|
610 | * @param Channel: TIM Channel to be disabled.
|
---|
611 | * This parameter can be one of the following values:
|
---|
612 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
613 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
614 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
615 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
616 | * @retval HAL status
|
---|
617 | */
|
---|
618 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
619 | {
|
---|
620 | /* Check the parameters */
|
---|
621 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
---|
622 |
|
---|
623 | /* Disable the Output compare channel */
|
---|
624 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
---|
625 |
|
---|
626 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
|
---|
627 | {
|
---|
628 | /* Disable the Main Output */
|
---|
629 | __HAL_TIM_MOE_DISABLE(htim);
|
---|
630 | }
|
---|
631 |
|
---|
632 | /* Disable the Peripheral */
|
---|
633 | __HAL_TIM_DISABLE(htim);
|
---|
634 |
|
---|
635 | /* Return function status */
|
---|
636 | return HAL_OK;
|
---|
637 | }
|
---|
638 |
|
---|
639 | /**
|
---|
640 | * @brief Starts the TIM Output Compare signal generation in interrupt mode.
|
---|
641 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
642 | * the configuration information for TIM module.
|
---|
643 | * @param Channel: TIM Channel to be enabled.
|
---|
644 | * This parameter can be one of the following values:
|
---|
645 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
646 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
647 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
648 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
649 | * @retval HAL status
|
---|
650 | */
|
---|
651 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
652 | {
|
---|
653 | /* Check the parameters */
|
---|
654 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
---|
655 |
|
---|
656 | switch (Channel)
|
---|
657 | {
|
---|
658 | case TIM_CHANNEL_1:
|
---|
659 | {
|
---|
660 | /* Enable the TIM Capture/Compare 1 interrupt */
|
---|
661 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
---|
662 | }
|
---|
663 | break;
|
---|
664 |
|
---|
665 | case TIM_CHANNEL_2:
|
---|
666 | {
|
---|
667 | /* Enable the TIM Capture/Compare 2 interrupt */
|
---|
668 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
---|
669 | }
|
---|
670 | break;
|
---|
671 |
|
---|
672 | case TIM_CHANNEL_3:
|
---|
673 | {
|
---|
674 | /* Enable the TIM Capture/Compare 3 interrupt */
|
---|
675 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
|
---|
676 | }
|
---|
677 | break;
|
---|
678 |
|
---|
679 | case TIM_CHANNEL_4:
|
---|
680 | {
|
---|
681 | /* Enable the TIM Capture/Compare 4 interrupt */
|
---|
682 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
|
---|
683 | }
|
---|
684 | break;
|
---|
685 |
|
---|
686 | default:
|
---|
687 | break;
|
---|
688 | }
|
---|
689 |
|
---|
690 | /* Enable the Output compare channel */
|
---|
691 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
---|
692 |
|
---|
693 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
|
---|
694 | {
|
---|
695 | /* Enable the main output */
|
---|
696 | __HAL_TIM_MOE_ENABLE(htim);
|
---|
697 | }
|
---|
698 |
|
---|
699 | /* Enable the Peripheral */
|
---|
700 | __HAL_TIM_ENABLE(htim);
|
---|
701 |
|
---|
702 | /* Return function status */
|
---|
703 | return HAL_OK;
|
---|
704 | }
|
---|
705 |
|
---|
706 | /**
|
---|
707 | * @brief Stops the TIM Output Compare signal generation in interrupt mode.
|
---|
708 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
709 | * the configuration information for TIM module.
|
---|
710 | * @param Channel: TIM Channel to be disabled.
|
---|
711 | * This parameter can be one of the following values:
|
---|
712 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
713 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
714 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
715 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
716 | * @retval HAL status
|
---|
717 | */
|
---|
718 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
719 | {
|
---|
720 | /* Check the parameters */
|
---|
721 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
---|
722 |
|
---|
723 | switch (Channel)
|
---|
724 | {
|
---|
725 | case TIM_CHANNEL_1:
|
---|
726 | {
|
---|
727 | /* Disable the TIM Capture/Compare 1 interrupt */
|
---|
728 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
---|
729 | }
|
---|
730 | break;
|
---|
731 |
|
---|
732 | case TIM_CHANNEL_2:
|
---|
733 | {
|
---|
734 | /* Disable the TIM Capture/Compare 2 interrupt */
|
---|
735 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
---|
736 | }
|
---|
737 | break;
|
---|
738 |
|
---|
739 | case TIM_CHANNEL_3:
|
---|
740 | {
|
---|
741 | /* Disable the TIM Capture/Compare 3 interrupt */
|
---|
742 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
|
---|
743 | }
|
---|
744 | break;
|
---|
745 |
|
---|
746 | case TIM_CHANNEL_4:
|
---|
747 | {
|
---|
748 | /* Disable the TIM Capture/Compare 4 interrupt */
|
---|
749 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
|
---|
750 | }
|
---|
751 | break;
|
---|
752 |
|
---|
753 | default:
|
---|
754 | break;
|
---|
755 | }
|
---|
756 |
|
---|
757 | /* Disable the Output compare channel */
|
---|
758 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
---|
759 |
|
---|
760 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
|
---|
761 | {
|
---|
762 | /* Disable the Main Output */
|
---|
763 | __HAL_TIM_MOE_DISABLE(htim);
|
---|
764 | }
|
---|
765 |
|
---|
766 | /* Disable the Peripheral */
|
---|
767 | __HAL_TIM_DISABLE(htim);
|
---|
768 |
|
---|
769 | /* Return function status */
|
---|
770 | return HAL_OK;
|
---|
771 | }
|
---|
772 |
|
---|
773 | /**
|
---|
774 | * @brief Starts the TIM Output Compare signal generation in DMA mode.
|
---|
775 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
776 | * the configuration information for TIM module.
|
---|
777 | * @param Channel: TIM Channel to be enabled.
|
---|
778 | * This parameter can be one of the following values:
|
---|
779 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
780 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
781 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
782 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
783 | * @param pData: The source Buffer address.
|
---|
784 | * @param Length: The length of data to be transferred from memory to TIM peripheral
|
---|
785 | * @retval HAL status
|
---|
786 | */
|
---|
787 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
|
---|
788 | {
|
---|
789 | /* Check the parameters */
|
---|
790 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
---|
791 |
|
---|
792 | if((htim->State == HAL_TIM_STATE_BUSY))
|
---|
793 | {
|
---|
794 | return HAL_BUSY;
|
---|
795 | }
|
---|
796 | else if((htim->State == HAL_TIM_STATE_READY))
|
---|
797 | {
|
---|
798 | if(((uint32_t)pData == 0 ) && (Length > 0))
|
---|
799 | {
|
---|
800 | return HAL_ERROR;
|
---|
801 | }
|
---|
802 | else
|
---|
803 | {
|
---|
804 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
805 | }
|
---|
806 | }
|
---|
807 | switch (Channel)
|
---|
808 | {
|
---|
809 | case TIM_CHANNEL_1:
|
---|
810 | {
|
---|
811 | /* Set the DMA Period elapsed callback */
|
---|
812 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
---|
813 |
|
---|
814 | /* Set the DMA error callback */
|
---|
815 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
---|
816 |
|
---|
817 | /* Enable the DMA Stream */
|
---|
818 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
|
---|
819 |
|
---|
820 | /* Enable the TIM Capture/Compare 1 DMA request */
|
---|
821 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
|
---|
822 | }
|
---|
823 | break;
|
---|
824 |
|
---|
825 | case TIM_CHANNEL_2:
|
---|
826 | {
|
---|
827 | /* Set the DMA Period elapsed callback */
|
---|
828 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
---|
829 |
|
---|
830 | /* Set the DMA error callback */
|
---|
831 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
---|
832 |
|
---|
833 | /* Enable the DMA Stream */
|
---|
834 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
|
---|
835 |
|
---|
836 | /* Enable the TIM Capture/Compare 2 DMA request */
|
---|
837 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
|
---|
838 | }
|
---|
839 | break;
|
---|
840 |
|
---|
841 | case TIM_CHANNEL_3:
|
---|
842 | {
|
---|
843 | /* Set the DMA Period elapsed callback */
|
---|
844 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
---|
845 |
|
---|
846 | /* Set the DMA error callback */
|
---|
847 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
---|
848 |
|
---|
849 | /* Enable the DMA Stream */
|
---|
850 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
|
---|
851 |
|
---|
852 | /* Enable the TIM Capture/Compare 3 DMA request */
|
---|
853 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
|
---|
854 | }
|
---|
855 | break;
|
---|
856 |
|
---|
857 | case TIM_CHANNEL_4:
|
---|
858 | {
|
---|
859 | /* Set the DMA Period elapsed callback */
|
---|
860 | htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
---|
861 |
|
---|
862 | /* Set the DMA error callback */
|
---|
863 | htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
|
---|
864 |
|
---|
865 | /* Enable the DMA Stream */
|
---|
866 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
|
---|
867 |
|
---|
868 | /* Enable the TIM Capture/Compare 4 DMA request */
|
---|
869 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
|
---|
870 | }
|
---|
871 | break;
|
---|
872 |
|
---|
873 | default:
|
---|
874 | break;
|
---|
875 | }
|
---|
876 |
|
---|
877 | /* Enable the Output compare channel */
|
---|
878 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
---|
879 |
|
---|
880 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
|
---|
881 | {
|
---|
882 | /* Enable the main output */
|
---|
883 | __HAL_TIM_MOE_ENABLE(htim);
|
---|
884 | }
|
---|
885 |
|
---|
886 | /* Enable the Peripheral */
|
---|
887 | __HAL_TIM_ENABLE(htim);
|
---|
888 |
|
---|
889 | /* Return function status */
|
---|
890 | return HAL_OK;
|
---|
891 | }
|
---|
892 |
|
---|
893 | /**
|
---|
894 | * @brief Stops the TIM Output Compare signal generation in DMA mode.
|
---|
895 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
896 | * the configuration information for TIM module.
|
---|
897 | * @param Channel: TIM Channel to be disabled.
|
---|
898 | * This parameter can be one of the following values:
|
---|
899 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
900 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
901 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
902 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
903 | * @retval HAL status
|
---|
904 | */
|
---|
905 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
906 | {
|
---|
907 | /* Check the parameters */
|
---|
908 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
---|
909 |
|
---|
910 | switch (Channel)
|
---|
911 | {
|
---|
912 | case TIM_CHANNEL_1:
|
---|
913 | {
|
---|
914 | /* Disable the TIM Capture/Compare 1 DMA request */
|
---|
915 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
|
---|
916 | }
|
---|
917 | break;
|
---|
918 |
|
---|
919 | case TIM_CHANNEL_2:
|
---|
920 | {
|
---|
921 | /* Disable the TIM Capture/Compare 2 DMA request */
|
---|
922 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
|
---|
923 | }
|
---|
924 | break;
|
---|
925 |
|
---|
926 | case TIM_CHANNEL_3:
|
---|
927 | {
|
---|
928 | /* Disable the TIM Capture/Compare 3 DMA request */
|
---|
929 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
|
---|
930 | }
|
---|
931 | break;
|
---|
932 |
|
---|
933 | case TIM_CHANNEL_4:
|
---|
934 | {
|
---|
935 | /* Disable the TIM Capture/Compare 4 interrupt */
|
---|
936 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
|
---|
937 | }
|
---|
938 | break;
|
---|
939 |
|
---|
940 | default:
|
---|
941 | break;
|
---|
942 | }
|
---|
943 |
|
---|
944 | /* Disable the Output compare channel */
|
---|
945 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
---|
946 |
|
---|
947 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
|
---|
948 | {
|
---|
949 | /* Disable the Main Output */
|
---|
950 | __HAL_TIM_MOE_DISABLE(htim);
|
---|
951 | }
|
---|
952 |
|
---|
953 | /* Disable the Peripheral */
|
---|
954 | __HAL_TIM_DISABLE(htim);
|
---|
955 |
|
---|
956 | /* Change the htim state */
|
---|
957 | htim->State = HAL_TIM_STATE_READY;
|
---|
958 |
|
---|
959 | /* Return function status */
|
---|
960 | return HAL_OK;
|
---|
961 | }
|
---|
962 | /**
|
---|
963 | * @}
|
---|
964 | */
|
---|
965 |
|
---|
966 | /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
|
---|
967 | * @brief Time PWM functions
|
---|
968 | *
|
---|
969 | @verbatim
|
---|
970 | ==============================================================================
|
---|
971 | ##### Time PWM functions #####
|
---|
972 | ==============================================================================
|
---|
973 | [..]
|
---|
974 | This section provides functions allowing to:
|
---|
975 | (+) Initialize and configure the TIM OPWM.
|
---|
976 | (+) De-initialize the TIM PWM.
|
---|
977 | (+) Start the Time PWM.
|
---|
978 | (+) Stop the Time PWM.
|
---|
979 | (+) Start the Time PWM and enable interrupt.
|
---|
980 | (+) Stop the Time PWM and disable interrupt.
|
---|
981 | (+) Start the Time PWM and enable DMA transfer.
|
---|
982 | (+) Stop the Time PWM and disable DMA transfer.
|
---|
983 |
|
---|
984 | @endverbatim
|
---|
985 | * @{
|
---|
986 | */
|
---|
987 | /**
|
---|
988 | * @brief Initializes the TIM PWM Time Base according to the specified
|
---|
989 | * parameters in the TIM_HandleTypeDef and create the associated handle.
|
---|
990 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
991 | * the configuration information for TIM module.
|
---|
992 | * @retval HAL status
|
---|
993 | */
|
---|
994 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
|
---|
995 | {
|
---|
996 | /* Check the TIM handle allocation */
|
---|
997 | if(htim == NULL)
|
---|
998 | {
|
---|
999 | return HAL_ERROR;
|
---|
1000 | }
|
---|
1001 |
|
---|
1002 | /* Check the parameters */
|
---|
1003 | assert_param(IS_TIM_INSTANCE(htim->Instance));
|
---|
1004 | assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
---|
1005 | assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
---|
1006 |
|
---|
1007 | if(htim->State == HAL_TIM_STATE_RESET)
|
---|
1008 | {
|
---|
1009 | /* Allocate lock resource and initialize it */
|
---|
1010 | htim->Lock = HAL_UNLOCKED;
|
---|
1011 | /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
---|
1012 | HAL_TIM_PWM_MspInit(htim);
|
---|
1013 | }
|
---|
1014 |
|
---|
1015 | /* Set the TIM state */
|
---|
1016 | htim->State= HAL_TIM_STATE_BUSY;
|
---|
1017 |
|
---|
1018 | /* Init the base time for the PWM */
|
---|
1019 | TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
---|
1020 |
|
---|
1021 | /* Initialize the TIM state*/
|
---|
1022 | htim->State= HAL_TIM_STATE_READY;
|
---|
1023 |
|
---|
1024 | return HAL_OK;
|
---|
1025 | }
|
---|
1026 |
|
---|
1027 | /**
|
---|
1028 | * @brief DeInitializes the TIM peripheral
|
---|
1029 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1030 | * the configuration information for TIM module.
|
---|
1031 | * @retval HAL status
|
---|
1032 | */
|
---|
1033 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
|
---|
1034 | {
|
---|
1035 | /* Check the parameters */
|
---|
1036 | assert_param(IS_TIM_INSTANCE(htim->Instance));
|
---|
1037 |
|
---|
1038 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
1039 |
|
---|
1040 | /* Disable the TIM Peripheral Clock */
|
---|
1041 | __HAL_TIM_DISABLE(htim);
|
---|
1042 |
|
---|
1043 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
|
---|
1044 | HAL_TIM_PWM_MspDeInit(htim);
|
---|
1045 |
|
---|
1046 | /* Change TIM state */
|
---|
1047 | htim->State = HAL_TIM_STATE_RESET;
|
---|
1048 |
|
---|
1049 | /* Release Lock */
|
---|
1050 | __HAL_UNLOCK(htim);
|
---|
1051 |
|
---|
1052 | return HAL_OK;
|
---|
1053 | }
|
---|
1054 |
|
---|
1055 | /**
|
---|
1056 | * @brief Initializes the TIM PWM MSP.
|
---|
1057 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1058 | * the configuration information for TIM module.
|
---|
1059 | * @retval None
|
---|
1060 | */
|
---|
1061 | __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
|
---|
1062 | {
|
---|
1063 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
1064 | the HAL_TIM_PWM_MspInit could be implemented in the user file
|
---|
1065 | */
|
---|
1066 | }
|
---|
1067 |
|
---|
1068 | /**
|
---|
1069 | * @brief DeInitializes TIM PWM MSP.
|
---|
1070 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1071 | * the configuration information for TIM module.
|
---|
1072 | * @retval None
|
---|
1073 | */
|
---|
1074 | __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
|
---|
1075 | {
|
---|
1076 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
1077 | the HAL_TIM_PWM_MspDeInit could be implemented in the user file
|
---|
1078 | */
|
---|
1079 | }
|
---|
1080 |
|
---|
1081 | /**
|
---|
1082 | * @brief Starts the PWM signal generation.
|
---|
1083 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1084 | * the configuration information for TIM module.
|
---|
1085 | * @param Channel: TIM Channels to be enabled.
|
---|
1086 | * This parameter can be one of the following values:
|
---|
1087 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
1088 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
1089 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
1090 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
1091 | * @retval HAL status
|
---|
1092 | */
|
---|
1093 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
1094 | {
|
---|
1095 | /* Check the parameters */
|
---|
1096 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
---|
1097 |
|
---|
1098 | /* Enable the Capture compare channel */
|
---|
1099 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
---|
1100 |
|
---|
1101 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
|
---|
1102 | {
|
---|
1103 | /* Enable the main output */
|
---|
1104 | __HAL_TIM_MOE_ENABLE(htim);
|
---|
1105 | }
|
---|
1106 |
|
---|
1107 | /* Enable the Peripheral */
|
---|
1108 | __HAL_TIM_ENABLE(htim);
|
---|
1109 |
|
---|
1110 | /* Return function status */
|
---|
1111 | return HAL_OK;
|
---|
1112 | }
|
---|
1113 |
|
---|
1114 | /**
|
---|
1115 | * @brief Stops the PWM signal generation.
|
---|
1116 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1117 | * the configuration information for TIM module.
|
---|
1118 | * @param Channel: TIM Channels to be disabled.
|
---|
1119 | * This parameter can be one of the following values:
|
---|
1120 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
1121 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
1122 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
1123 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
1124 | * @retval HAL status
|
---|
1125 | */
|
---|
1126 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
1127 | {
|
---|
1128 | /* Check the parameters */
|
---|
1129 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
---|
1130 |
|
---|
1131 | /* Disable the Capture compare channel */
|
---|
1132 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
---|
1133 |
|
---|
1134 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
|
---|
1135 | {
|
---|
1136 | /* Disable the Main Output */
|
---|
1137 | __HAL_TIM_MOE_DISABLE(htim);
|
---|
1138 | }
|
---|
1139 |
|
---|
1140 | /* Disable the Peripheral */
|
---|
1141 | __HAL_TIM_DISABLE(htim);
|
---|
1142 |
|
---|
1143 | /* Change the htim state */
|
---|
1144 | htim->State = HAL_TIM_STATE_READY;
|
---|
1145 |
|
---|
1146 | /* Return function status */
|
---|
1147 | return HAL_OK;
|
---|
1148 | }
|
---|
1149 |
|
---|
1150 | /**
|
---|
1151 | * @brief Starts the PWM signal generation in interrupt mode.
|
---|
1152 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1153 | * the configuration information for TIM module.
|
---|
1154 | * @param Channel: TIM Channel to be disabled.
|
---|
1155 | * This parameter can be one of the following values:
|
---|
1156 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
1157 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
1158 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
1159 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
1160 | * @retval HAL status
|
---|
1161 | */
|
---|
1162 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
1163 | {
|
---|
1164 | /* Check the parameters */
|
---|
1165 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
---|
1166 |
|
---|
1167 | switch (Channel)
|
---|
1168 | {
|
---|
1169 | case TIM_CHANNEL_1:
|
---|
1170 | {
|
---|
1171 | /* Enable the TIM Capture/Compare 1 interrupt */
|
---|
1172 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
---|
1173 | }
|
---|
1174 | break;
|
---|
1175 |
|
---|
1176 | case TIM_CHANNEL_2:
|
---|
1177 | {
|
---|
1178 | /* Enable the TIM Capture/Compare 2 interrupt */
|
---|
1179 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
---|
1180 | }
|
---|
1181 | break;
|
---|
1182 |
|
---|
1183 | case TIM_CHANNEL_3:
|
---|
1184 | {
|
---|
1185 | /* Enable the TIM Capture/Compare 3 interrupt */
|
---|
1186 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
|
---|
1187 | }
|
---|
1188 | break;
|
---|
1189 |
|
---|
1190 | case TIM_CHANNEL_4:
|
---|
1191 | {
|
---|
1192 | /* Enable the TIM Capture/Compare 4 interrupt */
|
---|
1193 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
|
---|
1194 | }
|
---|
1195 | break;
|
---|
1196 |
|
---|
1197 | default:
|
---|
1198 | break;
|
---|
1199 | }
|
---|
1200 |
|
---|
1201 | /* Enable the Capture compare channel */
|
---|
1202 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
---|
1203 |
|
---|
1204 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
|
---|
1205 | {
|
---|
1206 | /* Enable the main output */
|
---|
1207 | __HAL_TIM_MOE_ENABLE(htim);
|
---|
1208 | }
|
---|
1209 |
|
---|
1210 | /* Enable the Peripheral */
|
---|
1211 | __HAL_TIM_ENABLE(htim);
|
---|
1212 |
|
---|
1213 | /* Return function status */
|
---|
1214 | return HAL_OK;
|
---|
1215 | }
|
---|
1216 |
|
---|
1217 | /**
|
---|
1218 | * @brief Stops the PWM signal generation in interrupt mode.
|
---|
1219 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1220 | * the configuration information for TIM module.
|
---|
1221 | * @param Channel: TIM Channels to be disabled.
|
---|
1222 | * This parameter can be one of the following values:
|
---|
1223 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
1224 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
1225 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
1226 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
1227 | * @retval HAL status
|
---|
1228 | */
|
---|
1229 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
1230 | {
|
---|
1231 | /* Check the parameters */
|
---|
1232 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
---|
1233 |
|
---|
1234 | switch (Channel)
|
---|
1235 | {
|
---|
1236 | case TIM_CHANNEL_1:
|
---|
1237 | {
|
---|
1238 | /* Disable the TIM Capture/Compare 1 interrupt */
|
---|
1239 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
---|
1240 | }
|
---|
1241 | break;
|
---|
1242 |
|
---|
1243 | case TIM_CHANNEL_2:
|
---|
1244 | {
|
---|
1245 | /* Disable the TIM Capture/Compare 2 interrupt */
|
---|
1246 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
---|
1247 | }
|
---|
1248 | break;
|
---|
1249 |
|
---|
1250 | case TIM_CHANNEL_3:
|
---|
1251 | {
|
---|
1252 | /* Disable the TIM Capture/Compare 3 interrupt */
|
---|
1253 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
|
---|
1254 | }
|
---|
1255 | break;
|
---|
1256 |
|
---|
1257 | case TIM_CHANNEL_4:
|
---|
1258 | {
|
---|
1259 | /* Disable the TIM Capture/Compare 4 interrupt */
|
---|
1260 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
|
---|
1261 | }
|
---|
1262 | break;
|
---|
1263 |
|
---|
1264 | default:
|
---|
1265 | break;
|
---|
1266 | }
|
---|
1267 |
|
---|
1268 | /* Disable the Capture compare channel */
|
---|
1269 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
---|
1270 |
|
---|
1271 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
|
---|
1272 | {
|
---|
1273 | /* Disable the Main Output */
|
---|
1274 | __HAL_TIM_MOE_DISABLE(htim);
|
---|
1275 | }
|
---|
1276 |
|
---|
1277 | /* Disable the Peripheral */
|
---|
1278 | __HAL_TIM_DISABLE(htim);
|
---|
1279 |
|
---|
1280 | /* Return function status */
|
---|
1281 | return HAL_OK;
|
---|
1282 | }
|
---|
1283 |
|
---|
1284 | /**
|
---|
1285 | * @brief Starts the TIM PWM signal generation in DMA mode.
|
---|
1286 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1287 | * the configuration information for TIM module.
|
---|
1288 | * @param Channel: TIM Channels to be enabled.
|
---|
1289 | * This parameter can be one of the following values:
|
---|
1290 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
1291 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
1292 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
1293 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
1294 | * @param pData: The source Buffer address.
|
---|
1295 | * @param Length: The length of data to be transferred from memory to TIM peripheral
|
---|
1296 | * @retval HAL status
|
---|
1297 | */
|
---|
1298 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
|
---|
1299 | {
|
---|
1300 | /* Check the parameters */
|
---|
1301 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
---|
1302 |
|
---|
1303 | if((htim->State == HAL_TIM_STATE_BUSY))
|
---|
1304 | {
|
---|
1305 | return HAL_BUSY;
|
---|
1306 | }
|
---|
1307 | else if((htim->State == HAL_TIM_STATE_READY))
|
---|
1308 | {
|
---|
1309 | if(((uint32_t)pData == 0 ) && (Length > 0))
|
---|
1310 | {
|
---|
1311 | return HAL_ERROR;
|
---|
1312 | }
|
---|
1313 | else
|
---|
1314 | {
|
---|
1315 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
1316 | }
|
---|
1317 | }
|
---|
1318 | switch (Channel)
|
---|
1319 | {
|
---|
1320 | case TIM_CHANNEL_1:
|
---|
1321 | {
|
---|
1322 | /* Set the DMA Period elapsed callback */
|
---|
1323 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
---|
1324 |
|
---|
1325 | /* Set the DMA error callback */
|
---|
1326 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
---|
1327 |
|
---|
1328 | /* Enable the DMA Stream */
|
---|
1329 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
|
---|
1330 |
|
---|
1331 | /* Enable the TIM Capture/Compare 1 DMA request */
|
---|
1332 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
|
---|
1333 | }
|
---|
1334 | break;
|
---|
1335 |
|
---|
1336 | case TIM_CHANNEL_2:
|
---|
1337 | {
|
---|
1338 | /* Set the DMA Period elapsed callback */
|
---|
1339 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
---|
1340 |
|
---|
1341 | /* Set the DMA error callback */
|
---|
1342 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
---|
1343 |
|
---|
1344 | /* Enable the DMA Stream */
|
---|
1345 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
|
---|
1346 |
|
---|
1347 | /* Enable the TIM Capture/Compare 2 DMA request */
|
---|
1348 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
|
---|
1349 | }
|
---|
1350 | break;
|
---|
1351 |
|
---|
1352 | case TIM_CHANNEL_3:
|
---|
1353 | {
|
---|
1354 | /* Set the DMA Period elapsed callback */
|
---|
1355 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
---|
1356 |
|
---|
1357 | /* Set the DMA error callback */
|
---|
1358 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
---|
1359 |
|
---|
1360 | /* Enable the DMA Stream */
|
---|
1361 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
|
---|
1362 |
|
---|
1363 | /* Enable the TIM Output Capture/Compare 3 request */
|
---|
1364 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
|
---|
1365 | }
|
---|
1366 | break;
|
---|
1367 |
|
---|
1368 | case TIM_CHANNEL_4:
|
---|
1369 | {
|
---|
1370 | /* Set the DMA Period elapsed callback */
|
---|
1371 | htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
---|
1372 |
|
---|
1373 | /* Set the DMA error callback */
|
---|
1374 | htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
|
---|
1375 |
|
---|
1376 | /* Enable the DMA Stream */
|
---|
1377 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
|
---|
1378 |
|
---|
1379 | /* Enable the TIM Capture/Compare 4 DMA request */
|
---|
1380 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
|
---|
1381 | }
|
---|
1382 | break;
|
---|
1383 |
|
---|
1384 | default:
|
---|
1385 | break;
|
---|
1386 | }
|
---|
1387 |
|
---|
1388 | /* Enable the Capture compare channel */
|
---|
1389 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
---|
1390 |
|
---|
1391 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
|
---|
1392 | {
|
---|
1393 | /* Enable the main output */
|
---|
1394 | __HAL_TIM_MOE_ENABLE(htim);
|
---|
1395 | }
|
---|
1396 |
|
---|
1397 | /* Enable the Peripheral */
|
---|
1398 | __HAL_TIM_ENABLE(htim);
|
---|
1399 |
|
---|
1400 | /* Return function status */
|
---|
1401 | return HAL_OK;
|
---|
1402 | }
|
---|
1403 |
|
---|
1404 | /**
|
---|
1405 | * @brief Stops the TIM PWM signal generation in DMA mode.
|
---|
1406 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1407 | * the configuration information for TIM module.
|
---|
1408 | * @param Channel: TIM Channels to be disabled.
|
---|
1409 | * This parameter can be one of the following values:
|
---|
1410 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
1411 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
1412 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
1413 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
1414 | * @retval HAL status
|
---|
1415 | */
|
---|
1416 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
1417 | {
|
---|
1418 | /* Check the parameters */
|
---|
1419 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
---|
1420 |
|
---|
1421 | switch (Channel)
|
---|
1422 | {
|
---|
1423 | case TIM_CHANNEL_1:
|
---|
1424 | {
|
---|
1425 | /* Disable the TIM Capture/Compare 1 DMA request */
|
---|
1426 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
|
---|
1427 | }
|
---|
1428 | break;
|
---|
1429 |
|
---|
1430 | case TIM_CHANNEL_2:
|
---|
1431 | {
|
---|
1432 | /* Disable the TIM Capture/Compare 2 DMA request */
|
---|
1433 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
|
---|
1434 | }
|
---|
1435 | break;
|
---|
1436 |
|
---|
1437 | case TIM_CHANNEL_3:
|
---|
1438 | {
|
---|
1439 | /* Disable the TIM Capture/Compare 3 DMA request */
|
---|
1440 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
|
---|
1441 | }
|
---|
1442 | break;
|
---|
1443 |
|
---|
1444 | case TIM_CHANNEL_4:
|
---|
1445 | {
|
---|
1446 | /* Disable the TIM Capture/Compare 4 interrupt */
|
---|
1447 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
|
---|
1448 | }
|
---|
1449 | break;
|
---|
1450 |
|
---|
1451 | default:
|
---|
1452 | break;
|
---|
1453 | }
|
---|
1454 |
|
---|
1455 | /* Disable the Capture compare channel */
|
---|
1456 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
---|
1457 |
|
---|
1458 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
|
---|
1459 | {
|
---|
1460 | /* Disable the Main Output */
|
---|
1461 | __HAL_TIM_MOE_DISABLE(htim);
|
---|
1462 | }
|
---|
1463 |
|
---|
1464 | /* Disable the Peripheral */
|
---|
1465 | __HAL_TIM_DISABLE(htim);
|
---|
1466 |
|
---|
1467 | /* Change the htim state */
|
---|
1468 | htim->State = HAL_TIM_STATE_READY;
|
---|
1469 |
|
---|
1470 | /* Return function status */
|
---|
1471 | return HAL_OK;
|
---|
1472 | }
|
---|
1473 | /**
|
---|
1474 | * @}
|
---|
1475 | */
|
---|
1476 |
|
---|
1477 | /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
|
---|
1478 | * @brief Time Input Capture functions
|
---|
1479 | *
|
---|
1480 | @verbatim
|
---|
1481 | ==============================================================================
|
---|
1482 | ##### Time Input Capture functions #####
|
---|
1483 | ==============================================================================
|
---|
1484 | [..]
|
---|
1485 | This section provides functions allowing to:
|
---|
1486 | (+) Initialize and configure the TIM Input Capture.
|
---|
1487 | (+) De-initialize the TIM Input Capture.
|
---|
1488 | (+) Start the Time Input Capture.
|
---|
1489 | (+) Stop the Time Input Capture.
|
---|
1490 | (+) Start the Time Input Capture and enable interrupt.
|
---|
1491 | (+) Stop the Time Input Capture and disable interrupt.
|
---|
1492 | (+) Start the Time Input Capture and enable DMA transfer.
|
---|
1493 | (+) Stop the Time Input Capture and disable DMA transfer.
|
---|
1494 |
|
---|
1495 | @endverbatim
|
---|
1496 | * @{
|
---|
1497 | */
|
---|
1498 | /**
|
---|
1499 | * @brief Initializes the TIM Input Capture Time base according to the specified
|
---|
1500 | * parameters in the TIM_HandleTypeDef and create the associated handle.
|
---|
1501 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1502 | * the configuration information for TIM module.
|
---|
1503 | * @retval HAL status
|
---|
1504 | */
|
---|
1505 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
|
---|
1506 | {
|
---|
1507 | /* Check the TIM handle allocation */
|
---|
1508 | if(htim == NULL)
|
---|
1509 | {
|
---|
1510 | return HAL_ERROR;
|
---|
1511 | }
|
---|
1512 |
|
---|
1513 | /* Check the parameters */
|
---|
1514 | assert_param(IS_TIM_INSTANCE(htim->Instance));
|
---|
1515 | assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
---|
1516 | assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
---|
1517 |
|
---|
1518 | if(htim->State == HAL_TIM_STATE_RESET)
|
---|
1519 | {
|
---|
1520 | /* Allocate lock resource and initialize it */
|
---|
1521 | htim->Lock = HAL_UNLOCKED;
|
---|
1522 | /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
---|
1523 | HAL_TIM_IC_MspInit(htim);
|
---|
1524 | }
|
---|
1525 |
|
---|
1526 | /* Set the TIM state */
|
---|
1527 | htim->State= HAL_TIM_STATE_BUSY;
|
---|
1528 |
|
---|
1529 | /* Init the base time for the input capture */
|
---|
1530 | TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
---|
1531 |
|
---|
1532 | /* Initialize the TIM state*/
|
---|
1533 | htim->State= HAL_TIM_STATE_READY;
|
---|
1534 |
|
---|
1535 | return HAL_OK;
|
---|
1536 | }
|
---|
1537 |
|
---|
1538 | /**
|
---|
1539 | * @brief DeInitializes the TIM peripheral
|
---|
1540 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1541 | * the configuration information for TIM module.
|
---|
1542 | * @retval HAL status
|
---|
1543 | */
|
---|
1544 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
|
---|
1545 | {
|
---|
1546 | /* Check the parameters */
|
---|
1547 | assert_param(IS_TIM_INSTANCE(htim->Instance));
|
---|
1548 |
|
---|
1549 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
1550 |
|
---|
1551 | /* Disable the TIM Peripheral Clock */
|
---|
1552 | __HAL_TIM_DISABLE(htim);
|
---|
1553 |
|
---|
1554 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
|
---|
1555 | HAL_TIM_IC_MspDeInit(htim);
|
---|
1556 |
|
---|
1557 | /* Change TIM state */
|
---|
1558 | htim->State = HAL_TIM_STATE_RESET;
|
---|
1559 |
|
---|
1560 | /* Release Lock */
|
---|
1561 | __HAL_UNLOCK(htim);
|
---|
1562 |
|
---|
1563 | return HAL_OK;
|
---|
1564 | }
|
---|
1565 |
|
---|
1566 | /**
|
---|
1567 | * @brief Initializes the TIM INput Capture MSP.
|
---|
1568 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1569 | * the configuration information for TIM module.
|
---|
1570 | * @retval None
|
---|
1571 | */
|
---|
1572 | __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
|
---|
1573 | {
|
---|
1574 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
1575 | the HAL_TIM_IC_MspInit could be implemented in the user file
|
---|
1576 | */
|
---|
1577 | }
|
---|
1578 |
|
---|
1579 | /**
|
---|
1580 | * @brief DeInitializes TIM Input Capture MSP.
|
---|
1581 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1582 | * the configuration information for TIM module.
|
---|
1583 | * @retval None
|
---|
1584 | */
|
---|
1585 | __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
|
---|
1586 | {
|
---|
1587 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
1588 | the HAL_TIM_IC_MspDeInit could be implemented in the user file
|
---|
1589 | */
|
---|
1590 | }
|
---|
1591 |
|
---|
1592 | /**
|
---|
1593 | * @brief Starts the TIM Input Capture measurement.
|
---|
1594 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1595 | * the configuration information for TIM module.
|
---|
1596 | * @param Channel: TIM Channels to be enabled.
|
---|
1597 | * This parameter can be one of the following values:
|
---|
1598 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
1599 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
1600 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
1601 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
1602 | * @retval HAL status
|
---|
1603 | */
|
---|
1604 | HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
1605 | {
|
---|
1606 | /* Check the parameters */
|
---|
1607 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
---|
1608 |
|
---|
1609 | /* Enable the Input Capture channel */
|
---|
1610 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
---|
1611 |
|
---|
1612 | /* Enable the Peripheral */
|
---|
1613 | __HAL_TIM_ENABLE(htim);
|
---|
1614 |
|
---|
1615 | /* Return function status */
|
---|
1616 | return HAL_OK;
|
---|
1617 | }
|
---|
1618 |
|
---|
1619 | /**
|
---|
1620 | * @brief Stops the TIM Input Capture measurement.
|
---|
1621 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1622 | * the configuration information for TIM module.
|
---|
1623 | * @param Channel: TIM Channels to be disabled.
|
---|
1624 | * This parameter can be one of the following values:
|
---|
1625 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
1626 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
1627 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
1628 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
1629 | * @retval HAL status
|
---|
1630 | */
|
---|
1631 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
1632 | {
|
---|
1633 | /* Check the parameters */
|
---|
1634 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
---|
1635 |
|
---|
1636 | /* Disable the Input Capture channel */
|
---|
1637 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
---|
1638 |
|
---|
1639 | /* Disable the Peripheral */
|
---|
1640 | __HAL_TIM_DISABLE(htim);
|
---|
1641 |
|
---|
1642 | /* Return function status */
|
---|
1643 | return HAL_OK;
|
---|
1644 | }
|
---|
1645 |
|
---|
1646 | /**
|
---|
1647 | * @brief Starts the TIM Input Capture measurement in interrupt mode.
|
---|
1648 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1649 | * the configuration information for TIM module.
|
---|
1650 | * @param Channel: TIM Channels to be enabled.
|
---|
1651 | * This parameter can be one of the following values:
|
---|
1652 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
1653 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
1654 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
1655 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
1656 | * @retval HAL status
|
---|
1657 | */
|
---|
1658 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
1659 | {
|
---|
1660 | /* Check the parameters */
|
---|
1661 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
---|
1662 |
|
---|
1663 | switch (Channel)
|
---|
1664 | {
|
---|
1665 | case TIM_CHANNEL_1:
|
---|
1666 | {
|
---|
1667 | /* Enable the TIM Capture/Compare 1 interrupt */
|
---|
1668 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
---|
1669 | }
|
---|
1670 | break;
|
---|
1671 |
|
---|
1672 | case TIM_CHANNEL_2:
|
---|
1673 | {
|
---|
1674 | /* Enable the TIM Capture/Compare 2 interrupt */
|
---|
1675 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
---|
1676 | }
|
---|
1677 | break;
|
---|
1678 |
|
---|
1679 | case TIM_CHANNEL_3:
|
---|
1680 | {
|
---|
1681 | /* Enable the TIM Capture/Compare 3 interrupt */
|
---|
1682 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
|
---|
1683 | }
|
---|
1684 | break;
|
---|
1685 |
|
---|
1686 | case TIM_CHANNEL_4:
|
---|
1687 | {
|
---|
1688 | /* Enable the TIM Capture/Compare 4 interrupt */
|
---|
1689 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
|
---|
1690 | }
|
---|
1691 | break;
|
---|
1692 |
|
---|
1693 | default:
|
---|
1694 | break;
|
---|
1695 | }
|
---|
1696 | /* Enable the Input Capture channel */
|
---|
1697 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
---|
1698 |
|
---|
1699 | /* Enable the Peripheral */
|
---|
1700 | __HAL_TIM_ENABLE(htim);
|
---|
1701 |
|
---|
1702 | /* Return function status */
|
---|
1703 | return HAL_OK;
|
---|
1704 | }
|
---|
1705 |
|
---|
1706 | /**
|
---|
1707 | * @brief Stops the TIM Input Capture measurement in interrupt mode.
|
---|
1708 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1709 | * the configuration information for TIM module.
|
---|
1710 | * @param Channel: TIM Channels to be disabled.
|
---|
1711 | * This parameter can be one of the following values:
|
---|
1712 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
1713 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
1714 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
1715 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
1716 | * @retval HAL status
|
---|
1717 | */
|
---|
1718 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
1719 | {
|
---|
1720 | /* Check the parameters */
|
---|
1721 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
---|
1722 |
|
---|
1723 | switch (Channel)
|
---|
1724 | {
|
---|
1725 | case TIM_CHANNEL_1:
|
---|
1726 | {
|
---|
1727 | /* Disable the TIM Capture/Compare 1 interrupt */
|
---|
1728 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
---|
1729 | }
|
---|
1730 | break;
|
---|
1731 |
|
---|
1732 | case TIM_CHANNEL_2:
|
---|
1733 | {
|
---|
1734 | /* Disable the TIM Capture/Compare 2 interrupt */
|
---|
1735 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
---|
1736 | }
|
---|
1737 | break;
|
---|
1738 |
|
---|
1739 | case TIM_CHANNEL_3:
|
---|
1740 | {
|
---|
1741 | /* Disable the TIM Capture/Compare 3 interrupt */
|
---|
1742 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
|
---|
1743 | }
|
---|
1744 | break;
|
---|
1745 |
|
---|
1746 | case TIM_CHANNEL_4:
|
---|
1747 | {
|
---|
1748 | /* Disable the TIM Capture/Compare 4 interrupt */
|
---|
1749 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
|
---|
1750 | }
|
---|
1751 | break;
|
---|
1752 |
|
---|
1753 | default:
|
---|
1754 | break;
|
---|
1755 | }
|
---|
1756 |
|
---|
1757 | /* Disable the Input Capture channel */
|
---|
1758 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
---|
1759 |
|
---|
1760 | /* Disable the Peripheral */
|
---|
1761 | __HAL_TIM_DISABLE(htim);
|
---|
1762 |
|
---|
1763 | /* Return function status */
|
---|
1764 | return HAL_OK;
|
---|
1765 | }
|
---|
1766 |
|
---|
1767 | /**
|
---|
1768 | * @brief Starts the TIM Input Capture measurement on in DMA mode.
|
---|
1769 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1770 | * the configuration information for TIM module.
|
---|
1771 | * @param Channel: TIM Channels to be enabled.
|
---|
1772 | * This parameter can be one of the following values:
|
---|
1773 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
1774 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
1775 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
1776 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
1777 | * @param pData: The destination Buffer address.
|
---|
1778 | * @param Length: The length of data to be transferred from TIM peripheral to memory.
|
---|
1779 | * @retval HAL status
|
---|
1780 | */
|
---|
1781 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
|
---|
1782 | {
|
---|
1783 | /* Check the parameters */
|
---|
1784 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
---|
1785 | assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
|
---|
1786 |
|
---|
1787 | if((htim->State == HAL_TIM_STATE_BUSY))
|
---|
1788 | {
|
---|
1789 | return HAL_BUSY;
|
---|
1790 | }
|
---|
1791 | else if((htim->State == HAL_TIM_STATE_READY))
|
---|
1792 | {
|
---|
1793 | if((pData == 0 ) && (Length > 0))
|
---|
1794 | {
|
---|
1795 | return HAL_ERROR;
|
---|
1796 | }
|
---|
1797 | else
|
---|
1798 | {
|
---|
1799 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
1800 | }
|
---|
1801 | }
|
---|
1802 |
|
---|
1803 | switch (Channel)
|
---|
1804 | {
|
---|
1805 | case TIM_CHANNEL_1:
|
---|
1806 | {
|
---|
1807 | /* Set the DMA Period elapsed callback */
|
---|
1808 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
|
---|
1809 |
|
---|
1810 | /* Set the DMA error callback */
|
---|
1811 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
---|
1812 |
|
---|
1813 | /* Enable the DMA Stream */
|
---|
1814 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
|
---|
1815 |
|
---|
1816 | /* Enable the TIM Capture/Compare 1 DMA request */
|
---|
1817 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
|
---|
1818 | }
|
---|
1819 | break;
|
---|
1820 |
|
---|
1821 | case TIM_CHANNEL_2:
|
---|
1822 | {
|
---|
1823 | /* Set the DMA Period elapsed callback */
|
---|
1824 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
|
---|
1825 |
|
---|
1826 | /* Set the DMA error callback */
|
---|
1827 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
---|
1828 |
|
---|
1829 | /* Enable the DMA Stream */
|
---|
1830 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
|
---|
1831 |
|
---|
1832 | /* Enable the TIM Capture/Compare 2 DMA request */
|
---|
1833 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
|
---|
1834 | }
|
---|
1835 | break;
|
---|
1836 |
|
---|
1837 | case TIM_CHANNEL_3:
|
---|
1838 | {
|
---|
1839 | /* Set the DMA Period elapsed callback */
|
---|
1840 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
|
---|
1841 |
|
---|
1842 | /* Set the DMA error callback */
|
---|
1843 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
---|
1844 |
|
---|
1845 | /* Enable the DMA Stream */
|
---|
1846 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
|
---|
1847 |
|
---|
1848 | /* Enable the TIM Capture/Compare 3 DMA request */
|
---|
1849 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
|
---|
1850 | }
|
---|
1851 | break;
|
---|
1852 |
|
---|
1853 | case TIM_CHANNEL_4:
|
---|
1854 | {
|
---|
1855 | /* Set the DMA Period elapsed callback */
|
---|
1856 | htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
|
---|
1857 |
|
---|
1858 | /* Set the DMA error callback */
|
---|
1859 | htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
|
---|
1860 |
|
---|
1861 | /* Enable the DMA Stream */
|
---|
1862 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
|
---|
1863 |
|
---|
1864 | /* Enable the TIM Capture/Compare 4 DMA request */
|
---|
1865 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
|
---|
1866 | }
|
---|
1867 | break;
|
---|
1868 |
|
---|
1869 | default:
|
---|
1870 | break;
|
---|
1871 | }
|
---|
1872 |
|
---|
1873 | /* Enable the Input Capture channel */
|
---|
1874 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
---|
1875 |
|
---|
1876 | /* Enable the Peripheral */
|
---|
1877 | __HAL_TIM_ENABLE(htim);
|
---|
1878 |
|
---|
1879 | /* Return function status */
|
---|
1880 | return HAL_OK;
|
---|
1881 | }
|
---|
1882 |
|
---|
1883 | /**
|
---|
1884 | * @brief Stops the TIM Input Capture measurement on in DMA mode.
|
---|
1885 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1886 | * the configuration information for TIM module.
|
---|
1887 | * @param Channel: TIM Channels to be disabled.
|
---|
1888 | * This parameter can be one of the following values:
|
---|
1889 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
1890 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
1891 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
1892 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
1893 | * @retval HAL status
|
---|
1894 | */
|
---|
1895 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
1896 | {
|
---|
1897 | /* Check the parameters */
|
---|
1898 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
---|
1899 | assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
|
---|
1900 |
|
---|
1901 | switch (Channel)
|
---|
1902 | {
|
---|
1903 | case TIM_CHANNEL_1:
|
---|
1904 | {
|
---|
1905 | /* Disable the TIM Capture/Compare 1 DMA request */
|
---|
1906 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
|
---|
1907 | }
|
---|
1908 | break;
|
---|
1909 |
|
---|
1910 | case TIM_CHANNEL_2:
|
---|
1911 | {
|
---|
1912 | /* Disable the TIM Capture/Compare 2 DMA request */
|
---|
1913 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
|
---|
1914 | }
|
---|
1915 | break;
|
---|
1916 |
|
---|
1917 | case TIM_CHANNEL_3:
|
---|
1918 | {
|
---|
1919 | /* Disable the TIM Capture/Compare 3 DMA request */
|
---|
1920 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
|
---|
1921 | }
|
---|
1922 | break;
|
---|
1923 |
|
---|
1924 | case TIM_CHANNEL_4:
|
---|
1925 | {
|
---|
1926 | /* Disable the TIM Capture/Compare 4 DMA request */
|
---|
1927 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
|
---|
1928 | }
|
---|
1929 | break;
|
---|
1930 |
|
---|
1931 | default:
|
---|
1932 | break;
|
---|
1933 | }
|
---|
1934 |
|
---|
1935 | /* Disable the Input Capture channel */
|
---|
1936 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
---|
1937 |
|
---|
1938 | /* Disable the Peripheral */
|
---|
1939 | __HAL_TIM_DISABLE(htim);
|
---|
1940 |
|
---|
1941 | /* Change the htim state */
|
---|
1942 | htim->State = HAL_TIM_STATE_READY;
|
---|
1943 |
|
---|
1944 | /* Return function status */
|
---|
1945 | return HAL_OK;
|
---|
1946 | }
|
---|
1947 | /**
|
---|
1948 | * @}
|
---|
1949 | */
|
---|
1950 |
|
---|
1951 | /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
|
---|
1952 | * @brief Time One Pulse functions
|
---|
1953 | *
|
---|
1954 | @verbatim
|
---|
1955 | ==============================================================================
|
---|
1956 | ##### Time One Pulse functions #####
|
---|
1957 | ==============================================================================
|
---|
1958 | [..]
|
---|
1959 | This section provides functions allowing to:
|
---|
1960 | (+) Initialize and configure the TIM One Pulse.
|
---|
1961 | (+) De-initialize the TIM One Pulse.
|
---|
1962 | (+) Start the Time One Pulse.
|
---|
1963 | (+) Stop the Time One Pulse.
|
---|
1964 | (+) Start the Time One Pulse and enable interrupt.
|
---|
1965 | (+) Stop the Time One Pulse and disable interrupt.
|
---|
1966 | (+) Start the Time One Pulse and enable DMA transfer.
|
---|
1967 | (+) Stop the Time One Pulse and disable DMA transfer.
|
---|
1968 |
|
---|
1969 | @endverbatim
|
---|
1970 | * @{
|
---|
1971 | */
|
---|
1972 | /**
|
---|
1973 | * @brief Initializes the TIM One Pulse Time Base according to the specified
|
---|
1974 | * parameters in the TIM_HandleTypeDef and create the associated handle.
|
---|
1975 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
1976 | * the configuration information for TIM module.
|
---|
1977 | * @param OnePulseMode: Select the One pulse mode.
|
---|
1978 | * This parameter can be one of the following values:
|
---|
1979 | * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
|
---|
1980 | * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
|
---|
1981 | * @retval HAL status
|
---|
1982 | */
|
---|
1983 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
|
---|
1984 | {
|
---|
1985 | /* Check the TIM handle allocation */
|
---|
1986 | if(htim == NULL)
|
---|
1987 | {
|
---|
1988 | return HAL_ERROR;
|
---|
1989 | }
|
---|
1990 |
|
---|
1991 | /* Check the parameters */
|
---|
1992 | assert_param(IS_TIM_INSTANCE(htim->Instance));
|
---|
1993 | assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
---|
1994 | assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
---|
1995 | assert_param(IS_TIM_OPM_MODE(OnePulseMode));
|
---|
1996 |
|
---|
1997 | if(htim->State == HAL_TIM_STATE_RESET)
|
---|
1998 | {
|
---|
1999 | /* Allocate lock resource and initialize it */
|
---|
2000 | htim->Lock = HAL_UNLOCKED;
|
---|
2001 | /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
---|
2002 | HAL_TIM_OnePulse_MspInit(htim);
|
---|
2003 | }
|
---|
2004 |
|
---|
2005 | /* Set the TIM state */
|
---|
2006 | htim->State= HAL_TIM_STATE_BUSY;
|
---|
2007 |
|
---|
2008 | /* Configure the Time base in the One Pulse Mode */
|
---|
2009 | TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
---|
2010 |
|
---|
2011 | /* Reset the OPM Bit */
|
---|
2012 | htim->Instance->CR1 &= ~TIM_CR1_OPM;
|
---|
2013 |
|
---|
2014 | /* Configure the OPM Mode */
|
---|
2015 | htim->Instance->CR1 |= OnePulseMode;
|
---|
2016 |
|
---|
2017 | /* Initialize the TIM state*/
|
---|
2018 | htim->State= HAL_TIM_STATE_READY;
|
---|
2019 |
|
---|
2020 | return HAL_OK;
|
---|
2021 | }
|
---|
2022 |
|
---|
2023 | /**
|
---|
2024 | * @brief DeInitializes the TIM One Pulse
|
---|
2025 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2026 | * the configuration information for TIM module.
|
---|
2027 | * @retval HAL status
|
---|
2028 | */
|
---|
2029 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
|
---|
2030 | {
|
---|
2031 | /* Check the parameters */
|
---|
2032 | assert_param(IS_TIM_INSTANCE(htim->Instance));
|
---|
2033 |
|
---|
2034 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
2035 |
|
---|
2036 | /* Disable the TIM Peripheral Clock */
|
---|
2037 | __HAL_TIM_DISABLE(htim);
|
---|
2038 |
|
---|
2039 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
|
---|
2040 | HAL_TIM_OnePulse_MspDeInit(htim);
|
---|
2041 |
|
---|
2042 | /* Change TIM state */
|
---|
2043 | htim->State = HAL_TIM_STATE_RESET;
|
---|
2044 |
|
---|
2045 | /* Release Lock */
|
---|
2046 | __HAL_UNLOCK(htim);
|
---|
2047 |
|
---|
2048 | return HAL_OK;
|
---|
2049 | }
|
---|
2050 |
|
---|
2051 | /**
|
---|
2052 | * @brief Initializes the TIM One Pulse MSP.
|
---|
2053 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2054 | * the configuration information for TIM module.
|
---|
2055 | * @retval None
|
---|
2056 | */
|
---|
2057 | __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
|
---|
2058 | {
|
---|
2059 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
2060 | the HAL_TIM_OnePulse_MspInit could be implemented in the user file
|
---|
2061 | */
|
---|
2062 | }
|
---|
2063 |
|
---|
2064 | /**
|
---|
2065 | * @brief DeInitializes TIM One Pulse MSP.
|
---|
2066 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2067 | * the configuration information for TIM module.
|
---|
2068 | * @retval None
|
---|
2069 | */
|
---|
2070 | __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
|
---|
2071 | {
|
---|
2072 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
2073 | the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
|
---|
2074 | */
|
---|
2075 | }
|
---|
2076 |
|
---|
2077 | /**
|
---|
2078 | * @brief Starts the TIM One Pulse signal generation.
|
---|
2079 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2080 | * the configuration information for TIM module.
|
---|
2081 | * @param OutputChannel : TIM Channels to be enabled.
|
---|
2082 | * This parameter can be one of the following values:
|
---|
2083 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
2084 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
2085 | * @retval HAL status
|
---|
2086 | */
|
---|
2087 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
---|
2088 | {
|
---|
2089 | /* Enable the Capture compare and the Input Capture channels
|
---|
2090 | (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
|
---|
2091 | if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
|
---|
2092 | if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
|
---|
2093 | in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
|
---|
2094 |
|
---|
2095 | No need to enable the counter, it's enabled automatically by hardware
|
---|
2096 | (the counter starts in response to a stimulus and generate a pulse */
|
---|
2097 |
|
---|
2098 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
---|
2099 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
---|
2100 |
|
---|
2101 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
|
---|
2102 | {
|
---|
2103 | /* Enable the main output */
|
---|
2104 | __HAL_TIM_MOE_ENABLE(htim);
|
---|
2105 | }
|
---|
2106 |
|
---|
2107 | /* Return function status */
|
---|
2108 | return HAL_OK;
|
---|
2109 | }
|
---|
2110 |
|
---|
2111 | /**
|
---|
2112 | * @brief Stops the TIM One Pulse signal generation.
|
---|
2113 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2114 | * the configuration information for TIM module.
|
---|
2115 | * @param OutputChannel : TIM Channels to be disable.
|
---|
2116 | * This parameter can be one of the following values:
|
---|
2117 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
2118 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
2119 | * @retval HAL status
|
---|
2120 | */
|
---|
2121 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
---|
2122 | {
|
---|
2123 | /* Disable the Capture compare and the Input Capture channels
|
---|
2124 | (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
|
---|
2125 | if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
|
---|
2126 | if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
|
---|
2127 | in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
|
---|
2128 |
|
---|
2129 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
---|
2130 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
|
---|
2131 |
|
---|
2132 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
|
---|
2133 | {
|
---|
2134 | /* Disable the Main Output */
|
---|
2135 | __HAL_TIM_MOE_DISABLE(htim);
|
---|
2136 | }
|
---|
2137 |
|
---|
2138 | /* Disable the Peripheral */
|
---|
2139 | __HAL_TIM_DISABLE(htim);
|
---|
2140 |
|
---|
2141 | /* Return function status */
|
---|
2142 | return HAL_OK;
|
---|
2143 | }
|
---|
2144 |
|
---|
2145 | /**
|
---|
2146 | * @brief Starts the TIM One Pulse signal generation in interrupt mode.
|
---|
2147 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2148 | * the configuration information for TIM module.
|
---|
2149 | * @param OutputChannel : TIM Channels to be enabled.
|
---|
2150 | * This parameter can be one of the following values:
|
---|
2151 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
2152 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
2153 | * @retval HAL status
|
---|
2154 | */
|
---|
2155 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
---|
2156 | {
|
---|
2157 | /* Enable the Capture compare and the Input Capture channels
|
---|
2158 | (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
|
---|
2159 | if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
|
---|
2160 | if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
|
---|
2161 | in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
|
---|
2162 |
|
---|
2163 | No need to enable the counter, it's enabled automatically by hardware
|
---|
2164 | (the counter starts in response to a stimulus and generate a pulse */
|
---|
2165 |
|
---|
2166 | /* Enable the TIM Capture/Compare 1 interrupt */
|
---|
2167 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
---|
2168 |
|
---|
2169 | /* Enable the TIM Capture/Compare 2 interrupt */
|
---|
2170 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
---|
2171 |
|
---|
2172 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
---|
2173 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
---|
2174 |
|
---|
2175 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
|
---|
2176 | {
|
---|
2177 | /* Enable the main output */
|
---|
2178 | __HAL_TIM_MOE_ENABLE(htim);
|
---|
2179 | }
|
---|
2180 |
|
---|
2181 | /* Return function status */
|
---|
2182 | return HAL_OK;
|
---|
2183 | }
|
---|
2184 |
|
---|
2185 | /**
|
---|
2186 | * @brief Stops the TIM One Pulse signal generation in interrupt mode.
|
---|
2187 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2188 | * the configuration information for TIM module.
|
---|
2189 | * @param OutputChannel : TIM Channels to be enabled.
|
---|
2190 | * This parameter can be one of the following values:
|
---|
2191 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
2192 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
2193 | * @retval HAL status
|
---|
2194 | */
|
---|
2195 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
---|
2196 | {
|
---|
2197 | /* Disable the TIM Capture/Compare 1 interrupt */
|
---|
2198 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
---|
2199 |
|
---|
2200 | /* Disable the TIM Capture/Compare 2 interrupt */
|
---|
2201 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
---|
2202 |
|
---|
2203 | /* Disable the Capture compare and the Input Capture channels
|
---|
2204 | (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
|
---|
2205 | if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
|
---|
2206 | if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
|
---|
2207 | in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
|
---|
2208 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
---|
2209 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
|
---|
2210 |
|
---|
2211 | if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
|
---|
2212 | {
|
---|
2213 | /* Disable the Main Output */
|
---|
2214 | __HAL_TIM_MOE_DISABLE(htim);
|
---|
2215 | }
|
---|
2216 |
|
---|
2217 | /* Disable the Peripheral */
|
---|
2218 | __HAL_TIM_DISABLE(htim);
|
---|
2219 |
|
---|
2220 | /* Return function status */
|
---|
2221 | return HAL_OK;
|
---|
2222 | }
|
---|
2223 | /**
|
---|
2224 | * @}
|
---|
2225 | */
|
---|
2226 |
|
---|
2227 | /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
|
---|
2228 | * @brief Time Encoder functions
|
---|
2229 | *
|
---|
2230 | @verbatim
|
---|
2231 | ==============================================================================
|
---|
2232 | ##### Time Encoder functions #####
|
---|
2233 | ==============================================================================
|
---|
2234 | [..]
|
---|
2235 | This section provides functions allowing to:
|
---|
2236 | (+) Initialize and configure the TIM Encoder.
|
---|
2237 | (+) De-initialize the TIM Encoder.
|
---|
2238 | (+) Start the Time Encoder.
|
---|
2239 | (+) Stop the Time Encoder.
|
---|
2240 | (+) Start the Time Encoder and enable interrupt.
|
---|
2241 | (+) Stop the Time Encoder and disable interrupt.
|
---|
2242 | (+) Start the Time Encoder and enable DMA transfer.
|
---|
2243 | (+) Stop the Time Encoder and disable DMA transfer.
|
---|
2244 |
|
---|
2245 | @endverbatim
|
---|
2246 | * @{
|
---|
2247 | */
|
---|
2248 | /**
|
---|
2249 | * @brief Initializes the TIM Encoder Interface and create the associated handle.
|
---|
2250 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2251 | * the configuration information for TIM module.
|
---|
2252 | * @param sConfig: TIM Encoder Interface configuration structure
|
---|
2253 | * @retval HAL status
|
---|
2254 | */
|
---|
2255 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
|
---|
2256 | {
|
---|
2257 | uint32_t tmpsmcr = 0;
|
---|
2258 | uint32_t tmpccmr1 = 0;
|
---|
2259 | uint32_t tmpccer = 0;
|
---|
2260 |
|
---|
2261 | /* Check the TIM handle allocation */
|
---|
2262 | if(htim == NULL)
|
---|
2263 | {
|
---|
2264 | return HAL_ERROR;
|
---|
2265 | }
|
---|
2266 |
|
---|
2267 | /* Check the parameters */
|
---|
2268 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
2269 | assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
|
---|
2270 | assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
|
---|
2271 | assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
|
---|
2272 | assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
|
---|
2273 | assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
|
---|
2274 | assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
|
---|
2275 | assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
|
---|
2276 | assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
|
---|
2277 | assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
|
---|
2278 |
|
---|
2279 | if(htim->State == HAL_TIM_STATE_RESET)
|
---|
2280 | {
|
---|
2281 | /* Allocate lock resource and initialize it */
|
---|
2282 | htim->Lock = HAL_UNLOCKED;
|
---|
2283 | /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
---|
2284 | HAL_TIM_Encoder_MspInit(htim);
|
---|
2285 | }
|
---|
2286 |
|
---|
2287 | /* Set the TIM state */
|
---|
2288 | htim->State= HAL_TIM_STATE_BUSY;
|
---|
2289 |
|
---|
2290 | /* Reset the SMS bits */
|
---|
2291 | htim->Instance->SMCR &= ~TIM_SMCR_SMS;
|
---|
2292 |
|
---|
2293 | /* Configure the Time base in the Encoder Mode */
|
---|
2294 | TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
---|
2295 |
|
---|
2296 | /* Get the TIMx SMCR register value */
|
---|
2297 | tmpsmcr = htim->Instance->SMCR;
|
---|
2298 |
|
---|
2299 | /* Get the TIMx CCMR1 register value */
|
---|
2300 | tmpccmr1 = htim->Instance->CCMR1;
|
---|
2301 |
|
---|
2302 | /* Get the TIMx CCER register value */
|
---|
2303 | tmpccer = htim->Instance->CCER;
|
---|
2304 |
|
---|
2305 | /* Set the encoder Mode */
|
---|
2306 | tmpsmcr |= sConfig->EncoderMode;
|
---|
2307 |
|
---|
2308 | /* Select the Capture Compare 1 and the Capture Compare 2 as input */
|
---|
2309 | tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
|
---|
2310 | tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
|
---|
2311 |
|
---|
2312 | /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
|
---|
2313 | tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
|
---|
2314 | tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
|
---|
2315 | tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
|
---|
2316 | tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
|
---|
2317 |
|
---|
2318 | /* Set the TI1 and the TI2 Polarities */
|
---|
2319 | tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
|
---|
2320 | tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
|
---|
2321 | tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
|
---|
2322 |
|
---|
2323 | /* Write to TIMx SMCR */
|
---|
2324 | htim->Instance->SMCR = tmpsmcr;
|
---|
2325 |
|
---|
2326 | /* Write to TIMx CCMR1 */
|
---|
2327 | htim->Instance->CCMR1 = tmpccmr1;
|
---|
2328 |
|
---|
2329 | /* Write to TIMx CCER */
|
---|
2330 | htim->Instance->CCER = tmpccer;
|
---|
2331 |
|
---|
2332 | /* Initialize the TIM state*/
|
---|
2333 | htim->State= HAL_TIM_STATE_READY;
|
---|
2334 |
|
---|
2335 | return HAL_OK;
|
---|
2336 | }
|
---|
2337 |
|
---|
2338 | /**
|
---|
2339 | * @brief DeInitializes the TIM Encoder interface
|
---|
2340 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2341 | * the configuration information for TIM module.
|
---|
2342 | * @retval HAL status
|
---|
2343 | */
|
---|
2344 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
|
---|
2345 | {
|
---|
2346 | /* Check the parameters */
|
---|
2347 | assert_param(IS_TIM_INSTANCE(htim->Instance));
|
---|
2348 |
|
---|
2349 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
2350 |
|
---|
2351 | /* Disable the TIM Peripheral Clock */
|
---|
2352 | __HAL_TIM_DISABLE(htim);
|
---|
2353 |
|
---|
2354 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
|
---|
2355 | HAL_TIM_Encoder_MspDeInit(htim);
|
---|
2356 |
|
---|
2357 | /* Change TIM state */
|
---|
2358 | htim->State = HAL_TIM_STATE_RESET;
|
---|
2359 |
|
---|
2360 | /* Release Lock */
|
---|
2361 | __HAL_UNLOCK(htim);
|
---|
2362 |
|
---|
2363 | return HAL_OK;
|
---|
2364 | }
|
---|
2365 |
|
---|
2366 | /**
|
---|
2367 | * @brief Initializes the TIM Encoder Interface MSP.
|
---|
2368 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2369 | * the configuration information for TIM module.
|
---|
2370 | * @retval None
|
---|
2371 | */
|
---|
2372 | __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
|
---|
2373 | {
|
---|
2374 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
2375 | the HAL_TIM_Encoder_MspInit could be implemented in the user file
|
---|
2376 | */
|
---|
2377 | }
|
---|
2378 |
|
---|
2379 | /**
|
---|
2380 | * @brief DeInitializes TIM Encoder Interface MSP.
|
---|
2381 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2382 | * the configuration information for TIM module.
|
---|
2383 | * @retval None
|
---|
2384 | */
|
---|
2385 | __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
|
---|
2386 | {
|
---|
2387 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
2388 | the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
|
---|
2389 | */
|
---|
2390 | }
|
---|
2391 |
|
---|
2392 | /**
|
---|
2393 | * @brief Starts the TIM Encoder Interface.
|
---|
2394 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2395 | * the configuration information for TIM module.
|
---|
2396 | * @param Channel: TIM Channels to be enabled.
|
---|
2397 | * This parameter can be one of the following values:
|
---|
2398 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
2399 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
2400 | * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
|
---|
2401 | * @retval HAL status
|
---|
2402 | */
|
---|
2403 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
2404 | {
|
---|
2405 | /* Check the parameters */
|
---|
2406 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
2407 |
|
---|
2408 | /* Enable the encoder interface channels */
|
---|
2409 | switch (Channel)
|
---|
2410 | {
|
---|
2411 | case TIM_CHANNEL_1:
|
---|
2412 | {
|
---|
2413 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
---|
2414 | break;
|
---|
2415 | }
|
---|
2416 | case TIM_CHANNEL_2:
|
---|
2417 | {
|
---|
2418 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
---|
2419 | break;
|
---|
2420 | }
|
---|
2421 | default :
|
---|
2422 | {
|
---|
2423 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
---|
2424 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
---|
2425 | break;
|
---|
2426 | }
|
---|
2427 | }
|
---|
2428 | /* Enable the Peripheral */
|
---|
2429 | __HAL_TIM_ENABLE(htim);
|
---|
2430 |
|
---|
2431 | /* Return function status */
|
---|
2432 | return HAL_OK;
|
---|
2433 | }
|
---|
2434 |
|
---|
2435 | /**
|
---|
2436 | * @brief Stops the TIM Encoder Interface.
|
---|
2437 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2438 | * the configuration information for TIM module.
|
---|
2439 | * @param Channel: TIM Channels to be disabled.
|
---|
2440 | * This parameter can be one of the following values:
|
---|
2441 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
2442 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
2443 | * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
|
---|
2444 | * @retval HAL status
|
---|
2445 | */
|
---|
2446 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
2447 | {
|
---|
2448 | /* Check the parameters */
|
---|
2449 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
2450 |
|
---|
2451 | /* Disable the Input Capture channels 1 and 2
|
---|
2452 | (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
|
---|
2453 | switch (Channel)
|
---|
2454 | {
|
---|
2455 | case TIM_CHANNEL_1:
|
---|
2456 | {
|
---|
2457 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
---|
2458 | break;
|
---|
2459 | }
|
---|
2460 | case TIM_CHANNEL_2:
|
---|
2461 | {
|
---|
2462 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
|
---|
2463 | break;
|
---|
2464 | }
|
---|
2465 | default :
|
---|
2466 | {
|
---|
2467 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
---|
2468 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
|
---|
2469 | break;
|
---|
2470 | }
|
---|
2471 | }
|
---|
2472 | /* Disable the Peripheral */
|
---|
2473 | __HAL_TIM_DISABLE(htim);
|
---|
2474 |
|
---|
2475 | /* Return function status */
|
---|
2476 | return HAL_OK;
|
---|
2477 | }
|
---|
2478 |
|
---|
2479 | /**
|
---|
2480 | * @brief Starts the TIM Encoder Interface in interrupt mode.
|
---|
2481 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2482 | * the configuration information for TIM module.
|
---|
2483 | * @param Channel: TIM Channels to be enabled.
|
---|
2484 | * This parameter can be one of the following values:
|
---|
2485 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
2486 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
2487 | * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
|
---|
2488 | * @retval HAL status
|
---|
2489 | */
|
---|
2490 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
2491 | {
|
---|
2492 | /* Check the parameters */
|
---|
2493 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
2494 |
|
---|
2495 | /* Enable the encoder interface channels */
|
---|
2496 | /* Enable the capture compare Interrupts 1 and/or 2 */
|
---|
2497 | switch (Channel)
|
---|
2498 | {
|
---|
2499 | case TIM_CHANNEL_1:
|
---|
2500 | {
|
---|
2501 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
---|
2502 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
---|
2503 | break;
|
---|
2504 | }
|
---|
2505 | case TIM_CHANNEL_2:
|
---|
2506 | {
|
---|
2507 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
---|
2508 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
---|
2509 | break;
|
---|
2510 | }
|
---|
2511 | default :
|
---|
2512 | {
|
---|
2513 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
---|
2514 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
---|
2515 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
---|
2516 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
---|
2517 | break;
|
---|
2518 | }
|
---|
2519 | }
|
---|
2520 |
|
---|
2521 | /* Enable the Peripheral */
|
---|
2522 | __HAL_TIM_ENABLE(htim);
|
---|
2523 |
|
---|
2524 | /* Return function status */
|
---|
2525 | return HAL_OK;
|
---|
2526 | }
|
---|
2527 |
|
---|
2528 | /**
|
---|
2529 | * @brief Stops the TIM Encoder Interface in interrupt mode.
|
---|
2530 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2531 | * the configuration information for TIM module.
|
---|
2532 | * @param Channel: TIM Channels to be disabled.
|
---|
2533 | * This parameter can be one of the following values:
|
---|
2534 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
2535 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
2536 | * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
|
---|
2537 | * @retval HAL status
|
---|
2538 | */
|
---|
2539 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
2540 | {
|
---|
2541 | /* Check the parameters */
|
---|
2542 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
2543 |
|
---|
2544 | /* Disable the Input Capture channels 1 and 2
|
---|
2545 | (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
|
---|
2546 | if(Channel == TIM_CHANNEL_1)
|
---|
2547 | {
|
---|
2548 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
---|
2549 |
|
---|
2550 | /* Disable the capture compare Interrupts 1 */
|
---|
2551 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
---|
2552 | }
|
---|
2553 | else if(Channel == TIM_CHANNEL_2)
|
---|
2554 | {
|
---|
2555 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
|
---|
2556 |
|
---|
2557 | /* Disable the capture compare Interrupts 2 */
|
---|
2558 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
---|
2559 | }
|
---|
2560 | else
|
---|
2561 | {
|
---|
2562 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
---|
2563 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
|
---|
2564 |
|
---|
2565 | /* Disable the capture compare Interrupts 1 and 2 */
|
---|
2566 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
---|
2567 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
---|
2568 | }
|
---|
2569 |
|
---|
2570 | /* Disable the Peripheral */
|
---|
2571 | __HAL_TIM_DISABLE(htim);
|
---|
2572 |
|
---|
2573 | /* Change the htim state */
|
---|
2574 | htim->State = HAL_TIM_STATE_READY;
|
---|
2575 |
|
---|
2576 | /* Return function status */
|
---|
2577 | return HAL_OK;
|
---|
2578 | }
|
---|
2579 |
|
---|
2580 | /**
|
---|
2581 | * @brief Starts the TIM Encoder Interface in DMA mode.
|
---|
2582 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2583 | * the configuration information for TIM module.
|
---|
2584 | * @param Channel: TIM Channels to be enabled.
|
---|
2585 | * This parameter can be one of the following values:
|
---|
2586 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
2587 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
2588 | * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
|
---|
2589 | * @param pData1: The destination Buffer address for IC1.
|
---|
2590 | * @param pData2: The destination Buffer address for IC2.
|
---|
2591 | * @param Length: The length of data to be transferred from TIM peripheral to memory.
|
---|
2592 | * @retval HAL status
|
---|
2593 | */
|
---|
2594 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
|
---|
2595 | {
|
---|
2596 | /* Check the parameters */
|
---|
2597 | assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
|
---|
2598 |
|
---|
2599 | if((htim->State == HAL_TIM_STATE_BUSY))
|
---|
2600 | {
|
---|
2601 | return HAL_BUSY;
|
---|
2602 | }
|
---|
2603 | else if((htim->State == HAL_TIM_STATE_READY))
|
---|
2604 | {
|
---|
2605 | if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
|
---|
2606 | {
|
---|
2607 | return HAL_ERROR;
|
---|
2608 | }
|
---|
2609 | else
|
---|
2610 | {
|
---|
2611 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
2612 | }
|
---|
2613 | }
|
---|
2614 |
|
---|
2615 | switch (Channel)
|
---|
2616 | {
|
---|
2617 | case TIM_CHANNEL_1:
|
---|
2618 | {
|
---|
2619 | /* Set the DMA Period elapsed callback */
|
---|
2620 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
|
---|
2621 |
|
---|
2622 | /* Set the DMA error callback */
|
---|
2623 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
---|
2624 |
|
---|
2625 | /* Enable the DMA Stream */
|
---|
2626 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
|
---|
2627 |
|
---|
2628 | /* Enable the TIM Input Capture DMA request */
|
---|
2629 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
|
---|
2630 |
|
---|
2631 | /* Enable the Peripheral */
|
---|
2632 | __HAL_TIM_ENABLE(htim);
|
---|
2633 |
|
---|
2634 | /* Enable the Capture compare channel */
|
---|
2635 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
---|
2636 | }
|
---|
2637 | break;
|
---|
2638 |
|
---|
2639 | case TIM_CHANNEL_2:
|
---|
2640 | {
|
---|
2641 | /* Set the DMA Period elapsed callback */
|
---|
2642 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
|
---|
2643 |
|
---|
2644 | /* Set the DMA error callback */
|
---|
2645 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
|
---|
2646 | /* Enable the DMA Stream */
|
---|
2647 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
|
---|
2648 |
|
---|
2649 | /* Enable the TIM Input Capture DMA request */
|
---|
2650 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
|
---|
2651 |
|
---|
2652 | /* Enable the Peripheral */
|
---|
2653 | __HAL_TIM_ENABLE(htim);
|
---|
2654 |
|
---|
2655 | /* Enable the Capture compare channel */
|
---|
2656 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
---|
2657 | }
|
---|
2658 | break;
|
---|
2659 |
|
---|
2660 | case TIM_CHANNEL_ALL:
|
---|
2661 | {
|
---|
2662 | /* Set the DMA Period elapsed callback */
|
---|
2663 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
|
---|
2664 |
|
---|
2665 | /* Set the DMA error callback */
|
---|
2666 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
---|
2667 |
|
---|
2668 | /* Enable the DMA Stream */
|
---|
2669 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
|
---|
2670 |
|
---|
2671 | /* Set the DMA Period elapsed callback */
|
---|
2672 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
|
---|
2673 |
|
---|
2674 | /* Set the DMA error callback */
|
---|
2675 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
---|
2676 |
|
---|
2677 | /* Enable the DMA Stream */
|
---|
2678 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
|
---|
2679 |
|
---|
2680 | /* Enable the Peripheral */
|
---|
2681 | __HAL_TIM_ENABLE(htim);
|
---|
2682 |
|
---|
2683 | /* Enable the Capture compare channel */
|
---|
2684 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
---|
2685 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
---|
2686 |
|
---|
2687 | /* Enable the TIM Input Capture DMA request */
|
---|
2688 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
|
---|
2689 | /* Enable the TIM Input Capture DMA request */
|
---|
2690 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
|
---|
2691 | }
|
---|
2692 | break;
|
---|
2693 |
|
---|
2694 | default:
|
---|
2695 | break;
|
---|
2696 | }
|
---|
2697 | /* Return function status */
|
---|
2698 | return HAL_OK;
|
---|
2699 | }
|
---|
2700 |
|
---|
2701 | /**
|
---|
2702 | * @brief Stops the TIM Encoder Interface in DMA mode.
|
---|
2703 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2704 | * the configuration information for TIM module.
|
---|
2705 | * @param Channel: TIM Channels to be enabled.
|
---|
2706 | * This parameter can be one of the following values:
|
---|
2707 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
2708 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
2709 | * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
|
---|
2710 | * @retval HAL status
|
---|
2711 | */
|
---|
2712 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
2713 | {
|
---|
2714 | /* Check the parameters */
|
---|
2715 | assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
|
---|
2716 |
|
---|
2717 | /* Disable the Input Capture channels 1 and 2
|
---|
2718 | (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
|
---|
2719 | if(Channel == TIM_CHANNEL_1)
|
---|
2720 | {
|
---|
2721 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
---|
2722 |
|
---|
2723 | /* Disable the capture compare DMA Request 1 */
|
---|
2724 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
|
---|
2725 | }
|
---|
2726 | else if(Channel == TIM_CHANNEL_2)
|
---|
2727 | {
|
---|
2728 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
|
---|
2729 |
|
---|
2730 | /* Disable the capture compare DMA Request 2 */
|
---|
2731 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
|
---|
2732 | }
|
---|
2733 | else
|
---|
2734 | {
|
---|
2735 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
---|
2736 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
|
---|
2737 |
|
---|
2738 | /* Disable the capture compare DMA Request 1 and 2 */
|
---|
2739 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
|
---|
2740 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
|
---|
2741 | }
|
---|
2742 |
|
---|
2743 | /* Disable the Peripheral */
|
---|
2744 | __HAL_TIM_DISABLE(htim);
|
---|
2745 |
|
---|
2746 | /* Change the htim state */
|
---|
2747 | htim->State = HAL_TIM_STATE_READY;
|
---|
2748 |
|
---|
2749 | /* Return function status */
|
---|
2750 | return HAL_OK;
|
---|
2751 | }
|
---|
2752 | /**
|
---|
2753 | * @}
|
---|
2754 | */
|
---|
2755 |
|
---|
2756 | /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
|
---|
2757 | * @brief IRQ handler management
|
---|
2758 | *
|
---|
2759 | @verbatim
|
---|
2760 | ==============================================================================
|
---|
2761 | ##### IRQ handler management #####
|
---|
2762 | ==============================================================================
|
---|
2763 | [..]
|
---|
2764 | This section provides Timer IRQ handler function.
|
---|
2765 |
|
---|
2766 | @endverbatim
|
---|
2767 | * @{
|
---|
2768 | */
|
---|
2769 | /**
|
---|
2770 | * @brief This function handles TIM interrupts requests.
|
---|
2771 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2772 | * the configuration information for TIM module.
|
---|
2773 | * @retval None
|
---|
2774 | */
|
---|
2775 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
---|
2776 | {
|
---|
2777 | /* Capture compare 1 event */
|
---|
2778 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
|
---|
2779 | {
|
---|
2780 | if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
|
---|
2781 | {
|
---|
2782 | {
|
---|
2783 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
|
---|
2784 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
---|
2785 |
|
---|
2786 | /* Input capture event */
|
---|
2787 | if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
|
---|
2788 | {
|
---|
2789 | HAL_TIM_IC_CaptureCallback(htim);
|
---|
2790 | }
|
---|
2791 | /* Output compare event */
|
---|
2792 | else
|
---|
2793 | {
|
---|
2794 | HAL_TIM_OC_DelayElapsedCallback(htim);
|
---|
2795 | HAL_TIM_PWM_PulseFinishedCallback(htim);
|
---|
2796 | }
|
---|
2797 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
---|
2798 | }
|
---|
2799 | }
|
---|
2800 | }
|
---|
2801 | /* Capture compare 2 event */
|
---|
2802 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
|
---|
2803 | {
|
---|
2804 | if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
|
---|
2805 | {
|
---|
2806 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
|
---|
2807 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
---|
2808 | /* Input capture event */
|
---|
2809 | if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
|
---|
2810 | {
|
---|
2811 | HAL_TIM_IC_CaptureCallback(htim);
|
---|
2812 | }
|
---|
2813 | /* Output compare event */
|
---|
2814 | else
|
---|
2815 | {
|
---|
2816 | HAL_TIM_OC_DelayElapsedCallback(htim);
|
---|
2817 | HAL_TIM_PWM_PulseFinishedCallback(htim);
|
---|
2818 | }
|
---|
2819 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
---|
2820 | }
|
---|
2821 | }
|
---|
2822 | /* Capture compare 3 event */
|
---|
2823 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
|
---|
2824 | {
|
---|
2825 | if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
|
---|
2826 | {
|
---|
2827 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
|
---|
2828 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
---|
2829 | /* Input capture event */
|
---|
2830 | if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
|
---|
2831 | {
|
---|
2832 | HAL_TIM_IC_CaptureCallback(htim);
|
---|
2833 | }
|
---|
2834 | /* Output compare event */
|
---|
2835 | else
|
---|
2836 | {
|
---|
2837 | HAL_TIM_OC_DelayElapsedCallback(htim);
|
---|
2838 | HAL_TIM_PWM_PulseFinishedCallback(htim);
|
---|
2839 | }
|
---|
2840 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
---|
2841 | }
|
---|
2842 | }
|
---|
2843 | /* Capture compare 4 event */
|
---|
2844 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
|
---|
2845 | {
|
---|
2846 | if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
|
---|
2847 | {
|
---|
2848 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
|
---|
2849 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
---|
2850 | /* Input capture event */
|
---|
2851 | if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
|
---|
2852 | {
|
---|
2853 | HAL_TIM_IC_CaptureCallback(htim);
|
---|
2854 | }
|
---|
2855 | /* Output compare event */
|
---|
2856 | else
|
---|
2857 | {
|
---|
2858 | HAL_TIM_OC_DelayElapsedCallback(htim);
|
---|
2859 | HAL_TIM_PWM_PulseFinishedCallback(htim);
|
---|
2860 | }
|
---|
2861 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
---|
2862 | }
|
---|
2863 | }
|
---|
2864 | /* TIM Update event */
|
---|
2865 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
|
---|
2866 | {
|
---|
2867 | if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
|
---|
2868 | {
|
---|
2869 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
|
---|
2870 | HAL_TIM_PeriodElapsedCallback(htim);
|
---|
2871 | }
|
---|
2872 | }
|
---|
2873 | /* TIM Break input event */
|
---|
2874 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
|
---|
2875 | {
|
---|
2876 | if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
|
---|
2877 | {
|
---|
2878 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
|
---|
2879 | HAL_TIMEx_BreakCallback(htim);
|
---|
2880 | }
|
---|
2881 | }
|
---|
2882 | /* TIM Trigger detection event */
|
---|
2883 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
|
---|
2884 | {
|
---|
2885 | if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
|
---|
2886 | {
|
---|
2887 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
|
---|
2888 | HAL_TIM_TriggerCallback(htim);
|
---|
2889 | }
|
---|
2890 | }
|
---|
2891 | /* TIM commutation event */
|
---|
2892 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
|
---|
2893 | {
|
---|
2894 | if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
|
---|
2895 | {
|
---|
2896 | __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
|
---|
2897 | HAL_TIMEx_CommutationCallback(htim);
|
---|
2898 | }
|
---|
2899 | }
|
---|
2900 | }
|
---|
2901 | /**
|
---|
2902 | * @}
|
---|
2903 | */
|
---|
2904 |
|
---|
2905 | /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
|
---|
2906 | * @brief Peripheral Control functions
|
---|
2907 | *
|
---|
2908 | @verbatim
|
---|
2909 | ==============================================================================
|
---|
2910 | ##### Peripheral Control functions #####
|
---|
2911 | ==============================================================================
|
---|
2912 | [..]
|
---|
2913 | This section provides functions allowing to:
|
---|
2914 | (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
|
---|
2915 | (+) Configure External Clock source.
|
---|
2916 | (+) Configure Complementary channels, break features and dead time.
|
---|
2917 | (+) Configure Master and the Slave synchronization.
|
---|
2918 | (+) Configure the DMA Burst Mode.
|
---|
2919 |
|
---|
2920 | @endverbatim
|
---|
2921 | * @{
|
---|
2922 | */
|
---|
2923 |
|
---|
2924 | /**
|
---|
2925 | * @brief Initializes the TIM Output Compare Channels according to the specified
|
---|
2926 | * parameters in the TIM_OC_InitTypeDef.
|
---|
2927 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
2928 | * the configuration information for TIM module.
|
---|
2929 | * @param sConfig: TIM Output Compare configuration structure
|
---|
2930 | * @param Channel: TIM Channels to be enabled.
|
---|
2931 | * This parameter can be one of the following values:
|
---|
2932 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
2933 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
2934 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
2935 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
2936 | * @retval HAL status
|
---|
2937 | */
|
---|
2938 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
|
---|
2939 | {
|
---|
2940 | /* Check the parameters */
|
---|
2941 | assert_param(IS_TIM_CHANNELS(Channel));
|
---|
2942 | assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
|
---|
2943 | assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
---|
2944 | assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
|
---|
2945 | assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
|
---|
2946 | assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
|
---|
2947 |
|
---|
2948 | /* Check input state */
|
---|
2949 | __HAL_LOCK(htim);
|
---|
2950 |
|
---|
2951 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
2952 |
|
---|
2953 | switch (Channel)
|
---|
2954 | {
|
---|
2955 | case TIM_CHANNEL_1:
|
---|
2956 | {
|
---|
2957 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
---|
2958 | /* Configure the TIM Channel 1 in Output Compare */
|
---|
2959 | TIM_OC1_SetConfig(htim->Instance, sConfig);
|
---|
2960 | }
|
---|
2961 | break;
|
---|
2962 |
|
---|
2963 | case TIM_CHANNEL_2:
|
---|
2964 | {
|
---|
2965 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
2966 | /* Configure the TIM Channel 2 in Output Compare */
|
---|
2967 | TIM_OC2_SetConfig(htim->Instance, sConfig);
|
---|
2968 | }
|
---|
2969 | break;
|
---|
2970 |
|
---|
2971 | case TIM_CHANNEL_3:
|
---|
2972 | {
|
---|
2973 | assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
---|
2974 | /* Configure the TIM Channel 3 in Output Compare */
|
---|
2975 | TIM_OC3_SetConfig(htim->Instance, sConfig);
|
---|
2976 | }
|
---|
2977 | break;
|
---|
2978 |
|
---|
2979 | case TIM_CHANNEL_4:
|
---|
2980 | {
|
---|
2981 | assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
---|
2982 | /* Configure the TIM Channel 4 in Output Compare */
|
---|
2983 | TIM_OC4_SetConfig(htim->Instance, sConfig);
|
---|
2984 | }
|
---|
2985 | break;
|
---|
2986 |
|
---|
2987 | default:
|
---|
2988 | break;
|
---|
2989 | }
|
---|
2990 | htim->State = HAL_TIM_STATE_READY;
|
---|
2991 |
|
---|
2992 | __HAL_UNLOCK(htim);
|
---|
2993 |
|
---|
2994 | return HAL_OK;
|
---|
2995 | }
|
---|
2996 |
|
---|
2997 | /**
|
---|
2998 | * @brief Initializes the TIM Input Capture Channels according to the specified
|
---|
2999 | * parameters in the TIM_IC_InitTypeDef.
|
---|
3000 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
3001 | * the configuration information for TIM module.
|
---|
3002 | * @param sConfig: TIM Input Capture configuration structure
|
---|
3003 | * @param Channel: TIM Channels to be enabled.
|
---|
3004 | * This parameter can be one of the following values:
|
---|
3005 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
3006 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
3007 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
3008 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
3009 | * @retval HAL status
|
---|
3010 | */
|
---|
3011 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
|
---|
3012 | {
|
---|
3013 | /* Check the parameters */
|
---|
3014 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
---|
3015 | assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
|
---|
3016 | assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
|
---|
3017 | assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
|
---|
3018 | assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
|
---|
3019 |
|
---|
3020 | __HAL_LOCK(htim);
|
---|
3021 |
|
---|
3022 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
3023 |
|
---|
3024 | if (Channel == TIM_CHANNEL_1)
|
---|
3025 | {
|
---|
3026 | /* TI1 Configuration */
|
---|
3027 | TIM_TI1_SetConfig(htim->Instance,
|
---|
3028 | sConfig->ICPolarity,
|
---|
3029 | sConfig->ICSelection,
|
---|
3030 | sConfig->ICFilter);
|
---|
3031 |
|
---|
3032 | /* Reset the IC1PSC Bits */
|
---|
3033 | htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
|
---|
3034 |
|
---|
3035 | /* Set the IC1PSC value */
|
---|
3036 | htim->Instance->CCMR1 |= sConfig->ICPrescaler;
|
---|
3037 | }
|
---|
3038 | else if (Channel == TIM_CHANNEL_2)
|
---|
3039 | {
|
---|
3040 | /* TI2 Configuration */
|
---|
3041 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
3042 |
|
---|
3043 | TIM_TI2_SetConfig(htim->Instance,
|
---|
3044 | sConfig->ICPolarity,
|
---|
3045 | sConfig->ICSelection,
|
---|
3046 | sConfig->ICFilter);
|
---|
3047 |
|
---|
3048 | /* Reset the IC2PSC Bits */
|
---|
3049 | htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
|
---|
3050 |
|
---|
3051 | /* Set the IC2PSC value */
|
---|
3052 | htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
|
---|
3053 | }
|
---|
3054 | else if (Channel == TIM_CHANNEL_3)
|
---|
3055 | {
|
---|
3056 | /* TI3 Configuration */
|
---|
3057 | assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
---|
3058 |
|
---|
3059 | TIM_TI3_SetConfig(htim->Instance,
|
---|
3060 | sConfig->ICPolarity,
|
---|
3061 | sConfig->ICSelection,
|
---|
3062 | sConfig->ICFilter);
|
---|
3063 |
|
---|
3064 | /* Reset the IC3PSC Bits */
|
---|
3065 | htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
|
---|
3066 |
|
---|
3067 | /* Set the IC3PSC value */
|
---|
3068 | htim->Instance->CCMR2 |= sConfig->ICPrescaler;
|
---|
3069 | }
|
---|
3070 | else
|
---|
3071 | {
|
---|
3072 | /* TI4 Configuration */
|
---|
3073 | assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
---|
3074 |
|
---|
3075 | TIM_TI4_SetConfig(htim->Instance,
|
---|
3076 | sConfig->ICPolarity,
|
---|
3077 | sConfig->ICSelection,
|
---|
3078 | sConfig->ICFilter);
|
---|
3079 |
|
---|
3080 | /* Reset the IC4PSC Bits */
|
---|
3081 | htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
|
---|
3082 |
|
---|
3083 | /* Set the IC4PSC value */
|
---|
3084 | htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
|
---|
3085 | }
|
---|
3086 |
|
---|
3087 | htim->State = HAL_TIM_STATE_READY;
|
---|
3088 |
|
---|
3089 | __HAL_UNLOCK(htim);
|
---|
3090 |
|
---|
3091 | return HAL_OK;
|
---|
3092 | }
|
---|
3093 |
|
---|
3094 | /**
|
---|
3095 | * @brief Initializes the TIM PWM channels according to the specified
|
---|
3096 | * parameters in the TIM_OC_InitTypeDef.
|
---|
3097 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
3098 | * the configuration information for TIM module.
|
---|
3099 | * @param sConfig: TIM PWM configuration structure
|
---|
3100 | * @param Channel: TIM Channels to be enabled.
|
---|
3101 | * This parameter can be one of the following values:
|
---|
3102 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
3103 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
3104 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
3105 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
3106 | * @retval HAL status
|
---|
3107 | */
|
---|
3108 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
|
---|
3109 | {
|
---|
3110 | __HAL_LOCK(htim);
|
---|
3111 |
|
---|
3112 | /* Check the parameters */
|
---|
3113 | assert_param(IS_TIM_CHANNELS(Channel));
|
---|
3114 | assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
|
---|
3115 | assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
---|
3116 | assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
|
---|
3117 | assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
|
---|
3118 | assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
|
---|
3119 | assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
|
---|
3120 |
|
---|
3121 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
3122 |
|
---|
3123 | switch (Channel)
|
---|
3124 | {
|
---|
3125 | case TIM_CHANNEL_1:
|
---|
3126 | {
|
---|
3127 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
---|
3128 | /* Configure the Channel 1 in PWM mode */
|
---|
3129 | TIM_OC1_SetConfig(htim->Instance, sConfig);
|
---|
3130 |
|
---|
3131 | /* Set the Preload enable bit for channel1 */
|
---|
3132 | htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
|
---|
3133 |
|
---|
3134 | /* Configure the Output Fast mode */
|
---|
3135 | htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
|
---|
3136 | htim->Instance->CCMR1 |= sConfig->OCFastMode;
|
---|
3137 | }
|
---|
3138 | break;
|
---|
3139 |
|
---|
3140 | case TIM_CHANNEL_2:
|
---|
3141 | {
|
---|
3142 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
3143 | /* Configure the Channel 2 in PWM mode */
|
---|
3144 | TIM_OC2_SetConfig(htim->Instance, sConfig);
|
---|
3145 |
|
---|
3146 | /* Set the Preload enable bit for channel2 */
|
---|
3147 | htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
|
---|
3148 |
|
---|
3149 | /* Configure the Output Fast mode */
|
---|
3150 | htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
|
---|
3151 | htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
|
---|
3152 | }
|
---|
3153 | break;
|
---|
3154 |
|
---|
3155 | case TIM_CHANNEL_3:
|
---|
3156 | {
|
---|
3157 | assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
---|
3158 | /* Configure the Channel 3 in PWM mode */
|
---|
3159 | TIM_OC3_SetConfig(htim->Instance, sConfig);
|
---|
3160 |
|
---|
3161 | /* Set the Preload enable bit for channel3 */
|
---|
3162 | htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
|
---|
3163 |
|
---|
3164 | /* Configure the Output Fast mode */
|
---|
3165 | htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
|
---|
3166 | htim->Instance->CCMR2 |= sConfig->OCFastMode;
|
---|
3167 | }
|
---|
3168 | break;
|
---|
3169 |
|
---|
3170 | case TIM_CHANNEL_4:
|
---|
3171 | {
|
---|
3172 | assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
---|
3173 | /* Configure the Channel 4 in PWM mode */
|
---|
3174 | TIM_OC4_SetConfig(htim->Instance, sConfig);
|
---|
3175 |
|
---|
3176 | /* Set the Preload enable bit for channel4 */
|
---|
3177 | htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
|
---|
3178 |
|
---|
3179 | /* Configure the Output Fast mode */
|
---|
3180 | htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
|
---|
3181 | htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
|
---|
3182 | }
|
---|
3183 | break;
|
---|
3184 |
|
---|
3185 | default:
|
---|
3186 | break;
|
---|
3187 | }
|
---|
3188 |
|
---|
3189 | htim->State = HAL_TIM_STATE_READY;
|
---|
3190 |
|
---|
3191 | __HAL_UNLOCK(htim);
|
---|
3192 |
|
---|
3193 | return HAL_OK;
|
---|
3194 | }
|
---|
3195 |
|
---|
3196 | /**
|
---|
3197 | * @brief Initializes the TIM One Pulse Channels according to the specified
|
---|
3198 | * parameters in the TIM_OnePulse_InitTypeDef.
|
---|
3199 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
3200 | * the configuration information for TIM module.
|
---|
3201 | * @param sConfig: TIM One Pulse configuration structure
|
---|
3202 | * @param OutputChannel: TIM Channels to be enabled.
|
---|
3203 | * This parameter can be one of the following values:
|
---|
3204 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
3205 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
3206 | * @param InputChannel: TIM Channels to be enabled.
|
---|
3207 | * This parameter can be one of the following values:
|
---|
3208 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
3209 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
3210 | * @retval HAL status
|
---|
3211 | */
|
---|
3212 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
|
---|
3213 | {
|
---|
3214 | TIM_OC_InitTypeDef temp1;
|
---|
3215 |
|
---|
3216 | /* Check the parameters */
|
---|
3217 | assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
|
---|
3218 | assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
|
---|
3219 |
|
---|
3220 | if(OutputChannel != InputChannel)
|
---|
3221 | {
|
---|
3222 | __HAL_LOCK(htim);
|
---|
3223 |
|
---|
3224 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
3225 |
|
---|
3226 | /* Extract the Output compare configuration from sConfig structure */
|
---|
3227 | temp1.OCMode = sConfig->OCMode;
|
---|
3228 | temp1.Pulse = sConfig->Pulse;
|
---|
3229 | temp1.OCPolarity = sConfig->OCPolarity;
|
---|
3230 | temp1.OCNPolarity = sConfig->OCNPolarity;
|
---|
3231 | temp1.OCIdleState = sConfig->OCIdleState;
|
---|
3232 | temp1.OCNIdleState = sConfig->OCNIdleState;
|
---|
3233 |
|
---|
3234 | switch (OutputChannel)
|
---|
3235 | {
|
---|
3236 | case TIM_CHANNEL_1:
|
---|
3237 | {
|
---|
3238 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
---|
3239 |
|
---|
3240 | TIM_OC1_SetConfig(htim->Instance, &temp1);
|
---|
3241 | }
|
---|
3242 | break;
|
---|
3243 | case TIM_CHANNEL_2:
|
---|
3244 | {
|
---|
3245 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
3246 |
|
---|
3247 | TIM_OC2_SetConfig(htim->Instance, &temp1);
|
---|
3248 | }
|
---|
3249 | break;
|
---|
3250 | default:
|
---|
3251 | break;
|
---|
3252 | }
|
---|
3253 | switch (InputChannel)
|
---|
3254 | {
|
---|
3255 | case TIM_CHANNEL_1:
|
---|
3256 | {
|
---|
3257 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
---|
3258 |
|
---|
3259 | TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
|
---|
3260 | sConfig->ICSelection, sConfig->ICFilter);
|
---|
3261 |
|
---|
3262 | /* Reset the IC1PSC Bits */
|
---|
3263 | htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
|
---|
3264 |
|
---|
3265 | /* Select the Trigger source */
|
---|
3266 | htim->Instance->SMCR &= ~TIM_SMCR_TS;
|
---|
3267 | htim->Instance->SMCR |= TIM_TS_TI1FP1;
|
---|
3268 |
|
---|
3269 | /* Select the Slave Mode */
|
---|
3270 | htim->Instance->SMCR &= ~TIM_SMCR_SMS;
|
---|
3271 | htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
|
---|
3272 | }
|
---|
3273 | break;
|
---|
3274 | case TIM_CHANNEL_2:
|
---|
3275 | {
|
---|
3276 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
3277 |
|
---|
3278 | TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
|
---|
3279 | sConfig->ICSelection, sConfig->ICFilter);
|
---|
3280 |
|
---|
3281 | /* Reset the IC2PSC Bits */
|
---|
3282 | htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
|
---|
3283 |
|
---|
3284 | /* Select the Trigger source */
|
---|
3285 | htim->Instance->SMCR &= ~TIM_SMCR_TS;
|
---|
3286 | htim->Instance->SMCR |= TIM_TS_TI2FP2;
|
---|
3287 |
|
---|
3288 | /* Select the Slave Mode */
|
---|
3289 | htim->Instance->SMCR &= ~TIM_SMCR_SMS;
|
---|
3290 | htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
|
---|
3291 | }
|
---|
3292 | break;
|
---|
3293 |
|
---|
3294 | default:
|
---|
3295 | break;
|
---|
3296 | }
|
---|
3297 |
|
---|
3298 | htim->State = HAL_TIM_STATE_READY;
|
---|
3299 |
|
---|
3300 | __HAL_UNLOCK(htim);
|
---|
3301 |
|
---|
3302 | return HAL_OK;
|
---|
3303 | }
|
---|
3304 | else
|
---|
3305 | {
|
---|
3306 | return HAL_ERROR;
|
---|
3307 | }
|
---|
3308 | }
|
---|
3309 |
|
---|
3310 | /**
|
---|
3311 | * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
|
---|
3312 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
3313 | * the configuration information for TIM module.
|
---|
3314 | * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
|
---|
3315 | * This parameters can be on of the following values:
|
---|
3316 | * @arg TIM_DMABASE_CR1
|
---|
3317 | * @arg TIM_DMABASE_CR2
|
---|
3318 | * @arg TIM_DMABASE_SMCR
|
---|
3319 | * @arg TIM_DMABASE_DIER
|
---|
3320 | * @arg TIM_DMABASE_SR
|
---|
3321 | * @arg TIM_DMABASE_EGR
|
---|
3322 | * @arg TIM_DMABASE_CCMR1
|
---|
3323 | * @arg TIM_DMABASE_CCMR2
|
---|
3324 | * @arg TIM_DMABASE_CCER
|
---|
3325 | * @arg TIM_DMABASE_CNT
|
---|
3326 | * @arg TIM_DMABASE_PSC
|
---|
3327 | * @arg TIM_DMABASE_ARR
|
---|
3328 | * @arg TIM_DMABASE_RCR
|
---|
3329 | * @arg TIM_DMABASE_CCR1
|
---|
3330 | * @arg TIM_DMABASE_CCR2
|
---|
3331 | * @arg TIM_DMABASE_CCR3
|
---|
3332 | * @arg TIM_DMABASE_CCR4
|
---|
3333 | * @arg TIM_DMABASE_BDTR
|
---|
3334 | * @arg TIM_DMABASE_DCR
|
---|
3335 | * @param BurstRequestSrc: TIM DMA Request sources.
|
---|
3336 | * This parameters can be on of the following values:
|
---|
3337 | * @arg TIM_DMA_UPDATE: TIM update Interrupt source
|
---|
3338 | * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
|
---|
3339 | * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
|
---|
3340 | * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
|
---|
3341 | * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
|
---|
3342 | * @arg TIM_DMA_COM: TIM Commutation DMA source
|
---|
3343 | * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
|
---|
3344 | * @param BurstBuffer: The Buffer address.
|
---|
3345 | * @param BurstLength: DMA Burst length. This parameter can be one value
|
---|
3346 | * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
|
---|
3347 | * @retval HAL status
|
---|
3348 | */
|
---|
3349 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
|
---|
3350 | uint32_t* BurstBuffer, uint32_t BurstLength)
|
---|
3351 | {
|
---|
3352 | /* Check the parameters */
|
---|
3353 | assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
|
---|
3354 | assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
|
---|
3355 | assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
|
---|
3356 | assert_param(IS_TIM_DMA_LENGTH(BurstLength));
|
---|
3357 |
|
---|
3358 | if((htim->State == HAL_TIM_STATE_BUSY))
|
---|
3359 | {
|
---|
3360 | return HAL_BUSY;
|
---|
3361 | }
|
---|
3362 | else if((htim->State == HAL_TIM_STATE_READY))
|
---|
3363 | {
|
---|
3364 | if((BurstBuffer == 0 ) && (BurstLength > 0))
|
---|
3365 | {
|
---|
3366 | return HAL_ERROR;
|
---|
3367 | }
|
---|
3368 | else
|
---|
3369 | {
|
---|
3370 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
3371 | }
|
---|
3372 | }
|
---|
3373 | switch(BurstRequestSrc)
|
---|
3374 | {
|
---|
3375 | case TIM_DMA_UPDATE:
|
---|
3376 | {
|
---|
3377 | /* Set the DMA Period elapsed callback */
|
---|
3378 | htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
|
---|
3379 |
|
---|
3380 | /* Set the DMA error callback */
|
---|
3381 | htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
|
---|
3382 |
|
---|
3383 | /* Enable the DMA Stream */
|
---|
3384 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
|
---|
3385 | }
|
---|
3386 | break;
|
---|
3387 | case TIM_DMA_CC1:
|
---|
3388 | {
|
---|
3389 | /* Set the DMA Period elapsed callback */
|
---|
3390 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
---|
3391 |
|
---|
3392 | /* Set the DMA error callback */
|
---|
3393 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
---|
3394 |
|
---|
3395 | /* Enable the DMA Stream */
|
---|
3396 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
|
---|
3397 | }
|
---|
3398 | break;
|
---|
3399 | case TIM_DMA_CC2:
|
---|
3400 | {
|
---|
3401 | /* Set the DMA Period elapsed callback */
|
---|
3402 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
---|
3403 |
|
---|
3404 | /* Set the DMA error callback */
|
---|
3405 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
---|
3406 |
|
---|
3407 | /* Enable the DMA Stream */
|
---|
3408 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
|
---|
3409 | }
|
---|
3410 | break;
|
---|
3411 | case TIM_DMA_CC3:
|
---|
3412 | {
|
---|
3413 | /* Set the DMA Period elapsed callback */
|
---|
3414 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
---|
3415 |
|
---|
3416 | /* Set the DMA error callback */
|
---|
3417 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
---|
3418 |
|
---|
3419 | /* Enable the DMA Stream */
|
---|
3420 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
|
---|
3421 | }
|
---|
3422 | break;
|
---|
3423 | case TIM_DMA_CC4:
|
---|
3424 | {
|
---|
3425 | /* Set the DMA Period elapsed callback */
|
---|
3426 | htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
---|
3427 |
|
---|
3428 | /* Set the DMA error callback */
|
---|
3429 | htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
|
---|
3430 |
|
---|
3431 | /* Enable the DMA Stream */
|
---|
3432 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
|
---|
3433 | }
|
---|
3434 | break;
|
---|
3435 | case TIM_DMA_COM:
|
---|
3436 | {
|
---|
3437 | /* Set the DMA Period elapsed callback */
|
---|
3438 | htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
|
---|
3439 |
|
---|
3440 | /* Set the DMA error callback */
|
---|
3441 | htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
|
---|
3442 |
|
---|
3443 | /* Enable the DMA Stream */
|
---|
3444 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
|
---|
3445 | }
|
---|
3446 | break;
|
---|
3447 | case TIM_DMA_TRIGGER:
|
---|
3448 | {
|
---|
3449 | /* Set the DMA Period elapsed callback */
|
---|
3450 | htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
|
---|
3451 |
|
---|
3452 | /* Set the DMA error callback */
|
---|
3453 | htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
|
---|
3454 |
|
---|
3455 | /* Enable the DMA Stream */
|
---|
3456 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
|
---|
3457 | }
|
---|
3458 | break;
|
---|
3459 | default:
|
---|
3460 | break;
|
---|
3461 | }
|
---|
3462 | /* configure the DMA Burst Mode */
|
---|
3463 | htim->Instance->DCR = BurstBaseAddress | BurstLength;
|
---|
3464 |
|
---|
3465 | /* Enable the TIM DMA Request */
|
---|
3466 | __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
|
---|
3467 |
|
---|
3468 | htim->State = HAL_TIM_STATE_READY;
|
---|
3469 |
|
---|
3470 | /* Return function status */
|
---|
3471 | return HAL_OK;
|
---|
3472 | }
|
---|
3473 |
|
---|
3474 | /**
|
---|
3475 | * @brief Stops the TIM DMA Burst mode
|
---|
3476 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
3477 | * the configuration information for TIM module.
|
---|
3478 | * @param BurstRequestSrc: TIM DMA Request sources to disable
|
---|
3479 | * @retval HAL status
|
---|
3480 | */
|
---|
3481 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
|
---|
3482 | {
|
---|
3483 | /* Check the parameters */
|
---|
3484 | assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
|
---|
3485 |
|
---|
3486 | /* Abort the DMA transfer (at least disable the DMA channel) */
|
---|
3487 | switch(BurstRequestSrc)
|
---|
3488 | {
|
---|
3489 | case TIM_DMA_UPDATE:
|
---|
3490 | {
|
---|
3491 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
|
---|
3492 | }
|
---|
3493 | break;
|
---|
3494 | case TIM_DMA_CC1:
|
---|
3495 | {
|
---|
3496 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
|
---|
3497 | }
|
---|
3498 | break;
|
---|
3499 | case TIM_DMA_CC2:
|
---|
3500 | {
|
---|
3501 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
|
---|
3502 | }
|
---|
3503 | break;
|
---|
3504 | case TIM_DMA_CC3:
|
---|
3505 | {
|
---|
3506 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
|
---|
3507 | }
|
---|
3508 | break;
|
---|
3509 | case TIM_DMA_CC4:
|
---|
3510 | {
|
---|
3511 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
|
---|
3512 | }
|
---|
3513 | break;
|
---|
3514 | case TIM_DMA_COM:
|
---|
3515 | {
|
---|
3516 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
|
---|
3517 | }
|
---|
3518 | break;
|
---|
3519 | case TIM_DMA_TRIGGER:
|
---|
3520 | {
|
---|
3521 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
|
---|
3522 | }
|
---|
3523 | break;
|
---|
3524 | default:
|
---|
3525 | break;
|
---|
3526 | }
|
---|
3527 |
|
---|
3528 | /* Disable the TIM Update DMA request */
|
---|
3529 | __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
|
---|
3530 |
|
---|
3531 | /* Return function status */
|
---|
3532 | return HAL_OK;
|
---|
3533 | }
|
---|
3534 |
|
---|
3535 | /**
|
---|
3536 | * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
|
---|
3537 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
3538 | * the configuration information for TIM module.
|
---|
3539 | * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
|
---|
3540 | * This parameters can be on of the following values:
|
---|
3541 | * @arg TIM_DMABASE_CR1
|
---|
3542 | * @arg TIM_DMABASE_CR2
|
---|
3543 | * @arg TIM_DMABASE_SMCR
|
---|
3544 | * @arg TIM_DMABASE_DIER
|
---|
3545 | * @arg TIM_DMABASE_SR
|
---|
3546 | * @arg TIM_DMABASE_EGR
|
---|
3547 | * @arg TIM_DMABASE_CCMR1
|
---|
3548 | * @arg TIM_DMABASE_CCMR2
|
---|
3549 | * @arg TIM_DMABASE_CCER
|
---|
3550 | * @arg TIM_DMABASE_CNT
|
---|
3551 | * @arg TIM_DMABASE_PSC
|
---|
3552 | * @arg TIM_DMABASE_ARR
|
---|
3553 | * @arg TIM_DMABASE_RCR
|
---|
3554 | * @arg TIM_DMABASE_CCR1
|
---|
3555 | * @arg TIM_DMABASE_CCR2
|
---|
3556 | * @arg TIM_DMABASE_CCR3
|
---|
3557 | * @arg TIM_DMABASE_CCR4
|
---|
3558 | * @arg TIM_DMABASE_BDTR
|
---|
3559 | * @arg TIM_DMABASE_DCR
|
---|
3560 | * @param BurstRequestSrc: TIM DMA Request sources.
|
---|
3561 | * This parameters can be on of the following values:
|
---|
3562 | * @arg TIM_DMA_UPDATE: TIM update Interrupt source
|
---|
3563 | * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
|
---|
3564 | * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
|
---|
3565 | * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
|
---|
3566 | * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
|
---|
3567 | * @arg TIM_DMA_COM: TIM Commutation DMA source
|
---|
3568 | * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
|
---|
3569 | * @param BurstBuffer: The Buffer address.
|
---|
3570 | * @param BurstLength: DMA Burst length. This parameter can be one value
|
---|
3571 | * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
|
---|
3572 | * @retval HAL status
|
---|
3573 | */
|
---|
3574 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
|
---|
3575 | uint32_t *BurstBuffer, uint32_t BurstLength)
|
---|
3576 | {
|
---|
3577 | /* Check the parameters */
|
---|
3578 | assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
|
---|
3579 | assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
|
---|
3580 | assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
|
---|
3581 | assert_param(IS_TIM_DMA_LENGTH(BurstLength));
|
---|
3582 |
|
---|
3583 | if((htim->State == HAL_TIM_STATE_BUSY))
|
---|
3584 | {
|
---|
3585 | return HAL_BUSY;
|
---|
3586 | }
|
---|
3587 | else if((htim->State == HAL_TIM_STATE_READY))
|
---|
3588 | {
|
---|
3589 | if((BurstBuffer == 0 ) && (BurstLength > 0))
|
---|
3590 | {
|
---|
3591 | return HAL_ERROR;
|
---|
3592 | }
|
---|
3593 | else
|
---|
3594 | {
|
---|
3595 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
3596 | }
|
---|
3597 | }
|
---|
3598 | switch(BurstRequestSrc)
|
---|
3599 | {
|
---|
3600 | case TIM_DMA_UPDATE:
|
---|
3601 | {
|
---|
3602 | /* Set the DMA Period elapsed callback */
|
---|
3603 | htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
|
---|
3604 |
|
---|
3605 | /* Set the DMA error callback */
|
---|
3606 | htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
|
---|
3607 |
|
---|
3608 | /* Enable the DMA Stream */
|
---|
3609 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
|
---|
3610 | }
|
---|
3611 | break;
|
---|
3612 | case TIM_DMA_CC1:
|
---|
3613 | {
|
---|
3614 | /* Set the DMA Period elapsed callback */
|
---|
3615 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
|
---|
3616 |
|
---|
3617 | /* Set the DMA error callback */
|
---|
3618 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
---|
3619 |
|
---|
3620 | /* Enable the DMA Stream */
|
---|
3621 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
|
---|
3622 | }
|
---|
3623 | break;
|
---|
3624 | case TIM_DMA_CC2:
|
---|
3625 | {
|
---|
3626 | /* Set the DMA Period elapsed callback */
|
---|
3627 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
|
---|
3628 |
|
---|
3629 | /* Set the DMA error callback */
|
---|
3630 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
---|
3631 |
|
---|
3632 | /* Enable the DMA Stream */
|
---|
3633 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
|
---|
3634 | }
|
---|
3635 | break;
|
---|
3636 | case TIM_DMA_CC3:
|
---|
3637 | {
|
---|
3638 | /* Set the DMA Period elapsed callback */
|
---|
3639 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
|
---|
3640 |
|
---|
3641 | /* Set the DMA error callback */
|
---|
3642 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
---|
3643 |
|
---|
3644 | /* Enable the DMA Stream */
|
---|
3645 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
|
---|
3646 | }
|
---|
3647 | break;
|
---|
3648 | case TIM_DMA_CC4:
|
---|
3649 | {
|
---|
3650 | /* Set the DMA Period elapsed callback */
|
---|
3651 | htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
|
---|
3652 |
|
---|
3653 | /* Set the DMA error callback */
|
---|
3654 | htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
|
---|
3655 |
|
---|
3656 | /* Enable the DMA Stream */
|
---|
3657 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
|
---|
3658 | }
|
---|
3659 | break;
|
---|
3660 | case TIM_DMA_COM:
|
---|
3661 | {
|
---|
3662 | /* Set the DMA Period elapsed callback */
|
---|
3663 | htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
|
---|
3664 |
|
---|
3665 | /* Set the DMA error callback */
|
---|
3666 | htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
|
---|
3667 |
|
---|
3668 | /* Enable the DMA Stream */
|
---|
3669 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
|
---|
3670 | }
|
---|
3671 | break;
|
---|
3672 | case TIM_DMA_TRIGGER:
|
---|
3673 | {
|
---|
3674 | /* Set the DMA Period elapsed callback */
|
---|
3675 | htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
|
---|
3676 |
|
---|
3677 | /* Set the DMA error callback */
|
---|
3678 | htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
|
---|
3679 |
|
---|
3680 | /* Enable the DMA Stream */
|
---|
3681 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
|
---|
3682 | }
|
---|
3683 | break;
|
---|
3684 | default:
|
---|
3685 | break;
|
---|
3686 | }
|
---|
3687 |
|
---|
3688 | /* configure the DMA Burst Mode */
|
---|
3689 | htim->Instance->DCR = BurstBaseAddress | BurstLength;
|
---|
3690 |
|
---|
3691 | /* Enable the TIM DMA Request */
|
---|
3692 | __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
|
---|
3693 |
|
---|
3694 | htim->State = HAL_TIM_STATE_READY;
|
---|
3695 |
|
---|
3696 | /* Return function status */
|
---|
3697 | return HAL_OK;
|
---|
3698 | }
|
---|
3699 |
|
---|
3700 | /**
|
---|
3701 | * @brief Stop the DMA burst reading
|
---|
3702 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
3703 | * the configuration information for TIM module.
|
---|
3704 | * @param BurstRequestSrc: TIM DMA Request sources to disable.
|
---|
3705 | * @retval HAL status
|
---|
3706 | */
|
---|
3707 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
|
---|
3708 | {
|
---|
3709 | /* Check the parameters */
|
---|
3710 | assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
|
---|
3711 |
|
---|
3712 | /* Abort the DMA transfer (at least disable the DMA channel) */
|
---|
3713 | switch(BurstRequestSrc)
|
---|
3714 | {
|
---|
3715 | case TIM_DMA_UPDATE:
|
---|
3716 | {
|
---|
3717 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
|
---|
3718 | }
|
---|
3719 | break;
|
---|
3720 | case TIM_DMA_CC1:
|
---|
3721 | {
|
---|
3722 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
|
---|
3723 | }
|
---|
3724 | break;
|
---|
3725 | case TIM_DMA_CC2:
|
---|
3726 | {
|
---|
3727 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
|
---|
3728 | }
|
---|
3729 | break;
|
---|
3730 | case TIM_DMA_CC3:
|
---|
3731 | {
|
---|
3732 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
|
---|
3733 | }
|
---|
3734 | break;
|
---|
3735 | case TIM_DMA_CC4:
|
---|
3736 | {
|
---|
3737 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
|
---|
3738 | }
|
---|
3739 | break;
|
---|
3740 | case TIM_DMA_COM:
|
---|
3741 | {
|
---|
3742 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
|
---|
3743 | }
|
---|
3744 | break;
|
---|
3745 | case TIM_DMA_TRIGGER:
|
---|
3746 | {
|
---|
3747 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
|
---|
3748 | }
|
---|
3749 | break;
|
---|
3750 | default:
|
---|
3751 | break;
|
---|
3752 | }
|
---|
3753 |
|
---|
3754 | /* Disable the TIM Update DMA request */
|
---|
3755 | __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
|
---|
3756 |
|
---|
3757 | /* Return function status */
|
---|
3758 | return HAL_OK;
|
---|
3759 | }
|
---|
3760 |
|
---|
3761 | /**
|
---|
3762 | * @brief Generate a software event
|
---|
3763 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
3764 | * the configuration information for TIM module.
|
---|
3765 | * @param EventSource: specifies the event source.
|
---|
3766 | * This parameter can be one of the following values:
|
---|
3767 | * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
|
---|
3768 | * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
|
---|
3769 | * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
|
---|
3770 | * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
|
---|
3771 | * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
|
---|
3772 | * @arg TIM_EVENTSOURCE_COM: Timer COM event source
|
---|
3773 | * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
|
---|
3774 | * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
|
---|
3775 | * @note TIM6 and TIM7 can only generate an update event.
|
---|
3776 | * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1 and TIM8.
|
---|
3777 | * @retval HAL status
|
---|
3778 | */
|
---|
3779 |
|
---|
3780 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
|
---|
3781 | {
|
---|
3782 | /* Check the parameters */
|
---|
3783 | assert_param(IS_TIM_INSTANCE(htim->Instance));
|
---|
3784 | assert_param(IS_TIM_EVENT_SOURCE(EventSource));
|
---|
3785 |
|
---|
3786 | /* Process Locked */
|
---|
3787 | __HAL_LOCK(htim);
|
---|
3788 |
|
---|
3789 | /* Change the TIM state */
|
---|
3790 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
3791 |
|
---|
3792 | /* Set the event sources */
|
---|
3793 | htim->Instance->EGR = EventSource;
|
---|
3794 |
|
---|
3795 | /* Change the TIM state */
|
---|
3796 | htim->State = HAL_TIM_STATE_READY;
|
---|
3797 |
|
---|
3798 | __HAL_UNLOCK(htim);
|
---|
3799 |
|
---|
3800 | /* Return function status */
|
---|
3801 | return HAL_OK;
|
---|
3802 | }
|
---|
3803 |
|
---|
3804 | /**
|
---|
3805 | * @brief Configures the OCRef clear feature
|
---|
3806 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
3807 | * the configuration information for TIM module.
|
---|
3808 | * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
|
---|
3809 | * contains the OCREF clear feature and parameters for the TIM peripheral.
|
---|
3810 | * @param Channel: specifies the TIM Channel.
|
---|
3811 | * This parameter can be one of the following values:
|
---|
3812 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
3813 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
3814 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
3815 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
3816 | * @retval HAL status
|
---|
3817 | */
|
---|
3818 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
|
---|
3819 | {
|
---|
3820 | /* Check the parameters */
|
---|
3821 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
---|
3822 | assert_param(IS_TIM_CHANNELS(Channel));
|
---|
3823 | assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
|
---|
3824 | assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
|
---|
3825 | assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
|
---|
3826 | assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
|
---|
3827 |
|
---|
3828 | /* Process Locked */
|
---|
3829 | __HAL_LOCK(htim);
|
---|
3830 |
|
---|
3831 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
3832 |
|
---|
3833 | if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
|
---|
3834 | {
|
---|
3835 | TIM_ETR_SetConfig(htim->Instance,
|
---|
3836 | sClearInputConfig->ClearInputPrescaler,
|
---|
3837 | sClearInputConfig->ClearInputPolarity,
|
---|
3838 | sClearInputConfig->ClearInputFilter);
|
---|
3839 | }
|
---|
3840 |
|
---|
3841 | switch (Channel)
|
---|
3842 | {
|
---|
3843 | case TIM_CHANNEL_1:
|
---|
3844 | {
|
---|
3845 | if(sClearInputConfig->ClearInputState != RESET)
|
---|
3846 | {
|
---|
3847 | /* Enable the Ocref clear feature for Channel 1 */
|
---|
3848 | htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
|
---|
3849 | }
|
---|
3850 | else
|
---|
3851 | {
|
---|
3852 | /* Disable the Ocref clear feature for Channel 1 */
|
---|
3853 | htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
|
---|
3854 | }
|
---|
3855 | }
|
---|
3856 | break;
|
---|
3857 | case TIM_CHANNEL_2:
|
---|
3858 | {
|
---|
3859 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
3860 | if(sClearInputConfig->ClearInputState != RESET)
|
---|
3861 | {
|
---|
3862 | /* Enable the Ocref clear feature for Channel 2 */
|
---|
3863 | htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
|
---|
3864 | }
|
---|
3865 | else
|
---|
3866 | {
|
---|
3867 | /* Disable the Ocref clear feature for Channel 2 */
|
---|
3868 | htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
|
---|
3869 | }
|
---|
3870 | }
|
---|
3871 | break;
|
---|
3872 | case TIM_CHANNEL_3:
|
---|
3873 | {
|
---|
3874 | assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
---|
3875 | if(sClearInputConfig->ClearInputState != RESET)
|
---|
3876 | {
|
---|
3877 | /* Enable the Ocref clear feature for Channel 3 */
|
---|
3878 | htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
|
---|
3879 | }
|
---|
3880 | else
|
---|
3881 | {
|
---|
3882 | /* Disable the Ocref clear feature for Channel 3 */
|
---|
3883 | htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
|
---|
3884 | }
|
---|
3885 | }
|
---|
3886 | break;
|
---|
3887 | case TIM_CHANNEL_4:
|
---|
3888 | {
|
---|
3889 | assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
---|
3890 | if(sClearInputConfig->ClearInputState != RESET)
|
---|
3891 | {
|
---|
3892 | /* Enable the Ocref clear feature for Channel 4 */
|
---|
3893 | htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
|
---|
3894 | }
|
---|
3895 | else
|
---|
3896 | {
|
---|
3897 | /* Disable the Ocref clear feature for Channel 4 */
|
---|
3898 | htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
|
---|
3899 | }
|
---|
3900 | }
|
---|
3901 | break;
|
---|
3902 | default:
|
---|
3903 | break;
|
---|
3904 | }
|
---|
3905 |
|
---|
3906 | htim->State = HAL_TIM_STATE_READY;
|
---|
3907 |
|
---|
3908 | __HAL_UNLOCK(htim);
|
---|
3909 |
|
---|
3910 | return HAL_OK;
|
---|
3911 | }
|
---|
3912 |
|
---|
3913 | /**
|
---|
3914 | * @brief Configures the clock source to be used
|
---|
3915 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
3916 | * the configuration information for TIM module.
|
---|
3917 | * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
|
---|
3918 | * contains the clock source information for the TIM peripheral.
|
---|
3919 | * @retval HAL status
|
---|
3920 | */
|
---|
3921 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
|
---|
3922 | {
|
---|
3923 | uint32_t tmpsmcr = 0;
|
---|
3924 |
|
---|
3925 | /* Process Locked */
|
---|
3926 | __HAL_LOCK(htim);
|
---|
3927 |
|
---|
3928 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
3929 |
|
---|
3930 | /* Check the parameters */
|
---|
3931 | assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
|
---|
3932 | assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
---|
3933 | assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
|
---|
3934 | assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
---|
3935 |
|
---|
3936 | /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
|
---|
3937 | tmpsmcr = htim->Instance->SMCR;
|
---|
3938 | tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
|
---|
3939 | tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
---|
3940 | htim->Instance->SMCR = tmpsmcr;
|
---|
3941 |
|
---|
3942 | switch (sClockSourceConfig->ClockSource)
|
---|
3943 | {
|
---|
3944 | case TIM_CLOCKSOURCE_INTERNAL:
|
---|
3945 | {
|
---|
3946 | assert_param(IS_TIM_INSTANCE(htim->Instance));
|
---|
3947 | /* Disable slave mode to clock the prescaler directly with the internal clock */
|
---|
3948 | htim->Instance->SMCR &= ~TIM_SMCR_SMS;
|
---|
3949 | }
|
---|
3950 | break;
|
---|
3951 |
|
---|
3952 | case TIM_CLOCKSOURCE_ETRMODE1:
|
---|
3953 | {
|
---|
3954 | assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
|
---|
3955 | /* Configure the ETR Clock source */
|
---|
3956 | TIM_ETR_SetConfig(htim->Instance,
|
---|
3957 | sClockSourceConfig->ClockPrescaler,
|
---|
3958 | sClockSourceConfig->ClockPolarity,
|
---|
3959 | sClockSourceConfig->ClockFilter);
|
---|
3960 | /* Get the TIMx SMCR register value */
|
---|
3961 | tmpsmcr = htim->Instance->SMCR;
|
---|
3962 | /* Reset the SMS and TS Bits */
|
---|
3963 | tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
|
---|
3964 | /* Select the External clock mode1 and the ETRF trigger */
|
---|
3965 | tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
|
---|
3966 | /* Write to TIMx SMCR */
|
---|
3967 | htim->Instance->SMCR = tmpsmcr;
|
---|
3968 | }
|
---|
3969 | break;
|
---|
3970 |
|
---|
3971 | case TIM_CLOCKSOURCE_ETRMODE2:
|
---|
3972 | {
|
---|
3973 | assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
|
---|
3974 | /* Configure the ETR Clock source */
|
---|
3975 | TIM_ETR_SetConfig(htim->Instance,
|
---|
3976 | sClockSourceConfig->ClockPrescaler,
|
---|
3977 | sClockSourceConfig->ClockPolarity,
|
---|
3978 | sClockSourceConfig->ClockFilter);
|
---|
3979 | /* Enable the External clock mode2 */
|
---|
3980 | htim->Instance->SMCR |= TIM_SMCR_ECE;
|
---|
3981 | }
|
---|
3982 | break;
|
---|
3983 |
|
---|
3984 | case TIM_CLOCKSOURCE_TI1:
|
---|
3985 | {
|
---|
3986 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
---|
3987 | TIM_TI1_ConfigInputStage(htim->Instance,
|
---|
3988 | sClockSourceConfig->ClockPolarity,
|
---|
3989 | sClockSourceConfig->ClockFilter);
|
---|
3990 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
|
---|
3991 | }
|
---|
3992 | break;
|
---|
3993 | case TIM_CLOCKSOURCE_TI2:
|
---|
3994 | {
|
---|
3995 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
3996 | TIM_TI2_ConfigInputStage(htim->Instance,
|
---|
3997 | sClockSourceConfig->ClockPolarity,
|
---|
3998 | sClockSourceConfig->ClockFilter);
|
---|
3999 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
|
---|
4000 | }
|
---|
4001 | break;
|
---|
4002 | case TIM_CLOCKSOURCE_TI1ED:
|
---|
4003 | {
|
---|
4004 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
---|
4005 | TIM_TI1_ConfigInputStage(htim->Instance,
|
---|
4006 | sClockSourceConfig->ClockPolarity,
|
---|
4007 | sClockSourceConfig->ClockFilter);
|
---|
4008 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
|
---|
4009 | }
|
---|
4010 | break;
|
---|
4011 | case TIM_CLOCKSOURCE_ITR0:
|
---|
4012 | {
|
---|
4013 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
4014 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
|
---|
4015 | }
|
---|
4016 | break;
|
---|
4017 | case TIM_CLOCKSOURCE_ITR1:
|
---|
4018 | {
|
---|
4019 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
4020 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
|
---|
4021 | }
|
---|
4022 | break;
|
---|
4023 | case TIM_CLOCKSOURCE_ITR2:
|
---|
4024 | {
|
---|
4025 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
4026 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
|
---|
4027 | }
|
---|
4028 | break;
|
---|
4029 | case TIM_CLOCKSOURCE_ITR3:
|
---|
4030 | {
|
---|
4031 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
4032 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
|
---|
4033 | }
|
---|
4034 | break;
|
---|
4035 |
|
---|
4036 | default:
|
---|
4037 | break;
|
---|
4038 | }
|
---|
4039 | htim->State = HAL_TIM_STATE_READY;
|
---|
4040 |
|
---|
4041 | __HAL_UNLOCK(htim);
|
---|
4042 |
|
---|
4043 | return HAL_OK;
|
---|
4044 | }
|
---|
4045 |
|
---|
4046 | /**
|
---|
4047 | * @brief Selects the signal connected to the TI1 input: direct from CH1_input
|
---|
4048 | * or a XOR combination between CH1_input, CH2_input & CH3_input
|
---|
4049 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
4050 | * the configuration information for TIM module.
|
---|
4051 | * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
|
---|
4052 | * output of a XOR gate.
|
---|
4053 | * This parameter can be one of the following values:
|
---|
4054 | * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
|
---|
4055 | * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
|
---|
4056 | * pins are connected to the TI1 input (XOR combination)
|
---|
4057 | * @retval HAL status
|
---|
4058 | */
|
---|
4059 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
|
---|
4060 | {
|
---|
4061 | uint32_t tmpcr2 = 0;
|
---|
4062 |
|
---|
4063 | /* Check the parameters */
|
---|
4064 | assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
|
---|
4065 | assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
|
---|
4066 |
|
---|
4067 | /* Get the TIMx CR2 register value */
|
---|
4068 | tmpcr2 = htim->Instance->CR2;
|
---|
4069 |
|
---|
4070 | /* Reset the TI1 selection */
|
---|
4071 | tmpcr2 &= ~TIM_CR2_TI1S;
|
---|
4072 |
|
---|
4073 | /* Set the TI1 selection */
|
---|
4074 | tmpcr2 |= TI1_Selection;
|
---|
4075 |
|
---|
4076 | /* Write to TIMxCR2 */
|
---|
4077 | htim->Instance->CR2 = tmpcr2;
|
---|
4078 |
|
---|
4079 | return HAL_OK;
|
---|
4080 | }
|
---|
4081 |
|
---|
4082 | /**
|
---|
4083 | * @brief Configures the TIM in Slave mode
|
---|
4084 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
4085 | * the configuration information for TIM module.
|
---|
4086 | * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
|
---|
4087 | * contains the selected trigger (internal trigger input, filtered
|
---|
4088 | * timer input or external trigger input) and the ) and the Slave
|
---|
4089 | * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
|
---|
4090 | * @retval HAL status
|
---|
4091 | */
|
---|
4092 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
|
---|
4093 | {
|
---|
4094 | /* Check the parameters */
|
---|
4095 | assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
|
---|
4096 | assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
|
---|
4097 | assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
|
---|
4098 |
|
---|
4099 | __HAL_LOCK(htim);
|
---|
4100 |
|
---|
4101 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
4102 |
|
---|
4103 | TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
|
---|
4104 |
|
---|
4105 | /* Disable Trigger Interrupt */
|
---|
4106 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
|
---|
4107 |
|
---|
4108 | /* Disable Trigger DMA request */
|
---|
4109 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
|
---|
4110 |
|
---|
4111 | htim->State = HAL_TIM_STATE_READY;
|
---|
4112 |
|
---|
4113 | __HAL_UNLOCK(htim);
|
---|
4114 |
|
---|
4115 | return HAL_OK;
|
---|
4116 | }
|
---|
4117 |
|
---|
4118 | /**
|
---|
4119 | * @brief Configures the TIM in Slave mode in interrupt mode
|
---|
4120 | * @param htim: TIM handle.
|
---|
4121 | * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
|
---|
4122 | * contains the selected trigger (internal trigger input, filtered
|
---|
4123 | * timer input or external trigger input) and the ) and the Slave
|
---|
4124 | * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
|
---|
4125 | * @retval HAL status
|
---|
4126 | */
|
---|
4127 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
|
---|
4128 | TIM_SlaveConfigTypeDef * sSlaveConfig)
|
---|
4129 | {
|
---|
4130 | /* Check the parameters */
|
---|
4131 | assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
|
---|
4132 | assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
|
---|
4133 | assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
|
---|
4134 |
|
---|
4135 | __HAL_LOCK(htim);
|
---|
4136 |
|
---|
4137 | htim->State = HAL_TIM_STATE_BUSY;
|
---|
4138 |
|
---|
4139 | TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
|
---|
4140 |
|
---|
4141 | /* Enable Trigger Interrupt */
|
---|
4142 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
|
---|
4143 |
|
---|
4144 | /* Disable Trigger DMA request */
|
---|
4145 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
|
---|
4146 |
|
---|
4147 | htim->State = HAL_TIM_STATE_READY;
|
---|
4148 |
|
---|
4149 | __HAL_UNLOCK(htim);
|
---|
4150 |
|
---|
4151 | return HAL_OK;
|
---|
4152 | }
|
---|
4153 |
|
---|
4154 | /**
|
---|
4155 | * @brief Read the captured value from Capture Compare unit
|
---|
4156 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
4157 | * the configuration information for TIM module.
|
---|
4158 | * @param Channel: TIM Channels to be enabled.
|
---|
4159 | * This parameter can be one of the following values:
|
---|
4160 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
4161 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
4162 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
4163 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
4164 | * @retval Captured value
|
---|
4165 | */
|
---|
4166 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
|
---|
4167 | {
|
---|
4168 | uint32_t tmpreg = 0;
|
---|
4169 |
|
---|
4170 | __HAL_LOCK(htim);
|
---|
4171 |
|
---|
4172 | switch (Channel)
|
---|
4173 | {
|
---|
4174 | case TIM_CHANNEL_1:
|
---|
4175 | {
|
---|
4176 | /* Check the parameters */
|
---|
4177 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
---|
4178 |
|
---|
4179 | /* Return the capture 1 value */
|
---|
4180 | tmpreg = htim->Instance->CCR1;
|
---|
4181 |
|
---|
4182 | break;
|
---|
4183 | }
|
---|
4184 | case TIM_CHANNEL_2:
|
---|
4185 | {
|
---|
4186 | /* Check the parameters */
|
---|
4187 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
4188 |
|
---|
4189 | /* Return the capture 2 value */
|
---|
4190 | tmpreg = htim->Instance->CCR2;
|
---|
4191 |
|
---|
4192 | break;
|
---|
4193 | }
|
---|
4194 |
|
---|
4195 | case TIM_CHANNEL_3:
|
---|
4196 | {
|
---|
4197 | /* Check the parameters */
|
---|
4198 | assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
---|
4199 |
|
---|
4200 | /* Return the capture 3 value */
|
---|
4201 | tmpreg = htim->Instance->CCR3;
|
---|
4202 |
|
---|
4203 | break;
|
---|
4204 | }
|
---|
4205 |
|
---|
4206 | case TIM_CHANNEL_4:
|
---|
4207 | {
|
---|
4208 | /* Check the parameters */
|
---|
4209 | assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
---|
4210 |
|
---|
4211 | /* Return the capture 4 value */
|
---|
4212 | tmpreg = htim->Instance->CCR4;
|
---|
4213 |
|
---|
4214 | break;
|
---|
4215 | }
|
---|
4216 |
|
---|
4217 | default:
|
---|
4218 | break;
|
---|
4219 | }
|
---|
4220 |
|
---|
4221 | __HAL_UNLOCK(htim);
|
---|
4222 | return tmpreg;
|
---|
4223 | }
|
---|
4224 | /**
|
---|
4225 | * @}
|
---|
4226 | */
|
---|
4227 |
|
---|
4228 | /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
|
---|
4229 | * @brief TIM Callbacks functions
|
---|
4230 | *
|
---|
4231 | @verbatim
|
---|
4232 | ==============================================================================
|
---|
4233 | ##### TIM Callbacks functions #####
|
---|
4234 | ==============================================================================
|
---|
4235 | [..]
|
---|
4236 | This section provides TIM callback functions:
|
---|
4237 | (+) Timer Period elapsed callback
|
---|
4238 | (+) Timer Output Compare callback
|
---|
4239 | (+) Timer Input capture callback
|
---|
4240 | (+) Timer Trigger callback
|
---|
4241 | (+) Timer Error callback
|
---|
4242 |
|
---|
4243 | @endverbatim
|
---|
4244 | * @{
|
---|
4245 | */
|
---|
4246 |
|
---|
4247 | /**
|
---|
4248 | * @brief Period elapsed callback in non blocking mode
|
---|
4249 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
4250 | * the configuration information for TIM module.
|
---|
4251 | * @retval None
|
---|
4252 | */
|
---|
4253 | __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
|
---|
4254 | {
|
---|
4255 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
4256 | the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
|
---|
4257 | */
|
---|
4258 |
|
---|
4259 | }
|
---|
4260 | /**
|
---|
4261 | * @brief Output Compare callback in non blocking mode
|
---|
4262 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
4263 | * the configuration information for TIM module.
|
---|
4264 | * @retval None
|
---|
4265 | */
|
---|
4266 | __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
|
---|
4267 | {
|
---|
4268 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
4269 | the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
|
---|
4270 | */
|
---|
4271 | }
|
---|
4272 | /**
|
---|
4273 | * @brief Input Capture callback in non blocking mode
|
---|
4274 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
4275 | * the configuration information for TIM module.
|
---|
4276 | * @retval None
|
---|
4277 | */
|
---|
4278 | __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
|
---|
4279 | {
|
---|
4280 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
4281 | the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
|
---|
4282 | */
|
---|
4283 | }
|
---|
4284 |
|
---|
4285 | /**
|
---|
4286 | * @brief PWM Pulse finished callback in non blocking mode
|
---|
4287 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
4288 | * the configuration information for TIM module.
|
---|
4289 | * @retval None
|
---|
4290 | */
|
---|
4291 | __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
|
---|
4292 | {
|
---|
4293 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
4294 | the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
|
---|
4295 | */
|
---|
4296 | }
|
---|
4297 |
|
---|
4298 | /**
|
---|
4299 | * @brief Hall Trigger detection callback in non blocking mode
|
---|
4300 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
4301 | * the configuration information for TIM module.
|
---|
4302 | * @retval None
|
---|
4303 | */
|
---|
4304 | __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
|
---|
4305 | {
|
---|
4306 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
4307 | the HAL_TIM_TriggerCallback could be implemented in the user file
|
---|
4308 | */
|
---|
4309 | }
|
---|
4310 |
|
---|
4311 | /**
|
---|
4312 | * @brief Timer error callback in non blocking mode
|
---|
4313 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
4314 | * the configuration information for TIM module.
|
---|
4315 | * @retval None
|
---|
4316 | */
|
---|
4317 | __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
|
---|
4318 | {
|
---|
4319 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
4320 | the HAL_TIM_ErrorCallback could be implemented in the user file
|
---|
4321 | */
|
---|
4322 | }
|
---|
4323 | /**
|
---|
4324 | * @}
|
---|
4325 | */
|
---|
4326 |
|
---|
4327 | /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
|
---|
4328 | * @brief Peripheral State functions
|
---|
4329 | *
|
---|
4330 | @verbatim
|
---|
4331 | ==============================================================================
|
---|
4332 | ##### Peripheral State functions #####
|
---|
4333 | ==============================================================================
|
---|
4334 | [..]
|
---|
4335 | This subsection permits to get in run-time the status of the peripheral
|
---|
4336 | and the data flow.
|
---|
4337 |
|
---|
4338 | @endverbatim
|
---|
4339 | * @{
|
---|
4340 | */
|
---|
4341 |
|
---|
4342 | /**
|
---|
4343 | * @brief Return the TIM Base state
|
---|
4344 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
4345 | * the configuration information for TIM module.
|
---|
4346 | * @retval HAL state
|
---|
4347 | */
|
---|
4348 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
|
---|
4349 | {
|
---|
4350 | return htim->State;
|
---|
4351 | }
|
---|
4352 |
|
---|
4353 | /**
|
---|
4354 | * @brief Return the TIM OC state
|
---|
4355 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
4356 | * the configuration information for TIM module.
|
---|
4357 | * @retval HAL state
|
---|
4358 | */
|
---|
4359 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
|
---|
4360 | {
|
---|
4361 | return htim->State;
|
---|
4362 | }
|
---|
4363 |
|
---|
4364 | /**
|
---|
4365 | * @brief Return the TIM PWM state
|
---|
4366 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
4367 | * the configuration information for TIM module.
|
---|
4368 | * @retval HAL state
|
---|
4369 | */
|
---|
4370 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
|
---|
4371 | {
|
---|
4372 | return htim->State;
|
---|
4373 | }
|
---|
4374 |
|
---|
4375 | /**
|
---|
4376 | * @brief Return the TIM Input Capture state
|
---|
4377 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
4378 | * the configuration information for TIM module.
|
---|
4379 | * @retval HAL state
|
---|
4380 | */
|
---|
4381 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
|
---|
4382 | {
|
---|
4383 | return htim->State;
|
---|
4384 | }
|
---|
4385 |
|
---|
4386 | /**
|
---|
4387 | * @brief Return the TIM One Pulse Mode state
|
---|
4388 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
4389 | * the configuration information for TIM module.
|
---|
4390 | * @retval HAL state
|
---|
4391 | */
|
---|
4392 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
|
---|
4393 | {
|
---|
4394 | return htim->State;
|
---|
4395 | }
|
---|
4396 |
|
---|
4397 | /**
|
---|
4398 | * @brief Return the TIM Encoder Mode state
|
---|
4399 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
4400 | * the configuration information for TIM module.
|
---|
4401 | * @retval HAL state
|
---|
4402 | */
|
---|
4403 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
|
---|
4404 | {
|
---|
4405 | return htim->State;
|
---|
4406 | }
|
---|
4407 | /**
|
---|
4408 | * @}
|
---|
4409 | */
|
---|
4410 |
|
---|
4411 | /**
|
---|
4412 | * @brief Time Base configuration
|
---|
4413 | * @param TIMx: TIM peripheral
|
---|
4414 | * @param Structure: pointer on TIM Time Base required parameters
|
---|
4415 | * @retval None
|
---|
4416 | */
|
---|
4417 | void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
|
---|
4418 | {
|
---|
4419 | uint32_t tmpcr1 = 0;
|
---|
4420 | tmpcr1 = TIMx->CR1;
|
---|
4421 |
|
---|
4422 | /* Set TIM Time Base Unit parameters ---------------------------------------*/
|
---|
4423 | if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
|
---|
4424 | {
|
---|
4425 | /* Select the Counter Mode */
|
---|
4426 | tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
---|
4427 | tmpcr1 |= Structure->CounterMode;
|
---|
4428 | }
|
---|
4429 |
|
---|
4430 | if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
|
---|
4431 | {
|
---|
4432 | /* Set the clock division */
|
---|
4433 | tmpcr1 &= ~TIM_CR1_CKD;
|
---|
4434 | tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
---|
4435 | }
|
---|
4436 |
|
---|
4437 | TIMx->CR1 = tmpcr1;
|
---|
4438 |
|
---|
4439 | /* Set the Auto-reload value */
|
---|
4440 | TIMx->ARR = (uint32_t)Structure->Period ;
|
---|
4441 |
|
---|
4442 | /* Set the Prescaler value */
|
---|
4443 | TIMx->PSC = (uint32_t)Structure->Prescaler;
|
---|
4444 |
|
---|
4445 | if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
|
---|
4446 | {
|
---|
4447 | /* Set the Repetition Counter value */
|
---|
4448 | TIMx->RCR = Structure->RepetitionCounter;
|
---|
4449 | }
|
---|
4450 |
|
---|
4451 | /* Generate an update event to reload the Prescaler
|
---|
4452 | and the repetition counter(only for TIM1 and TIM8) value immediately */
|
---|
4453 | TIMx->EGR = TIM_EGR_UG;
|
---|
4454 | }
|
---|
4455 |
|
---|
4456 | /**
|
---|
4457 | * @brief Configure the TI1 as Input.
|
---|
4458 | * @param TIMx to select the TIM peripheral.
|
---|
4459 | * @param TIM_ICPolarity : The Input Polarity.
|
---|
4460 | * This parameter can be one of the following values:
|
---|
4461 | * @arg TIM_ICPolarity_Rising
|
---|
4462 | * @arg TIM_ICPolarity_Falling
|
---|
4463 | * @arg TIM_ICPolarity_BothEdge
|
---|
4464 | * @param TIM_ICSelection: specifies the input to be used.
|
---|
4465 | * This parameter can be one of the following values:
|
---|
4466 | * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
|
---|
4467 | * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
|
---|
4468 | * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
|
---|
4469 | * @param TIM_ICFilter: Specifies the Input Capture Filter.
|
---|
4470 | * This parameter must be a value between 0x00 and 0x0F.
|
---|
4471 | * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
|
---|
4472 | * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
|
---|
4473 | * protected against un-initialized filter and polarity values.
|
---|
4474 | * @retval None
|
---|
4475 | */
|
---|
4476 | void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
|
---|
4477 | uint32_t TIM_ICFilter)
|
---|
4478 | {
|
---|
4479 | uint32_t tmpccmr1 = 0;
|
---|
4480 | uint32_t tmpccer = 0;
|
---|
4481 |
|
---|
4482 | /* Disable the Channel 1: Reset the CC1E Bit */
|
---|
4483 | TIMx->CCER &= ~TIM_CCER_CC1E;
|
---|
4484 | tmpccmr1 = TIMx->CCMR1;
|
---|
4485 | tmpccer = TIMx->CCER;
|
---|
4486 |
|
---|
4487 | /* Select the Input */
|
---|
4488 | if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
|
---|
4489 | {
|
---|
4490 | tmpccmr1 &= ~TIM_CCMR1_CC1S;
|
---|
4491 | tmpccmr1 |= TIM_ICSelection;
|
---|
4492 | }
|
---|
4493 | else
|
---|
4494 | {
|
---|
4495 | tmpccmr1 &= ~TIM_CCMR1_CC1S;
|
---|
4496 | tmpccmr1 |= TIM_CCMR1_CC1S_0;
|
---|
4497 | }
|
---|
4498 |
|
---|
4499 | /* Set the filter */
|
---|
4500 | tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
---|
4501 | tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
|
---|
4502 |
|
---|
4503 | /* Select the Polarity and set the CC1E Bit */
|
---|
4504 | tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
|
---|
4505 | tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
|
---|
4506 |
|
---|
4507 | /* Write to TIMx CCMR1 and CCER registers */
|
---|
4508 | TIMx->CCMR1 = tmpccmr1;
|
---|
4509 | TIMx->CCER = tmpccer;
|
---|
4510 | }
|
---|
4511 |
|
---|
4512 | /**
|
---|
4513 | * @brief Time Output Compare 2 configuration
|
---|
4514 | * @param TIMx to select the TIM peripheral
|
---|
4515 | * @param OC_Config: The output configuration structure
|
---|
4516 | * @retval None
|
---|
4517 | */
|
---|
4518 | void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
|
---|
4519 | {
|
---|
4520 | uint32_t tmpccmrx = 0;
|
---|
4521 | uint32_t tmpccer = 0;
|
---|
4522 | uint32_t tmpcr2 = 0;
|
---|
4523 |
|
---|
4524 | /* Disable the Channel 2: Reset the CC2E Bit */
|
---|
4525 | TIMx->CCER &= ~TIM_CCER_CC2E;
|
---|
4526 |
|
---|
4527 | /* Get the TIMx CCER register value */
|
---|
4528 | tmpccer = TIMx->CCER;
|
---|
4529 | /* Get the TIMx CR2 register value */
|
---|
4530 | tmpcr2 = TIMx->CR2;
|
---|
4531 |
|
---|
4532 | /* Get the TIMx CCMR1 register value */
|
---|
4533 | tmpccmrx = TIMx->CCMR1;
|
---|
4534 |
|
---|
4535 | /* Reset the Output Compare mode and Capture/Compare selection Bits */
|
---|
4536 | tmpccmrx &= ~TIM_CCMR1_OC2M;
|
---|
4537 | tmpccmrx &= ~TIM_CCMR1_CC2S;
|
---|
4538 |
|
---|
4539 | /* Select the Output Compare Mode */
|
---|
4540 | tmpccmrx |= (OC_Config->OCMode << 8);
|
---|
4541 |
|
---|
4542 | /* Reset the Output Polarity level */
|
---|
4543 | tmpccer &= ~TIM_CCER_CC2P;
|
---|
4544 | /* Set the Output Compare Polarity */
|
---|
4545 | tmpccer |= (OC_Config->OCPolarity << 4);
|
---|
4546 |
|
---|
4547 | if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
|
---|
4548 | {
|
---|
4549 | assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
---|
4550 | assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
---|
4551 | assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
---|
4552 |
|
---|
4553 | /* Reset the Output N Polarity level */
|
---|
4554 | tmpccer &= ~TIM_CCER_CC2NP;
|
---|
4555 | /* Set the Output N Polarity */
|
---|
4556 | tmpccer |= (OC_Config->OCNPolarity << 4);
|
---|
4557 | /* Reset the Output N State */
|
---|
4558 | tmpccer &= ~TIM_CCER_CC2NE;
|
---|
4559 |
|
---|
4560 | /* Reset the Output Compare and Output Compare N IDLE State */
|
---|
4561 | tmpcr2 &= ~TIM_CR2_OIS2;
|
---|
4562 | tmpcr2 &= ~TIM_CR2_OIS2N;
|
---|
4563 | /* Set the Output Idle state */
|
---|
4564 | tmpcr2 |= (OC_Config->OCIdleState << 2);
|
---|
4565 | /* Set the Output N Idle state */
|
---|
4566 | tmpcr2 |= (OC_Config->OCNIdleState << 2);
|
---|
4567 | }
|
---|
4568 | /* Write to TIMx CR2 */
|
---|
4569 | TIMx->CR2 = tmpcr2;
|
---|
4570 |
|
---|
4571 | /* Write to TIMx CCMR1 */
|
---|
4572 | TIMx->CCMR1 = tmpccmrx;
|
---|
4573 |
|
---|
4574 | /* Set the Capture Compare Register value */
|
---|
4575 | TIMx->CCR2 = OC_Config->Pulse;
|
---|
4576 |
|
---|
4577 | /* Write to TIMx CCER */
|
---|
4578 | TIMx->CCER = tmpccer;
|
---|
4579 | }
|
---|
4580 |
|
---|
4581 | /**
|
---|
4582 | * @brief TIM DMA Delay Pulse complete callback.
|
---|
4583 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
---|
4584 | * the configuration information for the specified DMA module.
|
---|
4585 | * @retval None
|
---|
4586 | */
|
---|
4587 | void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
|
---|
4588 | {
|
---|
4589 | TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
---|
4590 |
|
---|
4591 | htim->State= HAL_TIM_STATE_READY;
|
---|
4592 |
|
---|
4593 | if(hdma == htim->hdma[TIM_DMA_ID_CC1])
|
---|
4594 | {
|
---|
4595 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
---|
4596 | }
|
---|
4597 | else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
|
---|
4598 | {
|
---|
4599 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
---|
4600 | }
|
---|
4601 | else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
|
---|
4602 | {
|
---|
4603 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
---|
4604 | }
|
---|
4605 | else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
|
---|
4606 | {
|
---|
4607 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
---|
4608 | }
|
---|
4609 |
|
---|
4610 | HAL_TIM_PWM_PulseFinishedCallback(htim);
|
---|
4611 |
|
---|
4612 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
---|
4613 | }
|
---|
4614 |
|
---|
4615 | /**
|
---|
4616 | * @brief TIM DMA error callback
|
---|
4617 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
---|
4618 | * the configuration information for the specified DMA module.
|
---|
4619 | * @retval None
|
---|
4620 | */
|
---|
4621 | void TIM_DMAError(DMA_HandleTypeDef *hdma)
|
---|
4622 | {
|
---|
4623 | TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
---|
4624 |
|
---|
4625 | htim->State= HAL_TIM_STATE_READY;
|
---|
4626 |
|
---|
4627 | HAL_TIM_ErrorCallback(htim);
|
---|
4628 | }
|
---|
4629 |
|
---|
4630 | /**
|
---|
4631 | * @brief TIM DMA Capture complete callback.
|
---|
4632 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
---|
4633 | * the configuration information for the specified DMA module.
|
---|
4634 | * @retval None
|
---|
4635 | */
|
---|
4636 | void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
|
---|
4637 | {
|
---|
4638 | TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
---|
4639 |
|
---|
4640 | htim->State= HAL_TIM_STATE_READY;
|
---|
4641 |
|
---|
4642 | if(hdma == htim->hdma[TIM_DMA_ID_CC1])
|
---|
4643 | {
|
---|
4644 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
---|
4645 | }
|
---|
4646 | else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
|
---|
4647 | {
|
---|
4648 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
---|
4649 | }
|
---|
4650 | else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
|
---|
4651 | {
|
---|
4652 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
---|
4653 | }
|
---|
4654 | else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
|
---|
4655 | {
|
---|
4656 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
---|
4657 | }
|
---|
4658 |
|
---|
4659 | HAL_TIM_IC_CaptureCallback(htim);
|
---|
4660 |
|
---|
4661 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
---|
4662 | }
|
---|
4663 |
|
---|
4664 | /**
|
---|
4665 | * @brief Enables or disables the TIM Capture Compare Channel x.
|
---|
4666 | * @param TIMx to select the TIM peripheral
|
---|
4667 | * @param Channel: specifies the TIM Channel
|
---|
4668 | * This parameter can be one of the following values:
|
---|
4669 | * @arg TIM_Channel_1: TIM Channel 1
|
---|
4670 | * @arg TIM_Channel_2: TIM Channel 2
|
---|
4671 | * @arg TIM_Channel_3: TIM Channel 3
|
---|
4672 | * @arg TIM_Channel_4: TIM Channel 4
|
---|
4673 | * @param ChannelState: specifies the TIM Channel CCxE bit new state.
|
---|
4674 | * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
|
---|
4675 | * @retval None
|
---|
4676 | */
|
---|
4677 | void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
|
---|
4678 | {
|
---|
4679 | uint32_t tmp = 0;
|
---|
4680 |
|
---|
4681 | /* Check the parameters */
|
---|
4682 | assert_param(IS_TIM_CC1_INSTANCE(TIMx));
|
---|
4683 | assert_param(IS_TIM_CHANNELS(Channel));
|
---|
4684 |
|
---|
4685 | tmp = TIM_CCER_CC1E << Channel;
|
---|
4686 |
|
---|
4687 | /* Reset the CCxE Bit */
|
---|
4688 | TIMx->CCER &= ~tmp;
|
---|
4689 |
|
---|
4690 | /* Set or reset the CCxE Bit */
|
---|
4691 | TIMx->CCER |= (uint32_t)(ChannelState << Channel);
|
---|
4692 | }
|
---|
4693 |
|
---|
4694 | /**
|
---|
4695 | * @brief TIM DMA Period Elapse complete callback.
|
---|
4696 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
---|
4697 | * the configuration information for the specified DMA module.
|
---|
4698 | * @retval None
|
---|
4699 | */
|
---|
4700 | static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
|
---|
4701 | {
|
---|
4702 | TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
---|
4703 |
|
---|
4704 | htim->State= HAL_TIM_STATE_READY;
|
---|
4705 |
|
---|
4706 | HAL_TIM_PeriodElapsedCallback(htim);
|
---|
4707 | }
|
---|
4708 |
|
---|
4709 | /**
|
---|
4710 | * @brief TIM DMA Trigger callback.
|
---|
4711 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
---|
4712 | * the configuration information for the specified DMA module.
|
---|
4713 | * @retval None
|
---|
4714 | */
|
---|
4715 | static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
|
---|
4716 | {
|
---|
4717 | TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
---|
4718 |
|
---|
4719 | htim->State= HAL_TIM_STATE_READY;
|
---|
4720 |
|
---|
4721 | HAL_TIM_TriggerCallback(htim);
|
---|
4722 | }
|
---|
4723 |
|
---|
4724 | /**
|
---|
4725 | * @brief Time Output Compare 1 configuration
|
---|
4726 | * @param TIMx to select the TIM peripheral
|
---|
4727 | * @param OC_Config: The output configuration structure
|
---|
4728 | * @retval None
|
---|
4729 | */
|
---|
4730 | static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
|
---|
4731 | {
|
---|
4732 | uint32_t tmpccmrx = 0;
|
---|
4733 | uint32_t tmpccer = 0;
|
---|
4734 | uint32_t tmpcr2 = 0;
|
---|
4735 |
|
---|
4736 | /* Disable the Channel 1: Reset the CC1E Bit */
|
---|
4737 | TIMx->CCER &= ~TIM_CCER_CC1E;
|
---|
4738 |
|
---|
4739 | /* Get the TIMx CCER register value */
|
---|
4740 | tmpccer = TIMx->CCER;
|
---|
4741 | /* Get the TIMx CR2 register value */
|
---|
4742 | tmpcr2 = TIMx->CR2;
|
---|
4743 |
|
---|
4744 | /* Get the TIMx CCMR1 register value */
|
---|
4745 | tmpccmrx = TIMx->CCMR1;
|
---|
4746 |
|
---|
4747 | /* Reset the Output Compare Mode Bits */
|
---|
4748 | tmpccmrx &= ~TIM_CCMR1_OC1M;
|
---|
4749 | tmpccmrx &= ~TIM_CCMR1_CC1S;
|
---|
4750 | /* Select the Output Compare Mode */
|
---|
4751 | tmpccmrx |= OC_Config->OCMode;
|
---|
4752 |
|
---|
4753 | /* Reset the Output Polarity level */
|
---|
4754 | tmpccer &= ~TIM_CCER_CC1P;
|
---|
4755 | /* Set the Output Compare Polarity */
|
---|
4756 | tmpccer |= OC_Config->OCPolarity;
|
---|
4757 |
|
---|
4758 |
|
---|
4759 | if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
|
---|
4760 | {
|
---|
4761 | /* Reset the Output N Polarity level */
|
---|
4762 | tmpccer &= ~TIM_CCER_CC1NP;
|
---|
4763 | /* Set the Output N Polarity */
|
---|
4764 | tmpccer |= OC_Config->OCNPolarity;
|
---|
4765 | /* Reset the Output N State */
|
---|
4766 | tmpccer &= ~TIM_CCER_CC1NE;
|
---|
4767 |
|
---|
4768 | /* Reset the Output Compare and Output Compare N IDLE State */
|
---|
4769 | tmpcr2 &= ~TIM_CR2_OIS1;
|
---|
4770 | tmpcr2 &= ~TIM_CR2_OIS1N;
|
---|
4771 | /* Set the Output Idle state */
|
---|
4772 | tmpcr2 |= OC_Config->OCIdleState;
|
---|
4773 | /* Set the Output N Idle state */
|
---|
4774 | tmpcr2 |= OC_Config->OCNIdleState;
|
---|
4775 | }
|
---|
4776 | /* Write to TIMx CR2 */
|
---|
4777 | TIMx->CR2 = tmpcr2;
|
---|
4778 |
|
---|
4779 | /* Write to TIMx CCMR1 */
|
---|
4780 | TIMx->CCMR1 = tmpccmrx;
|
---|
4781 |
|
---|
4782 | /* Set the Capture Compare Register value */
|
---|
4783 | TIMx->CCR1 = OC_Config->Pulse;
|
---|
4784 |
|
---|
4785 | /* Write to TIMx CCER */
|
---|
4786 | TIMx->CCER = tmpccer;
|
---|
4787 | }
|
---|
4788 |
|
---|
4789 | /**
|
---|
4790 | * @brief Time Output Compare 3 configuration
|
---|
4791 | * @param TIMx to select the TIM peripheral
|
---|
4792 | * @param OC_Config: The output configuration structure
|
---|
4793 | * @retval None
|
---|
4794 | */
|
---|
4795 | static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
|
---|
4796 | {
|
---|
4797 | uint32_t tmpccmrx = 0;
|
---|
4798 | uint32_t tmpccer = 0;
|
---|
4799 | uint32_t tmpcr2 = 0;
|
---|
4800 |
|
---|
4801 | /* Disable the Channel 3: Reset the CC2E Bit */
|
---|
4802 | TIMx->CCER &= ~TIM_CCER_CC3E;
|
---|
4803 |
|
---|
4804 | /* Get the TIMx CCER register value */
|
---|
4805 | tmpccer = TIMx->CCER;
|
---|
4806 | /* Get the TIMx CR2 register value */
|
---|
4807 | tmpcr2 = TIMx->CR2;
|
---|
4808 |
|
---|
4809 | /* Get the TIMx CCMR2 register value */
|
---|
4810 | tmpccmrx = TIMx->CCMR2;
|
---|
4811 |
|
---|
4812 | /* Reset the Output Compare mode and Capture/Compare selection Bits */
|
---|
4813 | tmpccmrx &= ~TIM_CCMR2_OC3M;
|
---|
4814 | tmpccmrx &= ~TIM_CCMR2_CC3S;
|
---|
4815 | /* Select the Output Compare Mode */
|
---|
4816 | tmpccmrx |= OC_Config->OCMode;
|
---|
4817 |
|
---|
4818 | /* Reset the Output Polarity level */
|
---|
4819 | tmpccer &= ~TIM_CCER_CC3P;
|
---|
4820 | /* Set the Output Compare Polarity */
|
---|
4821 | tmpccer |= (OC_Config->OCPolarity << 8);
|
---|
4822 |
|
---|
4823 | if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
|
---|
4824 | {
|
---|
4825 | assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
---|
4826 | assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
---|
4827 | assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
---|
4828 |
|
---|
4829 | /* Reset the Output N Polarity level */
|
---|
4830 | tmpccer &= ~TIM_CCER_CC3NP;
|
---|
4831 | /* Set the Output N Polarity */
|
---|
4832 | tmpccer |= (OC_Config->OCNPolarity << 8);
|
---|
4833 | /* Reset the Output N State */
|
---|
4834 | tmpccer &= ~TIM_CCER_CC3NE;
|
---|
4835 |
|
---|
4836 | /* Reset the Output Compare and Output Compare N IDLE State */
|
---|
4837 | tmpcr2 &= ~TIM_CR2_OIS3;
|
---|
4838 | tmpcr2 &= ~TIM_CR2_OIS3N;
|
---|
4839 | /* Set the Output Idle state */
|
---|
4840 | tmpcr2 |= (OC_Config->OCIdleState << 4);
|
---|
4841 | /* Set the Output N Idle state */
|
---|
4842 | tmpcr2 |= (OC_Config->OCNIdleState << 4);
|
---|
4843 | }
|
---|
4844 | /* Write to TIMx CR2 */
|
---|
4845 | TIMx->CR2 = tmpcr2;
|
---|
4846 |
|
---|
4847 | /* Write to TIMx CCMR2 */
|
---|
4848 | TIMx->CCMR2 = tmpccmrx;
|
---|
4849 |
|
---|
4850 | /* Set the Capture Compare Register value */
|
---|
4851 | TIMx->CCR3 = OC_Config->Pulse;
|
---|
4852 |
|
---|
4853 | /* Write to TIMx CCER */
|
---|
4854 | TIMx->CCER = tmpccer;
|
---|
4855 | }
|
---|
4856 |
|
---|
4857 | /**
|
---|
4858 | * @brief Time Output Compare 4 configuration
|
---|
4859 | * @param TIMx to select the TIM peripheral
|
---|
4860 | * @param OC_Config: The output configuration structure
|
---|
4861 | * @retval None
|
---|
4862 | */
|
---|
4863 | static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
|
---|
4864 | {
|
---|
4865 | uint32_t tmpccmrx = 0;
|
---|
4866 | uint32_t tmpccer = 0;
|
---|
4867 | uint32_t tmpcr2 = 0;
|
---|
4868 |
|
---|
4869 | /* Disable the Channel 4: Reset the CC4E Bit */
|
---|
4870 | TIMx->CCER &= ~TIM_CCER_CC4E;
|
---|
4871 |
|
---|
4872 | /* Get the TIMx CCER register value */
|
---|
4873 | tmpccer = TIMx->CCER;
|
---|
4874 | /* Get the TIMx CR2 register value */
|
---|
4875 | tmpcr2 = TIMx->CR2;
|
---|
4876 |
|
---|
4877 | /* Get the TIMx CCMR2 register value */
|
---|
4878 | tmpccmrx = TIMx->CCMR2;
|
---|
4879 |
|
---|
4880 | /* Reset the Output Compare mode and Capture/Compare selection Bits */
|
---|
4881 | tmpccmrx &= ~TIM_CCMR2_OC4M;
|
---|
4882 | tmpccmrx &= ~TIM_CCMR2_CC4S;
|
---|
4883 |
|
---|
4884 | /* Select the Output Compare Mode */
|
---|
4885 | tmpccmrx |= (OC_Config->OCMode << 8);
|
---|
4886 |
|
---|
4887 | /* Reset the Output Polarity level */
|
---|
4888 | tmpccer &= ~TIM_CCER_CC4P;
|
---|
4889 | /* Set the Output Compare Polarity */
|
---|
4890 | tmpccer |= (OC_Config->OCPolarity << 12);
|
---|
4891 |
|
---|
4892 | /*if((TIMx == TIM1) || (TIMx == TIM8))*/
|
---|
4893 | if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
|
---|
4894 | {
|
---|
4895 | assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
---|
4896 | /* Reset the Output Compare IDLE State */
|
---|
4897 | tmpcr2 &= ~TIM_CR2_OIS4;
|
---|
4898 | /* Set the Output Idle state */
|
---|
4899 | tmpcr2 |= (OC_Config->OCIdleState << 6);
|
---|
4900 | }
|
---|
4901 | /* Write to TIMx CR2 */
|
---|
4902 | TIMx->CR2 = tmpcr2;
|
---|
4903 |
|
---|
4904 | /* Write to TIMx CCMR2 */
|
---|
4905 | TIMx->CCMR2 = tmpccmrx;
|
---|
4906 |
|
---|
4907 | /* Set the Capture Compare Register value */
|
---|
4908 | TIMx->CCR4 = OC_Config->Pulse;
|
---|
4909 |
|
---|
4910 | /* Write to TIMx CCER */
|
---|
4911 | TIMx->CCER = tmpccer;
|
---|
4912 | }
|
---|
4913 |
|
---|
4914 | /**
|
---|
4915 | * @brief Time Output Compare 4 configuration
|
---|
4916 | * @param htim: pointer to a TIM_HandleTypeDef structure that contains
|
---|
4917 | * the configuration information for TIM module.
|
---|
4918 | * @param sSlaveConfig: The slave configuration structure
|
---|
4919 | * @retval None
|
---|
4920 | */
|
---|
4921 | static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
|
---|
4922 | TIM_SlaveConfigTypeDef * sSlaveConfig)
|
---|
4923 | {
|
---|
4924 | uint32_t tmpsmcr = 0;
|
---|
4925 | uint32_t tmpccmr1 = 0;
|
---|
4926 | uint32_t tmpccer = 0;
|
---|
4927 |
|
---|
4928 | /* Get the TIMx SMCR register value */
|
---|
4929 | tmpsmcr = htim->Instance->SMCR;
|
---|
4930 |
|
---|
4931 | /* Reset the Trigger Selection Bits */
|
---|
4932 | tmpsmcr &= ~TIM_SMCR_TS;
|
---|
4933 | /* Set the Input Trigger source */
|
---|
4934 | tmpsmcr |= sSlaveConfig->InputTrigger;
|
---|
4935 |
|
---|
4936 | /* Reset the slave mode Bits */
|
---|
4937 | tmpsmcr &= ~TIM_SMCR_SMS;
|
---|
4938 | /* Set the slave mode */
|
---|
4939 | tmpsmcr |= sSlaveConfig->SlaveMode;
|
---|
4940 |
|
---|
4941 | /* Write to TIMx SMCR */
|
---|
4942 | htim->Instance->SMCR = tmpsmcr;
|
---|
4943 |
|
---|
4944 | /* Configure the trigger prescaler, filter, and polarity */
|
---|
4945 | switch (sSlaveConfig->InputTrigger)
|
---|
4946 | {
|
---|
4947 | case TIM_TS_ETRF:
|
---|
4948 | {
|
---|
4949 | /* Check the parameters */
|
---|
4950 | assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
|
---|
4951 | assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
|
---|
4952 | assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
|
---|
4953 | assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
|
---|
4954 | /* Configure the ETR Trigger source */
|
---|
4955 | TIM_ETR_SetConfig(htim->Instance,
|
---|
4956 | sSlaveConfig->TriggerPrescaler,
|
---|
4957 | sSlaveConfig->TriggerPolarity,
|
---|
4958 | sSlaveConfig->TriggerFilter);
|
---|
4959 | }
|
---|
4960 | break;
|
---|
4961 |
|
---|
4962 | case TIM_TS_TI1F_ED:
|
---|
4963 | {
|
---|
4964 | /* Check the parameters */
|
---|
4965 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
---|
4966 | assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
|
---|
4967 |
|
---|
4968 | /* Disable the Channel 1: Reset the CC1E Bit */
|
---|
4969 | tmpccer = htim->Instance->CCER;
|
---|
4970 | htim->Instance->CCER &= ~TIM_CCER_CC1E;
|
---|
4971 | tmpccmr1 = htim->Instance->CCMR1;
|
---|
4972 |
|
---|
4973 | /* Set the filter */
|
---|
4974 | tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
---|
4975 | tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
|
---|
4976 |
|
---|
4977 | /* Write to TIMx CCMR1 and CCER registers */
|
---|
4978 | htim->Instance->CCMR1 = tmpccmr1;
|
---|
4979 | htim->Instance->CCER = tmpccer;
|
---|
4980 |
|
---|
4981 | }
|
---|
4982 | break;
|
---|
4983 |
|
---|
4984 | case TIM_TS_TI1FP1:
|
---|
4985 | {
|
---|
4986 | /* Check the parameters */
|
---|
4987 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
---|
4988 | assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
|
---|
4989 | assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
|
---|
4990 |
|
---|
4991 | /* Configure TI1 Filter and Polarity */
|
---|
4992 | TIM_TI1_ConfigInputStage(htim->Instance,
|
---|
4993 | sSlaveConfig->TriggerPolarity,
|
---|
4994 | sSlaveConfig->TriggerFilter);
|
---|
4995 | }
|
---|
4996 | break;
|
---|
4997 |
|
---|
4998 | case TIM_TS_TI2FP2:
|
---|
4999 | {
|
---|
5000 | /* Check the parameters */
|
---|
5001 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
5002 | assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
|
---|
5003 | assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
|
---|
5004 |
|
---|
5005 | /* Configure TI2 Filter and Polarity */
|
---|
5006 | TIM_TI2_ConfigInputStage(htim->Instance,
|
---|
5007 | sSlaveConfig->TriggerPolarity,
|
---|
5008 | sSlaveConfig->TriggerFilter);
|
---|
5009 | }
|
---|
5010 | break;
|
---|
5011 |
|
---|
5012 | case TIM_TS_ITR0:
|
---|
5013 | {
|
---|
5014 | /* Check the parameter */
|
---|
5015 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
5016 | }
|
---|
5017 | break;
|
---|
5018 |
|
---|
5019 | case TIM_TS_ITR1:
|
---|
5020 | {
|
---|
5021 | /* Check the parameter */
|
---|
5022 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
5023 | }
|
---|
5024 | break;
|
---|
5025 |
|
---|
5026 | case TIM_TS_ITR2:
|
---|
5027 | {
|
---|
5028 | /* Check the parameter */
|
---|
5029 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
5030 | }
|
---|
5031 | break;
|
---|
5032 |
|
---|
5033 | case TIM_TS_ITR3:
|
---|
5034 | {
|
---|
5035 | /* Check the parameter */
|
---|
5036 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
---|
5037 | }
|
---|
5038 | break;
|
---|
5039 |
|
---|
5040 | default:
|
---|
5041 | break;
|
---|
5042 | }
|
---|
5043 | }
|
---|
5044 |
|
---|
5045 |
|
---|
5046 | /**
|
---|
5047 | * @brief Configure the Polarity and Filter for TI1.
|
---|
5048 | * @param TIMx to select the TIM peripheral.
|
---|
5049 | * @param TIM_ICPolarity : The Input Polarity.
|
---|
5050 | * This parameter can be one of the following values:
|
---|
5051 | * @arg TIM_ICPolarity_Rising
|
---|
5052 | * @arg TIM_ICPolarity_Falling
|
---|
5053 | * @arg TIM_ICPolarity_BothEdge
|
---|
5054 | * @param TIM_ICFilter: Specifies the Input Capture Filter.
|
---|
5055 | * This parameter must be a value between 0x00 and 0x0F.
|
---|
5056 | * @retval None
|
---|
5057 | */
|
---|
5058 | static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
---|
5059 | {
|
---|
5060 | uint32_t tmpccmr1 = 0;
|
---|
5061 | uint32_t tmpccer = 0;
|
---|
5062 |
|
---|
5063 | /* Disable the Channel 1: Reset the CC1E Bit */
|
---|
5064 | tmpccer = TIMx->CCER;
|
---|
5065 | TIMx->CCER &= ~TIM_CCER_CC1E;
|
---|
5066 | tmpccmr1 = TIMx->CCMR1;
|
---|
5067 |
|
---|
5068 | /* Set the filter */
|
---|
5069 | tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
---|
5070 | tmpccmr1 |= (TIM_ICFilter << 4);
|
---|
5071 |
|
---|
5072 | /* Select the Polarity and set the CC1E Bit */
|
---|
5073 | tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
|
---|
5074 | tmpccer |= TIM_ICPolarity;
|
---|
5075 |
|
---|
5076 | /* Write to TIMx CCMR1 and CCER registers */
|
---|
5077 | TIMx->CCMR1 = tmpccmr1;
|
---|
5078 | TIMx->CCER = tmpccer;
|
---|
5079 | }
|
---|
5080 |
|
---|
5081 | /**
|
---|
5082 | * @brief Configure the TI2 as Input.
|
---|
5083 | * @param TIMx to select the TIM peripheral
|
---|
5084 | * @param TIM_ICPolarity : The Input Polarity.
|
---|
5085 | * This parameter can be one of the following values:
|
---|
5086 | * @arg TIM_ICPolarity_Rising
|
---|
5087 | * @arg TIM_ICPolarity_Falling
|
---|
5088 | * @arg TIM_ICPolarity_BothEdge
|
---|
5089 | * @param TIM_ICSelection: specifies the input to be used.
|
---|
5090 | * This parameter can be one of the following values:
|
---|
5091 | * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
|
---|
5092 | * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
|
---|
5093 | * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
|
---|
5094 | * @param TIM_ICFilter: Specifies the Input Capture Filter.
|
---|
5095 | * This parameter must be a value between 0x00 and 0x0F.
|
---|
5096 | * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
|
---|
5097 | * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
|
---|
5098 | * protected against un-initialized filter and polarity values.
|
---|
5099 | * @retval None
|
---|
5100 | */
|
---|
5101 | static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
|
---|
5102 | uint32_t TIM_ICFilter)
|
---|
5103 | {
|
---|
5104 | uint32_t tmpccmr1 = 0;
|
---|
5105 | uint32_t tmpccer = 0;
|
---|
5106 |
|
---|
5107 | /* Disable the Channel 2: Reset the CC2E Bit */
|
---|
5108 | TIMx->CCER &= ~TIM_CCER_CC2E;
|
---|
5109 | tmpccmr1 = TIMx->CCMR1;
|
---|
5110 | tmpccer = TIMx->CCER;
|
---|
5111 |
|
---|
5112 | /* Select the Input */
|
---|
5113 | tmpccmr1 &= ~TIM_CCMR1_CC2S;
|
---|
5114 | tmpccmr1 |= (TIM_ICSelection << 8);
|
---|
5115 |
|
---|
5116 | /* Set the filter */
|
---|
5117 | tmpccmr1 &= ~TIM_CCMR1_IC2F;
|
---|
5118 | tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
|
---|
5119 |
|
---|
5120 | /* Select the Polarity and set the CC2E Bit */
|
---|
5121 | tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
|
---|
5122 | tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
|
---|
5123 |
|
---|
5124 | /* Write to TIMx CCMR1 and CCER registers */
|
---|
5125 | TIMx->CCMR1 = tmpccmr1 ;
|
---|
5126 | TIMx->CCER = tmpccer;
|
---|
5127 | }
|
---|
5128 |
|
---|
5129 | /**
|
---|
5130 | * @brief Configure the Polarity and Filter for TI2.
|
---|
5131 | * @param TIMx to select the TIM peripheral.
|
---|
5132 | * @param TIM_ICPolarity : The Input Polarity.
|
---|
5133 | * This parameter can be one of the following values:
|
---|
5134 | * @arg TIM_ICPolarity_Rising
|
---|
5135 | * @arg TIM_ICPolarity_Falling
|
---|
5136 | * @arg TIM_ICPolarity_BothEdge
|
---|
5137 | * @param TIM_ICFilter: Specifies the Input Capture Filter.
|
---|
5138 | * This parameter must be a value between 0x00 and 0x0F.
|
---|
5139 | * @retval None
|
---|
5140 | */
|
---|
5141 | static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
---|
5142 | {
|
---|
5143 | uint32_t tmpccmr1 = 0;
|
---|
5144 | uint32_t tmpccer = 0;
|
---|
5145 |
|
---|
5146 | /* Disable the Channel 2: Reset the CC2E Bit */
|
---|
5147 | TIMx->CCER &= ~TIM_CCER_CC2E;
|
---|
5148 | tmpccmr1 = TIMx->CCMR1;
|
---|
5149 | tmpccer = TIMx->CCER;
|
---|
5150 |
|
---|
5151 | /* Set the filter */
|
---|
5152 | tmpccmr1 &= ~TIM_CCMR1_IC2F;
|
---|
5153 | tmpccmr1 |= (TIM_ICFilter << 12);
|
---|
5154 |
|
---|
5155 | /* Select the Polarity and set the CC2E Bit */
|
---|
5156 | tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
|
---|
5157 | tmpccer |= (TIM_ICPolarity << 4);
|
---|
5158 |
|
---|
5159 | /* Write to TIMx CCMR1 and CCER registers */
|
---|
5160 | TIMx->CCMR1 = tmpccmr1 ;
|
---|
5161 | TIMx->CCER = tmpccer;
|
---|
5162 | }
|
---|
5163 |
|
---|
5164 | /**
|
---|
5165 | * @brief Configure the TI3 as Input.
|
---|
5166 | * @param TIMx to select the TIM peripheral
|
---|
5167 | * @param TIM_ICPolarity : The Input Polarity.
|
---|
5168 | * This parameter can be one of the following values:
|
---|
5169 | * @arg TIM_ICPolarity_Rising
|
---|
5170 | * @arg TIM_ICPolarity_Falling
|
---|
5171 | * @arg TIM_ICPolarity_BothEdge
|
---|
5172 | * @param TIM_ICSelection: specifies the input to be used.
|
---|
5173 | * This parameter can be one of the following values:
|
---|
5174 | * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
|
---|
5175 | * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
|
---|
5176 | * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
|
---|
5177 | * @param TIM_ICFilter: Specifies the Input Capture Filter.
|
---|
5178 | * This parameter must be a value between 0x00 and 0x0F.
|
---|
5179 | * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
|
---|
5180 | * (on channel4 path) is used as the input signal. Therefore CCMR2 must be
|
---|
5181 | * protected against un-initialized filter and polarity values.
|
---|
5182 | * @retval None
|
---|
5183 | */
|
---|
5184 | static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
|
---|
5185 | uint32_t TIM_ICFilter)
|
---|
5186 | {
|
---|
5187 | uint32_t tmpccmr2 = 0;
|
---|
5188 | uint32_t tmpccer = 0;
|
---|
5189 |
|
---|
5190 | /* Disable the Channel 3: Reset the CC3E Bit */
|
---|
5191 | TIMx->CCER &= ~TIM_CCER_CC3E;
|
---|
5192 | tmpccmr2 = TIMx->CCMR2;
|
---|
5193 | tmpccer = TIMx->CCER;
|
---|
5194 |
|
---|
5195 | /* Select the Input */
|
---|
5196 | tmpccmr2 &= ~TIM_CCMR2_CC3S;
|
---|
5197 | tmpccmr2 |= TIM_ICSelection;
|
---|
5198 |
|
---|
5199 | /* Set the filter */
|
---|
5200 | tmpccmr2 &= ~TIM_CCMR2_IC3F;
|
---|
5201 | tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
|
---|
5202 |
|
---|
5203 | /* Select the Polarity and set the CC3E Bit */
|
---|
5204 | tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
|
---|
5205 | tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
|
---|
5206 |
|
---|
5207 | /* Write to TIMx CCMR2 and CCER registers */
|
---|
5208 | TIMx->CCMR2 = tmpccmr2;
|
---|
5209 | TIMx->CCER = tmpccer;
|
---|
5210 | }
|
---|
5211 |
|
---|
5212 | /**
|
---|
5213 | * @brief Configure the TI4 as Input.
|
---|
5214 | * @param TIMx to select the TIM peripheral
|
---|
5215 | * @param TIM_ICPolarity : The Input Polarity.
|
---|
5216 | * This parameter can be one of the following values:
|
---|
5217 | * @arg TIM_ICPolarity_Rising
|
---|
5218 | * @arg TIM_ICPolarity_Falling
|
---|
5219 | * @arg TIM_ICPolarity_BothEdge
|
---|
5220 | * @param TIM_ICSelection: specifies the input to be used.
|
---|
5221 | * This parameter can be one of the following values:
|
---|
5222 | * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
|
---|
5223 | * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
|
---|
5224 | * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
|
---|
5225 | * @param TIM_ICFilter: Specifies the Input Capture Filter.
|
---|
5226 | * This parameter must be a value between 0x00 and 0x0F.
|
---|
5227 | * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
|
---|
5228 | * (on channel3 path) is used as the input signal. Therefore CCMR2 must be
|
---|
5229 | * protected against un-initialized filter and polarity values.
|
---|
5230 | * @retval None
|
---|
5231 | */
|
---|
5232 | static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
|
---|
5233 | uint32_t TIM_ICFilter)
|
---|
5234 | {
|
---|
5235 | uint32_t tmpccmr2 = 0;
|
---|
5236 | uint32_t tmpccer = 0;
|
---|
5237 |
|
---|
5238 | /* Disable the Channel 4: Reset the CC4E Bit */
|
---|
5239 | TIMx->CCER &= ~TIM_CCER_CC4E;
|
---|
5240 | tmpccmr2 = TIMx->CCMR2;
|
---|
5241 | tmpccer = TIMx->CCER;
|
---|
5242 |
|
---|
5243 | /* Select the Input */
|
---|
5244 | tmpccmr2 &= ~TIM_CCMR2_CC4S;
|
---|
5245 | tmpccmr2 |= (TIM_ICSelection << 8);
|
---|
5246 |
|
---|
5247 | /* Set the filter */
|
---|
5248 | tmpccmr2 &= ~TIM_CCMR2_IC4F;
|
---|
5249 | tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
|
---|
5250 |
|
---|
5251 | /* Select the Polarity and set the CC4E Bit */
|
---|
5252 | tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
|
---|
5253 | tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
|
---|
5254 |
|
---|
5255 | /* Write to TIMx CCMR2 and CCER registers */
|
---|
5256 | TIMx->CCMR2 = tmpccmr2;
|
---|
5257 | TIMx->CCER = tmpccer ;
|
---|
5258 | }
|
---|
5259 |
|
---|
5260 | /**
|
---|
5261 | * @brief Selects the Input Trigger source
|
---|
5262 | * @param TIMx to select the TIM peripheral
|
---|
5263 | * @param TIM_ITRx: The Input Trigger source.
|
---|
5264 | * This parameter can be one of the following values:
|
---|
5265 | * @arg TIM_TS_ITR0: Internal Trigger 0
|
---|
5266 | * @arg TIM_TS_ITR1: Internal Trigger 1
|
---|
5267 | * @arg TIM_TS_ITR2: Internal Trigger 2
|
---|
5268 | * @arg TIM_TS_ITR3: Internal Trigger 3
|
---|
5269 | * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
|
---|
5270 | * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
|
---|
5271 | * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
|
---|
5272 | * @arg TIM_TS_ETRF: External Trigger input
|
---|
5273 | * @retval None
|
---|
5274 | */
|
---|
5275 | static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
|
---|
5276 | {
|
---|
5277 | uint32_t tmpsmcr = 0;
|
---|
5278 |
|
---|
5279 | /* Get the TIMx SMCR register value */
|
---|
5280 | tmpsmcr = TIMx->SMCR;
|
---|
5281 | /* Reset the TS Bits */
|
---|
5282 | tmpsmcr &= ~TIM_SMCR_TS;
|
---|
5283 | /* Set the Input Trigger source and the slave mode*/
|
---|
5284 | tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
|
---|
5285 | /* Write to TIMx SMCR */
|
---|
5286 | TIMx->SMCR = tmpsmcr;
|
---|
5287 | }
|
---|
5288 |
|
---|
5289 | /**
|
---|
5290 | * @brief Configures the TIMx External Trigger (ETR).
|
---|
5291 | * @param TIMx to select the TIM peripheral
|
---|
5292 | * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
|
---|
5293 | * This parameter can be one of the following values:
|
---|
5294 | * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
|
---|
5295 | * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
|
---|
5296 | * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
|
---|
5297 | * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
|
---|
5298 | * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
|
---|
5299 | * This parameter can be one of the following values:
|
---|
5300 | * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
|
---|
5301 | * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
|
---|
5302 | * @param ExtTRGFilter: External Trigger Filter.
|
---|
5303 | * This parameter must be a value between 0x00 and 0x0F
|
---|
5304 | * @retval None
|
---|
5305 | */
|
---|
5306 | static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
|
---|
5307 | uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
|
---|
5308 | {
|
---|
5309 | uint32_t tmpsmcr = 0;
|
---|
5310 |
|
---|
5311 | tmpsmcr = TIMx->SMCR;
|
---|
5312 |
|
---|
5313 | /* Reset the ETR Bits */
|
---|
5314 | tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
---|
5315 |
|
---|
5316 | /* Set the Prescaler, the Filter value and the Polarity */
|
---|
5317 | tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
|
---|
5318 |
|
---|
5319 | /* Write to TIMx SMCR */
|
---|
5320 | TIMx->SMCR = tmpsmcr;
|
---|
5321 | }
|
---|
5322 |
|
---|
5323 | /**
|
---|
5324 | * @}
|
---|
5325 | */
|
---|
5326 |
|
---|
5327 | #endif /* HAL_TIM_MODULE_ENABLED */
|
---|
5328 | /**
|
---|
5329 | * @}
|
---|
5330 | */
|
---|
5331 |
|
---|
5332 | /**
|
---|
5333 | * @}
|
---|
5334 | */
|
---|
5335 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
---|