1 | /**
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2 | ******************************************************************************
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3 | * @file stm32f4xx_hal_sram.c
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4 | * @author MCD Application Team
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5 | * @version V1.4.1
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6 | * @date 09-October-2015
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7 | * @brief SRAM HAL module driver.
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8 | * This file provides a generic firmware to drive SRAM memories
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9 | * mounted as external device.
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10 | *
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11 | @verbatim
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12 | ==============================================================================
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13 | ##### How to use this driver #####
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14 | ==============================================================================
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15 | [..]
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16 | This driver is a generic layered driver which contains a set of APIs used to
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17 | control SRAM memories. It uses the FMC layer functions to interface
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18 | with SRAM devices.
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19 | The following sequence should be followed to configure the FMC/FSMC to interface
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20 | with SRAM/PSRAM memories:
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21 |
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22 | (#) Declare a SRAM_HandleTypeDef handle structure, for example:
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23 | SRAM_HandleTypeDef hsram; and:
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24 |
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25 | (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
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26 | values of the structure member.
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27 |
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28 | (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
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29 | base register instance for NOR or SRAM device
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30 |
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31 | (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
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32 | base register instance for NOR or SRAM extended mode
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33 |
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34 | (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
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35 | mode timings; for example:
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36 | FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
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37 | and fill its fields with the allowed values of the structure member.
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38 |
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39 | (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
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40 | performs the following sequence:
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41 |
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42 | (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
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43 | (##) Control register configuration using the FMC NORSRAM interface function
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44 | FMC_NORSRAM_Init()
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45 | (##) Timing register configuration using the FMC NORSRAM interface function
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46 | FMC_NORSRAM_Timing_Init()
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47 | (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
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48 | FMC_NORSRAM_Extended_Timing_Init()
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49 | (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
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50 |
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51 | (#) At this stage you can perform read/write accesses from/to the memory connected
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52 | to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
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53 | following APIs:
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54 | (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
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55 | (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
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56 |
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57 | (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
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58 | HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
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59 |
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60 | (#) You can continuously monitor the SRAM device HAL state by calling the function
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61 | HAL_SRAM_GetState()
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62 |
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63 | @endverbatim
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64 | ******************************************************************************
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65 | * @attention
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66 | *
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67 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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68 | *
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69 | * Redistribution and use in source and binary forms, with or without modification,
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70 | * are permitted provided that the following conditions are met:
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71 | * 1. Redistributions of source code must retain the above copyright notice,
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72 | * this list of conditions and the following disclaimer.
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73 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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74 | * this list of conditions and the following disclaimer in the documentation
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75 | * and/or other materials provided with the distribution.
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76 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
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77 | * may be used to endorse or promote products derived from this software
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78 | * without specific prior written permission.
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79 | *
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80 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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81 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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82 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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83 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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84 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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85 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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86 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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87 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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88 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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89 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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90 | *
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91 | ******************************************************************************
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92 | */
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93 |
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94 | /* Includes ------------------------------------------------------------------*/
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95 | #include "stm32f4xx_hal.h"
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96 |
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97 | /** @addtogroup STM32F4xx_HAL_Driver
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98 | * @{
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99 | */
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100 |
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101 | /** @defgroup SRAM SRAM
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102 | * @brief SRAM driver modules
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103 | * @{
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104 | */
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105 | #ifdef HAL_SRAM_MODULE_ENABLED
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106 |
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107 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
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108 | defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
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109 | defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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110 |
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111 | /* Private typedef -----------------------------------------------------------*/
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112 | /* Private define ------------------------------------------------------------*/
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113 | /* Private macro -------------------------------------------------------------*/
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114 | /* Private variables ---------------------------------------------------------*/
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115 | /* Private functions ---------------------------------------------------------*/
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116 |
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117 | /* Exported functions --------------------------------------------------------*/
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118 | /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
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119 | * @{
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120 | */
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121 | /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
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122 | * @brief Initialization and Configuration functions
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123 | *
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124 | @verbatim
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125 | ==============================================================================
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126 | ##### SRAM Initialization and de_initialization functions #####
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127 | ==============================================================================
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128 | [..] This section provides functions allowing to initialize/de-initialize
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129 | the SRAM memory
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130 |
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131 | @endverbatim
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132 | * @{
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133 | */
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134 |
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135 | /**
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136 | * @brief Performs the SRAM device initialization sequence
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137 | * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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138 | * the configuration information for SRAM module.
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139 | * @param Timing: Pointer to SRAM control timing structure
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140 | * @param ExtTiming: Pointer to SRAM extended mode timing structure
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141 | * @retval HAL status
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142 | */
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143 | HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
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144 | {
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145 | /* Check the SRAM handle parameter */
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146 | if(hsram == NULL)
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147 | {
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148 | return HAL_ERROR;
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149 | }
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150 |
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151 | if(hsram->State == HAL_SRAM_STATE_RESET)
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152 | {
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153 | /* Allocate lock resource and initialize it */
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154 | hsram->Lock = HAL_UNLOCKED;
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155 | /* Initialize the low level hardware (MSP) */
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156 | HAL_SRAM_MspInit(hsram);
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157 | }
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158 |
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159 | /* Initialize SRAM control Interface */
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160 | FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
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161 |
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162 | /* Initialize SRAM timing Interface */
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163 | FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
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164 |
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165 | /* Initialize SRAM extended mode timing Interface */
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166 | FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
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167 |
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168 | /* Enable the NORSRAM device */
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169 | __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
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170 |
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171 | return HAL_OK;
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172 | }
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173 |
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174 | /**
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175 | * @brief Performs the SRAM device De-initialization sequence.
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176 | * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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177 | * the configuration information for SRAM module.
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178 | * @retval HAL status
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179 | */
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180 | HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
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181 | {
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182 | /* De-Initialize the low level hardware (MSP) */
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183 | HAL_SRAM_MspDeInit(hsram);
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184 |
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185 | /* Configure the SRAM registers with their reset values */
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186 | FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
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187 |
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188 | hsram->State = HAL_SRAM_STATE_RESET;
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189 |
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190 | /* Release Lock */
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191 | __HAL_UNLOCK(hsram);
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192 |
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193 | return HAL_OK;
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194 | }
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195 |
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196 | /**
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197 | * @brief SRAM MSP Init.
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198 | * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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199 | * the configuration information for SRAM module.
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200 | * @retval None
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201 | */
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202 | __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
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203 | {
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204 | /* NOTE : This function Should not be modified, when the callback is needed,
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205 | the HAL_SRAM_MspInit could be implemented in the user file
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206 | */
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207 | }
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208 |
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209 | /**
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210 | * @brief SRAM MSP DeInit.
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211 | * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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212 | * the configuration information for SRAM module.
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213 | * @retval None
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214 | */
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215 | __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
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216 | {
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217 | /* NOTE : This function Should not be modified, when the callback is needed,
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218 | the HAL_SRAM_MspDeInit could be implemented in the user file
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219 | */
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220 | }
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221 |
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222 | /**
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223 | * @brief DMA transfer complete callback.
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224 | * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
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225 | * the configuration information for SRAM module.
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226 | * @retval None
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227 | */
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228 | __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
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229 | {
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230 | /* NOTE : This function Should not be modified, when the callback is needed,
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231 | the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
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232 | */
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233 | }
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234 |
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235 | /**
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236 | * @brief DMA transfer complete error callback.
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237 | * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
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238 | * the configuration information for SRAM module.
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239 | * @retval None
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240 | */
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241 | __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
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242 | {
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243 | /* NOTE : This function Should not be modified, when the callback is needed,
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244 | the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
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245 | */
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246 | }
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247 |
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248 | /**
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249 | * @}
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250 | */
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251 |
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252 | /** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions
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253 | * @brief Input Output and memory control functions
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254 | *
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255 | @verbatim
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256 | ==============================================================================
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257 | ##### SRAM Input and Output functions #####
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258 | ==============================================================================
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259 | [..]
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260 | This section provides functions allowing to use and control the SRAM memory
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261 |
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262 | @endverbatim
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263 | * @{
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264 | */
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265 |
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266 | /**
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267 | * @brief Reads 8-bit buffer from SRAM memory.
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268 | * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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269 | * the configuration information for SRAM module.
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270 | * @param pAddress: Pointer to read start address
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271 | * @param pDstBuffer: Pointer to destination buffer
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272 | * @param BufferSize: Size of the buffer to read from memory
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273 | * @retval HAL status
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274 | */
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275 | HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
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276 | {
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277 | __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
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278 |
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279 | /* Process Locked */
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280 | __HAL_LOCK(hsram);
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281 |
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282 | /* Update the SRAM controller state */
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283 | hsram->State = HAL_SRAM_STATE_BUSY;
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284 |
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285 | /* Read data from memory */
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286 | for(; BufferSize != 0; BufferSize--)
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287 | {
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288 | *pDstBuffer = *(__IO uint8_t *)pSramAddress;
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289 | pDstBuffer++;
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290 | pSramAddress++;
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291 | }
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292 |
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293 | /* Update the SRAM controller state */
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294 | hsram->State = HAL_SRAM_STATE_READY;
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295 |
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296 | /* Process unlocked */
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297 | __HAL_UNLOCK(hsram);
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298 |
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299 | return HAL_OK;
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300 | }
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301 |
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302 | /**
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303 | * @brief Writes 8-bit buffer to SRAM memory.
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304 | * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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305 | * the configuration information for SRAM module.
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306 | * @param pAddress: Pointer to write start address
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307 | * @param pSrcBuffer: Pointer to source buffer to write
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308 | * @param BufferSize: Size of the buffer to write to memory
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309 | * @retval HAL status
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310 | */
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311 | HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
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312 | {
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313 | __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
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314 |
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315 | /* Check the SRAM controller state */
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316 | if(hsram->State == HAL_SRAM_STATE_PROTECTED)
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317 | {
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318 | return HAL_ERROR;
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319 | }
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320 |
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321 | /* Process Locked */
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322 | __HAL_LOCK(hsram);
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323 |
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324 | /* Update the SRAM controller state */
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325 | hsram->State = HAL_SRAM_STATE_BUSY;
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326 |
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327 | /* Write data to memory */
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328 | for(; BufferSize != 0; BufferSize--)
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329 | {
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330 | *(__IO uint8_t *)pSramAddress = *pSrcBuffer;
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331 | pSrcBuffer++;
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332 | pSramAddress++;
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333 | }
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334 |
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335 | /* Update the SRAM controller state */
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336 | hsram->State = HAL_SRAM_STATE_READY;
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337 |
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338 | /* Process unlocked */
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339 | __HAL_UNLOCK(hsram);
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340 |
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341 | return HAL_OK;
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342 | }
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343 |
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344 | /**
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345 | * @brief Reads 16-bit buffer from SRAM memory.
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346 | * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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347 | * the configuration information for SRAM module.
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348 | * @param pAddress: Pointer to read start address
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349 | * @param pDstBuffer: Pointer to destination buffer
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350 | * @param BufferSize: Size of the buffer to read from memory
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351 | * @retval HAL status
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352 | */
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353 | HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
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354 | {
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355 | __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
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356 |
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357 | /* Process Locked */
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358 | __HAL_LOCK(hsram);
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359 |
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360 | /* Update the SRAM controller state */
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361 | hsram->State = HAL_SRAM_STATE_BUSY;
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362 |
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363 | /* Read data from memory */
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364 | for(; BufferSize != 0; BufferSize--)
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365 | {
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366 | *pDstBuffer = *(__IO uint16_t *)pSramAddress;
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367 | pDstBuffer++;
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368 | pSramAddress++;
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369 | }
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370 |
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371 | /* Update the SRAM controller state */
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372 | hsram->State = HAL_SRAM_STATE_READY;
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373 |
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374 | /* Process unlocked */
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375 | __HAL_UNLOCK(hsram);
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376 |
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377 | return HAL_OK;
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378 | }
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379 |
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380 | /**
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381 | * @brief Writes 16-bit buffer to SRAM memory.
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382 | * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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383 | * the configuration information for SRAM module.
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384 | * @param pAddress: Pointer to write start address
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385 | * @param pSrcBuffer: Pointer to source buffer to write
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386 | * @param BufferSize: Size of the buffer to write to memory
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387 | * @retval HAL status
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388 | */
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389 | HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
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390 | {
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391 | __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
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392 |
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393 | /* Check the SRAM controller state */
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394 | if(hsram->State == HAL_SRAM_STATE_PROTECTED)
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395 | {
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396 | return HAL_ERROR;
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397 | }
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398 |
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399 | /* Process Locked */
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400 | __HAL_LOCK(hsram);
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401 |
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402 | /* Update the SRAM controller state */
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403 | hsram->State = HAL_SRAM_STATE_BUSY;
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404 |
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405 | /* Write data to memory */
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406 | for(; BufferSize != 0; BufferSize--)
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407 | {
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408 | *(__IO uint16_t *)pSramAddress = *pSrcBuffer;
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409 | pSrcBuffer++;
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410 | pSramAddress++;
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411 | }
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412 |
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413 | /* Update the SRAM controller state */
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414 | hsram->State = HAL_SRAM_STATE_READY;
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415 |
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416 | /* Process unlocked */
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417 | __HAL_UNLOCK(hsram);
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418 |
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419 | return HAL_OK;
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420 | }
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421 |
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422 | /**
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423 | * @brief Reads 32-bit buffer from SRAM memory.
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424 | * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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425 | * the configuration information for SRAM module.
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426 | * @param pAddress: Pointer to read start address
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427 | * @param pDstBuffer: Pointer to destination buffer
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428 | * @param BufferSize: Size of the buffer to read from memory
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429 | * @retval HAL status
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430 | */
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431 | HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
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432 | {
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433 | /* Process Locked */
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434 | __HAL_LOCK(hsram);
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435 |
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436 | /* Update the SRAM controller state */
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437 | hsram->State = HAL_SRAM_STATE_BUSY;
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438 |
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439 | /* Read data from memory */
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440 | for(; BufferSize != 0; BufferSize--)
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441 | {
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442 | *pDstBuffer = *(__IO uint32_t *)pAddress;
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443 | pDstBuffer++;
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444 | pAddress++;
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445 | }
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446 |
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447 | /* Update the SRAM controller state */
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448 | hsram->State = HAL_SRAM_STATE_READY;
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449 |
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450 | /* Process unlocked */
|
---|
451 | __HAL_UNLOCK(hsram);
|
---|
452 |
|
---|
453 | return HAL_OK;
|
---|
454 | }
|
---|
455 |
|
---|
456 | /**
|
---|
457 | * @brief Writes 32-bit buffer to SRAM memory.
|
---|
458 | * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
---|
459 | * the configuration information for SRAM module.
|
---|
460 | * @param pAddress: Pointer to write start address
|
---|
461 | * @param pSrcBuffer: Pointer to source buffer to write
|
---|
462 | * @param BufferSize: Size of the buffer to write to memory
|
---|
463 | * @retval HAL status
|
---|
464 | */
|
---|
465 | HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
---|
466 | {
|
---|
467 | /* Check the SRAM controller state */
|
---|
468 | if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
---|
469 | {
|
---|
470 | return HAL_ERROR;
|
---|
471 | }
|
---|
472 |
|
---|
473 | /* Process Locked */
|
---|
474 | __HAL_LOCK(hsram);
|
---|
475 |
|
---|
476 | /* Update the SRAM controller state */
|
---|
477 | hsram->State = HAL_SRAM_STATE_BUSY;
|
---|
478 |
|
---|
479 | /* Write data to memory */
|
---|
480 | for(; BufferSize != 0; BufferSize--)
|
---|
481 | {
|
---|
482 | *(__IO uint32_t *)pAddress = *pSrcBuffer;
|
---|
483 | pSrcBuffer++;
|
---|
484 | pAddress++;
|
---|
485 | }
|
---|
486 |
|
---|
487 | /* Update the SRAM controller state */
|
---|
488 | hsram->State = HAL_SRAM_STATE_READY;
|
---|
489 |
|
---|
490 | /* Process unlocked */
|
---|
491 | __HAL_UNLOCK(hsram);
|
---|
492 |
|
---|
493 | return HAL_OK;
|
---|
494 | }
|
---|
495 |
|
---|
496 | /**
|
---|
497 | * @brief Reads a Words data from the SRAM memory using DMA transfer.
|
---|
498 | * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
---|
499 | * the configuration information for SRAM module.
|
---|
500 | * @param pAddress: Pointer to read start address
|
---|
501 | * @param pDstBuffer: Pointer to destination buffer
|
---|
502 | * @param BufferSize: Size of the buffer to read from memory
|
---|
503 | * @retval HAL status
|
---|
504 | */
|
---|
505 | HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
---|
506 | {
|
---|
507 | /* Process Locked */
|
---|
508 | __HAL_LOCK(hsram);
|
---|
509 |
|
---|
510 | /* Update the SRAM controller state */
|
---|
511 | hsram->State = HAL_SRAM_STATE_BUSY;
|
---|
512 |
|
---|
513 | /* Configure DMA user callbacks */
|
---|
514 | hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
|
---|
515 | hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
|
---|
516 |
|
---|
517 | /* Enable the DMA Stream */
|
---|
518 | HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
|
---|
519 |
|
---|
520 | /* Update the SRAM controller state */
|
---|
521 | hsram->State = HAL_SRAM_STATE_READY;
|
---|
522 |
|
---|
523 | /* Process unlocked */
|
---|
524 | __HAL_UNLOCK(hsram);
|
---|
525 |
|
---|
526 | return HAL_OK;
|
---|
527 | }
|
---|
528 |
|
---|
529 | /**
|
---|
530 | * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
|
---|
531 | * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
---|
532 | * the configuration information for SRAM module.
|
---|
533 | * @param pAddress: Pointer to write start address
|
---|
534 | * @param pSrcBuffer: Pointer to source buffer to write
|
---|
535 | * @param BufferSize: Size of the buffer to write to memory
|
---|
536 | * @retval HAL status
|
---|
537 | */
|
---|
538 | HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
---|
539 | {
|
---|
540 | /* Check the SRAM controller state */
|
---|
541 | if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
---|
542 | {
|
---|
543 | return HAL_ERROR;
|
---|
544 | }
|
---|
545 |
|
---|
546 | /* Process Locked */
|
---|
547 | __HAL_LOCK(hsram);
|
---|
548 |
|
---|
549 | /* Update the SRAM controller state */
|
---|
550 | hsram->State = HAL_SRAM_STATE_BUSY;
|
---|
551 |
|
---|
552 | /* Configure DMA user callbacks */
|
---|
553 | hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
|
---|
554 | hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
|
---|
555 |
|
---|
556 | /* Enable the DMA Stream */
|
---|
557 | HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
|
---|
558 |
|
---|
559 | /* Update the SRAM controller state */
|
---|
560 | hsram->State = HAL_SRAM_STATE_READY;
|
---|
561 |
|
---|
562 | /* Process unlocked */
|
---|
563 | __HAL_UNLOCK(hsram);
|
---|
564 |
|
---|
565 | return HAL_OK;
|
---|
566 | }
|
---|
567 |
|
---|
568 | /**
|
---|
569 | * @}
|
---|
570 | */
|
---|
571 |
|
---|
572 | /** @defgroup SRAM_Exported_Functions_Group3 Control functions
|
---|
573 | * @brief management functions
|
---|
574 | *
|
---|
575 | @verbatim
|
---|
576 | ==============================================================================
|
---|
577 | ##### SRAM Control functions #####
|
---|
578 | ==============================================================================
|
---|
579 | [..]
|
---|
580 | This subsection provides a set of functions allowing to control dynamically
|
---|
581 | the SRAM interface.
|
---|
582 |
|
---|
583 | @endverbatim
|
---|
584 | * @{
|
---|
585 | */
|
---|
586 |
|
---|
587 | /**
|
---|
588 | * @brief Enables dynamically SRAM write operation.
|
---|
589 | * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
---|
590 | * the configuration information for SRAM module.
|
---|
591 | * @retval HAL status
|
---|
592 | */
|
---|
593 | HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
|
---|
594 | {
|
---|
595 | /* Process Locked */
|
---|
596 | __HAL_LOCK(hsram);
|
---|
597 |
|
---|
598 | /* Enable write operation */
|
---|
599 | FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
|
---|
600 |
|
---|
601 | /* Update the SRAM controller state */
|
---|
602 | hsram->State = HAL_SRAM_STATE_READY;
|
---|
603 |
|
---|
604 | /* Process unlocked */
|
---|
605 | __HAL_UNLOCK(hsram);
|
---|
606 |
|
---|
607 | return HAL_OK;
|
---|
608 | }
|
---|
609 |
|
---|
610 | /**
|
---|
611 | * @brief Disables dynamically SRAM write operation.
|
---|
612 | * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
---|
613 | * the configuration information for SRAM module.
|
---|
614 | * @retval HAL status
|
---|
615 | */
|
---|
616 | HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
|
---|
617 | {
|
---|
618 | /* Process Locked */
|
---|
619 | __HAL_LOCK(hsram);
|
---|
620 |
|
---|
621 | /* Update the SRAM controller state */
|
---|
622 | hsram->State = HAL_SRAM_STATE_BUSY;
|
---|
623 |
|
---|
624 | /* Disable write operation */
|
---|
625 | FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
|
---|
626 |
|
---|
627 | /* Update the SRAM controller state */
|
---|
628 | hsram->State = HAL_SRAM_STATE_PROTECTED;
|
---|
629 |
|
---|
630 | /* Process unlocked */
|
---|
631 | __HAL_UNLOCK(hsram);
|
---|
632 |
|
---|
633 | return HAL_OK;
|
---|
634 | }
|
---|
635 |
|
---|
636 | /**
|
---|
637 | * @}
|
---|
638 | */
|
---|
639 |
|
---|
640 | /** @defgroup SRAM_Exported_Functions_Group4 State functions
|
---|
641 | * @brief Peripheral State functions
|
---|
642 | *
|
---|
643 | @verbatim
|
---|
644 | ==============================================================================
|
---|
645 | ##### SRAM State functions #####
|
---|
646 | ==============================================================================
|
---|
647 | [..]
|
---|
648 | This subsection permits to get in run-time the status of the SRAM controller
|
---|
649 | and the data flow.
|
---|
650 |
|
---|
651 | @endverbatim
|
---|
652 | * @{
|
---|
653 | */
|
---|
654 |
|
---|
655 | /**
|
---|
656 | * @brief Returns the SRAM controller state
|
---|
657 | * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
---|
658 | * the configuration information for SRAM module.
|
---|
659 | * @retval HAL state
|
---|
660 | */
|
---|
661 | HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
|
---|
662 | {
|
---|
663 | return hsram->State;
|
---|
664 | }
|
---|
665 | /**
|
---|
666 | * @}
|
---|
667 | */
|
---|
668 |
|
---|
669 | /**
|
---|
670 | * @}
|
---|
671 | */
|
---|
672 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
|
---|
673 | STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
|
---|
674 | #endif /* HAL_SRAM_MODULE_ENABLED */
|
---|
675 | /**
|
---|
676 | * @}
|
---|
677 | */
|
---|
678 |
|
---|
679 | /**
|
---|
680 | * @}
|
---|
681 | */
|
---|
682 |
|
---|
683 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
---|