[303] | 1 | /**
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| 2 | ******************************************************************************
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| 3 | * @file stm32f4xx_hal_sdram.c
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| 4 | * @author MCD Application Team
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| 5 | * @version V1.4.1
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| 6 | * @date 09-October-2015
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| 7 | * @brief SDRAM HAL module driver.
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| 8 | * This file provides a generic firmware to drive SDRAM memories mounted
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| 9 | * as external device.
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| 10 | *
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| 11 | @verbatim
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| 12 | ==============================================================================
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| 13 | ##### How to use this driver #####
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| 14 | ==============================================================================
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| 15 | [..]
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| 16 | This driver is a generic layered driver which contains a set of APIs used to
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| 17 | control SDRAM memories. It uses the FMC layer functions to interface
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| 18 | with SDRAM devices.
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| 19 | The following sequence should be followed to configure the FMC to interface
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| 20 | with SDRAM memories:
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| 21 |
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| 22 | (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
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| 23 | SDRAM_HandleTypeDef hdsram
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| 24 |
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| 25 | (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
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| 26 | values of the structure member.
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| 27 |
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| 28 | (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
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| 29 | base register instance for NOR or SDRAM device
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| 30 |
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| 31 | (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
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| 32 | FMC_SDRAM_TimingTypeDef Timing;
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| 33 | and fill its fields with the allowed values of the structure member.
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| 34 |
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| 35 | (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
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| 36 | performs the following sequence:
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| 37 |
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| 38 | (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
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| 39 | (##) Control register configuration using the FMC SDRAM interface function
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| 40 | FMC_SDRAM_Init()
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| 41 | (##) Timing register configuration using the FMC SDRAM interface function
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| 42 | FMC_SDRAM_Timing_Init()
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| 43 | (##) Program the SDRAM external device by applying its initialization sequence
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| 44 | according to the device plugged in your hardware. This step is mandatory
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| 45 | for accessing the SDRAM device.
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| 46 |
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| 47 | (#) At this stage you can perform read/write accesses from/to the memory connected
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| 48 | to the SDRAM Bank. You can perform either polling or DMA transfer using the
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| 49 | following APIs:
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| 50 | (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
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| 51 | (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
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| 52 |
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| 53 | (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
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| 54 | HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
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| 55 | the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
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| 56 | device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
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| 57 | structure.
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| 58 |
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| 59 | (#) You can continuously monitor the SDRAM device HAL state by calling the function
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| 60 | HAL_SDRAM_GetState()
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| 61 |
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| 62 | @endverbatim
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| 63 | ******************************************************************************
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| 64 | * @attention
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| 65 | *
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| 66 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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| 67 | *
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| 68 | * Redistribution and use in source and binary forms, with or without modification,
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| 69 | * are permitted provided that the following conditions are met:
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| 70 | * 1. Redistributions of source code must retain the above copyright notice,
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| 71 | * this list of conditions and the following disclaimer.
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| 72 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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| 73 | * this list of conditions and the following disclaimer in the documentation
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| 74 | * and/or other materials provided with the distribution.
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| 75 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
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| 76 | * may be used to endorse or promote products derived from this software
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| 77 | * without specific prior written permission.
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| 78 | *
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| 79 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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| 80 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| 81 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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| 82 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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| 83 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 84 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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| 85 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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| 86 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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| 87 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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| 88 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 89 | *
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| 90 | ******************************************************************************
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| 91 | */
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| 92 |
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| 93 | /* Includes ------------------------------------------------------------------*/
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| 94 | #include "stm32f4xx_hal.h"
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| 95 |
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| 96 | /** @addtogroup STM32F4xx_HAL_Driver
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| 97 | * @{
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| 98 | */
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| 99 |
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| 100 | /** @defgroup SDRAM SDRAM
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| 101 | * @brief SDRAM driver modules
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| 102 | * @{
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| 103 | */
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| 104 | #ifdef HAL_SDRAM_MODULE_ENABLED
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| 105 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
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| 106 | defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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| 107 |
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| 108 | /* Private typedef -----------------------------------------------------------*/
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| 109 | /* Private define ------------------------------------------------------------*/
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| 110 | /* Private macro -------------------------------------------------------------*/
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| 111 | /* Private variables ---------------------------------------------------------*/
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| 112 | /* Private functions ---------------------------------------------------------*/
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| 113 | /* Exported functions --------------------------------------------------------*/
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| 114 | /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
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| 115 | * @{
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| 116 | */
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| 117 |
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| 118 | /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
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| 119 | * @brief Initialization and Configuration functions
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| 120 | *
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| 121 | @verbatim
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| 122 | ==============================================================================
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| 123 | ##### SDRAM Initialization and de_initialization functions #####
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| 124 | ==============================================================================
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| 125 | [..]
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| 126 | This section provides functions allowing to initialize/de-initialize
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| 127 | the SDRAM memory
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| 128 |
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| 129 | @endverbatim
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| 130 | * @{
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| 131 | */
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| 132 |
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| 133 | /**
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| 134 | * @brief Performs the SDRAM device initialization sequence.
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| 135 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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| 136 | * the configuration information for SDRAM module.
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| 137 | * @param Timing: Pointer to SDRAM control timing structure
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| 138 | * @retval HAL status
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| 139 | */
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| 140 | HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
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| 141 | {
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| 142 | /* Check the SDRAM handle parameter */
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| 143 | if(hsdram == NULL)
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| 144 | {
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| 145 | return HAL_ERROR;
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| 146 | }
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| 147 |
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| 148 | if(hsdram->State == HAL_SDRAM_STATE_RESET)
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| 149 | {
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| 150 | /* Allocate lock resource and initialize it */
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| 151 | hsdram->Lock = HAL_UNLOCKED;
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| 152 | /* Initialize the low level hardware (MSP) */
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| 153 | HAL_SDRAM_MspInit(hsdram);
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| 154 | }
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| 155 |
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| 156 | /* Initialize the SDRAM controller state */
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| 157 | hsdram->State = HAL_SDRAM_STATE_BUSY;
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| 158 |
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| 159 | /* Initialize SDRAM control Interface */
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| 160 | FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
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| 161 |
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| 162 | /* Initialize SDRAM timing Interface */
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| 163 | FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
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| 164 |
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| 165 | /* Update the SDRAM controller state */
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| 166 | hsdram->State = HAL_SDRAM_STATE_READY;
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| 167 |
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| 168 | return HAL_OK;
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| 169 | }
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| 170 |
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| 171 | /**
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| 172 | * @brief Perform the SDRAM device initialization sequence.
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| 173 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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| 174 | * the configuration information for SDRAM module.
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| 175 | * @retval HAL status
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| 176 | */
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| 177 | HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
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| 178 | {
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| 179 | /* Initialize the low level hardware (MSP) */
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| 180 | HAL_SDRAM_MspDeInit(hsdram);
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| 181 |
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| 182 | /* Configure the SDRAM registers with their reset values */
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| 183 | FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
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| 184 |
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| 185 | /* Reset the SDRAM controller state */
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| 186 | hsdram->State = HAL_SDRAM_STATE_RESET;
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| 187 |
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| 188 | /* Release Lock */
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| 189 | __HAL_UNLOCK(hsdram);
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| 190 |
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| 191 | return HAL_OK;
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| 192 | }
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| 193 |
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| 194 | /**
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| 195 | * @brief SDRAM MSP Init.
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| 196 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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| 197 | * the configuration information for SDRAM module.
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| 198 | * @retval None
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| 199 | */
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| 200 | __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
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| 201 | {
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| 202 | /* NOTE: This function Should not be modified, when the callback is needed,
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| 203 | the HAL_SDRAM_MspInit could be implemented in the user file
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| 204 | */
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| 205 | }
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| 206 |
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| 207 | /**
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| 208 | * @brief SDRAM MSP DeInit.
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| 209 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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| 210 | * the configuration information for SDRAM module.
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| 211 | * @retval None
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| 212 | */
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| 213 | __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
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| 214 | {
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| 215 | /* NOTE: This function Should not be modified, when the callback is needed,
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| 216 | the HAL_SDRAM_MspDeInit could be implemented in the user file
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| 217 | */
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| 218 | }
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| 219 |
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| 220 | /**
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| 221 | * @brief This function handles SDRAM refresh error interrupt request.
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| 222 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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| 223 | * the configuration information for SDRAM module.
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| 224 | * @retval HAL status
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| 225 | */
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| 226 | void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
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| 227 | {
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| 228 | /* Check SDRAM interrupt Rising edge flag */
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| 229 | if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
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| 230 | {
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| 231 | /* SDRAM refresh error interrupt callback */
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| 232 | HAL_SDRAM_RefreshErrorCallback(hsdram);
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| 233 |
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| 234 | /* Clear SDRAM refresh error interrupt pending bit */
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| 235 | __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
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| 236 | }
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| 237 | }
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| 238 |
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| 239 | /**
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| 240 | * @brief SDRAM Refresh error callback.
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| 241 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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| 242 | * the configuration information for SDRAM module.
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| 243 | * @retval None
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| 244 | */
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| 245 | __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
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| 246 | {
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| 247 | /* NOTE: This function Should not be modified, when the callback is needed,
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| 248 | the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
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| 249 | */
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| 250 | }
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| 251 |
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| 252 | /**
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| 253 | * @brief DMA transfer complete callback.
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| 254 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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| 255 | * the configuration information for the specified DMA module.
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| 256 | * @retval None
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| 257 | */
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| 258 | __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
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| 259 | {
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| 260 | /* NOTE: This function Should not be modified, when the callback is needed,
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| 261 | the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
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| 262 | */
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| 263 | }
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| 264 |
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| 265 | /**
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| 266 | * @brief DMA transfer complete error callback.
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| 267 | * @param hdma: DMA handle
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| 268 | * @retval None
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| 269 | */
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| 270 | __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
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| 271 | {
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| 272 | /* NOTE: This function Should not be modified, when the callback is needed,
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| 273 | the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
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| 274 | */
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| 275 | }
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| 276 | /**
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| 277 | * @}
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| 278 | */
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| 279 |
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| 280 | /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
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| 281 | * @brief Input Output and memory control functions
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| 282 | *
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| 283 | @verbatim
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| 284 | ==============================================================================
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| 285 | ##### SDRAM Input and Output functions #####
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| 286 | ==============================================================================
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| 287 | [..]
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| 288 | This section provides functions allowing to use and control the SDRAM memory
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| 289 |
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| 290 | @endverbatim
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| 291 | * @{
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| 292 | */
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| 293 |
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| 294 | /**
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| 295 | * @brief Reads 8-bit data buffer from the SDRAM memory.
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| 296 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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| 297 | * the configuration information for SDRAM module.
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| 298 | * @param pAddress: Pointer to read start address
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| 299 | * @param pDstBuffer: Pointer to destination buffer
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| 300 | * @param BufferSize: Size of the buffer to read from memory
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| 301 | * @retval HAL status
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| 302 | */
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| 303 | HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
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| 304 | {
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| 305 | __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
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| 306 |
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| 307 | /* Process Locked */
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| 308 | __HAL_LOCK(hsdram);
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| 309 |
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| 310 | /* Check the SDRAM controller state */
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| 311 | if(hsdram->State == HAL_SDRAM_STATE_BUSY)
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| 312 | {
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| 313 | return HAL_BUSY;
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| 314 | }
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| 315 | else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
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| 316 | {
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| 317 | return HAL_ERROR;
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| 318 | }
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| 319 |
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| 320 | /* Read data from source */
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| 321 | for(; BufferSize != 0; BufferSize--)
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| 322 | {
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| 323 | *pDstBuffer = *(__IO uint8_t *)pSdramAddress;
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| 324 | pDstBuffer++;
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| 325 | pSdramAddress++;
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| 326 | }
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| 327 |
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| 328 | /* Process Unlocked */
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| 329 | __HAL_UNLOCK(hsdram);
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| 330 |
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| 331 | return HAL_OK;
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| 332 | }
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| 333 |
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| 334 | /**
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| 335 | * @brief Writes 8-bit data buffer to SDRAM memory.
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| 336 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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| 337 | * the configuration information for SDRAM module.
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| 338 | * @param pAddress: Pointer to write start address
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| 339 | * @param pSrcBuffer: Pointer to source buffer to write
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| 340 | * @param BufferSize: Size of the buffer to write to memory
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| 341 | * @retval HAL status
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| 342 | */
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| 343 | HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
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| 344 | {
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| 345 | __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
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| 346 | uint32_t tmp = 0;
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| 347 |
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| 348 | /* Process Locked */
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| 349 | __HAL_LOCK(hsdram);
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| 350 |
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| 351 | /* Check the SDRAM controller state */
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| 352 | tmp = hsdram->State;
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| 353 |
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| 354 | if(tmp == HAL_SDRAM_STATE_BUSY)
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| 355 | {
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| 356 | return HAL_BUSY;
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| 357 | }
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| 358 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
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| 359 | {
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| 360 | return HAL_ERROR;
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| 361 | }
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| 362 |
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| 363 | /* Write data to memory */
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| 364 | for(; BufferSize != 0; BufferSize--)
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| 365 | {
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| 366 | *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
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| 367 | pSrcBuffer++;
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| 368 | pSdramAddress++;
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| 369 | }
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| 370 |
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| 371 | /* Process Unlocked */
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| 372 | __HAL_UNLOCK(hsdram);
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| 373 |
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| 374 | return HAL_OK;
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| 375 | }
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| 376 |
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| 377 | /**
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| 378 | * @brief Reads 16-bit data buffer from the SDRAM memory.
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| 379 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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| 380 | * the configuration information for SDRAM module.
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| 381 | * @param pAddress: Pointer to read start address
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| 382 | * @param pDstBuffer: Pointer to destination buffer
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| 383 | * @param BufferSize: Size of the buffer to read from memory
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| 384 | * @retval HAL status
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| 385 | */
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| 386 | HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
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| 387 | {
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| 388 | __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
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| 389 |
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| 390 | /* Process Locked */
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| 391 | __HAL_LOCK(hsdram);
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| 392 |
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| 393 | /* Check the SDRAM controller state */
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| 394 | if(hsdram->State == HAL_SDRAM_STATE_BUSY)
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| 395 | {
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| 396 | return HAL_BUSY;
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| 397 | }
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| 398 | else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
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| 399 | {
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| 400 | return HAL_ERROR;
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| 401 | }
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| 402 |
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| 403 | /* Read data from source */
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| 404 | for(; BufferSize != 0; BufferSize--)
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| 405 | {
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| 406 | *pDstBuffer = *(__IO uint16_t *)pSdramAddress;
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| 407 | pDstBuffer++;
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| 408 | pSdramAddress++;
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| 409 | }
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| 410 |
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| 411 | /* Process Unlocked */
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| 412 | __HAL_UNLOCK(hsdram);
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| 413 |
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| 414 | return HAL_OK;
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| 415 | }
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| 416 |
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| 417 | /**
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| 418 | * @brief Writes 16-bit data buffer to SDRAM memory.
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| 419 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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| 420 | * the configuration information for SDRAM module.
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| 421 | * @param pAddress: Pointer to write start address
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| 422 | * @param pSrcBuffer: Pointer to source buffer to write
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| 423 | * @param BufferSize: Size of the buffer to write to memory
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| 424 | * @retval HAL status
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| 425 | */
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| 426 | HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
|
---|
| 427 | {
|
---|
| 428 | __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
|
---|
| 429 | uint32_t tmp = 0;
|
---|
| 430 |
|
---|
| 431 | /* Process Locked */
|
---|
| 432 | __HAL_LOCK(hsdram);
|
---|
| 433 |
|
---|
| 434 | /* Check the SDRAM controller state */
|
---|
| 435 | tmp = hsdram->State;
|
---|
| 436 |
|
---|
| 437 | if(tmp == HAL_SDRAM_STATE_BUSY)
|
---|
| 438 | {
|
---|
| 439 | return HAL_BUSY;
|
---|
| 440 | }
|
---|
| 441 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
|
---|
| 442 | {
|
---|
| 443 | return HAL_ERROR;
|
---|
| 444 | }
|
---|
| 445 |
|
---|
| 446 | /* Write data to memory */
|
---|
| 447 | for(; BufferSize != 0; BufferSize--)
|
---|
| 448 | {
|
---|
| 449 | *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
|
---|
| 450 | pSrcBuffer++;
|
---|
| 451 | pSdramAddress++;
|
---|
| 452 | }
|
---|
| 453 |
|
---|
| 454 | /* Process Unlocked */
|
---|
| 455 | __HAL_UNLOCK(hsdram);
|
---|
| 456 |
|
---|
| 457 | return HAL_OK;
|
---|
| 458 | }
|
---|
| 459 |
|
---|
| 460 | /**
|
---|
| 461 | * @brief Reads 32-bit data buffer from the SDRAM memory.
|
---|
| 462 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
---|
| 463 | * the configuration information for SDRAM module.
|
---|
| 464 | * @param pAddress: Pointer to read start address
|
---|
| 465 | * @param pDstBuffer: Pointer to destination buffer
|
---|
| 466 | * @param BufferSize: Size of the buffer to read from memory
|
---|
| 467 | * @retval HAL status
|
---|
| 468 | */
|
---|
| 469 | HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
---|
| 470 | {
|
---|
| 471 | __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
|
---|
| 472 |
|
---|
| 473 | /* Process Locked */
|
---|
| 474 | __HAL_LOCK(hsdram);
|
---|
| 475 |
|
---|
| 476 | /* Check the SDRAM controller state */
|
---|
| 477 | if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
---|
| 478 | {
|
---|
| 479 | return HAL_BUSY;
|
---|
| 480 | }
|
---|
| 481 | else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
|
---|
| 482 | {
|
---|
| 483 | return HAL_ERROR;
|
---|
| 484 | }
|
---|
| 485 |
|
---|
| 486 | /* Read data from source */
|
---|
| 487 | for(; BufferSize != 0; BufferSize--)
|
---|
| 488 | {
|
---|
| 489 | *pDstBuffer = *(__IO uint32_t *)pSdramAddress;
|
---|
| 490 | pDstBuffer++;
|
---|
| 491 | pSdramAddress++;
|
---|
| 492 | }
|
---|
| 493 |
|
---|
| 494 | /* Process Unlocked */
|
---|
| 495 | __HAL_UNLOCK(hsdram);
|
---|
| 496 |
|
---|
| 497 | return HAL_OK;
|
---|
| 498 | }
|
---|
| 499 |
|
---|
| 500 | /**
|
---|
| 501 | * @brief Writes 32-bit data buffer to SDRAM memory.
|
---|
| 502 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
---|
| 503 | * the configuration information for SDRAM module.
|
---|
| 504 | * @param pAddress: Pointer to write start address
|
---|
| 505 | * @param pSrcBuffer: Pointer to source buffer to write
|
---|
| 506 | * @param BufferSize: Size of the buffer to write to memory
|
---|
| 507 | * @retval HAL status
|
---|
| 508 | */
|
---|
| 509 | HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
---|
| 510 | {
|
---|
| 511 | __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
|
---|
| 512 | uint32_t tmp = 0;
|
---|
| 513 |
|
---|
| 514 | /* Process Locked */
|
---|
| 515 | __HAL_LOCK(hsdram);
|
---|
| 516 |
|
---|
| 517 | /* Check the SDRAM controller state */
|
---|
| 518 | tmp = hsdram->State;
|
---|
| 519 |
|
---|
| 520 | if(tmp == HAL_SDRAM_STATE_BUSY)
|
---|
| 521 | {
|
---|
| 522 | return HAL_BUSY;
|
---|
| 523 | }
|
---|
| 524 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
|
---|
| 525 | {
|
---|
| 526 | return HAL_ERROR;
|
---|
| 527 | }
|
---|
| 528 |
|
---|
| 529 | /* Write data to memory */
|
---|
| 530 | for(; BufferSize != 0; BufferSize--)
|
---|
| 531 | {
|
---|
| 532 | *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
|
---|
| 533 | pSrcBuffer++;
|
---|
| 534 | pSdramAddress++;
|
---|
| 535 | }
|
---|
| 536 |
|
---|
| 537 | /* Process Unlocked */
|
---|
| 538 | __HAL_UNLOCK(hsdram);
|
---|
| 539 |
|
---|
| 540 | return HAL_OK;
|
---|
| 541 | }
|
---|
| 542 |
|
---|
| 543 | /**
|
---|
| 544 | * @brief Reads a Words data from the SDRAM memory using DMA transfer.
|
---|
| 545 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
---|
| 546 | * the configuration information for SDRAM module.
|
---|
| 547 | * @param pAddress: Pointer to read start address
|
---|
| 548 | * @param pDstBuffer: Pointer to destination buffer
|
---|
| 549 | * @param BufferSize: Size of the buffer to read from memory
|
---|
| 550 | * @retval HAL status
|
---|
| 551 | */
|
---|
| 552 | HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
---|
| 553 | {
|
---|
| 554 | uint32_t tmp = 0;
|
---|
| 555 |
|
---|
| 556 | /* Process Locked */
|
---|
| 557 | __HAL_LOCK(hsdram);
|
---|
| 558 |
|
---|
| 559 | /* Check the SDRAM controller state */
|
---|
| 560 | tmp = hsdram->State;
|
---|
| 561 |
|
---|
| 562 | if(tmp == HAL_SDRAM_STATE_BUSY)
|
---|
| 563 | {
|
---|
| 564 | return HAL_BUSY;
|
---|
| 565 | }
|
---|
| 566 | else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
|
---|
| 567 | {
|
---|
| 568 | return HAL_ERROR;
|
---|
| 569 | }
|
---|
| 570 |
|
---|
| 571 | /* Configure DMA user callbacks */
|
---|
| 572 | hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
|
---|
| 573 | hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
|
---|
| 574 |
|
---|
| 575 | /* Enable the DMA Stream */
|
---|
| 576 | HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
|
---|
| 577 |
|
---|
| 578 | /* Process Unlocked */
|
---|
| 579 | __HAL_UNLOCK(hsdram);
|
---|
| 580 |
|
---|
| 581 | return HAL_OK;
|
---|
| 582 | }
|
---|
| 583 |
|
---|
| 584 | /**
|
---|
| 585 | * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
|
---|
| 586 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
---|
| 587 | * the configuration information for SDRAM module.
|
---|
| 588 | * @param pAddress: Pointer to write start address
|
---|
| 589 | * @param pSrcBuffer: Pointer to source buffer to write
|
---|
| 590 | * @param BufferSize: Size of the buffer to write to memory
|
---|
| 591 | * @retval HAL status
|
---|
| 592 | */
|
---|
| 593 | HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
---|
| 594 | {
|
---|
| 595 | uint32_t tmp = 0;
|
---|
| 596 |
|
---|
| 597 | /* Process Locked */
|
---|
| 598 | __HAL_LOCK(hsdram);
|
---|
| 599 |
|
---|
| 600 | /* Check the SDRAM controller state */
|
---|
| 601 | tmp = hsdram->State;
|
---|
| 602 |
|
---|
| 603 | if(tmp == HAL_SDRAM_STATE_BUSY)
|
---|
| 604 | {
|
---|
| 605 | return HAL_BUSY;
|
---|
| 606 | }
|
---|
| 607 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
|
---|
| 608 | {
|
---|
| 609 | return HAL_ERROR;
|
---|
| 610 | }
|
---|
| 611 |
|
---|
| 612 | /* Configure DMA user callbacks */
|
---|
| 613 | hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
|
---|
| 614 | hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
|
---|
| 615 |
|
---|
| 616 | /* Enable the DMA Stream */
|
---|
| 617 | HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
|
---|
| 618 |
|
---|
| 619 | /* Process Unlocked */
|
---|
| 620 | __HAL_UNLOCK(hsdram);
|
---|
| 621 |
|
---|
| 622 | return HAL_OK;
|
---|
| 623 | }
|
---|
| 624 | /**
|
---|
| 625 | * @}
|
---|
| 626 | */
|
---|
| 627 |
|
---|
| 628 | /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
|
---|
| 629 | * @brief management functions
|
---|
| 630 | *
|
---|
| 631 | @verbatim
|
---|
| 632 | ==============================================================================
|
---|
| 633 | ##### SDRAM Control functions #####
|
---|
| 634 | ==============================================================================
|
---|
| 635 | [..]
|
---|
| 636 | This subsection provides a set of functions allowing to control dynamically
|
---|
| 637 | the SDRAM interface.
|
---|
| 638 |
|
---|
| 639 | @endverbatim
|
---|
| 640 | * @{
|
---|
| 641 | */
|
---|
| 642 |
|
---|
| 643 | /**
|
---|
| 644 | * @brief Enables dynamically SDRAM write protection.
|
---|
| 645 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
---|
| 646 | * the configuration information for SDRAM module.
|
---|
| 647 | * @retval HAL status
|
---|
| 648 | */
|
---|
| 649 | HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
|
---|
| 650 | {
|
---|
| 651 | /* Check the SDRAM controller state */
|
---|
| 652 | if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
---|
| 653 | {
|
---|
| 654 | return HAL_BUSY;
|
---|
| 655 | }
|
---|
| 656 |
|
---|
| 657 | /* Update the SDRAM state */
|
---|
| 658 | hsdram->State = HAL_SDRAM_STATE_BUSY;
|
---|
| 659 |
|
---|
| 660 | /* Enable write protection */
|
---|
| 661 | FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
|
---|
| 662 |
|
---|
| 663 | /* Update the SDRAM state */
|
---|
| 664 | hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
|
---|
| 665 |
|
---|
| 666 | return HAL_OK;
|
---|
| 667 | }
|
---|
| 668 |
|
---|
| 669 | /**
|
---|
| 670 | * @brief Disables dynamically SDRAM write protection.
|
---|
| 671 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
---|
| 672 | * the configuration information for SDRAM module.
|
---|
| 673 | * @retval HAL status
|
---|
| 674 | */
|
---|
| 675 | HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
|
---|
| 676 | {
|
---|
| 677 | /* Check the SDRAM controller state */
|
---|
| 678 | if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
---|
| 679 | {
|
---|
| 680 | return HAL_BUSY;
|
---|
| 681 | }
|
---|
| 682 |
|
---|
| 683 | /* Update the SDRAM state */
|
---|
| 684 | hsdram->State = HAL_SDRAM_STATE_BUSY;
|
---|
| 685 |
|
---|
| 686 | /* Disable write protection */
|
---|
| 687 | FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
|
---|
| 688 |
|
---|
| 689 | /* Update the SDRAM state */
|
---|
| 690 | hsdram->State = HAL_SDRAM_STATE_READY;
|
---|
| 691 |
|
---|
| 692 | return HAL_OK;
|
---|
| 693 | }
|
---|
| 694 |
|
---|
| 695 | /**
|
---|
| 696 | * @brief Sends Command to the SDRAM bank.
|
---|
| 697 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
---|
| 698 | * the configuration information for SDRAM module.
|
---|
| 699 | * @param Command: SDRAM command structure
|
---|
| 700 | * @param Timeout: Timeout duration
|
---|
| 701 | * @retval HAL status
|
---|
| 702 | */
|
---|
| 703 | HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
|
---|
| 704 | {
|
---|
| 705 | /* Check the SDRAM controller state */
|
---|
| 706 | if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
---|
| 707 | {
|
---|
| 708 | return HAL_BUSY;
|
---|
| 709 | }
|
---|
| 710 |
|
---|
| 711 | /* Update the SDRAM state */
|
---|
| 712 | hsdram->State = HAL_SDRAM_STATE_BUSY;
|
---|
| 713 |
|
---|
| 714 | /* Send SDRAM command */
|
---|
| 715 | FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
|
---|
| 716 |
|
---|
| 717 | /* Update the SDRAM controller state */
|
---|
| 718 | if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
|
---|
| 719 | {
|
---|
| 720 | hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
|
---|
| 721 | }
|
---|
| 722 | else
|
---|
| 723 | {
|
---|
| 724 | hsdram->State = HAL_SDRAM_STATE_READY;
|
---|
| 725 | }
|
---|
| 726 |
|
---|
| 727 | return HAL_OK;
|
---|
| 728 | }
|
---|
| 729 |
|
---|
| 730 | /**
|
---|
| 731 | * @brief Programs the SDRAM Memory Refresh rate.
|
---|
| 732 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
---|
| 733 | * the configuration information for SDRAM module.
|
---|
| 734 | * @param RefreshRate: The SDRAM refresh rate value
|
---|
| 735 | * @retval HAL status
|
---|
| 736 | */
|
---|
| 737 | HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
|
---|
| 738 | {
|
---|
| 739 | /* Check the SDRAM controller state */
|
---|
| 740 | if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
---|
| 741 | {
|
---|
| 742 | return HAL_BUSY;
|
---|
| 743 | }
|
---|
| 744 |
|
---|
| 745 | /* Update the SDRAM state */
|
---|
| 746 | hsdram->State = HAL_SDRAM_STATE_BUSY;
|
---|
| 747 |
|
---|
| 748 | /* Program the refresh rate */
|
---|
| 749 | FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
|
---|
| 750 |
|
---|
| 751 | /* Update the SDRAM state */
|
---|
| 752 | hsdram->State = HAL_SDRAM_STATE_READY;
|
---|
| 753 |
|
---|
| 754 | return HAL_OK;
|
---|
| 755 | }
|
---|
| 756 |
|
---|
| 757 | /**
|
---|
| 758 | * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
|
---|
| 759 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
---|
| 760 | * the configuration information for SDRAM module.
|
---|
| 761 | * @param AutoRefreshNumber: The SDRAM auto Refresh number
|
---|
| 762 | * @retval HAL status
|
---|
| 763 | */
|
---|
| 764 | HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
|
---|
| 765 | {
|
---|
| 766 | /* Check the SDRAM controller state */
|
---|
| 767 | if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
---|
| 768 | {
|
---|
| 769 | return HAL_BUSY;
|
---|
| 770 | }
|
---|
| 771 |
|
---|
| 772 | /* Update the SDRAM state */
|
---|
| 773 | hsdram->State = HAL_SDRAM_STATE_BUSY;
|
---|
| 774 |
|
---|
| 775 | /* Set the Auto-Refresh number */
|
---|
| 776 | FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
|
---|
| 777 |
|
---|
| 778 | /* Update the SDRAM state */
|
---|
| 779 | hsdram->State = HAL_SDRAM_STATE_READY;
|
---|
| 780 |
|
---|
| 781 | return HAL_OK;
|
---|
| 782 | }
|
---|
| 783 |
|
---|
| 784 | /**
|
---|
| 785 | * @brief Returns the SDRAM memory current mode.
|
---|
| 786 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
---|
| 787 | * the configuration information for SDRAM module.
|
---|
| 788 | * @retval The SDRAM memory mode.
|
---|
| 789 | */
|
---|
| 790 | uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
|
---|
| 791 | {
|
---|
| 792 | /* Return the SDRAM memory current mode */
|
---|
| 793 | return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
|
---|
| 794 | }
|
---|
| 795 |
|
---|
| 796 | /**
|
---|
| 797 | * @}
|
---|
| 798 | */
|
---|
| 799 |
|
---|
| 800 | /** @defgroup SDRAM_Exported_Functions_Group4 State functions
|
---|
| 801 | * @brief Peripheral State functions
|
---|
| 802 | *
|
---|
| 803 | @verbatim
|
---|
| 804 | ==============================================================================
|
---|
| 805 | ##### SDRAM State functions #####
|
---|
| 806 | ==============================================================================
|
---|
| 807 | [..]
|
---|
| 808 | This subsection permits to get in run-time the status of the SDRAM controller
|
---|
| 809 | and the data flow.
|
---|
| 810 |
|
---|
| 811 | @endverbatim
|
---|
| 812 | * @{
|
---|
| 813 | */
|
---|
| 814 |
|
---|
| 815 | /**
|
---|
| 816 | * @brief Returns the SDRAM state.
|
---|
| 817 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
---|
| 818 | * the configuration information for SDRAM module.
|
---|
| 819 | * @retval HAL state
|
---|
| 820 | */
|
---|
| 821 | HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
|
---|
| 822 | {
|
---|
| 823 | return hsdram->State;
|
---|
| 824 | }
|
---|
| 825 |
|
---|
| 826 | /**
|
---|
| 827 | * @}
|
---|
| 828 | */
|
---|
| 829 |
|
---|
| 830 | /**
|
---|
| 831 | * @}
|
---|
| 832 | */
|
---|
| 833 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
|
---|
| 834 | #endif /* HAL_SDRAM_MODULE_ENABLED */
|
---|
| 835 | /**
|
---|
| 836 | * @}
|
---|
| 837 | */
|
---|
| 838 |
|
---|
| 839 | /**
|
---|
| 840 | * @}
|
---|
| 841 | */
|
---|
| 842 |
|
---|
| 843 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
---|