[303] | 1 | /**
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| 2 | ******************************************************************************
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| 3 | * @file stm32f4xx_hal_rcc_ex.c
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| 4 | * @author MCD Application Team
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| 5 | * @version V1.4.1
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| 6 | * @date 09-October-2015
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| 7 | * @brief Extension RCC HAL module driver.
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| 8 | * This file provides firmware functions to manage the following
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| 9 | * functionalities RCC extension peripheral:
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| 10 | * + Extended Peripheral Control functions
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| 11 | *
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| 12 | ******************************************************************************
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| 13 | * @attention
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| 14 | *
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| 15 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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| 16 | *
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| 17 | * Redistribution and use in source and binary forms, with or without modification,
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| 18 | * are permitted provided that the following conditions are met:
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| 19 | * 1. Redistributions of source code must retain the above copyright notice,
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| 20 | * this list of conditions and the following disclaimer.
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| 21 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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| 22 | * this list of conditions and the following disclaimer in the documentation
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| 23 | * and/or other materials provided with the distribution.
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| 24 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
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| 25 | * may be used to endorse or promote products derived from this software
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| 26 | * without specific prior written permission.
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| 27 | *
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| 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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| 29 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| 30 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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| 31 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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| 32 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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| 34 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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| 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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| 36 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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| 37 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 38 | *
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| 39 | ******************************************************************************
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| 40 | */
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| 41 |
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| 42 | /* Includes ------------------------------------------------------------------*/
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| 43 | #include "stm32f4xx_hal.h"
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| 44 |
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| 45 | /** @addtogroup STM32F4xx_HAL_Driver
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| 46 | * @{
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| 47 | */
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| 48 |
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| 49 | /** @defgroup RCCEx RCCEx
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| 50 | * @brief RCCEx HAL module driver
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| 51 | * @{
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| 52 | */
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| 53 |
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| 54 | #ifdef HAL_RCC_MODULE_ENABLED
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| 55 |
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| 56 | /* Private typedef -----------------------------------------------------------*/
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| 57 | /* Private define ------------------------------------------------------------*/
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| 58 | /** @addtogroup RCCEx_Private_Constants
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| 59 | * @{
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| 60 | */
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| 61 | /**
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| 62 | * @}
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| 63 | */
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| 64 | /* Private macro -------------------------------------------------------------*/
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| 65 | /* Private variables ---------------------------------------------------------*/
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| 66 | /* Private function prototypes -----------------------------------------------*/
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| 67 | /* Private functions ---------------------------------------------------------*/
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| 68 | /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
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| 69 | * @{
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| 70 | */
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| 71 |
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| 72 | /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
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| 73 | * @brief Extended Peripheral Control functions
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| 74 | *
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| 75 | @verbatim
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| 76 | ===============================================================================
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| 77 | ##### Extended Peripheral Control functions #####
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| 78 | ===============================================================================
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| 79 | [..]
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| 80 | This subsection provides a set of functions allowing to control the RCC Clocks
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| 81 | frequencies.
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| 82 | [..]
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| 83 | (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
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| 84 | select the RTC clock source; in this case the Backup domain will be reset in
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| 85 | order to modify the RTC Clock source, as consequence RTC registers (including
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| 86 | the backup registers) and RCC_BDCR register are set to their reset values.
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| 87 |
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| 88 | @endverbatim
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| 89 | * @{
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| 90 | */
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| 91 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
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| 92 | defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
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| 93 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
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| 94 | defined(STM32F469xx) || defined(STM32F479xx)
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| 95 | /**
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| 96 | * @brief Resets the RCC clock configuration to the default reset state.
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| 97 | * @note The default reset state of the clock configuration is given below:
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| 98 | * - HSI ON and used as system clock source
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| 99 | * - HSE, PLL and PLLI2S OFF
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| 100 | * - AHB, APB1 and APB2 prescaler set to 1.
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| 101 | * - CSS, MCO1 and MCO2 OFF
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| 102 | * - All interrupts disabled
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| 103 | * @note This function doesn't modify the configuration of the
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| 104 | * - Peripheral clocks
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| 105 | * - LSI, LSE and RTC clocks
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| 106 | * @retval None
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| 107 | */
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| 108 | void HAL_RCC_DeInit(void)
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| 109 | {
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| 110 | /* Set HSION bit */
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| 111 | SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
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| 112 |
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| 113 | /* Reset CFGR register */
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| 114 | CLEAR_REG(RCC->CFGR);
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| 115 |
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| 116 | /* Reset HSEON, CSSON, PLLON, PLLI2S */
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| 117 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON);
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| 118 |
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| 119 | /* Reset PLLCFGR register */
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| 120 | CLEAR_REG(RCC->PLLCFGR);
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| 121 | SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
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| 122 |
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| 123 | /* Reset PLLI2SCFGR register */
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| 124 | CLEAR_REG(RCC->PLLI2SCFGR);
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| 125 | SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
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| 126 |
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| 127 | /* Reset HSEBYP bit */
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| 128 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
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| 129 |
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| 130 | /* Disable all interrupts */
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| 131 | CLEAR_REG(RCC->CIR);
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| 132 | }
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| 133 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
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| 134 | STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
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| 135 |
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| 136 | #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
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| 137 | /**
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| 138 | * @brief Resets the RCC clock configuration to the default reset state.
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| 139 | * @note The default reset state of the clock configuration is given below:
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| 140 | * - HSI ON and used as system clock source
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| 141 | * - HSE and PLL OFF
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| 142 | * - AHB, APB1 and APB2 prescaler set to 1.
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| 143 | * - CSS, MCO1 and MCO2 OFF
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| 144 | * - All interrupts disabled
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| 145 | * @note This function doesn't modify the configuration of the
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| 146 | * - Peripheral clocks
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| 147 | * - LSI, LSE and RTC clocks
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| 148 | * @retval None
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| 149 | */
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| 150 | void HAL_RCC_DeInit(void)
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| 151 | {
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| 152 | /* Set HSION bit */
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| 153 | SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
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| 154 |
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| 155 | /* Reset CFGR register */
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| 156 | CLEAR_REG(RCC->CFGR);
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| 157 |
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| 158 | /* Reset HSEON, CSSON, PLLON */
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| 159 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
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| 160 |
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| 161 | /* Reset PLLCFGR register */
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| 162 | CLEAR_REG(RCC->PLLCFGR);
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| 163 | SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
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| 164 |
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| 165 | /* Reset HSEBYP bit */
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| 166 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
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| 167 |
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| 168 | /* Disable all interrupts */
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| 169 | CLEAR_REG(RCC->CIR);
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| 170 | }
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| 171 | #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
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| 172 |
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| 173 | #if defined(STM32F446xx)
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| 174 | /**
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| 175 | * @brief Initializes the RCC extended peripherals clocks according to the specified
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| 176 | * parameters in the RCC_PeriphCLKInitTypeDef.
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| 177 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
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| 178 | * contains the configuration information for the Extended Peripherals
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| 179 | * clocks(I2S, SAI, LTDC RTC and TIM).
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| 180 | *
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| 181 | * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
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| 182 | * the RTC clock source; in this case the Backup domain will be reset in
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| 183 | * order to modify the RTC Clock source, as consequence RTC registers (including
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| 184 | * the backup registers) and RCC_BDCR register are set to their reset values.
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| 185 | *
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| 186 | * @retval HAL status
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| 187 | */
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| 188 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
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| 189 | {
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| 190 | uint32_t tickstart = 0;
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| 191 | uint32_t tmpreg1 = 0;
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| 192 | uint32_t plli2sp = 0;
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| 193 | uint32_t plli2sq = 0;
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| 194 | uint32_t plli2sr = 0;
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| 195 | uint32_t pllsaip = 0;
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| 196 | uint32_t pllsaiq = 0;
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| 197 | uint32_t plli2sused = 0;
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| 198 | uint32_t pllsaiused = 0;
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| 199 |
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| 200 | /* Check the peripheral clock selection parameters */
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| 201 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
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| 202 |
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| 203 | /*------------------------ I2S APB1 configuration --------------------------*/
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| 204 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
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| 205 | {
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| 206 | /* Check the parameters */
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| 207 | assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
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| 208 |
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| 209 | /* Configure I2S Clock source */
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| 210 | __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
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| 211 | /* Enable the PLLI2S when it's used as clock source for I2S */
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| 212 | if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
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| 213 | {
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| 214 | plli2sused = 1;
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| 215 | }
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| 216 | }
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| 217 | /*--------------------------------------------------------------------------*/
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| 218 |
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| 219 | /*---------------------------- I2S APB2 configuration ----------------------*/
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| 220 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
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| 221 | {
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| 222 | /* Check the parameters */
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| 223 | assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
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| 224 |
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| 225 | /* Configure I2S Clock source */
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| 226 | __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
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| 227 | /* Enable the PLLI2S when it's used as clock source for I2S */
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| 228 | if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
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| 229 | {
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| 230 | plli2sused = 1;
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| 231 | }
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| 232 | }
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| 233 | /*--------------------------------------------------------------------------*/
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| 234 |
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| 235 | /*--------------------------- SAI1 configuration ---------------------------*/
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| 236 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
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| 237 | {
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| 238 | /* Check the parameters */
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| 239 | assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
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| 240 |
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| 241 | /* Configure SAI1 Clock source */
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| 242 | __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
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| 243 | /* Enable the PLLI2S when it's used as clock source for SAI */
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| 244 | if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
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| 245 | {
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| 246 | plli2sused = 1;
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| 247 | }
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| 248 | /* Enable the PLLSAI when it's used as clock source for SAI */
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| 249 | if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
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| 250 | {
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| 251 | pllsaiused = 1;
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| 252 | }
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| 253 | }
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| 254 | /*--------------------------------------------------------------------------*/
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| 255 |
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| 256 | /*-------------------------- SAI2 configuration ----------------------------*/
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| 257 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
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| 258 | {
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| 259 | /* Check the parameters */
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| 260 | assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
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| 261 |
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| 262 | /* Configure SAI2 Clock source */
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| 263 | __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
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| 264 |
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| 265 | /* Enable the PLLI2S when it's used as clock source for SAI */
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| 266 | if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
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| 267 | {
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| 268 | plli2sused = 1;
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| 269 | }
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| 270 | /* Enable the PLLSAI when it's used as clock source for SAI */
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| 271 | if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
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| 272 | {
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| 273 | pllsaiused = 1;
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| 274 | }
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| 275 | }
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| 276 | /*--------------------------------------------------------------------------*/
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| 277 |
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| 278 | /*----------------------------- RTC configuration --------------------------*/
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| 279 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
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| 280 | {
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| 281 | /* Enable Power Clock*/
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| 282 | __HAL_RCC_PWR_CLK_ENABLE();
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| 283 |
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| 284 | /* Enable write access to Backup domain */
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| 285 | PWR->CR |= PWR_CR_DBP;
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| 286 |
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| 287 | /* Get tick */
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| 288 | tickstart = HAL_GetTick();
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| 289 |
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| 290 | while((PWR->CR & PWR_CR_DBP) == RESET)
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| 291 | {
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| 292 | if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
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| 293 | {
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| 294 | return HAL_TIMEOUT;
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| 295 | }
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| 296 | }
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| 297 | /* Reset the Backup domain only if the RTC Clock source selction is modified */
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| 298 | if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
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| 299 | {
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| 300 | /* Store the content of BDCR register before the reset of Backup Domain */
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| 301 | tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
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| 302 | /* RTC Clock selection can be changed only if the Backup Domain is reset */
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| 303 | __HAL_RCC_BACKUPRESET_FORCE();
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| 304 | __HAL_RCC_BACKUPRESET_RELEASE();
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| 305 | /* Restore the Content of BDCR register */
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| 306 | RCC->BDCR = tmpreg1;
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| 307 |
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| 308 | /* Wait for LSERDY if LSE was enabled */
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| 309 | if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
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| 310 | {
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| 311 | /* Get tick */
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| 312 | tickstart = HAL_GetTick();
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| 313 |
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| 314 | /* Wait till LSE is ready */
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| 315 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
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| 316 | {
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| 317 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
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| 318 | {
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| 319 | return HAL_TIMEOUT;
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| 320 | }
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| 321 | }
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| 322 | }
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| 323 | __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
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| 324 | }
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| 325 | }
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| 326 | /*--------------------------------------------------------------------------*/
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| 327 |
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| 328 | /*---------------------------- TIM configuration ---------------------------*/
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| 329 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
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| 330 | {
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| 331 | /* Configure Timer Prescaler */
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| 332 | __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
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| 333 | }
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| 334 | /*--------------------------------------------------------------------------*/
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| 335 |
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| 336 | /*---------------------------- FMPI2C1 Configuration -----------------------*/
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| 337 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
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| 338 | {
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| 339 | /* Check the parameters */
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| 340 | assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
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| 341 |
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| 342 | /* Configure the FMPI2C1 clock source */
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| 343 | __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
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| 344 | }
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| 345 | /*--------------------------------------------------------------------------*/
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| 346 |
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| 347 | /*------------------------------ CEC Configuration -------------------------*/
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| 348 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
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| 349 | {
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| 350 | /* Check the parameters */
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| 351 | assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
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| 352 |
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| 353 | /* Configure the CEC clock source */
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| 354 | __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
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| 355 | }
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| 356 | /*--------------------------------------------------------------------------*/
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| 357 |
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| 358 | /*------------------------------ CK48 Configuration ------------------------*/
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| 359 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48)
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| 360 | {
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| 361 | /* Check the parameters */
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| 362 | assert_param(IS_RCC_CK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
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| 363 |
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| 364 | /* Configure the CK48 clock source */
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| 365 | __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
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| 366 |
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| 367 | /* Enable the PLLSAI when it's used as clock source for CK48 */
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| 368 | if(PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP)
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| 369 | {
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| 370 | pllsaiused = 1;
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| 371 | }
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| 372 | }
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| 373 | /*--------------------------------------------------------------------------*/
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| 374 |
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| 375 | /*----------------------------- SDIO Configuration -------------------------*/
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| 376 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
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| 377 | {
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| 378 | /* Check the parameters */
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| 379 | assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
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| 380 |
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| 381 | /* Configure the SDIO clock source */
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| 382 | __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
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| 383 | }
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| 384 | /*--------------------------------------------------------------------------*/
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| 385 |
|
---|
| 386 | /*------------------------------ SPDIFRX Configuration ---------------------*/
|
---|
| 387 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
|
---|
| 388 | {
|
---|
| 389 | /* Check the parameters */
|
---|
| 390 | assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
|
---|
| 391 |
|
---|
| 392 | /* Configure the SPDIFRX clock source */
|
---|
| 393 | __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
|
---|
| 394 | /* Enable the PLLI2S when it's used as clock source for SPDIFRX */
|
---|
| 395 | if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
|
---|
| 396 | {
|
---|
| 397 | plli2sused = 1;
|
---|
| 398 | }
|
---|
| 399 | }
|
---|
| 400 | /*--------------------------------------------------------------------------*/
|
---|
| 401 |
|
---|
| 402 | /*---------------------------- PLLI2S Configuration ------------------------*/
|
---|
| 403 | /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
|
---|
| 404 | I2S on APB2 or SPDIFRX */
|
---|
| 405 | if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
|
---|
| 406 | {
|
---|
| 407 | /* Disable the PLLI2S */
|
---|
| 408 | __HAL_RCC_PLLI2S_DISABLE();
|
---|
| 409 | /* Get tick */
|
---|
| 410 | tickstart = HAL_GetTick();
|
---|
| 411 | /* Wait till PLLI2S is disabled */
|
---|
| 412 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
---|
| 413 | {
|
---|
| 414 | if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
|
---|
| 415 | {
|
---|
| 416 | /* return in case of Timeout detected */
|
---|
| 417 | return HAL_TIMEOUT;
|
---|
| 418 | }
|
---|
| 419 | }
|
---|
| 420 |
|
---|
| 421 | /* check for common PLLI2S Parameters */
|
---|
| 422 | assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
|
---|
| 423 | assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
|
---|
| 424 |
|
---|
| 425 | /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/
|
---|
| 426 | if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
|
---|
| 427 | ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
|
---|
| 428 | {
|
---|
| 429 | /* check for Parameters */
|
---|
| 430 | assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
---|
| 431 |
|
---|
| 432 | /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
|
---|
| 433 | plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
|
---|
| 434 | plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
|
---|
| 435 | /* Configure the PLLI2S division factors */
|
---|
| 436 | /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
---|
| 437 | /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
|
---|
| 438 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
|
---|
| 439 | }
|
---|
| 440 |
|
---|
| 441 | /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
|
---|
| 442 | if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
|
---|
| 443 | ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
|
---|
| 444 | {
|
---|
| 445 | /* Check for PLLI2S Parameters */
|
---|
| 446 | assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
---|
| 447 | /* Check for PLLI2S/DIVQ parameters */
|
---|
| 448 | assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
|
---|
| 449 |
|
---|
| 450 | /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
|
---|
| 451 | plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
|
---|
| 452 | plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
|
---|
| 453 | /* Configure the PLLI2S division factors */
|
---|
| 454 | /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
|
---|
| 455 | /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
|
---|
| 456 | /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
|
---|
| 457 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
|
---|
| 458 |
|
---|
| 459 | /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
|
---|
| 460 | __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
|
---|
| 461 | }
|
---|
| 462 |
|
---|
| 463 | /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/
|
---|
| 464 | if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
|
---|
| 465 | {
|
---|
| 466 | /* check for Parameters */
|
---|
| 467 | assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
|
---|
| 468 | /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
|
---|
| 469 | plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
|
---|
| 470 | plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
|
---|
| 471 | /* Configure the PLLI2S division factors */
|
---|
| 472 | /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
---|
| 473 | /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
|
---|
| 474 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr);
|
---|
| 475 | }
|
---|
| 476 |
|
---|
| 477 | /*----------------- In Case of PLLI2S is just selected -----------------*/
|
---|
| 478 | if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
|
---|
| 479 | {
|
---|
| 480 | /* Check for Parameters */
|
---|
| 481 | assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
|
---|
| 482 | assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
---|
| 483 | assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
---|
| 484 |
|
---|
| 485 | /* Configure the PLLI2S division factors */
|
---|
| 486 | /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
---|
| 487 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
|
---|
| 488 | }
|
---|
| 489 |
|
---|
| 490 | /* Enable the PLLI2S */
|
---|
| 491 | __HAL_RCC_PLLI2S_ENABLE();
|
---|
| 492 | /* Get tick */
|
---|
| 493 | tickstart = HAL_GetTick();
|
---|
| 494 | /* Wait till PLLI2S is ready */
|
---|
| 495 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
---|
| 496 | {
|
---|
| 497 | if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
|
---|
| 498 | {
|
---|
| 499 | /* return in case of Timeout detected */
|
---|
| 500 | return HAL_TIMEOUT;
|
---|
| 501 | }
|
---|
| 502 | }
|
---|
| 503 | }
|
---|
| 504 | /*--------------------------------------------------------------------------*/
|
---|
| 505 |
|
---|
| 506 | /*----------------------------- PLLSAI Configuration -----------------------*/
|
---|
| 507 | /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CK48 or SDIO */
|
---|
| 508 | if(pllsaiused == 1)
|
---|
| 509 | {
|
---|
| 510 | /* Disable PLLSAI Clock */
|
---|
| 511 | __HAL_RCC_PLLSAI_DISABLE();
|
---|
| 512 | /* Get tick */
|
---|
| 513 | tickstart = HAL_GetTick();
|
---|
| 514 | /* Wait till PLLSAI is disabled */
|
---|
| 515 | while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
---|
| 516 | {
|
---|
| 517 | if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
|
---|
| 518 | {
|
---|
| 519 | /* return in case of Timeout detected */
|
---|
| 520 | return HAL_TIMEOUT;
|
---|
| 521 | }
|
---|
| 522 | }
|
---|
| 523 |
|
---|
| 524 | /* Check the PLLSAI division factors */
|
---|
| 525 | assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
|
---|
| 526 | assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
|
---|
| 527 |
|
---|
| 528 | /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/
|
---|
| 529 | if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
|
---|
| 530 | ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
|
---|
| 531 | {
|
---|
| 532 | /* check for PLLSAIQ Parameter */
|
---|
| 533 | assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
|
---|
| 534 | /* check for PLLSAI/DIVQ Parameter */
|
---|
| 535 | assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
|
---|
| 536 |
|
---|
| 537 | /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
|
---|
| 538 | pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1);
|
---|
| 539 | /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
|
---|
| 540 | /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
---|
| 541 | /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
|
---|
| 542 | __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0);
|
---|
| 543 |
|
---|
| 544 | /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
|
---|
| 545 | __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
|
---|
| 546 | }
|
---|
| 547 |
|
---|
| 548 | /*------ In Case of PLLSAI is selected as source clock for CK48 ----------*/
|
---|
| 549 | /* In Case of PLLI2S is selected as source clock for CK48 */
|
---|
| 550 | if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP))
|
---|
| 551 | {
|
---|
| 552 | /* check for Parameters */
|
---|
| 553 | assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
|
---|
| 554 | /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
|
---|
| 555 | pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
|
---|
| 556 | /* Configure the PLLSAI division factors */
|
---|
| 557 | /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
|
---|
| 558 | /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
|
---|
| 559 | __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0);
|
---|
| 560 | }
|
---|
| 561 |
|
---|
| 562 | /* Enable PLLSAI Clock */
|
---|
| 563 | __HAL_RCC_PLLSAI_ENABLE();
|
---|
| 564 | /* Get tick */
|
---|
| 565 | tickstart = HAL_GetTick();
|
---|
| 566 | /* Wait till PLLSAI is ready */
|
---|
| 567 | while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
---|
| 568 | {
|
---|
| 569 | if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
|
---|
| 570 | {
|
---|
| 571 | /* return in case of Timeout detected */
|
---|
| 572 | return HAL_TIMEOUT;
|
---|
| 573 | }
|
---|
| 574 | }
|
---|
| 575 | }
|
---|
| 576 | return HAL_OK;
|
---|
| 577 | }
|
---|
| 578 |
|
---|
| 579 | /**
|
---|
| 580 | * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
|
---|
| 581 | * RCC configuration registers.
|
---|
| 582 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
|
---|
| 583 | * will be configured.
|
---|
| 584 | * @retval None
|
---|
| 585 | */
|
---|
| 586 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
---|
| 587 | {
|
---|
| 588 | uint32_t tempreg;
|
---|
| 589 |
|
---|
| 590 | /* Set all possible values for the extended clock type parameter------------*/
|
---|
| 591 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
|
---|
| 592 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\
|
---|
| 593 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
|
---|
| 594 | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMPI2C1 |\
|
---|
| 595 | RCC_PERIPHCLK_CK48 | RCC_PERIPHCLK_SDIO |\
|
---|
| 596 | RCC_PERIPHCLK_SPDIFRX;
|
---|
| 597 |
|
---|
| 598 | /* Get the PLLI2S Clock configuration --------------------------------------*/
|
---|
| 599 | PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM));
|
---|
| 600 | PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
|
---|
| 601 | PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
|
---|
| 602 | PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
|
---|
| 603 | PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
|
---|
| 604 | /* Get the PLLSAI Clock configuration --------------------------------------*/
|
---|
| 605 | PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIM));
|
---|
| 606 | PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
|
---|
| 607 | PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1);
|
---|
| 608 | PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
|
---|
| 609 | /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
|
---|
| 610 | PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
|
---|
| 611 | PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
|
---|
| 612 |
|
---|
| 613 | /* Get the SAI1 clock configuration ----------------------------------------*/
|
---|
| 614 | PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
|
---|
| 615 |
|
---|
| 616 | /* Get the SAI2 clock configuration ----------------------------------------*/
|
---|
| 617 | PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
|
---|
| 618 |
|
---|
| 619 | /* Get the I2S APB1 clock configuration ------------------------------------*/
|
---|
| 620 | PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
|
---|
| 621 |
|
---|
| 622 | /* Get the I2S APB2 clock configuration ------------------------------------*/
|
---|
| 623 | PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
|
---|
| 624 |
|
---|
| 625 | /* Get the RTC Clock configuration -----------------------------------------*/
|
---|
| 626 | tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
|
---|
| 627 | PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
|
---|
| 628 |
|
---|
| 629 | /* Get the CEC clock configuration -----------------------------------------*/
|
---|
| 630 | PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
|
---|
| 631 |
|
---|
| 632 | /* Get the FMPI2C1 clock configuration -------------------------------------*/
|
---|
| 633 | PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
|
---|
| 634 |
|
---|
| 635 | /* Get the CK48 clock configuration ----------------------------------------*/
|
---|
| 636 | PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
|
---|
| 637 |
|
---|
| 638 | /* Get the SDIO clock configuration ----------------------------------------*/
|
---|
| 639 | PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
|
---|
| 640 |
|
---|
| 641 | /* Get the SPDIFRX clock configuration -------------------------------------*/
|
---|
| 642 | PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
|
---|
| 643 |
|
---|
| 644 | /* Get the TIM Prescaler configuration -------------------------------------*/
|
---|
| 645 | if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
|
---|
| 646 | {
|
---|
| 647 | PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
|
---|
| 648 | }
|
---|
| 649 | else
|
---|
| 650 | {
|
---|
| 651 | PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
|
---|
| 652 | }
|
---|
| 653 | }
|
---|
| 654 |
|
---|
| 655 | /**
|
---|
| 656 | * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
|
---|
| 657 | * @note Return 0 if peripheral clock identifier not managed by this API
|
---|
| 658 | * @param PeriphClk: Peripheral clock identifier
|
---|
| 659 | * This parameter can be one of the following values:
|
---|
| 660 | * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
|
---|
| 661 | * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
|
---|
| 662 | * @retval Frequency in KHz
|
---|
| 663 | */
|
---|
| 664 | uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
|
---|
| 665 | {
|
---|
| 666 | uint32_t tmpreg1 = 0;
|
---|
| 667 | /* This variable used to store the SAI clock frequency (value in Hz) */
|
---|
| 668 | uint32_t frequency = 0;
|
---|
| 669 | /* This variable used to store the VCO Input (value in Hz) */
|
---|
| 670 | uint32_t vcoinput = 0;
|
---|
| 671 | /* This variable used to store the SAI clock source */
|
---|
| 672 | uint32_t saiclocksource = 0;
|
---|
| 673 | if ((PeriphClk == RCC_PERIPHCLK_SAI1) || (PeriphClk == RCC_PERIPHCLK_SAI2))
|
---|
| 674 | {
|
---|
| 675 | saiclocksource = RCC->DCKCFGR;
|
---|
| 676 | saiclocksource &= (RCC_DCKCFGR_SAI1SRC | RCC_DCKCFGR_SAI2SRC);
|
---|
| 677 | switch (saiclocksource)
|
---|
| 678 | {
|
---|
| 679 | case 0: /* PLLSAI is the clock source for SAI*/
|
---|
| 680 | {
|
---|
| 681 | /* Configure the PLLSAI division factor */
|
---|
| 682 | /* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */
|
---|
| 683 | if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
|
---|
| 684 | {
|
---|
| 685 | /* In Case the PLL Source is HSI (Internal Clock) */
|
---|
| 686 | vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM));
|
---|
| 687 | }
|
---|
| 688 | else
|
---|
| 689 | {
|
---|
| 690 | /* In Case the PLL Source is HSE (External Clock) */
|
---|
| 691 | vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)));
|
---|
| 692 | }
|
---|
| 693 | /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
---|
| 694 | /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
|
---|
| 695 | tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
|
---|
| 696 | frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg1);
|
---|
| 697 |
|
---|
| 698 | /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
|
---|
| 699 | tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8) + 1);
|
---|
| 700 | frequency = frequency/(tmpreg1);
|
---|
| 701 | break;
|
---|
| 702 | }
|
---|
| 703 | case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/
|
---|
| 704 | case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/
|
---|
| 705 | {
|
---|
| 706 | /* Configure the PLLI2S division factor */
|
---|
| 707 | /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
|
---|
| 708 | if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
|
---|
| 709 | {
|
---|
| 710 | /* In Case the PLL Source is HSI (Internal Clock) */
|
---|
| 711 | vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
|
---|
| 712 | }
|
---|
| 713 | else
|
---|
| 714 | {
|
---|
| 715 | /* In Case the PLL Source is HSE (External Clock) */
|
---|
| 716 | vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)));
|
---|
| 717 | }
|
---|
| 718 |
|
---|
| 719 | /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
|
---|
| 720 | /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
|
---|
| 721 | tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
|
---|
| 722 | frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg1);
|
---|
| 723 |
|
---|
| 724 | /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
|
---|
| 725 | tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1);
|
---|
| 726 | frequency = frequency/(tmpreg1);
|
---|
| 727 | break;
|
---|
| 728 | }
|
---|
| 729 | case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/
|
---|
| 730 | case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/
|
---|
| 731 | {
|
---|
| 732 | /* Configure the PLLI2S division factor */
|
---|
| 733 | /* PLL_VCO Input = PLL_SOURCE/PLLM */
|
---|
| 734 | if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
|
---|
| 735 | {
|
---|
| 736 | /* In Case the PLL Source is HSI (Internal Clock) */
|
---|
| 737 | vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
|
---|
| 738 | }
|
---|
| 739 | else
|
---|
| 740 | {
|
---|
| 741 | /* In Case the PLL Source is HSE (External Clock) */
|
---|
| 742 | vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
|
---|
| 743 | }
|
---|
| 744 |
|
---|
| 745 | /* PLL_VCO Output = PLL_VCO Input * PLLN */
|
---|
| 746 | /* SAI_CLK_x = PLL_VCO Output/PLLR */
|
---|
| 747 | tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28;
|
---|
| 748 | frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6))/(tmpreg1);
|
---|
| 749 | break;
|
---|
| 750 | }
|
---|
| 751 | case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/
|
---|
| 752 | {
|
---|
| 753 | frequency = EXTERNAL_CLOCK_VALUE;
|
---|
| 754 | break;
|
---|
| 755 | }
|
---|
| 756 | case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/
|
---|
| 757 | {
|
---|
| 758 | if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
|
---|
| 759 | {
|
---|
| 760 | /* In Case the PLL Source is HSI (Internal Clock) */
|
---|
| 761 | frequency = (uint32_t)(HSI_VALUE);
|
---|
| 762 | }
|
---|
| 763 | else
|
---|
| 764 | {
|
---|
| 765 | /* In Case the PLL Source is HSE (External Clock) */
|
---|
| 766 | frequency = (uint32_t)(HSE_VALUE);
|
---|
| 767 | }
|
---|
| 768 | break;
|
---|
| 769 | }
|
---|
| 770 | default :
|
---|
| 771 | {
|
---|
| 772 | break;
|
---|
| 773 | }
|
---|
| 774 | }
|
---|
| 775 | }
|
---|
| 776 | return frequency;
|
---|
| 777 | }
|
---|
| 778 |
|
---|
| 779 | #endif /* STM32F446xx */
|
---|
| 780 |
|
---|
| 781 | #if defined(STM32F469xx) || defined(STM32F479xx)
|
---|
| 782 | /**
|
---|
| 783 | * @brief Initializes the RCC extended peripherals clocks according to the specified
|
---|
| 784 | * parameters in the RCC_PeriphCLKInitTypeDef.
|
---|
| 785 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
|
---|
| 786 | * contains the configuration information for the Extended Peripherals
|
---|
| 787 | * clocks(I2S, SAI, LTDC, RTC and TIM).
|
---|
| 788 | *
|
---|
| 789 | * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
|
---|
| 790 | * the RTC clock source; in this case the Backup domain will be reset in
|
---|
| 791 | * order to modify the RTC Clock source, as consequence RTC registers (including
|
---|
| 792 | * the backup registers) and RCC_BDCR register are set to their reset values.
|
---|
| 793 | *
|
---|
| 794 | * @retval HAL status
|
---|
| 795 | */
|
---|
| 796 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
---|
| 797 | {
|
---|
| 798 | uint32_t tickstart = 0;
|
---|
| 799 | uint32_t tmpreg1 = 0;
|
---|
| 800 | uint32_t pllsaip = 0;
|
---|
| 801 | uint32_t pllsaiq = 0;
|
---|
| 802 | uint32_t pllsair = 0;
|
---|
| 803 |
|
---|
| 804 | /* Check the parameters */
|
---|
| 805 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
---|
| 806 |
|
---|
| 807 | /*--------------------------- CLK48 Configuration --------------------------*/
|
---|
| 808 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48)
|
---|
| 809 | {
|
---|
| 810 | /* Check the parameters */
|
---|
| 811 | assert_param(IS_RCC_CK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
|
---|
| 812 |
|
---|
| 813 | /* Configure the CLK48 clock source */
|
---|
| 814 | __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
|
---|
| 815 | }
|
---|
| 816 | /*--------------------------------------------------------------------------*/
|
---|
| 817 |
|
---|
| 818 | /*------------------------------ SDIO Configuration ------------------------*/
|
---|
| 819 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
|
---|
| 820 | {
|
---|
| 821 | /* Check the parameters */
|
---|
| 822 | assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
|
---|
| 823 |
|
---|
| 824 | /* Configure the SDIO clock source */
|
---|
| 825 | __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
|
---|
| 826 | }
|
---|
| 827 | /*--------------------------------------------------------------------------*/
|
---|
| 828 |
|
---|
| 829 | /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
|
---|
| 830 | /*------------------- Common configuration SAI/I2S -------------------------*/
|
---|
| 831 | /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
|
---|
| 832 | factor is common parameters for both peripherals */
|
---|
| 833 | if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
|
---|
| 834 | (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
|
---|
| 835 | (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
|
---|
| 836 | {
|
---|
| 837 | /* check for Parameters */
|
---|
| 838 | assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
|
---|
| 839 |
|
---|
| 840 | /* Disable the PLLI2S */
|
---|
| 841 | __HAL_RCC_PLLI2S_DISABLE();
|
---|
| 842 | /* Get tick */
|
---|
| 843 | tickstart = HAL_GetTick();
|
---|
| 844 | /* Wait till PLLI2S is disabled */
|
---|
| 845 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
---|
| 846 | {
|
---|
| 847 | if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
|
---|
| 848 | {
|
---|
| 849 | /* return in case of Timeout detected */
|
---|
| 850 | return HAL_TIMEOUT;
|
---|
| 851 | }
|
---|
| 852 | }
|
---|
| 853 |
|
---|
| 854 | /*---------------------- I2S configuration -------------------------------*/
|
---|
| 855 | /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
|
---|
| 856 | only for I2S configuration */
|
---|
| 857 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
|
---|
| 858 | {
|
---|
| 859 | /* check for Parameters */
|
---|
| 860 | assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
---|
| 861 | /* Configure the PLLI2S division factors */
|
---|
| 862 | /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) ï¾ (PLLI2SN/PLLM) */
|
---|
| 863 | /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
|
---|
| 864 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
|
---|
| 865 | }
|
---|
| 866 |
|
---|
| 867 | /*---------------------------- SAI configuration -------------------------*/
|
---|
| 868 | /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
|
---|
| 869 | be added only for SAI configuration */
|
---|
| 870 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
|
---|
| 871 | {
|
---|
| 872 | /* Check the PLLI2S division factors */
|
---|
| 873 | assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
---|
| 874 | assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
|
---|
| 875 |
|
---|
| 876 | /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
|
---|
| 877 | tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
|
---|
| 878 | /* Configure the PLLI2S division factors */
|
---|
| 879 | /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
|
---|
| 880 | /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
|
---|
| 881 | /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
|
---|
| 882 | __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
|
---|
| 883 | /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
|
---|
| 884 | __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
|
---|
| 885 | }
|
---|
| 886 |
|
---|
| 887 | /*----------------- In Case of PLLI2S is just selected -----------------*/
|
---|
| 888 | if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
|
---|
| 889 | {
|
---|
| 890 | /* Check for Parameters */
|
---|
| 891 | assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
---|
| 892 | assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
---|
| 893 |
|
---|
| 894 | /* Configure the PLLI2S multiplication and division factors */
|
---|
| 895 | __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
|
---|
| 896 | }
|
---|
| 897 |
|
---|
| 898 | /* Enable the PLLI2S */
|
---|
| 899 | __HAL_RCC_PLLI2S_ENABLE();
|
---|
| 900 | /* Get tick */
|
---|
| 901 | tickstart = HAL_GetTick();
|
---|
| 902 | /* Wait till PLLI2S is ready */
|
---|
| 903 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
---|
| 904 | {
|
---|
| 905 | if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
|
---|
| 906 | {
|
---|
| 907 | /* return in case of Timeout detected */
|
---|
| 908 | return HAL_TIMEOUT;
|
---|
| 909 | }
|
---|
| 910 | }
|
---|
| 911 | }
|
---|
| 912 | /*--------------------------------------------------------------------------*/
|
---|
| 913 |
|
---|
| 914 | /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
|
---|
| 915 | /*----------------------- Common configuration SAI/LTDC --------------------*/
|
---|
| 916 | /* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division
|
---|
| 917 | factor is common parameters for these peripherals */
|
---|
| 918 | if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
|
---|
| 919 | (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) ||
|
---|
| 920 | ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48) &&
|
---|
| 921 | (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP)))
|
---|
| 922 | {
|
---|
| 923 | /* Check the PLLSAI division factors */
|
---|
| 924 | assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
|
---|
| 925 |
|
---|
| 926 | /* Disable PLLSAI Clock */
|
---|
| 927 | __HAL_RCC_PLLSAI_DISABLE();
|
---|
| 928 | /* Get tick */
|
---|
| 929 | tickstart = HAL_GetTick();
|
---|
| 930 | /* Wait till PLLSAI is disabled */
|
---|
| 931 | while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
---|
| 932 | {
|
---|
| 933 | if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
|
---|
| 934 | {
|
---|
| 935 | /* return in case of Timeout detected */
|
---|
| 936 | return HAL_TIMEOUT;
|
---|
| 937 | }
|
---|
| 938 | }
|
---|
| 939 |
|
---|
| 940 | /*---------------------------- SAI configuration -------------------------*/
|
---|
| 941 | /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
|
---|
| 942 | be added only for SAI configuration */
|
---|
| 943 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
|
---|
| 944 | {
|
---|
| 945 | assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
|
---|
| 946 | assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
|
---|
| 947 |
|
---|
| 948 | /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
|
---|
| 949 | pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1);
|
---|
| 950 | /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
|
---|
| 951 | pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
|
---|
| 952 | /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
|
---|
| 953 | /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
---|
| 954 | /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
|
---|
| 955 | __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair);
|
---|
| 956 | /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
|
---|
| 957 | __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
|
---|
| 958 | }
|
---|
| 959 |
|
---|
| 960 | /*---------------------------- LTDC configuration ------------------------*/
|
---|
| 961 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
|
---|
| 962 | {
|
---|
| 963 | assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
|
---|
| 964 | assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
|
---|
| 965 |
|
---|
| 966 | /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
|
---|
| 967 | pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1);
|
---|
| 968 | /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
|
---|
| 969 | pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
|
---|
| 970 | /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
|
---|
| 971 | /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
---|
| 972 | /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
|
---|
| 973 | __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR);
|
---|
| 974 | /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
|
---|
| 975 | __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
|
---|
| 976 | }
|
---|
| 977 |
|
---|
| 978 | /*---------------------------- CLK48 configuration ------------------------*/
|
---|
| 979 | /* Configure the PLLSAI when it is used as clock source for CLK48 */
|
---|
| 980 | if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == (RCC_PERIPHCLK_CK48)) &&
|
---|
| 981 | (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP))
|
---|
| 982 | {
|
---|
| 983 | assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
|
---|
| 984 |
|
---|
| 985 | /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
|
---|
| 986 | pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
|
---|
| 987 | /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
|
---|
| 988 | pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
|
---|
| 989 | /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
|
---|
| 990 | /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
---|
| 991 | /* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */
|
---|
| 992 | __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair);
|
---|
| 993 | }
|
---|
| 994 |
|
---|
| 995 | /* Enable PLLSAI Clock */
|
---|
| 996 | __HAL_RCC_PLLSAI_ENABLE();
|
---|
| 997 | /* Get tick */
|
---|
| 998 | tickstart = HAL_GetTick();
|
---|
| 999 | /* Wait till PLLSAI is ready */
|
---|
| 1000 | while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
---|
| 1001 | {
|
---|
| 1002 | if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
|
---|
| 1003 | {
|
---|
| 1004 | /* return in case of Timeout detected */
|
---|
| 1005 | return HAL_TIMEOUT;
|
---|
| 1006 | }
|
---|
| 1007 | }
|
---|
| 1008 | }
|
---|
| 1009 |
|
---|
| 1010 | /*--------------------------------------------------------------------------*/
|
---|
| 1011 |
|
---|
| 1012 | /*---------------------------- RTC configuration ---------------------------*/
|
---|
| 1013 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
---|
| 1014 | {
|
---|
| 1015 | /* Enable Power Clock*/
|
---|
| 1016 | __HAL_RCC_PWR_CLK_ENABLE();
|
---|
| 1017 |
|
---|
| 1018 | /* Enable write access to Backup domain */
|
---|
| 1019 | PWR->CR |= PWR_CR_DBP;
|
---|
| 1020 |
|
---|
| 1021 | /* Get tick */
|
---|
| 1022 | tickstart = HAL_GetTick();
|
---|
| 1023 |
|
---|
| 1024 | while((PWR->CR & PWR_CR_DBP) == RESET)
|
---|
| 1025 | {
|
---|
| 1026 | if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
|
---|
| 1027 | {
|
---|
| 1028 | return HAL_TIMEOUT;
|
---|
| 1029 | }
|
---|
| 1030 | }
|
---|
| 1031 | /* Reset the Backup domain only if the RTC Clock source selection is modified */
|
---|
| 1032 | if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
|
---|
| 1033 | {
|
---|
| 1034 | /* Store the content of BDCR register before the reset of Backup Domain */
|
---|
| 1035 | tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
---|
| 1036 | /* RTC Clock selection can be changed only if the Backup Domain is reset */
|
---|
| 1037 | __HAL_RCC_BACKUPRESET_FORCE();
|
---|
| 1038 | __HAL_RCC_BACKUPRESET_RELEASE();
|
---|
| 1039 | /* Restore the Content of BDCR register */
|
---|
| 1040 | RCC->BDCR = tmpreg1;
|
---|
| 1041 |
|
---|
| 1042 | /* Wait for LSERDY if LSE was enabled */
|
---|
| 1043 | if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
|
---|
| 1044 | {
|
---|
| 1045 | /* Get tick */
|
---|
| 1046 | tickstart = HAL_GetTick();
|
---|
| 1047 |
|
---|
| 1048 | /* Wait till LSE is ready */
|
---|
| 1049 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
---|
| 1050 | {
|
---|
| 1051 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
---|
| 1052 | {
|
---|
| 1053 | return HAL_TIMEOUT;
|
---|
| 1054 | }
|
---|
| 1055 | }
|
---|
| 1056 | }
|
---|
| 1057 | __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
---|
| 1058 | }
|
---|
| 1059 | }
|
---|
| 1060 | /*--------------------------------------------------------------------------*/
|
---|
| 1061 |
|
---|
| 1062 | /*---------------------------- TIM configuration ---------------------------*/
|
---|
| 1063 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
|
---|
| 1064 | {
|
---|
| 1065 | __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
|
---|
| 1066 | }
|
---|
| 1067 | return HAL_OK;
|
---|
| 1068 | }
|
---|
| 1069 |
|
---|
| 1070 | /**
|
---|
| 1071 | * @brief Configures the RCC_PeriphCLKInitTypeDef according to the internal
|
---|
| 1072 | * RCC configuration registers.
|
---|
| 1073 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
|
---|
| 1074 | * will be configured.
|
---|
| 1075 | * @retval None
|
---|
| 1076 | */
|
---|
| 1077 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
---|
| 1078 | {
|
---|
| 1079 | uint32_t tempreg;
|
---|
| 1080 |
|
---|
| 1081 | /* Set all possible values for the extended clock type parameter------------*/
|
---|
| 1082 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI |\
|
---|
| 1083 | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC |\
|
---|
| 1084 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
|
---|
| 1085 | RCC_PERIPHCLK_CK48 | RCC_PERIPHCLK_SDIO;
|
---|
| 1086 |
|
---|
| 1087 | /* Get the PLLI2S Clock configuration --------------------------------------*/
|
---|
| 1088 | PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
|
---|
| 1089 | PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
|
---|
| 1090 | PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
|
---|
| 1091 | /* Get the PLLSAI Clock configuration --------------------------------------*/
|
---|
| 1092 | PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
|
---|
| 1093 | PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
|
---|
| 1094 | PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
|
---|
| 1095 | /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
|
---|
| 1096 | PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
|
---|
| 1097 | PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
|
---|
| 1098 | PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
|
---|
| 1099 | /* Get the RTC Clock configuration -----------------------------------------*/
|
---|
| 1100 | tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
|
---|
| 1101 | PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
|
---|
| 1102 |
|
---|
| 1103 | /* Get the CK48 clock configuration --------------------------------------*/
|
---|
| 1104 | PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
|
---|
| 1105 |
|
---|
| 1106 | /* Get the SDIO clock configuration ----------------------------------------*/
|
---|
| 1107 | PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
|
---|
| 1108 |
|
---|
| 1109 | if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
|
---|
| 1110 | {
|
---|
| 1111 | PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
|
---|
| 1112 | }
|
---|
| 1113 | else
|
---|
| 1114 | {
|
---|
| 1115 | PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
|
---|
| 1116 | }
|
---|
| 1117 | }
|
---|
| 1118 | #endif /* STM32F469xx || STM32F479xx */
|
---|
| 1119 |
|
---|
| 1120 | #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
|
---|
| 1121 | /**
|
---|
| 1122 | * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
|
---|
| 1123 | * RCC_PeriphCLKInitTypeDef.
|
---|
| 1124 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
|
---|
| 1125 | * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
|
---|
| 1126 | *
|
---|
| 1127 | * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
|
---|
| 1128 | * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
|
---|
| 1129 | * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
|
---|
| 1130 | *
|
---|
| 1131 | * @retval HAL status
|
---|
| 1132 | */
|
---|
| 1133 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
---|
| 1134 | {
|
---|
| 1135 | uint32_t tickstart = 0;
|
---|
| 1136 | uint32_t tmpreg1 = 0;
|
---|
| 1137 |
|
---|
| 1138 | /* Check the parameters */
|
---|
| 1139 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
---|
| 1140 |
|
---|
| 1141 | /*---------------------------- RTC configuration ---------------------------*/
|
---|
| 1142 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
---|
| 1143 | {
|
---|
| 1144 | /* Enable Power Clock*/
|
---|
| 1145 | __HAL_RCC_PWR_CLK_ENABLE();
|
---|
| 1146 |
|
---|
| 1147 | /* Enable write access to Backup domain */
|
---|
| 1148 | PWR->CR |= PWR_CR_DBP;
|
---|
| 1149 |
|
---|
| 1150 | /* Get tick */
|
---|
| 1151 | tickstart = HAL_GetTick();
|
---|
| 1152 |
|
---|
| 1153 | while((PWR->CR & PWR_CR_DBP) == RESET)
|
---|
| 1154 | {
|
---|
| 1155 | if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
|
---|
| 1156 | {
|
---|
| 1157 | return HAL_TIMEOUT;
|
---|
| 1158 | }
|
---|
| 1159 | }
|
---|
| 1160 | /* Reset the Backup domain only if the RTC Clock source selection is modified */
|
---|
| 1161 | if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
|
---|
| 1162 | {
|
---|
| 1163 | /* Store the content of BDCR register before the reset of Backup Domain */
|
---|
| 1164 | tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
---|
| 1165 | /* RTC Clock selection can be changed only if the Backup Domain is reset */
|
---|
| 1166 | __HAL_RCC_BACKUPRESET_FORCE();
|
---|
| 1167 | __HAL_RCC_BACKUPRESET_RELEASE();
|
---|
| 1168 | /* Restore the Content of BDCR register */
|
---|
| 1169 | RCC->BDCR = tmpreg1;
|
---|
| 1170 |
|
---|
| 1171 | /* Wait for LSERDY if LSE was enabled */
|
---|
| 1172 | if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
|
---|
| 1173 | {
|
---|
| 1174 | /* Get tick */
|
---|
| 1175 | tickstart = HAL_GetTick();
|
---|
| 1176 |
|
---|
| 1177 | /* Wait till LSE is ready */
|
---|
| 1178 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
---|
| 1179 | {
|
---|
| 1180 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
---|
| 1181 | {
|
---|
| 1182 | return HAL_TIMEOUT;
|
---|
| 1183 | }
|
---|
| 1184 | }
|
---|
| 1185 | }
|
---|
| 1186 | __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
---|
| 1187 | }
|
---|
| 1188 | }
|
---|
| 1189 | /*--------------------------------------------------------------------------*/
|
---|
| 1190 |
|
---|
| 1191 | /*---------------------------- TIM configuration ---------------------------*/
|
---|
| 1192 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
|
---|
| 1193 | {
|
---|
| 1194 | __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
|
---|
| 1195 | }
|
---|
| 1196 | /*--------------------------------------------------------------------------*/
|
---|
| 1197 |
|
---|
| 1198 | /*---------------------------- FMPI2C1 Configuration -----------------------*/
|
---|
| 1199 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
|
---|
| 1200 | {
|
---|
| 1201 | /* Check the parameters */
|
---|
| 1202 | assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
|
---|
| 1203 |
|
---|
| 1204 | /* Configure the FMPI2C1 clock source */
|
---|
| 1205 | __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
|
---|
| 1206 | }
|
---|
| 1207 | /*--------------------------------------------------------------------------*/
|
---|
| 1208 |
|
---|
| 1209 | /*---------------------------- LPTIM1 Configuration ------------------------*/
|
---|
| 1210 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
|
---|
| 1211 | {
|
---|
| 1212 | /* Check the parameters */
|
---|
| 1213 | assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
|
---|
| 1214 |
|
---|
| 1215 | /* Configure the LPTIM1 clock source */
|
---|
| 1216 | __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
|
---|
| 1217 | }
|
---|
| 1218 |
|
---|
| 1219 | /*---------------------------- I2S Configuration ------------------------*/
|
---|
| 1220 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
|
---|
| 1221 | {
|
---|
| 1222 | /* Check the parameters */
|
---|
| 1223 | assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection));
|
---|
| 1224 |
|
---|
| 1225 | /* Configure the I2S clock source */
|
---|
| 1226 | __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection);
|
---|
| 1227 | }
|
---|
| 1228 |
|
---|
| 1229 | return HAL_OK;
|
---|
| 1230 | }
|
---|
| 1231 |
|
---|
| 1232 | /**
|
---|
| 1233 | * @brief Configures the RCC_OscInitStruct according to the internal
|
---|
| 1234 | * RCC configuration registers.
|
---|
| 1235 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
|
---|
| 1236 | * will be configured.
|
---|
| 1237 | * @retval None
|
---|
| 1238 | */
|
---|
| 1239 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
---|
| 1240 | {
|
---|
| 1241 | uint32_t tempreg;
|
---|
| 1242 |
|
---|
| 1243 | /* Set all possible values for the extended clock type parameter------------*/
|
---|
| 1244 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
|
---|
| 1245 |
|
---|
| 1246 | tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
|
---|
| 1247 | PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
|
---|
| 1248 |
|
---|
| 1249 | if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
|
---|
| 1250 | {
|
---|
| 1251 | PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
|
---|
| 1252 | }
|
---|
| 1253 | else
|
---|
| 1254 | {
|
---|
| 1255 | PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
|
---|
| 1256 | }
|
---|
| 1257 | /* Get the FMPI2C1 clock configuration -------------------------------------*/
|
---|
| 1258 | PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
|
---|
| 1259 |
|
---|
| 1260 | /* Get the I2S clock configuration -----------------------------------------*/
|
---|
| 1261 | PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE();
|
---|
| 1262 |
|
---|
| 1263 |
|
---|
| 1264 | }
|
---|
| 1265 | #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
|
---|
| 1266 |
|
---|
| 1267 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
---|
| 1268 | /**
|
---|
| 1269 | * @brief Initializes the RCC extended peripherals clocks according to the specified
|
---|
| 1270 | * parameters in the RCC_PeriphCLKInitTypeDef.
|
---|
| 1271 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
|
---|
| 1272 | * contains the configuration information for the Extended Peripherals
|
---|
| 1273 | * clocks(I2S, SAI, LTDC RTC and TIM).
|
---|
| 1274 | *
|
---|
| 1275 | * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
|
---|
| 1276 | * the RTC clock source; in this case the Backup domain will be reset in
|
---|
| 1277 | * order to modify the RTC Clock source, as consequence RTC registers (including
|
---|
| 1278 | * the backup registers) and RCC_BDCR register are set to their reset values.
|
---|
| 1279 | *
|
---|
| 1280 | * @retval HAL status
|
---|
| 1281 | */
|
---|
| 1282 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
---|
| 1283 | {
|
---|
| 1284 | uint32_t tickstart = 0;
|
---|
| 1285 | uint32_t tmpreg1 = 0;
|
---|
| 1286 |
|
---|
| 1287 | /* Check the parameters */
|
---|
| 1288 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
---|
| 1289 |
|
---|
| 1290 | /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
|
---|
| 1291 | /*----------------------- Common configuration SAI/I2S ----------------------*/
|
---|
| 1292 | /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
|
---|
| 1293 | factor is common parameters for both peripherals */
|
---|
| 1294 | if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
|
---|
| 1295 | (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
|
---|
| 1296 | {
|
---|
| 1297 | /* check for Parameters */
|
---|
| 1298 | assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
|
---|
| 1299 |
|
---|
| 1300 | /* Disable the PLLI2S */
|
---|
| 1301 | __HAL_RCC_PLLI2S_DISABLE();
|
---|
| 1302 | /* Get tick */
|
---|
| 1303 | tickstart = HAL_GetTick();
|
---|
| 1304 | /* Wait till PLLI2S is disabled */
|
---|
| 1305 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
---|
| 1306 | {
|
---|
| 1307 | if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
|
---|
| 1308 | {
|
---|
| 1309 | /* return in case of Timeout detected */
|
---|
| 1310 | return HAL_TIMEOUT;
|
---|
| 1311 | }
|
---|
| 1312 | }
|
---|
| 1313 |
|
---|
| 1314 | /*---------------------------- I2S configuration -------------------------------*/
|
---|
| 1315 | /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
|
---|
| 1316 | only for I2S configuration */
|
---|
| 1317 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
|
---|
| 1318 | {
|
---|
| 1319 | /* check for Parameters */
|
---|
| 1320 | assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
---|
| 1321 | /* Configure the PLLI2S division factors */
|
---|
| 1322 | /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
|
---|
| 1323 | /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
|
---|
| 1324 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
|
---|
| 1325 | }
|
---|
| 1326 |
|
---|
| 1327 | /*---------------------------- SAI configuration -------------------------------*/
|
---|
| 1328 | /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
|
---|
| 1329 | be added only for SAI configuration */
|
---|
| 1330 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
|
---|
| 1331 | {
|
---|
| 1332 | /* Check the PLLI2S division factors */
|
---|
| 1333 | assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
---|
| 1334 | assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
|
---|
| 1335 |
|
---|
| 1336 | /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
|
---|
| 1337 | tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
|
---|
| 1338 | /* Configure the PLLI2S division factors */
|
---|
| 1339 | /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
|
---|
| 1340 | /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
|
---|
| 1341 | /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
|
---|
| 1342 | __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
|
---|
| 1343 | /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
|
---|
| 1344 | __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
|
---|
| 1345 | }
|
---|
| 1346 |
|
---|
| 1347 | /* Enable the PLLI2S */
|
---|
| 1348 | __HAL_RCC_PLLI2S_ENABLE();
|
---|
| 1349 | /* Get tick */
|
---|
| 1350 | tickstart = HAL_GetTick();
|
---|
| 1351 | /* Wait till PLLI2S is ready */
|
---|
| 1352 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
---|
| 1353 | {
|
---|
| 1354 | if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
|
---|
| 1355 | {
|
---|
| 1356 | /* return in case of Timeout detected */
|
---|
| 1357 | return HAL_TIMEOUT;
|
---|
| 1358 | }
|
---|
| 1359 | }
|
---|
| 1360 | }
|
---|
| 1361 | /*--------------------------------------------------------------------------*/
|
---|
| 1362 |
|
---|
| 1363 | /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
|
---|
| 1364 | /*----------------------- Common configuration SAI/LTDC --------------------*/
|
---|
| 1365 | /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
|
---|
| 1366 | factor is common parameters for both peripherals */
|
---|
| 1367 | if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
|
---|
| 1368 | (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
|
---|
| 1369 | {
|
---|
| 1370 | /* Check the PLLSAI division factors */
|
---|
| 1371 | assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
|
---|
| 1372 |
|
---|
| 1373 | /* Disable PLLSAI Clock */
|
---|
| 1374 | __HAL_RCC_PLLSAI_DISABLE();
|
---|
| 1375 | /* Get tick */
|
---|
| 1376 | tickstart = HAL_GetTick();
|
---|
| 1377 | /* Wait till PLLSAI is disabled */
|
---|
| 1378 | while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
---|
| 1379 | {
|
---|
| 1380 | if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
|
---|
| 1381 | {
|
---|
| 1382 | /* return in case of Timeout detected */
|
---|
| 1383 | return HAL_TIMEOUT;
|
---|
| 1384 | }
|
---|
| 1385 | }
|
---|
| 1386 |
|
---|
| 1387 | /*---------------------------- SAI configuration -------------------------*/
|
---|
| 1388 | /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
|
---|
| 1389 | be added only for SAI configuration */
|
---|
| 1390 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
|
---|
| 1391 | {
|
---|
| 1392 | assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
|
---|
| 1393 | assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
|
---|
| 1394 |
|
---|
| 1395 | /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
|
---|
| 1396 | tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
|
---|
| 1397 | /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
|
---|
| 1398 | /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
---|
| 1399 | /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
|
---|
| 1400 | __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
|
---|
| 1401 | /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
|
---|
| 1402 | __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
|
---|
| 1403 | }
|
---|
| 1404 |
|
---|
| 1405 | /*---------------------------- LTDC configuration ------------------------*/
|
---|
| 1406 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
|
---|
| 1407 | {
|
---|
| 1408 | assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
|
---|
| 1409 | assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
|
---|
| 1410 |
|
---|
| 1411 | /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
|
---|
| 1412 | tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
|
---|
| 1413 | /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
|
---|
| 1414 | /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
---|
| 1415 | /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
|
---|
| 1416 | __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
|
---|
| 1417 | /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
|
---|
| 1418 | __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
|
---|
| 1419 | }
|
---|
| 1420 | /* Enable PLLSAI Clock */
|
---|
| 1421 | __HAL_RCC_PLLSAI_ENABLE();
|
---|
| 1422 | /* Get tick */
|
---|
| 1423 | tickstart = HAL_GetTick();
|
---|
| 1424 | /* Wait till PLLSAI is ready */
|
---|
| 1425 | while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
---|
| 1426 | {
|
---|
| 1427 | if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
|
---|
| 1428 | {
|
---|
| 1429 | /* return in case of Timeout detected */
|
---|
| 1430 | return HAL_TIMEOUT;
|
---|
| 1431 | }
|
---|
| 1432 | }
|
---|
| 1433 | }
|
---|
| 1434 | /*--------------------------------------------------------------------------*/
|
---|
| 1435 |
|
---|
| 1436 | /*---------------------------- RTC configuration ---------------------------*/
|
---|
| 1437 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
---|
| 1438 | {
|
---|
| 1439 | /* Enable Power Clock*/
|
---|
| 1440 | __HAL_RCC_PWR_CLK_ENABLE();
|
---|
| 1441 |
|
---|
| 1442 | /* Enable write access to Backup domain */
|
---|
| 1443 | PWR->CR |= PWR_CR_DBP;
|
---|
| 1444 |
|
---|
| 1445 | /* Get tick */
|
---|
| 1446 | tickstart = HAL_GetTick();
|
---|
| 1447 |
|
---|
| 1448 | while((PWR->CR & PWR_CR_DBP) == RESET)
|
---|
| 1449 | {
|
---|
| 1450 | if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
|
---|
| 1451 | {
|
---|
| 1452 | return HAL_TIMEOUT;
|
---|
| 1453 | }
|
---|
| 1454 | }
|
---|
| 1455 |
|
---|
| 1456 | /* Reset the Backup domain only if the RTC Clock source selection is modified */
|
---|
| 1457 | if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
|
---|
| 1458 | {
|
---|
| 1459 | /* Store the content of BDCR register before the reset of Backup Domain */
|
---|
| 1460 | tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
---|
| 1461 | /* RTC Clock selection can be changed only if the Backup Domain is reset */
|
---|
| 1462 | __HAL_RCC_BACKUPRESET_FORCE();
|
---|
| 1463 | __HAL_RCC_BACKUPRESET_RELEASE();
|
---|
| 1464 | /* Restore the Content of BDCR register */
|
---|
| 1465 | RCC->BDCR = tmpreg1;
|
---|
| 1466 |
|
---|
| 1467 | /* Wait for LSERDY if LSE was enabled */
|
---|
| 1468 | if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
|
---|
| 1469 | {
|
---|
| 1470 | /* Get tick */
|
---|
| 1471 | tickstart = HAL_GetTick();
|
---|
| 1472 |
|
---|
| 1473 | /* Wait till LSE is ready */
|
---|
| 1474 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
---|
| 1475 | {
|
---|
| 1476 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
---|
| 1477 | {
|
---|
| 1478 | return HAL_TIMEOUT;
|
---|
| 1479 | }
|
---|
| 1480 | }
|
---|
| 1481 | }
|
---|
| 1482 | __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
---|
| 1483 | }
|
---|
| 1484 | }
|
---|
| 1485 | /*--------------------------------------------------------------------------*/
|
---|
| 1486 |
|
---|
| 1487 | /*---------------------------- TIM configuration ---------------------------*/
|
---|
| 1488 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
|
---|
| 1489 | {
|
---|
| 1490 | __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
|
---|
| 1491 | }
|
---|
| 1492 | return HAL_OK;
|
---|
| 1493 | }
|
---|
| 1494 |
|
---|
| 1495 | /**
|
---|
| 1496 | * @brief Configures the PeriphClkInit according to the internal
|
---|
| 1497 | * RCC configuration registers.
|
---|
| 1498 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
|
---|
| 1499 | * will be configured.
|
---|
| 1500 | * @retval None
|
---|
| 1501 | */
|
---|
| 1502 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
---|
| 1503 | {
|
---|
| 1504 | uint32_t tempreg;
|
---|
| 1505 |
|
---|
| 1506 | /* Set all possible values for the extended clock type parameter------------*/
|
---|
| 1507 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
|
---|
| 1508 |
|
---|
| 1509 | /* Get the PLLI2S Clock configuration -----------------------------------------------*/
|
---|
| 1510 | PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
|
---|
| 1511 | PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
|
---|
| 1512 | PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
|
---|
| 1513 | /* Get the PLLSAI Clock configuration -----------------------------------------------*/
|
---|
| 1514 | PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
|
---|
| 1515 | PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
|
---|
| 1516 | PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
|
---|
| 1517 | /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
|
---|
| 1518 | PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
|
---|
| 1519 | PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
|
---|
| 1520 | PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
|
---|
| 1521 | /* Get the RTC Clock configuration -----------------------------------------------*/
|
---|
| 1522 | tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
|
---|
| 1523 | PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
|
---|
| 1524 |
|
---|
| 1525 | if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
|
---|
| 1526 | {
|
---|
| 1527 | PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
|
---|
| 1528 | }
|
---|
| 1529 | else
|
---|
| 1530 | {
|
---|
| 1531 | PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
|
---|
| 1532 | }
|
---|
| 1533 | }
|
---|
| 1534 |
|
---|
| 1535 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
---|
| 1536 |
|
---|
| 1537 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
|
---|
| 1538 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
|
---|
| 1539 | /**
|
---|
| 1540 | * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
|
---|
| 1541 | * RCC_PeriphCLKInitTypeDef.
|
---|
| 1542 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
|
---|
| 1543 | * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
|
---|
| 1544 | *
|
---|
| 1545 | * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
|
---|
| 1546 | * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
|
---|
| 1547 | * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
|
---|
| 1548 | *
|
---|
| 1549 | * @retval HAL status
|
---|
| 1550 | */
|
---|
| 1551 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
---|
| 1552 | {
|
---|
| 1553 | uint32_t tickstart = 0;
|
---|
| 1554 | uint32_t tmpreg1 = 0;
|
---|
| 1555 |
|
---|
| 1556 | /* Check the parameters */
|
---|
| 1557 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
---|
| 1558 |
|
---|
| 1559 | /*---------------------------- I2S configuration ---------------------------*/
|
---|
| 1560 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
|
---|
| 1561 | {
|
---|
| 1562 | /* check for Parameters */
|
---|
| 1563 | assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
---|
| 1564 | assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
|
---|
| 1565 | #if defined(STM32F411xE)
|
---|
| 1566 | assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
|
---|
| 1567 | #endif /* STM32F411xE */
|
---|
| 1568 | /* Disable the PLLI2S */
|
---|
| 1569 | __HAL_RCC_PLLI2S_DISABLE();
|
---|
| 1570 | /* Get tick */
|
---|
| 1571 | tickstart = HAL_GetTick();
|
---|
| 1572 | /* Wait till PLLI2S is disabled */
|
---|
| 1573 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
---|
| 1574 | {
|
---|
| 1575 | if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
|
---|
| 1576 | {
|
---|
| 1577 | /* return in case of Timeout detected */
|
---|
| 1578 | return HAL_TIMEOUT;
|
---|
| 1579 | }
|
---|
| 1580 | }
|
---|
| 1581 |
|
---|
| 1582 | #if defined(STM32F411xE)
|
---|
| 1583 | /* Configure the PLLI2S division factors */
|
---|
| 1584 | /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
---|
| 1585 | /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
|
---|
| 1586 | __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
|
---|
| 1587 | #else
|
---|
| 1588 | /* Configure the PLLI2S division factors */
|
---|
| 1589 | /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
|
---|
| 1590 | /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
|
---|
| 1591 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
|
---|
| 1592 | #endif /* STM32F411xE */
|
---|
| 1593 |
|
---|
| 1594 | /* Enable the PLLI2S */
|
---|
| 1595 | __HAL_RCC_PLLI2S_ENABLE();
|
---|
| 1596 | /* Get tick */
|
---|
| 1597 | tickstart = HAL_GetTick();
|
---|
| 1598 | /* Wait till PLLI2S is ready */
|
---|
| 1599 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
---|
| 1600 | {
|
---|
| 1601 | if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
|
---|
| 1602 | {
|
---|
| 1603 | /* return in case of Timeout detected */
|
---|
| 1604 | return HAL_TIMEOUT;
|
---|
| 1605 | }
|
---|
| 1606 | }
|
---|
| 1607 | }
|
---|
| 1608 |
|
---|
| 1609 | /*---------------------------- RTC configuration ---------------------------*/
|
---|
| 1610 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
---|
| 1611 | {
|
---|
| 1612 | /* Enable Power Clock*/
|
---|
| 1613 | __HAL_RCC_PWR_CLK_ENABLE();
|
---|
| 1614 |
|
---|
| 1615 | /* Enable write access to Backup domain */
|
---|
| 1616 | PWR->CR |= PWR_CR_DBP;
|
---|
| 1617 |
|
---|
| 1618 | /* Get tick */
|
---|
| 1619 | tickstart = HAL_GetTick();
|
---|
| 1620 |
|
---|
| 1621 | while((PWR->CR & PWR_CR_DBP) == RESET)
|
---|
| 1622 | {
|
---|
| 1623 | if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
|
---|
| 1624 | {
|
---|
| 1625 | return HAL_TIMEOUT;
|
---|
| 1626 | }
|
---|
| 1627 | }
|
---|
| 1628 |
|
---|
| 1629 | /* Reset the Backup domain only if the RTC Clock source selection is modified */
|
---|
| 1630 | if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
|
---|
| 1631 | {
|
---|
| 1632 | /* Store the content of BDCR register before the reset of Backup Domain */
|
---|
| 1633 | tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
---|
| 1634 | /* RTC Clock selection can be changed only if the Backup Domain is reset */
|
---|
| 1635 | __HAL_RCC_BACKUPRESET_FORCE();
|
---|
| 1636 | __HAL_RCC_BACKUPRESET_RELEASE();
|
---|
| 1637 | /* Restore the Content of BDCR register */
|
---|
| 1638 | RCC->BDCR = tmpreg1;
|
---|
| 1639 |
|
---|
| 1640 | /* Wait for LSERDY if LSE was enabled */
|
---|
| 1641 | if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
|
---|
| 1642 | {
|
---|
| 1643 | /* Get tick */
|
---|
| 1644 | tickstart = HAL_GetTick();
|
---|
| 1645 |
|
---|
| 1646 | /* Wait till LSE is ready */
|
---|
| 1647 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
---|
| 1648 | {
|
---|
| 1649 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
---|
| 1650 | {
|
---|
| 1651 | return HAL_TIMEOUT;
|
---|
| 1652 | }
|
---|
| 1653 | }
|
---|
| 1654 | }
|
---|
| 1655 | __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
---|
| 1656 | }
|
---|
| 1657 | }
|
---|
| 1658 |
|
---|
| 1659 | return HAL_OK;
|
---|
| 1660 | }
|
---|
| 1661 |
|
---|
| 1662 | /**
|
---|
| 1663 | * @brief Configures the RCC_OscInitStruct according to the internal
|
---|
| 1664 | * RCC configuration registers.
|
---|
| 1665 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
|
---|
| 1666 | * will be configured.
|
---|
| 1667 | * @retval None
|
---|
| 1668 | */
|
---|
| 1669 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
---|
| 1670 | {
|
---|
| 1671 | uint32_t tempreg;
|
---|
| 1672 |
|
---|
| 1673 | /* Set all possible values for the extended clock type parameter------------*/
|
---|
| 1674 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
|
---|
| 1675 |
|
---|
| 1676 | /* Get the PLLI2S Clock configuration --------------------------------------*/
|
---|
| 1677 | PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
|
---|
| 1678 | PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
|
---|
| 1679 | #if defined(STM32F411xE)
|
---|
| 1680 | PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
|
---|
| 1681 | #endif /* STM32F411xE */
|
---|
| 1682 | /* Get the RTC Clock configuration -----------------------------------------*/
|
---|
| 1683 | tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
|
---|
| 1684 | PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
|
---|
| 1685 |
|
---|
| 1686 | }
|
---|
| 1687 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
|
---|
| 1688 |
|
---|
| 1689 | #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
---|
| 1690 | /**
|
---|
| 1691 | * @brief Initializes the RCC Oscillators according to the specified parameters in the
|
---|
| 1692 | * RCC_OscInitTypeDef.
|
---|
| 1693 | * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
|
---|
| 1694 | * contains the configuration information for the RCC Oscillators.
|
---|
| 1695 | * @note The PLL is not disabled when used as system clock.
|
---|
| 1696 | * @note This function add the PLL/PLLR factor management during PLL configuration this feature
|
---|
| 1697 | * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx devices
|
---|
| 1698 | * @retval HAL status
|
---|
| 1699 | */
|
---|
| 1700 | HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
---|
| 1701 | {
|
---|
| 1702 | uint32_t tickstart = 0;
|
---|
| 1703 |
|
---|
| 1704 | /* Check the parameters */
|
---|
| 1705 | assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
---|
| 1706 | /*------------------------------- HSE Configuration ------------------------*/
|
---|
| 1707 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
---|
| 1708 | {
|
---|
| 1709 | /* Check the parameters */
|
---|
| 1710 | assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
---|
| 1711 | /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
|
---|
| 1712 | #if defined(STM32F446xx)
|
---|
| 1713 | if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
|
---|
| 1714 | ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\
|
---|
| 1715 | ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
---|
| 1716 | #else
|
---|
| 1717 | if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
|
---|
| 1718 | ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
---|
| 1719 | #endif /* STM32F446xx */
|
---|
| 1720 | {
|
---|
| 1721 | if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
---|
| 1722 | {
|
---|
| 1723 | return HAL_ERROR;
|
---|
| 1724 | }
|
---|
| 1725 | }
|
---|
| 1726 | else
|
---|
| 1727 | {
|
---|
| 1728 | /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
|
---|
| 1729 | __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
|
---|
| 1730 |
|
---|
| 1731 | /* Get Start Tick*/
|
---|
| 1732 | tickstart = HAL_GetTick();
|
---|
| 1733 |
|
---|
| 1734 | /* Wait till HSE is disabled */
|
---|
| 1735 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
---|
| 1736 | {
|
---|
| 1737 | if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
|
---|
| 1738 | {
|
---|
| 1739 | return HAL_TIMEOUT;
|
---|
| 1740 | }
|
---|
| 1741 | }
|
---|
| 1742 |
|
---|
| 1743 | /* Set the new HSE configuration ---------------------------------------*/
|
---|
| 1744 | __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
---|
| 1745 |
|
---|
| 1746 | /* Check the HSE State */
|
---|
| 1747 | if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
|
---|
| 1748 | {
|
---|
| 1749 | /* Get Start Tick*/
|
---|
| 1750 | tickstart = HAL_GetTick();
|
---|
| 1751 |
|
---|
| 1752 | /* Wait till HSE is ready */
|
---|
| 1753 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
---|
| 1754 | {
|
---|
| 1755 | if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
|
---|
| 1756 | {
|
---|
| 1757 | return HAL_TIMEOUT;
|
---|
| 1758 | }
|
---|
| 1759 | }
|
---|
| 1760 | }
|
---|
| 1761 | else
|
---|
| 1762 | {
|
---|
| 1763 | /* Get Start Tick*/
|
---|
| 1764 | tickstart = HAL_GetTick();
|
---|
| 1765 |
|
---|
| 1766 | /* Wait till HSE is bypassed or disabled */
|
---|
| 1767 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
---|
| 1768 | {
|
---|
| 1769 | if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
|
---|
| 1770 | {
|
---|
| 1771 | return HAL_TIMEOUT;
|
---|
| 1772 | }
|
---|
| 1773 | }
|
---|
| 1774 | }
|
---|
| 1775 | }
|
---|
| 1776 | }
|
---|
| 1777 | /*----------------------------- HSI Configuration --------------------------*/
|
---|
| 1778 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
---|
| 1779 | {
|
---|
| 1780 | /* Check the parameters */
|
---|
| 1781 | assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
---|
| 1782 | assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
---|
| 1783 |
|
---|
| 1784 | /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
---|
| 1785 | #if defined(STM32F446xx)
|
---|
| 1786 | if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
|
---|
| 1787 | ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\
|
---|
| 1788 | ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
---|
| 1789 | #else
|
---|
| 1790 | if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
|
---|
| 1791 | ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
---|
| 1792 | #endif /* STM32F446xx */
|
---|
| 1793 | {
|
---|
| 1794 | /* When HSI is used as system clock it will not disabled */
|
---|
| 1795 | if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
---|
| 1796 | {
|
---|
| 1797 | return HAL_ERROR;
|
---|
| 1798 | }
|
---|
| 1799 | /* Otherwise, just the calibration is allowed */
|
---|
| 1800 | else
|
---|
| 1801 | {
|
---|
| 1802 | /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
---|
| 1803 | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
---|
| 1804 | }
|
---|
| 1805 | }
|
---|
| 1806 | else
|
---|
| 1807 | {
|
---|
| 1808 | /* Check the HSI State */
|
---|
| 1809 | if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
|
---|
| 1810 | {
|
---|
| 1811 | /* Enable the Internal High Speed oscillator (HSI). */
|
---|
| 1812 | __HAL_RCC_HSI_ENABLE();
|
---|
| 1813 |
|
---|
| 1814 | /* Get Start Tick*/
|
---|
| 1815 | tickstart = HAL_GetTick();
|
---|
| 1816 |
|
---|
| 1817 | /* Wait till HSI is ready */
|
---|
| 1818 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
---|
| 1819 | {
|
---|
| 1820 | if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
|
---|
| 1821 | {
|
---|
| 1822 | return HAL_TIMEOUT;
|
---|
| 1823 | }
|
---|
| 1824 | }
|
---|
| 1825 |
|
---|
| 1826 | /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
---|
| 1827 | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
---|
| 1828 | }
|
---|
| 1829 | else
|
---|
| 1830 | {
|
---|
| 1831 | /* Disable the Internal High Speed oscillator (HSI). */
|
---|
| 1832 | __HAL_RCC_HSI_DISABLE();
|
---|
| 1833 |
|
---|
| 1834 | /* Get Start Tick*/
|
---|
| 1835 | tickstart = HAL_GetTick();
|
---|
| 1836 |
|
---|
| 1837 | /* Wait till HSI is ready */
|
---|
| 1838 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
---|
| 1839 | {
|
---|
| 1840 | if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
|
---|
| 1841 | {
|
---|
| 1842 | return HAL_TIMEOUT;
|
---|
| 1843 | }
|
---|
| 1844 | }
|
---|
| 1845 | }
|
---|
| 1846 | }
|
---|
| 1847 | }
|
---|
| 1848 | /*------------------------------ LSI Configuration -------------------------*/
|
---|
| 1849 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
---|
| 1850 | {
|
---|
| 1851 | /* Check the parameters */
|
---|
| 1852 | assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
---|
| 1853 |
|
---|
| 1854 | /* Check the LSI State */
|
---|
| 1855 | if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
|
---|
| 1856 | {
|
---|
| 1857 | /* Enable the Internal Low Speed oscillator (LSI). */
|
---|
| 1858 | __HAL_RCC_LSI_ENABLE();
|
---|
| 1859 |
|
---|
| 1860 | /* Get Start Tick*/
|
---|
| 1861 | tickstart = HAL_GetTick();
|
---|
| 1862 |
|
---|
| 1863 | /* Wait till LSI is ready */
|
---|
| 1864 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
---|
| 1865 | {
|
---|
| 1866 | if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
|
---|
| 1867 | {
|
---|
| 1868 | return HAL_TIMEOUT;
|
---|
| 1869 | }
|
---|
| 1870 | }
|
---|
| 1871 | }
|
---|
| 1872 | else
|
---|
| 1873 | {
|
---|
| 1874 | /* Disable the Internal Low Speed oscillator (LSI). */
|
---|
| 1875 | __HAL_RCC_LSI_DISABLE();
|
---|
| 1876 |
|
---|
| 1877 | /* Get Start Tick*/
|
---|
| 1878 | tickstart = HAL_GetTick();
|
---|
| 1879 |
|
---|
| 1880 | /* Wait till LSI is ready */
|
---|
| 1881 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
---|
| 1882 | {
|
---|
| 1883 | if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
|
---|
| 1884 | {
|
---|
| 1885 | return HAL_TIMEOUT;
|
---|
| 1886 | }
|
---|
| 1887 | }
|
---|
| 1888 | }
|
---|
| 1889 | }
|
---|
| 1890 | /*------------------------------ LSE Configuration -------------------------*/
|
---|
| 1891 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
---|
| 1892 | {
|
---|
| 1893 | /* Check the parameters */
|
---|
| 1894 | assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
---|
| 1895 |
|
---|
| 1896 | /* Enable Power Clock*/
|
---|
| 1897 | __HAL_RCC_PWR_CLK_ENABLE();
|
---|
| 1898 |
|
---|
| 1899 | /* Enable write access to Backup domain */
|
---|
| 1900 | PWR->CR |= PWR_CR_DBP;
|
---|
| 1901 |
|
---|
| 1902 | /* Wait for Backup domain Write protection disable */
|
---|
| 1903 | tickstart = HAL_GetTick();
|
---|
| 1904 |
|
---|
| 1905 | while((PWR->CR & PWR_CR_DBP) == RESET)
|
---|
| 1906 | {
|
---|
| 1907 | if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
|
---|
| 1908 | {
|
---|
| 1909 | return HAL_TIMEOUT;
|
---|
| 1910 | }
|
---|
| 1911 | }
|
---|
| 1912 |
|
---|
| 1913 | /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
|
---|
| 1914 | __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
|
---|
| 1915 |
|
---|
| 1916 | /* Get Start Tick*/
|
---|
| 1917 | tickstart = HAL_GetTick();
|
---|
| 1918 |
|
---|
| 1919 | /* Wait till LSE is ready */
|
---|
| 1920 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
---|
| 1921 | {
|
---|
| 1922 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
---|
| 1923 | {
|
---|
| 1924 | return HAL_TIMEOUT;
|
---|
| 1925 | }
|
---|
| 1926 | }
|
---|
| 1927 |
|
---|
| 1928 | /* Set the new LSE configuration -----------------------------------------*/
|
---|
| 1929 | __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
---|
| 1930 | /* Check the LSE State */
|
---|
| 1931 | if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
|
---|
| 1932 | {
|
---|
| 1933 | /* Get Start Tick*/
|
---|
| 1934 | tickstart = HAL_GetTick();
|
---|
| 1935 |
|
---|
| 1936 | /* Wait till LSE is ready */
|
---|
| 1937 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
---|
| 1938 | {
|
---|
| 1939 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
---|
| 1940 | {
|
---|
| 1941 | return HAL_TIMEOUT;
|
---|
| 1942 | }
|
---|
| 1943 | }
|
---|
| 1944 | }
|
---|
| 1945 | else
|
---|
| 1946 | {
|
---|
| 1947 | /* Get Start Tick*/
|
---|
| 1948 | tickstart = HAL_GetTick();
|
---|
| 1949 |
|
---|
| 1950 | /* Wait till LSE is ready */
|
---|
| 1951 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
---|
| 1952 | {
|
---|
| 1953 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
---|
| 1954 | {
|
---|
| 1955 | return HAL_TIMEOUT;
|
---|
| 1956 | }
|
---|
| 1957 | }
|
---|
| 1958 | }
|
---|
| 1959 | }
|
---|
| 1960 | /*-------------------------------- PLL Configuration -----------------------*/
|
---|
| 1961 | /* Check the parameters */
|
---|
| 1962 | assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
---|
| 1963 | if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
---|
| 1964 | {
|
---|
| 1965 | /* Check if the PLL is used as system clock or not */
|
---|
| 1966 | if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
|
---|
| 1967 | {
|
---|
| 1968 | if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
---|
| 1969 | {
|
---|
| 1970 | /* Check the parameters */
|
---|
| 1971 | assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
|
---|
| 1972 | assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
|
---|
| 1973 | assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
|
---|
| 1974 | assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
|
---|
| 1975 | assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
---|
| 1976 | assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
---|
| 1977 |
|
---|
| 1978 | /* Disable the main PLL. */
|
---|
| 1979 | __HAL_RCC_PLL_DISABLE();
|
---|
| 1980 |
|
---|
| 1981 | /* Get Start Tick*/
|
---|
| 1982 | tickstart = HAL_GetTick();
|
---|
| 1983 |
|
---|
| 1984 | /* Wait till PLL is ready */
|
---|
| 1985 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
---|
| 1986 | {
|
---|
| 1987 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
---|
| 1988 | {
|
---|
| 1989 | return HAL_TIMEOUT;
|
---|
| 1990 | }
|
---|
| 1991 | }
|
---|
| 1992 |
|
---|
| 1993 | /* Configure the main PLL clock source, multiplication and division factors. */
|
---|
| 1994 | __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
---|
| 1995 | RCC_OscInitStruct->PLL.PLLM,
|
---|
| 1996 | RCC_OscInitStruct->PLL.PLLN,
|
---|
| 1997 | RCC_OscInitStruct->PLL.PLLP,
|
---|
| 1998 | RCC_OscInitStruct->PLL.PLLQ,
|
---|
| 1999 | RCC_OscInitStruct->PLL.PLLR);
|
---|
| 2000 |
|
---|
| 2001 | /* Enable the main PLL. */
|
---|
| 2002 | __HAL_RCC_PLL_ENABLE();
|
---|
| 2003 |
|
---|
| 2004 | /* Get Start Tick*/
|
---|
| 2005 | tickstart = HAL_GetTick();
|
---|
| 2006 |
|
---|
| 2007 | /* Wait till PLL is ready */
|
---|
| 2008 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
---|
| 2009 | {
|
---|
| 2010 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
---|
| 2011 | {
|
---|
| 2012 | return HAL_TIMEOUT;
|
---|
| 2013 | }
|
---|
| 2014 | }
|
---|
| 2015 | }
|
---|
| 2016 | else
|
---|
| 2017 | {
|
---|
| 2018 | /* Disable the main PLL. */
|
---|
| 2019 | __HAL_RCC_PLL_DISABLE();
|
---|
| 2020 |
|
---|
| 2021 | /* Get Start Tick*/
|
---|
| 2022 | tickstart = HAL_GetTick();
|
---|
| 2023 |
|
---|
| 2024 | /* Wait till PLL is ready */
|
---|
| 2025 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
---|
| 2026 | {
|
---|
| 2027 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
---|
| 2028 | {
|
---|
| 2029 | return HAL_TIMEOUT;
|
---|
| 2030 | }
|
---|
| 2031 | }
|
---|
| 2032 | }
|
---|
| 2033 | }
|
---|
| 2034 | else
|
---|
| 2035 | {
|
---|
| 2036 | return HAL_ERROR;
|
---|
| 2037 | }
|
---|
| 2038 | }
|
---|
| 2039 | return HAL_OK;
|
---|
| 2040 | }
|
---|
| 2041 |
|
---|
| 2042 | /**
|
---|
| 2043 | * @brief Configures the RCC_OscInitStruct according to the internal
|
---|
| 2044 | * RCC configuration registers.
|
---|
| 2045 | * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that will be configured.
|
---|
| 2046 | *
|
---|
| 2047 | * @note This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
|
---|
| 2048 | * @note This function add the PLL/PLLR factor management
|
---|
| 2049 | * @retval None
|
---|
| 2050 | */
|
---|
| 2051 | void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
---|
| 2052 | {
|
---|
| 2053 | /* Set all possible values for the Oscillator type parameter ---------------*/
|
---|
| 2054 | RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
|
---|
| 2055 |
|
---|
| 2056 | /* Get the HSE configuration -----------------------------------------------*/
|
---|
| 2057 | if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
|
---|
| 2058 | {
|
---|
| 2059 | RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
|
---|
| 2060 | }
|
---|
| 2061 | else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
|
---|
| 2062 | {
|
---|
| 2063 | RCC_OscInitStruct->HSEState = RCC_HSE_ON;
|
---|
| 2064 | }
|
---|
| 2065 | else
|
---|
| 2066 | {
|
---|
| 2067 | RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
|
---|
| 2068 | }
|
---|
| 2069 |
|
---|
| 2070 | /* Get the HSI configuration -----------------------------------------------*/
|
---|
| 2071 | if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
|
---|
| 2072 | {
|
---|
| 2073 | RCC_OscInitStruct->HSIState = RCC_HSI_ON;
|
---|
| 2074 | }
|
---|
| 2075 | else
|
---|
| 2076 | {
|
---|
| 2077 | RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
|
---|
| 2078 | }
|
---|
| 2079 |
|
---|
| 2080 | RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
|
---|
| 2081 |
|
---|
| 2082 | /* Get the LSE configuration -----------------------------------------------*/
|
---|
| 2083 | if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
|
---|
| 2084 | {
|
---|
| 2085 | RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
|
---|
| 2086 | }
|
---|
| 2087 | else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
|
---|
| 2088 | {
|
---|
| 2089 | RCC_OscInitStruct->LSEState = RCC_LSE_ON;
|
---|
| 2090 | }
|
---|
| 2091 | else
|
---|
| 2092 | {
|
---|
| 2093 | RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
|
---|
| 2094 | }
|
---|
| 2095 |
|
---|
| 2096 | /* Get the LSI configuration -----------------------------------------------*/
|
---|
| 2097 | if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
|
---|
| 2098 | {
|
---|
| 2099 | RCC_OscInitStruct->LSIState = RCC_LSI_ON;
|
---|
| 2100 | }
|
---|
| 2101 | else
|
---|
| 2102 | {
|
---|
| 2103 | RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
|
---|
| 2104 | }
|
---|
| 2105 |
|
---|
| 2106 | /* Get the PLL configuration -----------------------------------------------*/
|
---|
| 2107 | if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
|
---|
| 2108 | {
|
---|
| 2109 | RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
|
---|
| 2110 | }
|
---|
| 2111 | else
|
---|
| 2112 | {
|
---|
| 2113 | RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
|
---|
| 2114 | }
|
---|
| 2115 | RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
|
---|
| 2116 | RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
|
---|
| 2117 | RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
|
---|
| 2118 | RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
|
---|
| 2119 | RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
|
---|
| 2120 | RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
|
---|
| 2121 | }
|
---|
| 2122 | #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
|
---|
| 2123 |
|
---|
| 2124 | #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
---|
| 2125 | /**
|
---|
| 2126 | * @brief Select LSE mode
|
---|
| 2127 | *
|
---|
| 2128 | * @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
|
---|
| 2129 | *
|
---|
| 2130 | * @param Mode: specifies the LSE mode.
|
---|
| 2131 | * This parameter can be one of the following values:
|
---|
| 2132 | * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection
|
---|
| 2133 | * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
|
---|
| 2134 | * @retval None
|
---|
| 2135 | */
|
---|
| 2136 | void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
|
---|
| 2137 | {
|
---|
| 2138 | /* Check the parameters */
|
---|
| 2139 | assert_param(IS_RCC_LSE_MODE(Mode));
|
---|
| 2140 | if(Mode == RCC_LSE_HIGHDRIVE_MODE)
|
---|
| 2141 | {
|
---|
| 2142 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
|
---|
| 2143 | }
|
---|
| 2144 | else
|
---|
| 2145 | {
|
---|
| 2146 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
|
---|
| 2147 | }
|
---|
| 2148 | }
|
---|
| 2149 |
|
---|
| 2150 | #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
|
---|
| 2151 |
|
---|
| 2152 | #if defined(STM32F446xx)
|
---|
| 2153 | /**
|
---|
| 2154 | * @brief Returns the SYSCLK frequency
|
---|
| 2155 | *
|
---|
| 2156 | * @note This function implementation is valide only for STM32F446xx devices.
|
---|
| 2157 | * @note This function add the PLL/PLLR System clock source
|
---|
| 2158 | *
|
---|
| 2159 | * @note The system frequency computed by this function is not the real
|
---|
| 2160 | * frequency in the chip. It is calculated based on the predefined
|
---|
| 2161 | * constant and the selected clock source:
|
---|
| 2162 | * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
|
---|
| 2163 | * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
|
---|
| 2164 | * @note If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**)
|
---|
| 2165 | * or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
---|
| 2166 | * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
|
---|
| 2167 | * 16 MHz) but the real value may vary depending on the variations
|
---|
| 2168 | * in voltage and temperature.
|
---|
| 2169 | * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
|
---|
| 2170 | * 25 MHz), user has to ensure that HSE_VALUE is same as the real
|
---|
| 2171 | * frequency of the crystal used. Otherwise, this function may
|
---|
| 2172 | * have wrong result.
|
---|
| 2173 | *
|
---|
| 2174 | * @note The result of this function could be not correct when using fractional
|
---|
| 2175 | * value for HSE crystal.
|
---|
| 2176 | *
|
---|
| 2177 | * @note This function can be used by the user application to compute the
|
---|
| 2178 | * baudrate for the communication peripherals or configure other parameters.
|
---|
| 2179 | *
|
---|
| 2180 | * @note Each time SYSCLK changes, this function must be called to update the
|
---|
| 2181 | * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
---|
| 2182 | *
|
---|
| 2183 | *
|
---|
| 2184 | * @retval SYSCLK frequency
|
---|
| 2185 | */
|
---|
| 2186 | uint32_t HAL_RCC_GetSysClockFreq(void)
|
---|
| 2187 | {
|
---|
| 2188 | uint32_t pllm = 0;
|
---|
| 2189 | uint32_t pllvco = 0;
|
---|
| 2190 | uint32_t pllp = 0;
|
---|
| 2191 | uint32_t pllr = 0;
|
---|
| 2192 | uint32_t sysclockfreq = 0;
|
---|
| 2193 |
|
---|
| 2194 | /* Get SYSCLK source -------------------------------------------------------*/
|
---|
| 2195 | switch (RCC->CFGR & RCC_CFGR_SWS)
|
---|
| 2196 | {
|
---|
| 2197 | case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
|
---|
| 2198 | {
|
---|
| 2199 | sysclockfreq = HSI_VALUE;
|
---|
| 2200 | break;
|
---|
| 2201 | }
|
---|
| 2202 | case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
|
---|
| 2203 | {
|
---|
| 2204 | sysclockfreq = HSE_VALUE;
|
---|
| 2205 | break;
|
---|
| 2206 | }
|
---|
| 2207 | case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */
|
---|
| 2208 | {
|
---|
| 2209 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
---|
| 2210 | SYSCLK = PLL_VCO / PLLP */
|
---|
| 2211 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
---|
| 2212 | if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
---|
| 2213 | {
|
---|
| 2214 | /* HSE used as PLL clock source */
|
---|
| 2215 | pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
|
---|
| 2216 | }
|
---|
| 2217 | else
|
---|
| 2218 | {
|
---|
| 2219 | /* HSI used as PLL clock source */
|
---|
| 2220 | pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
|
---|
| 2221 | }
|
---|
| 2222 | pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
|
---|
| 2223 |
|
---|
| 2224 | sysclockfreq = pllvco/pllp;
|
---|
| 2225 | break;
|
---|
| 2226 | }
|
---|
| 2227 | case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */
|
---|
| 2228 | {
|
---|
| 2229 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
---|
| 2230 | SYSCLK = PLL_VCO / PLLR */
|
---|
| 2231 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
---|
| 2232 | if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
---|
| 2233 | {
|
---|
| 2234 | /* HSE used as PLL clock source */
|
---|
| 2235 | pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
|
---|
| 2236 | }
|
---|
| 2237 | else
|
---|
| 2238 | {
|
---|
| 2239 | /* HSI used as PLL clock source */
|
---|
| 2240 | pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
|
---|
| 2241 | }
|
---|
| 2242 | pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
|
---|
| 2243 |
|
---|
| 2244 | sysclockfreq = pllvco/pllr;
|
---|
| 2245 | break;
|
---|
| 2246 | }
|
---|
| 2247 | default:
|
---|
| 2248 | {
|
---|
| 2249 | sysclockfreq = HSI_VALUE;
|
---|
| 2250 | break;
|
---|
| 2251 | }
|
---|
| 2252 | }
|
---|
| 2253 | return sysclockfreq;
|
---|
| 2254 | }
|
---|
| 2255 | #endif /* STM32F446xx */
|
---|
| 2256 |
|
---|
| 2257 | /**
|
---|
| 2258 | * @}
|
---|
| 2259 | */
|
---|
| 2260 |
|
---|
| 2261 | /**
|
---|
| 2262 | * @}
|
---|
| 2263 | */
|
---|
| 2264 |
|
---|
| 2265 | #endif /* HAL_RCC_MODULE_ENABLED */
|
---|
| 2266 | /**
|
---|
| 2267 | * @}
|
---|
| 2268 | */
|
---|
| 2269 |
|
---|
| 2270 | /**
|
---|
| 2271 | * @}
|
---|
| 2272 | */
|
---|
| 2273 |
|
---|
| 2274 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
---|