1 | /**
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2 | ******************************************************************************
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3 | * @file stm32f4xx_hal_rcc.c
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4 | * @author MCD Application Team
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5 | * @version V1.4.1
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6 | * @date 09-October-2015
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7 | * @brief RCC HAL module driver.
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8 | * This file provides firmware functions to manage the following
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9 | * functionalities of the Reset and Clock Control (RCC) peripheral:
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10 | * + Initialization and de-initialization functions
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11 | * + Peripheral Control functions
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12 | *
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13 | @verbatim
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14 | ==============================================================================
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15 | ##### RCC specific features #####
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16 | ==============================================================================
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17 | [..]
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18 | After reset the device is running from Internal High Speed oscillator
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19 | (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
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20 | and I-Cache are disabled, and all peripherals are off except internal
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21 | SRAM, Flash and JTAG.
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22 | (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
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23 | all peripherals mapped on these busses are running at HSI speed.
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24 | (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
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25 | (+) All GPIOs are in input floating state, except the JTAG pins which
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26 | are assigned to be used for debug purpose.
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27 |
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28 | [..]
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29 | Once the device started from reset, the user application has to:
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30 | (+) Configure the clock source to be used to drive the System clock
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31 | (if the application needs higher frequency/performance)
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32 | (+) Configure the System clock frequency and Flash settings
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33 | (+) Configure the AHB and APB busses prescalers
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34 | (+) Enable the clock for the peripheral(s) to be used
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35 | (+) Configure the clock source(s) for peripherals which clocks are not
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36 | derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
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37 |
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38 | ##### RCC Limitations #####
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39 | ==============================================================================
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40 | [..]
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41 | A delay between an RCC peripheral clock enable and the effective peripheral
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42 | enabling should be taken into account in order to manage the peripheral read/write
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43 | from/to registers.
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44 | (+) This delay depends on the peripheral mapping.
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45 | (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
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46 | after the clock enable bit is set on the hardware register
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47 | (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
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48 | after the clock enable bit is set on the hardware register
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49 |
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50 | [..]
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51 | Possible Workarounds:
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52 | (#) Enable the peripheral clock sometimes before the peripheral read/write
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53 | register is required.
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54 | (#) For AHB peripheral, insert two dummy read to the peripheral register.
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55 | (#) For APB peripheral, insert a dummy read to the peripheral register.
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56 |
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57 | @endverbatim
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58 | ******************************************************************************
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59 | * @attention
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60 | *
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61 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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62 | *
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63 | * Redistribution and use in source and binary forms, with or without modification,
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64 | * are permitted provided that the following conditions are met:
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65 | * 1. Redistributions of source code must retain the above copyright notice,
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66 | * this list of conditions and the following disclaimer.
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67 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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68 | * this list of conditions and the following disclaimer in the documentation
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69 | * and/or other materials provided with the distribution.
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70 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
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71 | * may be used to endorse or promote products derived from this software
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72 | * without specific prior written permission.
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73 | *
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74 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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75 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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76 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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77 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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78 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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79 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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80 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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81 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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82 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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83 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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84 | *
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85 | ******************************************************************************
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86 | */
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87 |
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88 | /* Includes ------------------------------------------------------------------*/
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89 | #include "stm32f4xx_hal.h"
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90 |
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91 | /** @addtogroup STM32F4xx_HAL_Driver
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92 | * @{
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93 | */
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94 |
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95 | /** @defgroup RCC RCC
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96 | * @brief RCC HAL module driver
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97 | * @{
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98 | */
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99 |
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100 | #ifdef HAL_RCC_MODULE_ENABLED
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101 |
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102 | /* Private typedef -----------------------------------------------------------*/
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103 | /* Private define ------------------------------------------------------------*/
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104 | /** @addtogroup RCC_Private_Constants
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105 | * @{
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106 | */
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107 | #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
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108 |
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109 | /* Private macro -------------------------------------------------------------*/
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110 | #define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
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111 | #define MCO1_GPIO_PORT GPIOA
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112 | #define MCO1_PIN GPIO_PIN_8
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113 |
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114 | #define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
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115 | #define MCO2_GPIO_PORT GPIOC
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116 | #define MCO2_PIN GPIO_PIN_9
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117 | /**
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118 | * @}
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119 | */
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120 |
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121 | /* Private variables ---------------------------------------------------------*/
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122 | /** @defgroup RCC_Private_Variables RCC Private Variables
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123 | * @{
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124 | */
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125 | const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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126 | /**
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127 | * @}
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128 | */
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129 |
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130 | /* Private function prototypes -----------------------------------------------*/
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131 | /* Private functions ---------------------------------------------------------*/
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132 |
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133 | /** @defgroup RCC_Exported_Functions RCC Exported Functions
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134 | * @{
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135 | */
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136 |
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137 | /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
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138 | * @brief Initialization and Configuration functions
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139 | *
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140 | @verbatim
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141 | ===============================================================================
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142 | ##### Initialization and de-initialization functions #####
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143 | ===============================================================================
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144 | [..]
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145 | This section provides functions allowing to configure the internal/external oscillators
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146 | (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
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147 | and APB2).
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148 |
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149 | [..] Internal/external clock and PLL configuration
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150 | (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
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151 | the PLL as System clock source.
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152 |
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153 | (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
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154 | clock source.
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155 |
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156 | (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
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157 | through the PLL as System clock source. Can be used also as RTC clock source.
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158 |
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159 | (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
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160 |
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161 | (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
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162 | (++) The first output is used to generate the high speed system clock (up to 168 MHz)
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163 | (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
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164 | the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
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165 |
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166 | (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
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167 | and if a HSE clock failure occurs(HSE used directly or through PLL as System
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168 | clock source), the System clocks automatically switched to HSI and an interrupt
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169 | is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
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170 | (Non-Maskable Interrupt) exception vector.
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171 |
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172 | (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
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173 | clock (through a configurable prescaler) on PA8 pin.
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174 |
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175 | (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
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176 | clock (through a configurable prescaler) on PC9 pin.
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177 |
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178 | [..] System, AHB and APB busses clocks configuration
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179 | (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
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180 | HSE and PLL.
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181 | The AHB clock (HCLK) is derived from System clock through configurable
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182 | prescaler and used to clock the CPU, memory and peripherals mapped
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183 | on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
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184 | from AHB clock through configurable prescalers and used to clock
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185 | the peripherals mapped on these busses. You can use
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186 | "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
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187 |
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188 | -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
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189 | (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
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190 | from an external clock mapped on the I2S_CKIN pin.
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191 | You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
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192 | (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
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193 | from an external clock mapped on the I2S_CKIN pin.
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194 | You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
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195 | (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
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196 | divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
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197 | macros to configure this clock.
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198 | (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
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199 | to work correctly, while the SDIO require a frequency equal or lower than
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200 | to 48. This clock is derived of the main PLL through PLLQ divider.
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201 | (+@) IWDG clock which is always the LSI clock.
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202 |
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203 | (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
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204 | frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
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205 | Depending on the device voltage range, the maximum frequency should
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206 | be adapted accordingly (refer to the product datasheets for more details).
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207 |
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208 | (#) For the STM32F42xxx and STM32F43xxx devices, the maximum frequency
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209 | of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
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210 | Depending on the device voltage range, the maximum frequency should
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211 | be adapted accordingly (refer to the product datasheets for more details).
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212 |
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213 | (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
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214 | PCLK2 84 MHz and PCLK1 42 MHz.
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215 | Depending on the device voltage range, the maximum frequency should
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216 | be adapted accordingly (refer to the product datasheets for more details).
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217 |
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218 | (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
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219 | PCLK2 100 MHz and PCLK1 50 MHz.
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220 | Depending on the device voltage range, the maximum frequency should
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221 | be adapted accordingly (refer to the product datasheets for more details).
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222 |
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223 | @endverbatim
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224 | * @{
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225 | */
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226 |
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227 | /**
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228 | * @brief Resets the RCC clock configuration to the default reset state.
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229 | * @note The default reset state of the clock configuration is given below:
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230 | * - HSI ON and used as system clock source
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231 | * - HSE and PLL OFF
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232 | * - AHB, APB1 and APB2 prescaler set to 1.
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233 | * - CSS, MCO1 and MCO2 OFF
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234 | * - All interrupts disabled
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235 | * @note This function doesn't modify the configuration of the
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236 | * - Peripheral clocks
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237 | * - LSI, LSE and RTC clocks
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238 | * @retval None
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239 | */
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240 | __weak void HAL_RCC_DeInit(void)
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241 | {}
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242 |
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243 | /**
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244 | * @brief Initializes the RCC Oscillators according to the specified parameters in the
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245 | * RCC_OscInitTypeDef.
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246 | * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
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247 | * contains the configuration information for the RCC Oscillators.
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248 | * @note The PLL is not disabled when used as system clock.
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249 | * @retval HAL status
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250 | */
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251 | __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
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252 | {
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253 | uint32_t tickstart = 0;
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254 |
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255 | /* Check the parameters */
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256 | assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
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257 | /*------------------------------- HSE Configuration ------------------------*/
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258 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
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259 | {
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260 | /* Check the parameters */
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261 | assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
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262 | /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
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263 | if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
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264 | ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
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265 | {
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266 | if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
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267 | {
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268 | return HAL_ERROR;
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269 | }
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270 | }
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271 | else
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272 | {
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273 | /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
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274 | __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
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275 |
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276 | /* Get Start Tick*/
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277 | tickstart = HAL_GetTick();
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278 |
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279 | /* Wait till HSE is disabled */
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280 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
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281 | {
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282 | if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
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283 | {
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284 | return HAL_TIMEOUT;
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285 | }
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286 | }
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287 |
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288 | /* Set the new HSE configuration ---------------------------------------*/
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289 | __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
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290 |
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291 | /* Check the HSE State */
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292 | if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
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293 | {
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294 | /* Get Start Tick*/
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295 | tickstart = HAL_GetTick();
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296 |
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297 | /* Wait till HSE is ready */
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298 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
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299 | {
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300 | if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
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301 | {
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302 | return HAL_TIMEOUT;
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303 | }
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304 | }
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305 | }
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306 | else
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307 | {
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308 | /* Get Start Tick*/
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309 | tickstart = HAL_GetTick();
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310 |
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311 | /* Wait till HSE is bypassed or disabled */
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312 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
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313 | {
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314 | if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
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315 | {
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316 | return HAL_TIMEOUT;
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317 | }
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318 | }
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319 | }
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320 | }
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321 | }
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322 | /*----------------------------- HSI Configuration --------------------------*/
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323 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
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324 | {
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325 | /* Check the parameters */
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326 | assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
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327 | assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
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328 |
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329 | /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
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330 | if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
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331 | ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
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332 | {
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333 | /* When HSI is used as system clock it will not disabled */
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334 | if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
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335 | {
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336 | return HAL_ERROR;
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337 | }
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338 | /* Otherwise, just the calibration is allowed */
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339 | else
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340 | {
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341 | /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
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342 | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
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343 | }
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344 | }
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345 | else
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346 | {
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347 | /* Check the HSI State */
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348 | if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
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349 | {
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350 | /* Enable the Internal High Speed oscillator (HSI). */
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351 | __HAL_RCC_HSI_ENABLE();
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352 |
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353 | /* Get Start Tick*/
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354 | tickstart = HAL_GetTick();
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355 |
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356 | /* Wait till HSI is ready */
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357 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
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358 | {
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359 | if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
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360 | {
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361 | return HAL_TIMEOUT;
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362 | }
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363 | }
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364 |
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365 | /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
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366 | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
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367 | }
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368 | else
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369 | {
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370 | /* Disable the Internal High Speed oscillator (HSI). */
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371 | __HAL_RCC_HSI_DISABLE();
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372 |
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373 | /* Get Start Tick*/
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374 | tickstart = HAL_GetTick();
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375 |
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376 | /* Wait till HSI is ready */
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377 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
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378 | {
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379 | if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
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380 | {
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381 | return HAL_TIMEOUT;
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382 | }
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383 | }
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384 | }
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385 | }
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386 | }
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387 | /*------------------------------ LSI Configuration -------------------------*/
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388 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
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389 | {
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390 | /* Check the parameters */
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391 | assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
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392 |
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393 | /* Check the LSI State */
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394 | if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
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395 | {
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396 | /* Enable the Internal Low Speed oscillator (LSI). */
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397 | __HAL_RCC_LSI_ENABLE();
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398 |
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399 | /* Get Start Tick*/
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400 | tickstart = HAL_GetTick();
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401 |
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402 | /* Wait till LSI is ready */
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403 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
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404 | {
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405 | if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
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406 | {
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407 | return HAL_TIMEOUT;
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408 | }
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409 | }
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410 | }
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411 | else
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412 | {
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413 | /* Disable the Internal Low Speed oscillator (LSI). */
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414 | __HAL_RCC_LSI_DISABLE();
|
---|
415 |
|
---|
416 | /* Get Start Tick*/
|
---|
417 | tickstart = HAL_GetTick();
|
---|
418 |
|
---|
419 | /* Wait till LSI is ready */
|
---|
420 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
---|
421 | {
|
---|
422 | if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
|
---|
423 | {
|
---|
424 | return HAL_TIMEOUT;
|
---|
425 | }
|
---|
426 | }
|
---|
427 | }
|
---|
428 | }
|
---|
429 | /*------------------------------ LSE Configuration -------------------------*/
|
---|
430 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
---|
431 | {
|
---|
432 | /* Check the parameters */
|
---|
433 | assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
---|
434 |
|
---|
435 | /* Enable Power Clock*/
|
---|
436 | __HAL_RCC_PWR_CLK_ENABLE();
|
---|
437 |
|
---|
438 | /* Enable write access to Backup domain */
|
---|
439 | PWR->CR |= PWR_CR_DBP;
|
---|
440 |
|
---|
441 | /* Wait for Backup domain Write protection disable */
|
---|
442 | tickstart = HAL_GetTick();
|
---|
443 |
|
---|
444 | while((PWR->CR & PWR_CR_DBP) == RESET)
|
---|
445 | {
|
---|
446 | if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
|
---|
447 | {
|
---|
448 | return HAL_TIMEOUT;
|
---|
449 | }
|
---|
450 | }
|
---|
451 |
|
---|
452 | /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
|
---|
453 | __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
|
---|
454 |
|
---|
455 | /* Get Start Tick*/
|
---|
456 | tickstart = HAL_GetTick();
|
---|
457 |
|
---|
458 | /* Wait till LSE is ready */
|
---|
459 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
---|
460 | {
|
---|
461 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
---|
462 | {
|
---|
463 | return HAL_TIMEOUT;
|
---|
464 | }
|
---|
465 | }
|
---|
466 |
|
---|
467 | /* Set the new LSE configuration -----------------------------------------*/
|
---|
468 | __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
---|
469 | /* Check the LSE State */
|
---|
470 | if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
|
---|
471 | {
|
---|
472 | /* Get Start Tick*/
|
---|
473 | tickstart = HAL_GetTick();
|
---|
474 |
|
---|
475 | /* Wait till LSE is ready */
|
---|
476 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
---|
477 | {
|
---|
478 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
---|
479 | {
|
---|
480 | return HAL_TIMEOUT;
|
---|
481 | }
|
---|
482 | }
|
---|
483 | }
|
---|
484 | else
|
---|
485 | {
|
---|
486 | /* Get Start Tick*/
|
---|
487 | tickstart = HAL_GetTick();
|
---|
488 |
|
---|
489 | /* Wait till LSE is ready */
|
---|
490 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
---|
491 | {
|
---|
492 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
---|
493 | {
|
---|
494 | return HAL_TIMEOUT;
|
---|
495 | }
|
---|
496 | }
|
---|
497 | }
|
---|
498 | }
|
---|
499 | /*-------------------------------- PLL Configuration -----------------------*/
|
---|
500 | /* Check the parameters */
|
---|
501 | assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
---|
502 | if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
---|
503 | {
|
---|
504 | /* Check if the PLL is used as system clock or not */
|
---|
505 | if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
|
---|
506 | {
|
---|
507 | if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
---|
508 | {
|
---|
509 | /* Check the parameters */
|
---|
510 | assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
|
---|
511 | assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
|
---|
512 | assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
|
---|
513 | assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
|
---|
514 | assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
---|
515 |
|
---|
516 | /* Disable the main PLL. */
|
---|
517 | __HAL_RCC_PLL_DISABLE();
|
---|
518 |
|
---|
519 | /* Get Start Tick*/
|
---|
520 | tickstart = HAL_GetTick();
|
---|
521 |
|
---|
522 | /* Wait till PLL is ready */
|
---|
523 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
---|
524 | {
|
---|
525 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
---|
526 | {
|
---|
527 | return HAL_TIMEOUT;
|
---|
528 | }
|
---|
529 | }
|
---|
530 |
|
---|
531 | /* Configure the main PLL clock source, multiplication and division factors. */
|
---|
532 | WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
|
---|
533 | RCC_OscInitStruct->PLL.PLLM | \
|
---|
534 | (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
|
---|
535 | (((RCC_OscInitStruct->PLL.PLLP >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
|
---|
536 | (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
|
---|
537 | /* Enable the main PLL. */
|
---|
538 | __HAL_RCC_PLL_ENABLE();
|
---|
539 |
|
---|
540 | /* Get Start Tick*/
|
---|
541 | tickstart = HAL_GetTick();
|
---|
542 |
|
---|
543 | /* Wait till PLL is ready */
|
---|
544 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
---|
545 | {
|
---|
546 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
---|
547 | {
|
---|
548 | return HAL_TIMEOUT;
|
---|
549 | }
|
---|
550 | }
|
---|
551 | }
|
---|
552 | else
|
---|
553 | {
|
---|
554 | /* Disable the main PLL. */
|
---|
555 | __HAL_RCC_PLL_DISABLE();
|
---|
556 |
|
---|
557 | /* Get Start Tick*/
|
---|
558 | tickstart = HAL_GetTick();
|
---|
559 |
|
---|
560 | /* Wait till PLL is ready */
|
---|
561 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
---|
562 | {
|
---|
563 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
---|
564 | {
|
---|
565 | return HAL_TIMEOUT;
|
---|
566 | }
|
---|
567 | }
|
---|
568 | }
|
---|
569 | }
|
---|
570 | else
|
---|
571 | {
|
---|
572 | return HAL_ERROR;
|
---|
573 | }
|
---|
574 | }
|
---|
575 | return HAL_OK;
|
---|
576 | }
|
---|
577 |
|
---|
578 | /**
|
---|
579 | * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
|
---|
580 | * parameters in the RCC_ClkInitStruct.
|
---|
581 | * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
|
---|
582 | * contains the configuration information for the RCC peripheral.
|
---|
583 | * @param FLatency: FLASH Latency, this parameter depend on device selected
|
---|
584 | *
|
---|
585 | * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
---|
586 | * and updated by HAL_RCC_GetHCLKFreq() function called within this function
|
---|
587 | *
|
---|
588 | * @note The HSI is used (enabled by hardware) as system clock source after
|
---|
589 | * startup from Reset, wake-up from STOP and STANDBY mode, or in case
|
---|
590 | * of failure of the HSE used directly or indirectly as system clock
|
---|
591 | * (if the Clock Security System CSS is enabled).
|
---|
592 | *
|
---|
593 | * @note A switch from one clock source to another occurs only if the target
|
---|
594 | * clock source is ready (clock stable after startup delay or PLL locked).
|
---|
595 | * If a clock source which is not yet ready is selected, the switch will
|
---|
596 | * occur when the clock source will be ready.
|
---|
597 | *
|
---|
598 | * @note Depending on the device voltage range, the software has to set correctly
|
---|
599 | * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
---|
600 | * (for more details refer to section above "Initialization/de-initialization functions")
|
---|
601 | * @retval None
|
---|
602 | */
|
---|
603 | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
---|
604 | {
|
---|
605 | uint32_t tickstart = 0;
|
---|
606 |
|
---|
607 | /* Check the parameters */
|
---|
608 | assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
|
---|
609 | assert_param(IS_FLASH_LATENCY(FLatency));
|
---|
610 |
|
---|
611 | /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
---|
612 | must be correctly programmed according to the frequency of the CPU clock
|
---|
613 | (HCLK) and the supply voltage of the device. */
|
---|
614 |
|
---|
615 | /* Increasing the CPU frequency */
|
---|
616 | if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
|
---|
617 | {
|
---|
618 | /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
---|
619 | __HAL_FLASH_SET_LATENCY(FLatency);
|
---|
620 |
|
---|
621 | /* Check that the new number of wait states is taken into account to access the Flash
|
---|
622 | memory by reading the FLASH_ACR register */
|
---|
623 | if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
|
---|
624 | {
|
---|
625 | return HAL_ERROR;
|
---|
626 | }
|
---|
627 |
|
---|
628 | /*-------------------------- HCLK Configuration --------------------------*/
|
---|
629 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
---|
630 | {
|
---|
631 | assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
---|
632 | MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
---|
633 | }
|
---|
634 |
|
---|
635 | /*------------------------- SYSCLK Configuration ---------------------------*/
|
---|
636 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
---|
637 | {
|
---|
638 | assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
---|
639 |
|
---|
640 | /* HSE is selected as System Clock Source */
|
---|
641 | if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
---|
642 | {
|
---|
643 | /* Check the HSE ready flag */
|
---|
644 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
---|
645 | {
|
---|
646 | return HAL_ERROR;
|
---|
647 | }
|
---|
648 | }
|
---|
649 | /* PLL is selected as System Clock Source */
|
---|
650 | else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
|
---|
651 | (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
|
---|
652 | {
|
---|
653 | /* Check the PLL ready flag */
|
---|
654 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
---|
655 | {
|
---|
656 | return HAL_ERROR;
|
---|
657 | }
|
---|
658 | }
|
---|
659 | /* HSI is selected as System Clock Source */
|
---|
660 | else
|
---|
661 | {
|
---|
662 | /* Check the HSI ready flag */
|
---|
663 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
---|
664 | {
|
---|
665 | return HAL_ERROR;
|
---|
666 | }
|
---|
667 | }
|
---|
668 |
|
---|
669 | __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
---|
670 | /* Get Start Tick*/
|
---|
671 | tickstart = HAL_GetTick();
|
---|
672 |
|
---|
673 | if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
---|
674 | {
|
---|
675 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
|
---|
676 | {
|
---|
677 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
---|
678 | {
|
---|
679 | return HAL_TIMEOUT;
|
---|
680 | }
|
---|
681 | }
|
---|
682 | }
|
---|
683 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
---|
684 | {
|
---|
685 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
---|
686 | {
|
---|
687 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
---|
688 | {
|
---|
689 | return HAL_TIMEOUT;
|
---|
690 | }
|
---|
691 | }
|
---|
692 | }
|
---|
693 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)
|
---|
694 | {
|
---|
695 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK)
|
---|
696 | {
|
---|
697 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
---|
698 | {
|
---|
699 | return HAL_TIMEOUT;
|
---|
700 | }
|
---|
701 | }
|
---|
702 | }
|
---|
703 | else
|
---|
704 | {
|
---|
705 | while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
|
---|
706 | {
|
---|
707 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
---|
708 | {
|
---|
709 | return HAL_TIMEOUT;
|
---|
710 | }
|
---|
711 | }
|
---|
712 | }
|
---|
713 | }
|
---|
714 | }
|
---|
715 | /* Decreasing the CPU frequency */
|
---|
716 | else
|
---|
717 | {
|
---|
718 | /*-------------------------- HCLK Configuration --------------------------*/
|
---|
719 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
---|
720 | {
|
---|
721 | assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
---|
722 | MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
---|
723 | }
|
---|
724 |
|
---|
725 | /*------------------------- SYSCLK Configuration -------------------------*/
|
---|
726 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
---|
727 | {
|
---|
728 | assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
---|
729 |
|
---|
730 | /* HSE is selected as System Clock Source */
|
---|
731 | if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
---|
732 | {
|
---|
733 | /* Check the HSE ready flag */
|
---|
734 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
---|
735 | {
|
---|
736 | return HAL_ERROR;
|
---|
737 | }
|
---|
738 | }
|
---|
739 | /* PLL is selected as System Clock Source */
|
---|
740 | else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
|
---|
741 | (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
|
---|
742 | {
|
---|
743 | /* Check the PLL ready flag */
|
---|
744 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
---|
745 | {
|
---|
746 | return HAL_ERROR;
|
---|
747 | }
|
---|
748 | }
|
---|
749 | /* HSI is selected as System Clock Source */
|
---|
750 | else
|
---|
751 | {
|
---|
752 | /* Check the HSI ready flag */
|
---|
753 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
---|
754 | {
|
---|
755 | return HAL_ERROR;
|
---|
756 | }
|
---|
757 | }
|
---|
758 | __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
---|
759 | /* Get Start Tick*/
|
---|
760 | tickstart = HAL_GetTick();
|
---|
761 |
|
---|
762 | if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
---|
763 | {
|
---|
764 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
|
---|
765 | {
|
---|
766 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
---|
767 | {
|
---|
768 | return HAL_TIMEOUT;
|
---|
769 | }
|
---|
770 | }
|
---|
771 | }
|
---|
772 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
---|
773 | {
|
---|
774 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
---|
775 | {
|
---|
776 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
---|
777 | {
|
---|
778 | return HAL_TIMEOUT;
|
---|
779 | }
|
---|
780 | }
|
---|
781 | }
|
---|
782 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)
|
---|
783 | {
|
---|
784 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK)
|
---|
785 | {
|
---|
786 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
---|
787 | {
|
---|
788 | return HAL_TIMEOUT;
|
---|
789 | }
|
---|
790 | }
|
---|
791 | }
|
---|
792 | else
|
---|
793 | {
|
---|
794 | while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
|
---|
795 | {
|
---|
796 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
---|
797 | {
|
---|
798 | return HAL_TIMEOUT;
|
---|
799 | }
|
---|
800 | }
|
---|
801 | }
|
---|
802 | }
|
---|
803 |
|
---|
804 | /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
---|
805 | __HAL_FLASH_SET_LATENCY(FLatency);
|
---|
806 |
|
---|
807 | /* Check that the new number of wait states is taken into account to access the Flash
|
---|
808 | memory by reading the FLASH_ACR register */
|
---|
809 | if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
|
---|
810 | {
|
---|
811 | return HAL_ERROR;
|
---|
812 | }
|
---|
813 | }
|
---|
814 |
|
---|
815 | /*-------------------------- PCLK1 Configuration ---------------------------*/
|
---|
816 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
---|
817 | {
|
---|
818 | assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
---|
819 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
---|
820 | }
|
---|
821 |
|
---|
822 | /*-------------------------- PCLK2 Configuration ---------------------------*/
|
---|
823 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
---|
824 | {
|
---|
825 | assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
---|
826 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
|
---|
827 | }
|
---|
828 |
|
---|
829 | /* Configure the source of time base considering new system clocks settings*/
|
---|
830 | HAL_InitTick (TICK_INT_PRIORITY);
|
---|
831 |
|
---|
832 | return HAL_OK;
|
---|
833 | }
|
---|
834 |
|
---|
835 | /**
|
---|
836 | * @}
|
---|
837 | */
|
---|
838 |
|
---|
839 | /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
|
---|
840 | * @brief RCC clocks control functions
|
---|
841 | *
|
---|
842 | @verbatim
|
---|
843 | ===============================================================================
|
---|
844 | ##### Peripheral Control functions #####
|
---|
845 | ===============================================================================
|
---|
846 | [..]
|
---|
847 | This subsection provides a set of functions allowing to control the RCC Clocks
|
---|
848 | frequencies.
|
---|
849 |
|
---|
850 | @endverbatim
|
---|
851 | * @{
|
---|
852 | */
|
---|
853 |
|
---|
854 | /**
|
---|
855 | * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
|
---|
856 | * @note PA8/PC9 should be configured in alternate function mode.
|
---|
857 | * @param RCC_MCOx: specifies the output direction for the clock source.
|
---|
858 | * This parameter can be one of the following values:
|
---|
859 | * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
|
---|
860 | * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
|
---|
861 | * @param RCC_MCOSource: specifies the clock source to output.
|
---|
862 | * This parameter can be one of the following values:
|
---|
863 | * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
|
---|
864 | * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
|
---|
865 | * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
|
---|
866 | * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
|
---|
867 | * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
|
---|
868 | * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
|
---|
869 | * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
|
---|
870 | * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
|
---|
871 | * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
|
---|
872 | * @param RCC_MCODiv: specifies the MCOx prescaler.
|
---|
873 | * This parameter can be one of the following values:
|
---|
874 | * @arg RCC_MCODIV_1: no division applied to MCOx clock
|
---|
875 | * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
|
---|
876 | * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
|
---|
877 | * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
|
---|
878 | * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
|
---|
879 | * @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
|
---|
880 | * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
|
---|
881 | * @retval None
|
---|
882 | */
|
---|
883 | void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
|
---|
884 | {
|
---|
885 | GPIO_InitTypeDef GPIO_InitStruct;
|
---|
886 | /* Check the parameters */
|
---|
887 | assert_param(IS_RCC_MCO(RCC_MCOx));
|
---|
888 | assert_param(IS_RCC_MCODIV(RCC_MCODiv));
|
---|
889 | /* RCC_MCO1 */
|
---|
890 | if(RCC_MCOx == RCC_MCO1)
|
---|
891 | {
|
---|
892 | assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
|
---|
893 |
|
---|
894 | /* MCO1 Clock Enable */
|
---|
895 | __MCO1_CLK_ENABLE();
|
---|
896 |
|
---|
897 | /* Configure the MCO1 pin in alternate function mode */
|
---|
898 | GPIO_InitStruct.Pin = MCO1_PIN;
|
---|
899 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
---|
900 | GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
|
---|
901 | GPIO_InitStruct.Pull = GPIO_NOPULL;
|
---|
902 | GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
|
---|
903 | HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
|
---|
904 |
|
---|
905 | /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
|
---|
906 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
|
---|
907 |
|
---|
908 | /* This RCC MCO1 enable feature is available only on STM32F410xx devices */
|
---|
909 | #if defined(RCC_CFGR_MCO1EN)
|
---|
910 | __HAL_RCC_MCO1_ENABLE();
|
---|
911 | #endif /* RCC_CFGR_MCO1EN */
|
---|
912 | }
|
---|
913 | else
|
---|
914 | {
|
---|
915 | assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
|
---|
916 |
|
---|
917 | /* MCO2 Clock Enable */
|
---|
918 | __MCO2_CLK_ENABLE();
|
---|
919 |
|
---|
920 | /* Configure the MCO2 pin in alternate function mode */
|
---|
921 | GPIO_InitStruct.Pin = MCO2_PIN;
|
---|
922 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
---|
923 | GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
|
---|
924 | GPIO_InitStruct.Pull = GPIO_NOPULL;
|
---|
925 | GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
|
---|
926 | HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
|
---|
927 |
|
---|
928 | /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
|
---|
929 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
|
---|
930 |
|
---|
931 | /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */
|
---|
932 | #if defined(RCC_CFGR_MCO2EN)
|
---|
933 | __HAL_RCC_MCO2_ENABLE();
|
---|
934 | #endif /* RCC_CFGR_MCO2EN */
|
---|
935 | }
|
---|
936 | }
|
---|
937 |
|
---|
938 | /**
|
---|
939 | * @brief Enables the Clock Security System.
|
---|
940 | * @note If a failure is detected on the HSE oscillator clock, this oscillator
|
---|
941 | * is automatically disabled and an interrupt is generated to inform the
|
---|
942 | * software about the failure (Clock Security System Interrupt, CSSI),
|
---|
943 | * allowing the MCU to perform rescue operations. The CSSI is linked to
|
---|
944 | * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
|
---|
945 | * @retval None
|
---|
946 | */
|
---|
947 | void HAL_RCC_EnableCSS(void)
|
---|
948 | {
|
---|
949 | *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
|
---|
950 | }
|
---|
951 |
|
---|
952 | /**
|
---|
953 | * @brief Disables the Clock Security System.
|
---|
954 | * @retval None
|
---|
955 | */
|
---|
956 | void HAL_RCC_DisableCSS(void)
|
---|
957 | {
|
---|
958 | *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
|
---|
959 | }
|
---|
960 |
|
---|
961 | /**
|
---|
962 | * @brief Returns the SYSCLK frequency
|
---|
963 | *
|
---|
964 | * @note The system frequency computed by this function is not the real
|
---|
965 | * frequency in the chip. It is calculated based on the predefined
|
---|
966 | * constant and the selected clock source:
|
---|
967 | * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
|
---|
968 | * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
|
---|
969 | * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
|
---|
970 | * or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
---|
971 | * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
|
---|
972 | * 16 MHz) but the real value may vary depending on the variations
|
---|
973 | * in voltage and temperature.
|
---|
974 | * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
|
---|
975 | * 25 MHz), user has to ensure that HSE_VALUE is same as the real
|
---|
976 | * frequency of the crystal used. Otherwise, this function may
|
---|
977 | * have wrong result.
|
---|
978 | *
|
---|
979 | * @note The result of this function could be not correct when using fractional
|
---|
980 | * value for HSE crystal.
|
---|
981 | *
|
---|
982 | * @note This function can be used by the user application to compute the
|
---|
983 | * baudrate for the communication peripherals or configure other parameters.
|
---|
984 | *
|
---|
985 | * @note Each time SYSCLK changes, this function must be called to update the
|
---|
986 | * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
---|
987 | *
|
---|
988 | *
|
---|
989 | * @retval SYSCLK frequency
|
---|
990 | */
|
---|
991 | __weak uint32_t HAL_RCC_GetSysClockFreq(void)
|
---|
992 | {
|
---|
993 | uint32_t pllm = 0, pllvco = 0, pllp = 0;
|
---|
994 | uint32_t sysclockfreq = 0;
|
---|
995 |
|
---|
996 | /* Get SYSCLK source -------------------------------------------------------*/
|
---|
997 | switch (RCC->CFGR & RCC_CFGR_SWS)
|
---|
998 | {
|
---|
999 | case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
|
---|
1000 | {
|
---|
1001 | sysclockfreq = HSI_VALUE;
|
---|
1002 | break;
|
---|
1003 | }
|
---|
1004 | case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
|
---|
1005 | {
|
---|
1006 | sysclockfreq = HSE_VALUE;
|
---|
1007 | break;
|
---|
1008 | }
|
---|
1009 | case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
|
---|
1010 | {
|
---|
1011 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
---|
1012 | SYSCLK = PLL_VCO / PLLP */
|
---|
1013 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
---|
1014 | if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
---|
1015 | {
|
---|
1016 | /* HSE used as PLL clock source */
|
---|
1017 | pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
|
---|
1018 | }
|
---|
1019 | else
|
---|
1020 | {
|
---|
1021 | /* HSI used as PLL clock source */
|
---|
1022 | pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
|
---|
1023 | }
|
---|
1024 | pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
|
---|
1025 |
|
---|
1026 | sysclockfreq = pllvco/pllp;
|
---|
1027 | break;
|
---|
1028 | }
|
---|
1029 | default:
|
---|
1030 | {
|
---|
1031 | sysclockfreq = HSI_VALUE;
|
---|
1032 | break;
|
---|
1033 | }
|
---|
1034 | }
|
---|
1035 | return sysclockfreq;
|
---|
1036 | }
|
---|
1037 |
|
---|
1038 | /**
|
---|
1039 | * @brief Returns the HCLK frequency
|
---|
1040 | * @note Each time HCLK changes, this function must be called to update the
|
---|
1041 | * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
|
---|
1042 | *
|
---|
1043 | * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
---|
1044 | * and updated within this function
|
---|
1045 | * @retval HCLK frequency
|
---|
1046 | */
|
---|
1047 | uint32_t HAL_RCC_GetHCLKFreq(void)
|
---|
1048 | {
|
---|
1049 | SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
|
---|
1050 | return SystemCoreClock;
|
---|
1051 | }
|
---|
1052 |
|
---|
1053 | /**
|
---|
1054 | * @brief Returns the PCLK1 frequency
|
---|
1055 | * @note Each time PCLK1 changes, this function must be called to update the
|
---|
1056 | * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
---|
1057 | * @retval PCLK1 frequency
|
---|
1058 | */
|
---|
1059 | uint32_t HAL_RCC_GetPCLK1Freq(void)
|
---|
1060 | {
|
---|
1061 | /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
---|
1062 | return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
|
---|
1063 | }
|
---|
1064 |
|
---|
1065 | /**
|
---|
1066 | * @brief Returns the PCLK2 frequency
|
---|
1067 | * @note Each time PCLK2 changes, this function must be called to update the
|
---|
1068 | * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
---|
1069 | * @retval PCLK2 frequency
|
---|
1070 | */
|
---|
1071 | uint32_t HAL_RCC_GetPCLK2Freq(void)
|
---|
1072 | {
|
---|
1073 | /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
---|
1074 | return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
|
---|
1075 | }
|
---|
1076 |
|
---|
1077 | /**
|
---|
1078 | * @brief Configures the RCC_OscInitStruct according to the internal
|
---|
1079 | * RCC configuration registers.
|
---|
1080 | * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
|
---|
1081 | * will be configured.
|
---|
1082 | * @retval None
|
---|
1083 | */
|
---|
1084 | __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
---|
1085 | {
|
---|
1086 | /* Set all possible values for the Oscillator type parameter ---------------*/
|
---|
1087 | RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
|
---|
1088 |
|
---|
1089 | /* Get the HSE configuration -----------------------------------------------*/
|
---|
1090 | if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
|
---|
1091 | {
|
---|
1092 | RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
|
---|
1093 | }
|
---|
1094 | else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
|
---|
1095 | {
|
---|
1096 | RCC_OscInitStruct->HSEState = RCC_HSE_ON;
|
---|
1097 | }
|
---|
1098 | else
|
---|
1099 | {
|
---|
1100 | RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
|
---|
1101 | }
|
---|
1102 |
|
---|
1103 | /* Get the HSI configuration -----------------------------------------------*/
|
---|
1104 | if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
|
---|
1105 | {
|
---|
1106 | RCC_OscInitStruct->HSIState = RCC_HSI_ON;
|
---|
1107 | }
|
---|
1108 | else
|
---|
1109 | {
|
---|
1110 | RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
|
---|
1111 | }
|
---|
1112 |
|
---|
1113 | RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
|
---|
1114 |
|
---|
1115 | /* Get the LSE configuration -----------------------------------------------*/
|
---|
1116 | if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
|
---|
1117 | {
|
---|
1118 | RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
|
---|
1119 | }
|
---|
1120 | else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
|
---|
1121 | {
|
---|
1122 | RCC_OscInitStruct->LSEState = RCC_LSE_ON;
|
---|
1123 | }
|
---|
1124 | else
|
---|
1125 | {
|
---|
1126 | RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
|
---|
1127 | }
|
---|
1128 |
|
---|
1129 | /* Get the LSI configuration -----------------------------------------------*/
|
---|
1130 | if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
|
---|
1131 | {
|
---|
1132 | RCC_OscInitStruct->LSIState = RCC_LSI_ON;
|
---|
1133 | }
|
---|
1134 | else
|
---|
1135 | {
|
---|
1136 | RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
|
---|
1137 | }
|
---|
1138 |
|
---|
1139 | /* Get the PLL configuration -----------------------------------------------*/
|
---|
1140 | if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
|
---|
1141 | {
|
---|
1142 | RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
|
---|
1143 | }
|
---|
1144 | else
|
---|
1145 | {
|
---|
1146 | RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
|
---|
1147 | }
|
---|
1148 | RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
|
---|
1149 | RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
|
---|
1150 | RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
|
---|
1151 | RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
|
---|
1152 | RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
|
---|
1153 | }
|
---|
1154 |
|
---|
1155 | /**
|
---|
1156 | * @brief Configures the RCC_ClkInitStruct according to the internal
|
---|
1157 | * RCC configuration registers.
|
---|
1158 | * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
|
---|
1159 | * will be configured.
|
---|
1160 | * @param pFLatency: Pointer on the Flash Latency.
|
---|
1161 | * @retval None
|
---|
1162 | */
|
---|
1163 | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
|
---|
1164 | {
|
---|
1165 | /* Set all possible values for the Clock type parameter --------------------*/
|
---|
1166 | RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
|
---|
1167 |
|
---|
1168 | /* Get the SYSCLK configuration --------------------------------------------*/
|
---|
1169 | RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
|
---|
1170 |
|
---|
1171 | /* Get the HCLK configuration ----------------------------------------------*/
|
---|
1172 | RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
|
---|
1173 |
|
---|
1174 | /* Get the APB1 configuration ----------------------------------------------*/
|
---|
1175 | RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
|
---|
1176 |
|
---|
1177 | /* Get the APB2 configuration ----------------------------------------------*/
|
---|
1178 | RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
|
---|
1179 |
|
---|
1180 | /* Get the Flash Wait State (Latency) configuration ------------------------*/
|
---|
1181 | *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
|
---|
1182 | }
|
---|
1183 |
|
---|
1184 | /**
|
---|
1185 | * @brief This function handles the RCC CSS interrupt request.
|
---|
1186 | * @note This API should be called under the NMI_Handler().
|
---|
1187 | * @retval None
|
---|
1188 | */
|
---|
1189 | void HAL_RCC_NMI_IRQHandler(void)
|
---|
1190 | {
|
---|
1191 | /* Check RCC CSSF flag */
|
---|
1192 | if(__HAL_RCC_GET_IT(RCC_IT_CSS))
|
---|
1193 | {
|
---|
1194 | /* RCC Clock Security System interrupt user callback */
|
---|
1195 | HAL_RCC_CSSCallback();
|
---|
1196 |
|
---|
1197 | /* Clear RCC CSS pending bit */
|
---|
1198 | __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
|
---|
1199 | }
|
---|
1200 | }
|
---|
1201 |
|
---|
1202 | /**
|
---|
1203 | * @brief RCC Clock Security System interrupt callback
|
---|
1204 | * @retval None
|
---|
1205 | */
|
---|
1206 | __weak void HAL_RCC_CSSCallback(void)
|
---|
1207 | {
|
---|
1208 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
1209 | the HAL_RCC_CSSCallback could be implemented in the user file
|
---|
1210 | */
|
---|
1211 | }
|
---|
1212 |
|
---|
1213 | /**
|
---|
1214 | * @}
|
---|
1215 | */
|
---|
1216 |
|
---|
1217 | /**
|
---|
1218 | * @}
|
---|
1219 | */
|
---|
1220 |
|
---|
1221 | #endif /* HAL_RCC_MODULE_ENABLED */
|
---|
1222 | /**
|
---|
1223 | * @}
|
---|
1224 | */
|
---|
1225 |
|
---|
1226 | /**
|
---|
1227 | * @}
|
---|
1228 | */
|
---|
1229 |
|
---|
1230 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
---|