source: asp3_wo_tecs/trunk/arch/arm_m_gcc/stm32f4xx_stm32cube/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c@ 303

Last change on this file since 303 was 303, checked in by ertl-honda, 7 years ago

nucleo_f401re依存部の追加
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1/**
2 ******************************************************************************
3 * @file stm32f4xx_hal_pwr_ex.c
4 * @author MCD Application Team
5 * @version V1.4.1
6 * @date 09-October-2015
7 * @brief Extended PWR HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of PWR extension peripheral:
10 * + Peripheral Extended features functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42/* Includes ------------------------------------------------------------------*/
43#include "stm32f4xx_hal.h"
44
45/** @addtogroup STM32F4xx_HAL_Driver
46 * @{
47 */
48
49/** @defgroup PWREx PWREx
50 * @brief PWR HAL module driver
51 * @{
52 */
53
54#ifdef HAL_PWR_MODULE_ENABLED
55
56/* Private typedef -----------------------------------------------------------*/
57/* Private define ------------------------------------------------------------*/
58/** @addtogroup PWREx_Private_Constants
59 * @{
60 */
61#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000
62#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000
63#define PWR_BKPREG_TIMEOUT_VALUE 1000
64#define PWR_VOSRDY_TIMEOUT_VALUE 1000
65/**
66 * @}
67 */
68
69
70/* Private macro -------------------------------------------------------------*/
71/* Private variables ---------------------------------------------------------*/
72/* Private function prototypes -----------------------------------------------*/
73/* Private functions ---------------------------------------------------------*/
74/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
75 * @{
76 */
77
78/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
79 * @brief Peripheral Extended features functions
80 *
81@verbatim
82
83 ===============================================================================
84 ##### Peripheral extended features functions #####
85 ===============================================================================
86
87 *** Main and Backup Regulators configuration ***
88 ================================================
89 [..]
90 (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
91 the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
92 retained even in Standby or VBAT mode when the low power backup regulator
93 is enabled. It can be considered as an internal EEPROM when VBAT is
94 always present. You can use the HAL_PWREx_EnableBkUpReg() function to
95 enable the low power backup regulator.
96
97 (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
98 the backup SRAM is powered from VDD which replaces the VBAT power supply to
99 save battery life.
100
101 (+) The backup SRAM is not mass erased by a tamper event. It is read
102 protected to prevent confidential data, such as cryptographic private
103 key, from being accessed. The backup SRAM can be erased only through
104 the Flash interface when a protection level change from level 1 to
105 level 0 is requested.
106 -@- Refer to the description of Read protection (RDP) in the Flash
107 programming manual.
108
109 (+) The main internal regulator can be configured to have a tradeoff between
110 performance and power consumption when the device does not operate at
111 the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
112 macro which configure VOS bit in PWR_CR register
113
114 Refer to the product datasheets for more details.
115
116 *** FLASH Power Down configuration ****
117 =======================================
118 [..]
119 (+) By setting the FPDS bit in the PWR_CR register by using the
120 HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
121 down mode when the device enters Stop mode. When the Flash memory
122 is in power down mode, an additional startup delay is incurred when
123 waking up from Stop mode.
124
125 (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL
126 is OFF and the HSI or HSE clock source is selected as system clock.
127 The new value programmed is active only when the PLL is ON.
128 When the PLL is OFF, the voltage scale 3 is automatically selected.
129 Refer to the datasheets for more details.
130
131 *** Over-Drive and Under-Drive configuration ****
132 =================================================
133 [..]
134 (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has
135 2 operating modes available:
136 (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
137 voltage scaling (scale 1, scale 2 or scale 3)
138 (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
139 higher frequency than the normal mode for a given voltage scaling (scale 1,
140 scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
141 disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
142 the sequence described in Reference manual.
143
144 (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator
145 supplies a low power voltage to the 1.2V domain, thus preserving the content of registers
146 and internal SRAM. 2 operating modes are available:
147 (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
148 available when the main regulator or the low power regulator is used in Scale 3 or
149 low voltage mode.
150 (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
151 available when the main regulator or the low power regulator is in low voltage mode.
152
153@endverbatim
154 * @{
155 */
156
157/**
158 * @brief Enables the Backup Regulator.
159 * @retval HAL status
160 */
161HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
162{
163 uint32_t tickstart = 0;
164
165 *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;
166
167 /* Get tick */
168 tickstart = HAL_GetTick();
169
170 /* Wait till Backup regulator ready flag is set */
171 while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
172 {
173 if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
174 {
175 return HAL_TIMEOUT;
176 }
177 }
178 return HAL_OK;
179}
180
181/**
182 * @brief Disables the Backup Regulator.
183 * @retval HAL status
184 */
185HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
186{
187 uint32_t tickstart = 0;
188
189 *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;
190
191 /* Get tick */
192 tickstart = HAL_GetTick();
193
194 /* Wait till Backup regulator ready flag is set */
195 while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
196 {
197 if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
198 {
199 return HAL_TIMEOUT;
200 }
201 }
202 return HAL_OK;
203}
204
205/**
206 * @brief Enables the Flash Power Down in Stop mode.
207 * @retval None
208 */
209void HAL_PWREx_EnableFlashPowerDown(void)
210{
211 *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE;
212}
213
214/**
215 * @brief Disables the Flash Power Down in Stop mode.
216 * @retval None
217 */
218void HAL_PWREx_DisableFlashPowerDown(void)
219{
220 *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;
221}
222
223/**
224 * @brief Return Voltage Scaling Range.
225 * @retval The configured scale for the regulator voltage(VOS bit field).
226 * The returned value can be one of the following:
227 * - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
228 * - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
229 * - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
230 */
231uint32_t HAL_PWREx_GetVoltageRange(void)
232{
233 return (PWR->CR & PWR_CR_VOS);
234}
235
236#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
237/**
238 * @brief Configures the main internal regulator output voltage.
239 * @param VoltageScaling: specifies the regulator output voltage to achieve
240 * a tradeoff between performance and power consumption.
241 * This parameter can be one of the following values:
242 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
243 * the maximum value of fHCLK = 168 MHz.
244 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
245 * the maximum value of fHCLK = 144 MHz.
246 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
247 * a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API.
248 * When moving from Range 2 to Range 1, the system frequency can be increased to
249 * a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API.
250 * @retval HAL Status
251 */
252HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
253{
254 uint32_t tickstart = 0;
255
256 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
257
258 /* Enable PWR RCC Clock Peripheral */
259 __HAL_RCC_PWR_CLK_ENABLE();
260
261 /* Set Range */
262 __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
263
264 /* Get Start Tick*/
265 tickstart = HAL_GetTick();
266 while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
267 {
268 if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
269 {
270 return HAL_TIMEOUT;
271 }
272 }
273
274 return HAL_OK;
275}
276
277#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
278 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
279 defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \
280 defined(STM32F479xx)
281/**
282 * @brief Configures the main internal regulator output voltage.
283 * @param VoltageScaling: specifies the regulator output voltage to achieve
284 * a tradeoff between performance and power consumption.
285 * This parameter can be one of the following values:
286 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
287 * the maximum value of fHCLK is 168 MHz. It can be extended to
288 * 180 MHz by activating the over-drive mode.
289 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
290 * the maximum value of fHCLK is 144 MHz. It can be extended to,
291 * 168 MHz by activating the over-drive mode.
292 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode,
293 * the maximum value of fHCLK is 120 MHz.
294 * @note To update the system clock frequency(SYSCLK):
295 * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
296 * - Call the HAL_RCC_OscConfig() to configure the PLL.
297 * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
298 * - Set the new system clock frequency using the HAL_RCC_ClockConfig().
299 * @note The scale can be modified only when the HSI or HSE clock source is selected
300 * as system clock source, otherwise the API returns HAL_ERROR.
301 * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
302 * value in the PWR_CR1 register are not taken in account.
303 * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
304 * @note The new voltage scale is active only when the PLL is ON.
305 * @retval HAL Status
306 */
307HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
308{
309 uint32_t tickstart = 0;
310
311 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
312
313 /* Enable PWR RCC Clock Peripheral */
314 __HAL_RCC_PWR_CLK_ENABLE();
315
316 /* Check if the PLL is used as system clock or not */
317 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
318 {
319 /* Disable the main PLL */
320 __HAL_RCC_PLL_DISABLE();
321
322 /* Get Start Tick */
323 tickstart = HAL_GetTick();
324 /* Wait till PLL is disabled */
325 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
326 {
327 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
328 {
329 return HAL_TIMEOUT;
330 }
331 }
332
333 /* Set Range */
334 __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
335
336 /* Enable the main PLL */
337 __HAL_RCC_PLL_ENABLE();
338
339 /* Get Start Tick */
340 tickstart = HAL_GetTick();
341 /* Wait till PLL is ready */
342 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
343 {
344 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
345 {
346 return HAL_TIMEOUT;
347 }
348 }
349
350 /* Get Start Tick */
351 tickstart = HAL_GetTick();
352 while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
353 {
354 if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
355 {
356 return HAL_TIMEOUT;
357 }
358 }
359 }
360 else
361 {
362 return HAL_ERROR;
363 }
364
365 return HAL_OK;
366}
367#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
368
369#if defined(STM32F469xx) || defined(STM32F479xx)
370/**
371 * @brief Enables Wakeup Pin Detection on high level (rising edge).
372 * @retval None
373 */
374void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void)
375{
376 *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)DISABLE;
377}
378
379/**
380 * @brief Enables Wakeup Pin Detection on low level (falling edge).
381 * @retval None
382 */
383void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void)
384{
385 *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)ENABLE;
386}
387#endif /* STM32F469xx || STM32F479xx */
388
389#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
390 defined(STM32F411xE)
391/**
392 * @brief Enables Main Regulator low voltage mode.
393 * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
394 * @retval None
395 */
396void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
397{
398 *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE;
399}
400
401/**
402 * @brief Disables Main Regulator low voltage mode.
403 * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
404 * @retval None
405 */
406void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
407{
408 *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE;
409}
410
411/**
412 * @brief Enables Low Power Regulator low voltage mode.
413 * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
414 * @retval None
415 */
416void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
417{
418 *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE;
419}
420
421/**
422 * @brief Disables Low Power Regulator low voltage mode.
423 * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
424 * @retval None
425 */
426void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
427{
428 *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
429}
430
431#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE */
432
433#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
434 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
435/**
436 * @brief Activates the Over-Drive mode.
437 * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
438 * This mode allows the CPU and the core logic to operate at a higher frequency
439 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
440 * @note It is recommended to enter or exit Over-drive mode when the application is not running
441 * critical tasks and when the system clock source is either HSI or HSE.
442 * During the Over-drive switch activation, no peripheral clocks should be enabled.
443 * The peripheral clocks must be enabled once the Over-drive mode is activated.
444 * @retval HAL status
445 */
446HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
447{
448 uint32_t tickstart = 0;
449
450 __HAL_RCC_PWR_CLK_ENABLE();
451
452 /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
453 __HAL_PWR_OVERDRIVE_ENABLE();
454
455 /* Get tick */
456 tickstart = HAL_GetTick();
457
458 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
459 {
460 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
461 {
462 return HAL_TIMEOUT;
463 }
464 }
465
466 /* Enable the Over-drive switch */
467 __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
468
469 /* Get tick */
470 tickstart = HAL_GetTick();
471
472 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
473 {
474 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
475 {
476 return HAL_TIMEOUT;
477 }
478 }
479 return HAL_OK;
480}
481
482/**
483 * @brief Deactivates the Over-Drive mode.
484 * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
485 * This mode allows the CPU and the core logic to operate at a higher frequency
486 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
487 * @note It is recommended to enter or exit Over-drive mode when the application is not running
488 * critical tasks and when the system clock source is either HSI or HSE.
489 * During the Over-drive switch activation, no peripheral clocks should be enabled.
490 * The peripheral clocks must be enabled once the Over-drive mode is activated.
491 * @retval HAL status
492 */
493HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
494{
495 uint32_t tickstart = 0;
496
497 __HAL_RCC_PWR_CLK_ENABLE();
498
499 /* Disable the Over-drive switch */
500 __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
501
502 /* Get tick */
503 tickstart = HAL_GetTick();
504
505 while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
506 {
507 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
508 {
509 return HAL_TIMEOUT;
510 }
511 }
512
513 /* Disable the Over-drive */
514 __HAL_PWR_OVERDRIVE_DISABLE();
515
516 /* Get tick */
517 tickstart = HAL_GetTick();
518
519 while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
520 {
521 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
522 {
523 return HAL_TIMEOUT;
524 }
525 }
526
527 return HAL_OK;
528}
529
530/**
531 * @brief Enters in Under-Drive STOP mode.
532 *
533 * @note This mode is only available for STM32F42xxx/STM324F3xxx/STM32F446xx/STM32F469xx/STM32F479xx devices.
534 *
535 * @note This mode can be selected only when the Under-Drive is already active
536 *
537 * @note This mode is enabled only with STOP low power mode.
538 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
539 * mode is only available when the main regulator or the low power regulator
540 * is in low voltage mode
541 *
542 * @note If the Under-drive mode was enabled, it is automatically disabled after
543 * exiting Stop mode.
544 * When the voltage regulator operates in Under-drive mode, an additional
545 * startup delay is induced when waking up from Stop mode.
546 *
547 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
548 *
549 * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
550 * the HSI RC oscillator is selected as system clock.
551 *
552 * @note When the voltage regulator operates in low power mode, an additional
553 * startup delay is incurred when waking up from Stop mode.
554 * By keeping the internal regulator ON during Stop mode, the consumption
555 * is higher although the startup time is reduced.
556 *
557 * @param Regulator: specifies the regulator state in STOP mode.
558 * This parameter can be one of the following values:
559 * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode
560 * and Flash memory in power-down when the device is in Stop under-drive mode
561 * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode
562 * and Flash memory in power-down when the device is in Stop under-drive mode
563 * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
564 * This parameter can be one of the following values:
565 * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
566 * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
567 * @retval None
568 */
569HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
570{
571 uint32_t tmpreg1 = 0;
572 uint32_t tickstart = 0;
573
574 /* Check the parameters */
575 assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
576 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
577
578 /* Enable Power ctrl clock */
579 __HAL_RCC_PWR_CLK_ENABLE();
580 /* Enable the Under-drive Mode ---------------------------------------------*/
581 /* Clear Under-drive flag */
582 __HAL_PWR_CLEAR_ODRUDR_FLAG();
583
584 /* Enable the Under-drive */
585 __HAL_PWR_UNDERDRIVE_ENABLE();
586
587 /* Get tick */
588 tickstart = HAL_GetTick();
589
590 /* Wait for UnderDrive mode is ready */
591 while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))
592 {
593 if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)
594 {
595 return HAL_TIMEOUT;
596 }
597 }
598
599 /* Select the regulator state in STOP mode ---------------------------------*/
600 tmpreg1 = PWR->CR;
601 /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
602 tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);
603
604 /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
605 tmpreg1 |= Regulator;
606
607 /* Store the new value */
608 PWR->CR = tmpreg1;
609
610 /* Set SLEEPDEEP bit of Cortex System Control Register */
611 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
612
613 /* Select STOP mode entry --------------------------------------------------*/
614 if(STOPEntry == PWR_SLEEPENTRY_WFI)
615 {
616 /* Request Wait For Interrupt */
617 __WFI();
618 }
619 else
620 {
621 /* Request Wait For Event */
622 __WFE();
623 }
624 /* Reset SLEEPDEEP bit of Cortex System Control Register */
625 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
626
627 return HAL_OK;
628}
629
630#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
631/**
632 * @}
633 */
634
635/**
636 * @}
637 */
638
639#endif /* HAL_PWR_MODULE_ENABLED */
640/**
641 * @}
642 */
643
644/**
645 * @}
646 */
647
648/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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