1 | /**
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2 | ******************************************************************************
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3 | * @file stm32f4xx_hal_nor.c
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4 | * @author MCD Application Team
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5 | * @version V1.4.1
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6 | * @date 09-October-2015
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7 | * @brief NOR HAL module driver.
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8 | * This file provides a generic firmware to drive NOR memories mounted
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9 | * as external device.
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10 | *
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11 | @verbatim
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12 | ==============================================================================
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13 | ##### How to use this driver #####
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14 | ==============================================================================
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15 | [..]
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16 | This driver is a generic layered driver which contains a set of APIs used to
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17 | control NOR flash memories. It uses the FMC/FSMC layer functions to interface
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18 | with NOR devices. This driver is used as follows:
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19 |
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20 | (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
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21 | with control and timing parameters for both normal and extended mode.
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22 |
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23 | (+) Read NOR flash memory manufacturer code and device IDs using the function
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24 | HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
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25 | structure declared by the function caller.
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26 |
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27 | (+) Access NOR flash memory by read/write data unit operations using the functions
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28 | HAL_NOR_Read(), HAL_NOR_Program().
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29 |
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30 | (+) Perform NOR flash erase block/chip operations using the functions
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31 | HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
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32 |
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33 | (+) Read the NOR flash CFI (common flash interface) IDs using the function
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34 | HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
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35 | structure declared by the function caller.
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36 |
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37 | (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
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38 | HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
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39 |
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40 | (+) You can monitor the NOR device HAL state by calling the function
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41 | HAL_NOR_GetState()
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42 | [..]
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43 | (@) This driver is a set of generic APIs which handle standard NOR flash operations.
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44 | If a NOR flash device contains different operations and/or implementations,
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45 | it should be implemented separately.
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46 |
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47 | *** NOR HAL driver macros list ***
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48 | =============================================
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49 | [..]
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50 | Below the list of most used macros in NOR HAL driver.
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51 |
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52 | (+) NOR_WRITE : NOR memory write data to specified address
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53 |
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54 | @endverbatim
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55 | ******************************************************************************
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56 | * @attention
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57 | *
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58 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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59 | *
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60 | * Redistribution and use in source and binary forms, with or without modification,
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61 | * are permitted provided that the following conditions are met:
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62 | * 1. Redistributions of source code must retain the above copyright notice,
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63 | * this list of conditions and the following disclaimer.
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64 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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65 | * this list of conditions and the following disclaimer in the documentation
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66 | * and/or other materials provided with the distribution.
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67 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
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68 | * may be used to endorse or promote products derived from this software
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69 | * without specific prior written permission.
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70 | *
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71 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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72 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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73 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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74 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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75 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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76 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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77 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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78 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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79 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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80 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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81 | *
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82 | ******************************************************************************
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83 | */
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84 |
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85 | /* Includes ------------------------------------------------------------------*/
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86 | #include "stm32f4xx_hal.h"
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87 |
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88 | /** @addtogroup STM32F4xx_HAL_Driver
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89 | * @{
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90 | */
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91 |
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92 | /** @defgroup NOR NOR
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93 | * @brief NOR driver modules
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94 | * @{
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95 | */
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96 | #ifdef HAL_NOR_MODULE_ENABLED
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97 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
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98 | defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
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99 | defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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100 | /* Private typedef -----------------------------------------------------------*/
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101 | /* Private define ------------------------------------------------------------*/
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102 |
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103 | /** @defgroup NOR_Private_Defines NOR Private Defines
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104 | * @{
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105 | */
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106 |
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107 | /* Constants to define address to set to write a command */
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108 | #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
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109 | #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
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110 | #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
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111 | #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
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112 | #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
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113 | #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
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114 | #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
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115 |
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116 | /* Constants to define data to program a command */
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117 | #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
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118 | #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
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119 | #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
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120 | #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
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121 | #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
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122 | #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
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123 | #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
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124 | #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
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125 | #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
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126 | #define NOR_CMD_DATA_CFI (uint16_t)0x0098
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127 |
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128 | #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
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129 | #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
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130 | #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
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131 |
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132 | /* Mask on NOR STATUS REGISTER */
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133 | #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
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134 | #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
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135 |
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136 | /**
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137 | * @}
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138 | */
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139 |
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140 | /* Private macro -------------------------------------------------------------*/
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141 | /* Private variables ---------------------------------------------------------*/
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142 | /* Private functions ---------------------------------------------------------*/
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143 | /* Exported functions --------------------------------------------------------*/
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144 | /** @defgroup NOR_Exported_Functions NOR Exported Functions
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145 | * @{
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146 | */
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147 |
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148 | /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
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149 | * @brief Initialization and Configuration functions
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150 | *
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151 | @verbatim
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152 | ==============================================================================
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153 | ##### NOR Initialization and de_initialization functions #####
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154 | ==============================================================================
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155 | [..]
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156 | This section provides functions allowing to initialize/de-initialize
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157 | the NOR memory
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158 |
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159 | @endverbatim
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160 | * @{
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161 | */
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162 |
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163 | /**
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164 | * @brief Perform the NOR memory Initialization sequence
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165 | * @param hnor: pointer to the NOR handle
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166 | * @param Timing: pointer to NOR control timing structure
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167 | * @param ExtTiming: pointer to NOR extended mode timing structure
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168 | * @retval HAL status
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169 | */
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170 | HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
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171 | {
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172 | /* Check the NOR handle parameter */
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173 | if(hnor == NULL)
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174 | {
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175 | return HAL_ERROR;
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176 | }
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177 |
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178 | if(hnor->State == HAL_NOR_STATE_RESET)
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179 | {
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180 | /* Allocate lock resource and initialize it */
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181 | hnor->Lock = HAL_UNLOCKED;
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182 | /* Initialize the low level hardware (MSP) */
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183 | HAL_NOR_MspInit(hnor);
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184 | }
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185 |
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186 | /* Initialize NOR control Interface */
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187 | FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
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188 |
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189 | /* Initialize NOR timing Interface */
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190 | FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
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191 |
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192 | /* Initialize NOR extended mode timing Interface */
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193 | FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
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194 |
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195 | /* Enable the NORSRAM device */
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196 | __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
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197 |
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198 | /* Check the NOR controller state */
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199 | hnor->State = HAL_NOR_STATE_READY;
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200 |
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201 | return HAL_OK;
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202 | }
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203 |
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204 | /**
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205 | * @brief Perform NOR memory De-Initialization sequence
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206 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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207 | * the configuration information for NOR module.
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208 | * @retval HAL status
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209 | */
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210 | HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
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211 | {
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212 | /* De-Initialize the low level hardware (MSP) */
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213 | HAL_NOR_MspDeInit(hnor);
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214 |
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215 | /* Configure the NOR registers with their reset values */
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216 | FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
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217 |
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218 | /* Update the NOR controller state */
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219 | hnor->State = HAL_NOR_STATE_RESET;
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220 |
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221 | /* Release Lock */
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222 | __HAL_UNLOCK(hnor);
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223 |
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224 | return HAL_OK;
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225 | }
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226 |
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227 | /**
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228 | * @brief NOR MSP Init
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229 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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230 | * the configuration information for NOR module.
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231 | * @retval None
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232 | */
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233 | __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
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234 | {
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235 | /* NOTE : This function Should not be modified, when the callback is needed,
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236 | the HAL_NOR_MspInit could be implemented in the user file
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237 | */
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238 | }
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239 |
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240 | /**
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241 | * @brief NOR MSP DeInit
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242 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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243 | * the configuration information for NOR module.
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244 | * @retval None
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245 | */
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246 | __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
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247 | {
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248 | /* NOTE : This function Should not be modified, when the callback is needed,
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249 | the HAL_NOR_MspDeInit could be implemented in the user file
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250 | */
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251 | }
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252 |
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253 | /**
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254 | * @brief NOR BSP Wait for Ready/Busy signal
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255 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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256 | * the configuration information for NOR module.
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257 | * @param Timeout: Maximum timeout value
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258 | * @retval None
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259 | */
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260 | __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
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261 | {
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262 | /* NOTE : This function Should not be modified, when the callback is needed,
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263 | the HAL_NOR_BspWait could be implemented in the user file
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264 | */
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265 | }
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266 |
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267 | /**
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268 | * @}
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269 | */
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270 |
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271 | /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
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272 | * @brief Input Output and memory control functions
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273 | *
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274 | @verbatim
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275 | ==============================================================================
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276 | ##### NOR Input and Output functions #####
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277 | ==============================================================================
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278 | [..]
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279 | This section provides functions allowing to use and control the NOR memory
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280 |
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281 | @endverbatim
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282 | * @{
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283 | */
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284 |
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285 | /**
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286 | * @brief Read NOR flash IDs
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287 | * @param hnor: pointer to the NOR handle
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288 | * @param pNOR_ID : pointer to NOR ID structure
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289 | * @retval HAL status
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290 | */
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291 | HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
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292 | {
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293 | uint32_t deviceaddress = 0;
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294 |
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295 | /* Process Locked */
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296 | __HAL_LOCK(hnor);
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297 |
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298 | /* Check the NOR controller state */
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299 | if(hnor->State == HAL_NOR_STATE_BUSY)
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300 | {
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301 | return HAL_BUSY;
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302 | }
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303 |
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304 | /* Select the NOR device address */
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305 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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306 | {
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307 | deviceaddress = NOR_MEMORY_ADRESS1;
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308 | }
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309 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
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310 | {
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311 | deviceaddress = NOR_MEMORY_ADRESS2;
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312 | }
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313 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
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314 | {
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315 | deviceaddress = NOR_MEMORY_ADRESS3;
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316 | }
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317 | else /* FMC_NORSRAM_BANK4 */
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318 | {
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319 | deviceaddress = NOR_MEMORY_ADRESS4;
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320 | }
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321 |
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322 | /* Update the NOR controller state */
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323 | hnor->State = HAL_NOR_STATE_BUSY;
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324 |
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325 | /* Send read ID command */
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326 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
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327 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
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328 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
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329 |
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330 | /* Read the NOR IDs */
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331 | pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, MC_ADDRESS);
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332 | pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
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333 | pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
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334 | pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
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335 |
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336 | /* Check the NOR controller state */
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337 | hnor->State = HAL_NOR_STATE_READY;
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338 |
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339 | /* Process unlocked */
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340 | __HAL_UNLOCK(hnor);
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341 |
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342 | return HAL_OK;
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343 | }
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344 |
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345 | /**
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346 | * @brief Returns the NOR memory to Read mode.
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347 | * @param hnor: pointer to the NOR handle
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348 | * @retval HAL status
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349 | */
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350 | HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
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351 | {
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352 | uint32_t deviceaddress = 0;
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353 |
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354 | /* Process Locked */
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355 | __HAL_LOCK(hnor);
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356 |
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357 | /* Check the NOR controller state */
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358 | if(hnor->State == HAL_NOR_STATE_BUSY)
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359 | {
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360 | return HAL_BUSY;
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361 | }
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362 |
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363 | /* Select the NOR device address */
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364 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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365 | {
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366 | deviceaddress = NOR_MEMORY_ADRESS1;
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367 | }
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368 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
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369 | {
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370 | deviceaddress = NOR_MEMORY_ADRESS2;
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371 | }
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372 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
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373 | {
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374 | deviceaddress = NOR_MEMORY_ADRESS3;
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375 | }
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376 | else /* FMC_NORSRAM_BANK4 */
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377 | {
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378 | deviceaddress = NOR_MEMORY_ADRESS4;
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379 | }
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380 |
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381 | NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
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382 |
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383 | /* Check the NOR controller state */
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384 | hnor->State = HAL_NOR_STATE_READY;
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385 |
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386 | /* Process unlocked */
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387 | __HAL_UNLOCK(hnor);
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388 |
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389 | return HAL_OK;
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390 | }
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391 |
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392 | /**
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393 | * @brief Read data from NOR memory
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394 | * @param hnor: pointer to the NOR handle
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395 | * @param pAddress: pointer to Device address
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396 | * @param pData : pointer to read data
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397 | * @retval HAL status
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398 | */
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399 | HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
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400 | {
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401 | uint32_t deviceaddress = 0;
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402 |
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403 | /* Process Locked */
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404 | __HAL_LOCK(hnor);
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405 |
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406 | /* Check the NOR controller state */
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407 | if(hnor->State == HAL_NOR_STATE_BUSY)
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408 | {
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409 | return HAL_BUSY;
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410 | }
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411 |
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412 | /* Select the NOR device address */
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413 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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414 | {
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415 | deviceaddress = NOR_MEMORY_ADRESS1;
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416 | }
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417 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
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418 | {
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419 | deviceaddress = NOR_MEMORY_ADRESS2;
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420 | }
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421 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
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422 | {
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423 | deviceaddress = NOR_MEMORY_ADRESS3;
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424 | }
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425 | else /* FMC_NORSRAM_BANK4 */
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426 | {
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427 | deviceaddress = NOR_MEMORY_ADRESS4;
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428 | }
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429 |
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430 | /* Update the NOR controller state */
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431 | hnor->State = HAL_NOR_STATE_BUSY;
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432 |
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433 | /* Send read data command */
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434 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
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435 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
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436 | NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
|
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437 |
|
---|
438 | /* Read the data */
|
---|
439 | *pData = *(__IO uint32_t *)(uint32_t)pAddress;
|
---|
440 |
|
---|
441 | /* Check the NOR controller state */
|
---|
442 | hnor->State = HAL_NOR_STATE_READY;
|
---|
443 |
|
---|
444 | /* Process unlocked */
|
---|
445 | __HAL_UNLOCK(hnor);
|
---|
446 |
|
---|
447 | return HAL_OK;
|
---|
448 | }
|
---|
449 |
|
---|
450 | /**
|
---|
451 | * @brief Program data to NOR memory
|
---|
452 | * @param hnor: pointer to the NOR handle
|
---|
453 | * @param pAddress: Device address
|
---|
454 | * @param pData : pointer to the data to write
|
---|
455 | * @retval HAL status
|
---|
456 | */
|
---|
457 | HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
|
---|
458 | {
|
---|
459 | uint32_t deviceaddress = 0;
|
---|
460 |
|
---|
461 | /* Process Locked */
|
---|
462 | __HAL_LOCK(hnor);
|
---|
463 |
|
---|
464 | /* Check the NOR controller state */
|
---|
465 | if(hnor->State == HAL_NOR_STATE_BUSY)
|
---|
466 | {
|
---|
467 | return HAL_BUSY;
|
---|
468 | }
|
---|
469 |
|
---|
470 | /* Select the NOR device address */
|
---|
471 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
---|
472 | {
|
---|
473 | deviceaddress = NOR_MEMORY_ADRESS1;
|
---|
474 | }
|
---|
475 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
---|
476 | {
|
---|
477 | deviceaddress = NOR_MEMORY_ADRESS2;
|
---|
478 | }
|
---|
479 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
---|
480 | {
|
---|
481 | deviceaddress = NOR_MEMORY_ADRESS3;
|
---|
482 | }
|
---|
483 | else /* FMC_NORSRAM_BANK4 */
|
---|
484 | {
|
---|
485 | deviceaddress = NOR_MEMORY_ADRESS4;
|
---|
486 | }
|
---|
487 |
|
---|
488 | /* Update the NOR controller state */
|
---|
489 | hnor->State = HAL_NOR_STATE_BUSY;
|
---|
490 |
|
---|
491 | /* Send program data command */
|
---|
492 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
---|
493 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
---|
494 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
|
---|
495 |
|
---|
496 | /* Write the data */
|
---|
497 | NOR_WRITE(pAddress, *pData);
|
---|
498 |
|
---|
499 | /* Check the NOR controller state */
|
---|
500 | hnor->State = HAL_NOR_STATE_READY;
|
---|
501 |
|
---|
502 | /* Process unlocked */
|
---|
503 | __HAL_UNLOCK(hnor);
|
---|
504 |
|
---|
505 | return HAL_OK;
|
---|
506 | }
|
---|
507 |
|
---|
508 | /**
|
---|
509 | * @brief Reads a half-word buffer from the NOR memory.
|
---|
510 | * @param hnor: pointer to the NOR handle
|
---|
511 | * @param uwAddress: NOR memory internal address to read from.
|
---|
512 | * @param pData: pointer to the buffer that receives the data read from the
|
---|
513 | * NOR memory.
|
---|
514 | * @param uwBufferSize : number of Half word to read.
|
---|
515 | * @retval HAL status
|
---|
516 | */
|
---|
517 | HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
|
---|
518 | {
|
---|
519 | uint32_t deviceaddress = 0;
|
---|
520 |
|
---|
521 | /* Process Locked */
|
---|
522 | __HAL_LOCK(hnor);
|
---|
523 |
|
---|
524 | /* Check the NOR controller state */
|
---|
525 | if(hnor->State == HAL_NOR_STATE_BUSY)
|
---|
526 | {
|
---|
527 | return HAL_BUSY;
|
---|
528 | }
|
---|
529 |
|
---|
530 | /* Select the NOR device address */
|
---|
531 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
---|
532 | {
|
---|
533 | deviceaddress = NOR_MEMORY_ADRESS1;
|
---|
534 | }
|
---|
535 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
---|
536 | {
|
---|
537 | deviceaddress = NOR_MEMORY_ADRESS2;
|
---|
538 | }
|
---|
539 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
---|
540 | {
|
---|
541 | deviceaddress = NOR_MEMORY_ADRESS3;
|
---|
542 | }
|
---|
543 | else /* FMC_NORSRAM_BANK4 */
|
---|
544 | {
|
---|
545 | deviceaddress = NOR_MEMORY_ADRESS4;
|
---|
546 | }
|
---|
547 |
|
---|
548 | /* Update the NOR controller state */
|
---|
549 | hnor->State = HAL_NOR_STATE_BUSY;
|
---|
550 |
|
---|
551 | /* Send read data command */
|
---|
552 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
---|
553 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
---|
554 | NOR_WRITE(uwAddress, 0x00F0);
|
---|
555 |
|
---|
556 | /* Read buffer */
|
---|
557 | while( uwBufferSize > 0)
|
---|
558 | {
|
---|
559 | *pData++ = *(__IO uint16_t *)uwAddress;
|
---|
560 | uwAddress += 2;
|
---|
561 | uwBufferSize--;
|
---|
562 | }
|
---|
563 |
|
---|
564 | /* Check the NOR controller state */
|
---|
565 | hnor->State = HAL_NOR_STATE_READY;
|
---|
566 |
|
---|
567 | /* Process unlocked */
|
---|
568 | __HAL_UNLOCK(hnor);
|
---|
569 |
|
---|
570 | return HAL_OK;
|
---|
571 | }
|
---|
572 |
|
---|
573 | /**
|
---|
574 | * @brief Writes a half-word buffer to the NOR memory. This function must be used
|
---|
575 | only with S29GL128P NOR memory.
|
---|
576 | * @param hnor: pointer to the NOR handle
|
---|
577 | * @param uwAddress: NOR memory internal start write address
|
---|
578 | * @param pData: pointer to source data buffer.
|
---|
579 | * @param uwBufferSize: Size of the buffer to write
|
---|
580 | * @retval HAL status
|
---|
581 | */
|
---|
582 | HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
|
---|
583 | {
|
---|
584 | uint16_t * p_currentaddress = (uint16_t *)NULL;
|
---|
585 | uint16_t * p_endaddress = (uint16_t *)NULL;
|
---|
586 | uint32_t lastloadedaddress = 0, deviceaddress = 0;
|
---|
587 |
|
---|
588 | /* Process Locked */
|
---|
589 | __HAL_LOCK(hnor);
|
---|
590 |
|
---|
591 | /* Check the NOR controller state */
|
---|
592 | if(hnor->State == HAL_NOR_STATE_BUSY)
|
---|
593 | {
|
---|
594 | return HAL_BUSY;
|
---|
595 | }
|
---|
596 |
|
---|
597 | /* Select the NOR device address */
|
---|
598 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
---|
599 | {
|
---|
600 | deviceaddress = NOR_MEMORY_ADRESS1;
|
---|
601 | }
|
---|
602 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
---|
603 | {
|
---|
604 | deviceaddress = NOR_MEMORY_ADRESS2;
|
---|
605 | }
|
---|
606 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
---|
607 | {
|
---|
608 | deviceaddress = NOR_MEMORY_ADRESS3;
|
---|
609 | }
|
---|
610 | else /* FMC_NORSRAM_BANK4 */
|
---|
611 | {
|
---|
612 | deviceaddress = NOR_MEMORY_ADRESS4;
|
---|
613 | }
|
---|
614 |
|
---|
615 | /* Update the NOR controller state */
|
---|
616 | hnor->State = HAL_NOR_STATE_BUSY;
|
---|
617 |
|
---|
618 | /* Initialize variables */
|
---|
619 | p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
|
---|
620 | p_endaddress = p_currentaddress + (uwBufferSize-1);
|
---|
621 | lastloadedaddress = (uint32_t)(uwAddress);
|
---|
622 |
|
---|
623 | /* Issue unlock command sequence */
|
---|
624 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
---|
625 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
---|
626 |
|
---|
627 | /* Write Buffer Load Command */
|
---|
628 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
|
---|
629 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1));
|
---|
630 |
|
---|
631 | /* Load Data into NOR Buffer */
|
---|
632 | while(p_currentaddress <= p_endaddress)
|
---|
633 | {
|
---|
634 | /* Store last loaded address & data value (for polling) */
|
---|
635 | lastloadedaddress = (uint32_t)p_currentaddress;
|
---|
636 |
|
---|
637 | NOR_WRITE(p_currentaddress, *pData++);
|
---|
638 |
|
---|
639 | p_currentaddress ++;
|
---|
640 | }
|
---|
641 |
|
---|
642 | NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
|
---|
643 |
|
---|
644 | /* Check the NOR controller state */
|
---|
645 | hnor->State = HAL_NOR_STATE_READY;
|
---|
646 |
|
---|
647 | /* Process unlocked */
|
---|
648 | __HAL_UNLOCK(hnor);
|
---|
649 |
|
---|
650 | return HAL_OK;
|
---|
651 |
|
---|
652 | }
|
---|
653 |
|
---|
654 | /**
|
---|
655 | * @brief Erase the specified block of the NOR memory
|
---|
656 | * @param hnor: pointer to the NOR handle
|
---|
657 | * @param BlockAddress : Block to erase address
|
---|
658 | * @param Address: Device address
|
---|
659 | * @retval HAL status
|
---|
660 | */
|
---|
661 | HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
|
---|
662 | {
|
---|
663 | uint32_t deviceaddress = 0;
|
---|
664 |
|
---|
665 | /* Process Locked */
|
---|
666 | __HAL_LOCK(hnor);
|
---|
667 |
|
---|
668 | /* Check the NOR controller state */
|
---|
669 | if(hnor->State == HAL_NOR_STATE_BUSY)
|
---|
670 | {
|
---|
671 | return HAL_BUSY;
|
---|
672 | }
|
---|
673 |
|
---|
674 | /* Select the NOR device address */
|
---|
675 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
---|
676 | {
|
---|
677 | deviceaddress = NOR_MEMORY_ADRESS1;
|
---|
678 | }
|
---|
679 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
---|
680 | {
|
---|
681 | deviceaddress = NOR_MEMORY_ADRESS2;
|
---|
682 | }
|
---|
683 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
---|
684 | {
|
---|
685 | deviceaddress = NOR_MEMORY_ADRESS3;
|
---|
686 | }
|
---|
687 | else /* FMC_NORSRAM_BANK4 */
|
---|
688 | {
|
---|
689 | deviceaddress = NOR_MEMORY_ADRESS4;
|
---|
690 | }
|
---|
691 |
|
---|
692 | /* Update the NOR controller state */
|
---|
693 | hnor->State = HAL_NOR_STATE_BUSY;
|
---|
694 |
|
---|
695 | /* Send block erase command sequence */
|
---|
696 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
---|
697 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
---|
698 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
|
---|
699 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
|
---|
700 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
|
---|
701 | NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
|
---|
702 |
|
---|
703 | /* Check the NOR memory status and update the controller state */
|
---|
704 | hnor->State = HAL_NOR_STATE_READY;
|
---|
705 |
|
---|
706 | /* Process unlocked */
|
---|
707 | __HAL_UNLOCK(hnor);
|
---|
708 |
|
---|
709 | return HAL_OK;
|
---|
710 |
|
---|
711 | }
|
---|
712 |
|
---|
713 | /**
|
---|
714 | * @brief Erase the entire NOR chip.
|
---|
715 | * @param hnor: pointer to the NOR handle
|
---|
716 | * @param Address : Device address
|
---|
717 | * @retval HAL status
|
---|
718 | */
|
---|
719 | HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
|
---|
720 | {
|
---|
721 | uint32_t deviceaddress = 0;
|
---|
722 |
|
---|
723 | /* Process Locked */
|
---|
724 | __HAL_LOCK(hnor);
|
---|
725 |
|
---|
726 | /* Check the NOR controller state */
|
---|
727 | if(hnor->State == HAL_NOR_STATE_BUSY)
|
---|
728 | {
|
---|
729 | return HAL_BUSY;
|
---|
730 | }
|
---|
731 |
|
---|
732 | /* Select the NOR device address */
|
---|
733 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
---|
734 | {
|
---|
735 | deviceaddress = NOR_MEMORY_ADRESS1;
|
---|
736 | }
|
---|
737 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
---|
738 | {
|
---|
739 | deviceaddress = NOR_MEMORY_ADRESS2;
|
---|
740 | }
|
---|
741 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
---|
742 | {
|
---|
743 | deviceaddress = NOR_MEMORY_ADRESS3;
|
---|
744 | }
|
---|
745 | else /* FMC_NORSRAM_BANK4 */
|
---|
746 | {
|
---|
747 | deviceaddress = NOR_MEMORY_ADRESS4;
|
---|
748 | }
|
---|
749 |
|
---|
750 | /* Update the NOR controller state */
|
---|
751 | hnor->State = HAL_NOR_STATE_BUSY;
|
---|
752 |
|
---|
753 | /* Send NOR chip erase command sequence */
|
---|
754 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
---|
755 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
---|
756 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
|
---|
757 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
|
---|
758 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
|
---|
759 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
|
---|
760 |
|
---|
761 | /* Check the NOR memory status and update the controller state */
|
---|
762 | hnor->State = HAL_NOR_STATE_READY;
|
---|
763 |
|
---|
764 | /* Process unlocked */
|
---|
765 | __HAL_UNLOCK(hnor);
|
---|
766 |
|
---|
767 | return HAL_OK;
|
---|
768 | }
|
---|
769 |
|
---|
770 | /**
|
---|
771 | * @brief Read NOR flash CFI IDs
|
---|
772 | * @param hnor: pointer to the NOR handle
|
---|
773 | * @param pNOR_CFI : pointer to NOR CFI IDs structure
|
---|
774 | * @retval HAL status
|
---|
775 | */
|
---|
776 | HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
|
---|
777 | {
|
---|
778 | uint32_t deviceaddress = 0;
|
---|
779 |
|
---|
780 | /* Process Locked */
|
---|
781 | __HAL_LOCK(hnor);
|
---|
782 |
|
---|
783 | /* Check the NOR controller state */
|
---|
784 | if(hnor->State == HAL_NOR_STATE_BUSY)
|
---|
785 | {
|
---|
786 | return HAL_BUSY;
|
---|
787 | }
|
---|
788 |
|
---|
789 | /* Select the NOR device address */
|
---|
790 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
---|
791 | {
|
---|
792 | deviceaddress = NOR_MEMORY_ADRESS1;
|
---|
793 | }
|
---|
794 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
---|
795 | {
|
---|
796 | deviceaddress = NOR_MEMORY_ADRESS2;
|
---|
797 | }
|
---|
798 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
---|
799 | {
|
---|
800 | deviceaddress = NOR_MEMORY_ADRESS3;
|
---|
801 | }
|
---|
802 | else /* FMC_NORSRAM_BANK4 */
|
---|
803 | {
|
---|
804 | deviceaddress = NOR_MEMORY_ADRESS4;
|
---|
805 | }
|
---|
806 |
|
---|
807 | /* Update the NOR controller state */
|
---|
808 | hnor->State = HAL_NOR_STATE_BUSY;
|
---|
809 |
|
---|
810 | /* Send read CFI query command */
|
---|
811 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
|
---|
812 |
|
---|
813 | /* read the NOR CFI information */
|
---|
814 | pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI1_ADDRESS);
|
---|
815 | pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI2_ADDRESS);
|
---|
816 | pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI3_ADDRESS);
|
---|
817 | pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI4_ADDRESS);
|
---|
818 |
|
---|
819 | /* Check the NOR controller state */
|
---|
820 | hnor->State = HAL_NOR_STATE_READY;
|
---|
821 |
|
---|
822 | /* Process unlocked */
|
---|
823 | __HAL_UNLOCK(hnor);
|
---|
824 |
|
---|
825 | return HAL_OK;
|
---|
826 | }
|
---|
827 |
|
---|
828 | /**
|
---|
829 | * @}
|
---|
830 | */
|
---|
831 |
|
---|
832 | /** @defgroup NOR_Exported_Functions_Group3 Control functions
|
---|
833 | * @brief management functions
|
---|
834 | *
|
---|
835 | @verbatim
|
---|
836 | ==============================================================================
|
---|
837 | ##### NOR Control functions #####
|
---|
838 | ==============================================================================
|
---|
839 | [..]
|
---|
840 | This subsection provides a set of functions allowing to control dynamically
|
---|
841 | the NOR interface.
|
---|
842 |
|
---|
843 | @endverbatim
|
---|
844 | * @{
|
---|
845 | */
|
---|
846 |
|
---|
847 | /**
|
---|
848 | * @brief Enables dynamically NOR write operation.
|
---|
849 | * @param hnor: pointer to the NOR handle
|
---|
850 | * @retval HAL status
|
---|
851 | */
|
---|
852 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
|
---|
853 | {
|
---|
854 | /* Process Locked */
|
---|
855 | __HAL_LOCK(hnor);
|
---|
856 |
|
---|
857 | /* Enable write operation */
|
---|
858 | FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
|
---|
859 |
|
---|
860 | /* Update the NOR controller state */
|
---|
861 | hnor->State = HAL_NOR_STATE_READY;
|
---|
862 |
|
---|
863 | /* Process unlocked */
|
---|
864 | __HAL_UNLOCK(hnor);
|
---|
865 |
|
---|
866 | return HAL_OK;
|
---|
867 | }
|
---|
868 |
|
---|
869 | /**
|
---|
870 | * @brief Disables dynamically NOR write operation.
|
---|
871 | * @param hnor: pointer to the NOR handle
|
---|
872 | * @retval HAL status
|
---|
873 | */
|
---|
874 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
|
---|
875 | {
|
---|
876 | /* Process Locked */
|
---|
877 | __HAL_LOCK(hnor);
|
---|
878 |
|
---|
879 | /* Update the SRAM controller state */
|
---|
880 | hnor->State = HAL_NOR_STATE_BUSY;
|
---|
881 |
|
---|
882 | /* Disable write operation */
|
---|
883 | FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
|
---|
884 |
|
---|
885 | /* Update the NOR controller state */
|
---|
886 | hnor->State = HAL_NOR_STATE_PROTECTED;
|
---|
887 |
|
---|
888 | /* Process unlocked */
|
---|
889 | __HAL_UNLOCK(hnor);
|
---|
890 |
|
---|
891 | return HAL_OK;
|
---|
892 | }
|
---|
893 |
|
---|
894 | /**
|
---|
895 | * @}
|
---|
896 | */
|
---|
897 |
|
---|
898 | /** @defgroup NOR_Exported_Functions_Group4 State functions
|
---|
899 | * @brief Peripheral State functions
|
---|
900 | *
|
---|
901 | @verbatim
|
---|
902 | ==============================================================================
|
---|
903 | ##### NOR State functions #####
|
---|
904 | ==============================================================================
|
---|
905 | [..]
|
---|
906 | This subsection permits to get in run-time the status of the NOR controller
|
---|
907 | and the data flow.
|
---|
908 |
|
---|
909 | @endverbatim
|
---|
910 | * @{
|
---|
911 | */
|
---|
912 |
|
---|
913 | /**
|
---|
914 | * @brief return the NOR controller state
|
---|
915 | * @param hnor: pointer to the NOR handle
|
---|
916 | * @retval NOR controller state
|
---|
917 | */
|
---|
918 | HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
|
---|
919 | {
|
---|
920 | return hnor->State;
|
---|
921 | }
|
---|
922 |
|
---|
923 | /**
|
---|
924 | * @brief Returns the NOR operation status.
|
---|
925 | * @param hnor: pointer to the NOR handle
|
---|
926 | * @param Address: Device address
|
---|
927 | * @param Timeout: NOR programming Timeout
|
---|
928 | * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
|
---|
929 | * or HAL_NOR_STATUS_TIMEOUT
|
---|
930 | */
|
---|
931 | HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
|
---|
932 | {
|
---|
933 | HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
|
---|
934 | uint16_t tmpSR1 = 0, tmpSR2 = 0;
|
---|
935 | uint32_t tickstart = 0;
|
---|
936 |
|
---|
937 | /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
|
---|
938 | HAL_NOR_MspWait(hnor, Timeout);
|
---|
939 |
|
---|
940 | /* Get the NOR memory operation status -------------------------------------*/
|
---|
941 |
|
---|
942 | /* Get tick */
|
---|
943 | tickstart = HAL_GetTick();
|
---|
944 | while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
|
---|
945 | {
|
---|
946 | /* Check for the Timeout */
|
---|
947 | if(Timeout != HAL_MAX_DELAY)
|
---|
948 | {
|
---|
949 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
|
---|
950 | {
|
---|
951 | status = HAL_NOR_STATUS_TIMEOUT;
|
---|
952 | }
|
---|
953 | }
|
---|
954 |
|
---|
955 | /* Read NOR status register (DQ6 and DQ5) */
|
---|
956 | tmpSR1 = *(__IO uint16_t *)Address;
|
---|
957 | tmpSR2 = *(__IO uint16_t *)Address;
|
---|
958 |
|
---|
959 | /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
|
---|
960 | if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
|
---|
961 | {
|
---|
962 | return HAL_NOR_STATUS_SUCCESS ;
|
---|
963 | }
|
---|
964 |
|
---|
965 | if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
|
---|
966 | {
|
---|
967 | status = HAL_NOR_STATUS_ONGOING;
|
---|
968 | }
|
---|
969 |
|
---|
970 | tmpSR1 = *(__IO uint16_t *)Address;
|
---|
971 | tmpSR2 = *(__IO uint16_t *)Address;
|
---|
972 |
|
---|
973 | /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
|
---|
974 | if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
|
---|
975 | {
|
---|
976 | return HAL_NOR_STATUS_SUCCESS;
|
---|
977 | }
|
---|
978 | if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
|
---|
979 | {
|
---|
980 | return HAL_NOR_STATUS_ERROR;
|
---|
981 | }
|
---|
982 | }
|
---|
983 |
|
---|
984 | /* Return the operation status */
|
---|
985 | return status;
|
---|
986 | }
|
---|
987 |
|
---|
988 | /**
|
---|
989 | * @}
|
---|
990 | */
|
---|
991 |
|
---|
992 |
|
---|
993 | /**
|
---|
994 | * @}
|
---|
995 | */
|
---|
996 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
|
---|
997 | STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
|
---|
998 | STM32F479xx */
|
---|
999 | #endif /* HAL_NOR_MODULE_ENABLED */
|
---|
1000 | /**
|
---|
1001 | * @}
|
---|
1002 | */
|
---|
1003 |
|
---|
1004 | /**
|
---|
1005 | * @}
|
---|
1006 | */
|
---|
1007 |
|
---|
1008 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
---|