1 | /**
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2 | ******************************************************************************
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3 | * @file stm32f4xx_hal_nand.c
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4 | * @author MCD Application Team
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5 | * @version V1.4.1
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6 | * @date 09-October-2015
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7 | * @brief NAND HAL module driver.
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8 | * This file provides a generic firmware to drive NAND memories mounted
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9 | * as external device.
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10 | *
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11 | @verbatim
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12 | ==============================================================================
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13 | ##### How to use this driver #####
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14 | ==============================================================================
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15 | [..]
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16 | This driver is a generic layered driver which contains a set of APIs used to
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17 | control NAND flash memories. It uses the FMC/FSMC layer functions to interface
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18 | with NAND devices. This driver is used as follows:
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19 |
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20 | (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
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21 | with control and timing parameters for both common and attribute spaces.
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22 |
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23 | (+) Read NAND flash memory maker and device IDs using the function
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24 | HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
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25 | structure declared by the function caller.
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26 |
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27 | (+) Access NAND flash memory by read/write operations using the functions
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28 | HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
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29 | to read/write page(s)/spare area(s). These functions use specific device
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30 | information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
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31 | structure. The read/write address information is contained by the Nand_Address_Typedef
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32 | structure passed as parameter.
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33 |
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34 | (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
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35 |
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36 | (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
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37 | The erase block address information is contained in the Nand_Address_Typedef
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38 | structure passed as parameter.
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39 |
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40 | (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
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41 |
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42 | (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
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43 | HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
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44 | feature or the function HAL_NAND_GetECC() to get the ECC correction code.
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45 |
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46 | (+) You can monitor the NAND device HAL state by calling the function
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47 | HAL_NAND_GetState()
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48 |
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49 | [..]
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50 | (@) This driver is a set of generic APIs which handle standard NAND flash operations.
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51 | If a NAND flash device contains different operations and/or implementations,
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52 | it should be implemented separately.
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53 |
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54 | @endverbatim
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55 | ******************************************************************************
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56 | * @attention
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57 | *
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58 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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59 | *
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60 | * Redistribution and use in source and binary forms, with or without modification,
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61 | * are permitted provided that the following conditions are met:
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62 | * 1. Redistributions of source code must retain the above copyright notice,
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63 | * this list of conditions and the following disclaimer.
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64 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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65 | * this list of conditions and the following disclaimer in the documentation
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66 | * and/or other materials provided with the distribution.
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67 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
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68 | * may be used to endorse or promote products derived from this software
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69 | * without specific prior written permission.
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70 | *
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71 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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72 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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73 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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74 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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75 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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76 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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77 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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78 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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79 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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80 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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81 | *
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82 | ******************************************************************************
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83 | */
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84 |
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85 | /* Includes ------------------------------------------------------------------*/
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86 | #include "stm32f4xx_hal.h"
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87 |
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88 | /** @addtogroup STM32F4xx_HAL_Driver
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89 | * @{
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90 | */
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91 |
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92 |
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93 | #ifdef HAL_NAND_MODULE_ENABLED
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94 |
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95 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
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96 | defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
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97 | defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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98 |
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99 | /** @defgroup NAND NAND
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100 | * @brief NAND HAL module driver
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101 | * @{
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102 | */
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103 |
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104 | /* Private typedef -----------------------------------------------------------*/
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105 | /* Private define ------------------------------------------------------------*/
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106 | /** @defgroup NAND_Private_Constants NAND Private Constants
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107 | * @{
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108 | */
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109 |
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110 | /**
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111 | * @}
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112 | */
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113 |
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114 | /* Private macro -------------------------------------------------------------*/
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115 | /** @defgroup NAND_Private_Macros NAND Private Macros
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116 | * @{
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117 | */
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118 |
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119 | /**
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120 | * @}
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121 | */
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122 | /* Private variables ---------------------------------------------------------*/
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123 | /* Private function prototypes -----------------------------------------------*/
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124 | /* Exported functions --------------------------------------------------------*/
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125 | /** @defgroup NAND_Exported_Functions NAND Exported Functions
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126 | * @{
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127 | */
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128 |
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129 | /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
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130 | * @brief Initialization and Configuration functions
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131 | *
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132 | @verbatim
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133 | ==============================================================================
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134 | ##### NAND Initialization and de-initialization functions #####
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135 | ==============================================================================
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136 | [..]
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137 | This section provides functions allowing to initialize/de-initialize
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138 | the NAND memory
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139 |
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140 | @endverbatim
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141 | * @{
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142 | */
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143 |
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144 | /**
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145 | * @brief Perform NAND memory Initialization sequence
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146 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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147 | * the configuration information for NAND module.
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148 | * @param ComSpace_Timing: pointer to Common space timing structure
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149 | * @param AttSpace_Timing: pointer to Attribute space timing structure
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150 | * @retval HAL status
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151 | */
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152 | HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
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153 | {
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154 | /* Check the NAND handle state */
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155 | if(hnand == NULL)
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156 | {
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157 | return HAL_ERROR;
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158 | }
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159 |
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160 | if(hnand->State == HAL_NAND_STATE_RESET)
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161 | {
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162 | /* Allocate lock resource and initialize it */
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163 | hnand->Lock = HAL_UNLOCKED;
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164 | /* Initialize the low level hardware (MSP) */
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165 | HAL_NAND_MspInit(hnand);
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166 | }
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167 |
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168 | /* Initialize NAND control Interface */
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169 | FMC_NAND_Init(hnand->Instance, &(hnand->Init));
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170 |
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171 | /* Initialize NAND common space timing Interface */
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172 | FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
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173 |
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174 | /* Initialize NAND attribute space timing Interface */
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175 | FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
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176 |
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177 | /* Enable the NAND device */
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178 | __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
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179 |
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180 | /* Update the NAND controller state */
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181 | hnand->State = HAL_NAND_STATE_READY;
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182 |
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183 | return HAL_OK;
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184 | }
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185 |
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186 | /**
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187 | * @brief Perform NAND memory De-Initialization sequence
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188 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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189 | * the configuration information for NAND module.
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190 | * @retval HAL status
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191 | */
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192 | HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
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193 | {
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194 | /* Initialize the low level hardware (MSP) */
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195 | HAL_NAND_MspDeInit(hnand);
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196 |
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197 | /* Configure the NAND registers with their reset values */
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198 | FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
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199 |
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200 | /* Reset the NAND controller state */
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201 | hnand->State = HAL_NAND_STATE_RESET;
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202 |
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203 | /* Release Lock */
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204 | __HAL_UNLOCK(hnand);
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205 |
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206 | return HAL_OK;
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207 | }
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208 |
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209 | /**
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210 | * @brief NAND MSP Init
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211 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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212 | * the configuration information for NAND module.
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213 | * @retval None
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214 | */
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215 | __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
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216 | {
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217 | /* NOTE : This function Should not be modified, when the callback is needed,
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218 | the HAL_NAND_MspInit could be implemented in the user file
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219 | */
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220 | }
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221 |
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222 | /**
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223 | * @brief NAND MSP DeInit
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224 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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225 | * the configuration information for NAND module.
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226 | * @retval None
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227 | */
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228 | __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
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229 | {
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230 | /* NOTE : This function Should not be modified, when the callback is needed,
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231 | the HAL_NAND_MspDeInit could be implemented in the user file
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232 | */
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233 | }
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234 |
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235 |
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236 | /**
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237 | * @brief This function handles NAND device interrupt request.
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238 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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239 | * the configuration information for NAND module.
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240 | * @retval HAL status
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241 | */
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242 | void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
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243 | {
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244 | /* Check NAND interrupt Rising edge flag */
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245 | if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
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246 | {
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247 | /* NAND interrupt callback*/
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248 | HAL_NAND_ITCallback(hnand);
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249 |
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250 | /* Clear NAND interrupt Rising edge pending bit */
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251 | __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
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252 | }
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253 |
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254 | /* Check NAND interrupt Level flag */
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255 | if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
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256 | {
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257 | /* NAND interrupt callback*/
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258 | HAL_NAND_ITCallback(hnand);
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259 |
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260 | /* Clear NAND interrupt Level pending bit */
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261 | __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
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262 | }
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263 |
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264 | /* Check NAND interrupt Falling edge flag */
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265 | if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
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266 | {
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267 | /* NAND interrupt callback*/
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268 | HAL_NAND_ITCallback(hnand);
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269 |
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270 | /* Clear NAND interrupt Falling edge pending bit */
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271 | __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
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272 | }
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273 |
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274 | /* Check NAND interrupt FIFO empty flag */
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275 | if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
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276 | {
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277 | /* NAND interrupt callback*/
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278 | HAL_NAND_ITCallback(hnand);
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279 |
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280 | /* Clear NAND interrupt FIFO empty pending bit */
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281 | __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
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282 | }
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283 |
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284 | }
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285 |
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286 | /**
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287 | * @brief NAND interrupt feature callback
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288 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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289 | * the configuration information for NAND module.
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290 | * @retval None
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291 | */
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292 | __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
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293 | {
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294 | /* NOTE : This function Should not be modified, when the callback is needed,
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295 | the HAL_NAND_ITCallback could be implemented in the user file
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296 | */
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297 | }
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298 |
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299 | /**
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300 | * @}
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301 | */
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302 |
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303 | /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
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304 | * @brief Input Output and memory control functions
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305 | *
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306 | @verbatim
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307 | ==============================================================================
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308 | ##### NAND Input and Output functions #####
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309 | ==============================================================================
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310 | [..]
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311 | This section provides functions allowing to use and control the NAND
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312 | memory
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313 |
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314 | @endverbatim
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315 | * @{
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316 | */
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317 |
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318 | /**
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319 | * @brief Read the NAND memory electronic signature
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320 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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321 | * the configuration information for NAND module.
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322 | * @param pNAND_ID: NAND ID structure
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323 | * @retval HAL status
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324 | */
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325 | HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
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326 | {
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327 | __IO uint32_t data = 0;
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328 | uint32_t deviceaddress = 0;
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329 |
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330 | /* Process Locked */
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331 | __HAL_LOCK(hnand);
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332 |
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333 | /* Check the NAND controller state */
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334 | if(hnand->State == HAL_NAND_STATE_BUSY)
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335 | {
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336 | return HAL_BUSY;
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337 | }
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338 |
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339 | /* Identify the device address */
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340 | if(hnand->Init.NandBank == FMC_NAND_BANK2)
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341 | {
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342 | deviceaddress = NAND_DEVICE1;
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343 | }
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344 | else
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345 | {
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346 | deviceaddress = NAND_DEVICE2;
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347 | }
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348 |
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349 | /* Update the NAND controller state */
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350 | hnand->State = HAL_NAND_STATE_BUSY;
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351 |
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352 | /* Send Read ID command sequence */
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353 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
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354 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
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355 |
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356 | /* Read the electronic signature from NAND flash */
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357 | data = *(__IO uint32_t *)deviceaddress;
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358 |
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359 | /* Return the data read */
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360 | pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
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361 | pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
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362 | pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
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363 | pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
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364 |
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365 | /* Update the NAND controller state */
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366 | hnand->State = HAL_NAND_STATE_READY;
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367 |
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368 | /* Process unlocked */
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369 | __HAL_UNLOCK(hnand);
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370 |
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371 | return HAL_OK;
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372 | }
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373 |
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374 | /**
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375 | * @brief NAND memory reset
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376 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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377 | * the configuration information for NAND module.
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378 | * @retval HAL status
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379 | */
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380 | HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
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381 | {
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382 | uint32_t deviceaddress = 0;
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383 |
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384 | /* Process Locked */
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385 | __HAL_LOCK(hnand);
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386 |
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387 | /* Check the NAND controller state */
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388 | if(hnand->State == HAL_NAND_STATE_BUSY)
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389 | {
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390 | return HAL_BUSY;
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391 | }
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392 |
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393 | /* Identify the device address */
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394 | if(hnand->Init.NandBank == FMC_NAND_BANK2)
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395 | {
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396 | deviceaddress = NAND_DEVICE1;
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397 | }
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398 | else
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399 | {
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400 | deviceaddress = NAND_DEVICE2;
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401 | }
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402 |
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403 | /* Update the NAND controller state */
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404 | hnand->State = HAL_NAND_STATE_BUSY;
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405 |
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406 | /* Send NAND reset command */
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407 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
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408 |
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409 |
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410 | /* Update the NAND controller state */
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411 | hnand->State = HAL_NAND_STATE_READY;
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412 |
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413 | /* Process unlocked */
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414 | __HAL_UNLOCK(hnand);
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415 |
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416 | return HAL_OK;
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417 |
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418 | }
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419 |
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420 | /**
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421 | * @brief Read Page(s) from NAND memory block
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422 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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423 | * the configuration information for NAND module.
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424 | * @param pAddress : pointer to NAND address structure
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425 | * @param pBuffer : pointer to destination read buffer
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426 | * @param NumPageToRead : number of pages to read from block
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427 | * @retval HAL status
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428 | */
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429 | HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
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430 | {
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431 | __IO uint32_t index = 0;
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432 | uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS;
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433 | NAND_AddressTypeDef nandaddress;
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434 | uint32_t addressoffset = 0;
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435 |
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436 | /* Process Locked */
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437 | __HAL_LOCK(hnand);
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438 |
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439 | /* Check the NAND controller state */
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440 | if(hnand->State == HAL_NAND_STATE_BUSY)
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441 | {
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442 | return HAL_BUSY;
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443 | }
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444 |
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445 | /* Identify the device address */
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446 | if(hnand->Init.NandBank == FMC_NAND_BANK2)
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447 | {
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448 | deviceaddress = NAND_DEVICE1;
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449 | }
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450 | else
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451 | {
|
---|
452 | deviceaddress = NAND_DEVICE2;
|
---|
453 | }
|
---|
454 |
|
---|
455 | /* Update the NAND controller state */
|
---|
456 | hnand->State = HAL_NAND_STATE_BUSY;
|
---|
457 |
|
---|
458 | /* Save the content of pAddress as it will be modified */
|
---|
459 | nandaddress.Block = pAddress->Block;
|
---|
460 | nandaddress.Page = pAddress->Page;
|
---|
461 | nandaddress.Zone = pAddress->Zone;
|
---|
462 |
|
---|
463 | /* Page(s) read loop */
|
---|
464 | while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
|
---|
465 | {
|
---|
466 | /* update the buffer size */
|
---|
467 | size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
|
---|
468 |
|
---|
469 | /* Get the address offset */
|
---|
470 | addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
|
---|
471 |
|
---|
472 | /* Send read page command sequence */
|
---|
473 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
|
---|
474 |
|
---|
475 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
|
---|
476 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
|
---|
477 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
|
---|
478 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
|
---|
479 |
|
---|
480 | /* for 512 and 1 GB devices, 4th cycle is required */
|
---|
481 | if(hnand->Info.BlockNbr >= 1024)
|
---|
482 | {
|
---|
483 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
|
---|
484 | }
|
---|
485 |
|
---|
486 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
|
---|
487 |
|
---|
488 | /* Get Data into Buffer */
|
---|
489 | for(index = size; index != 0; index--)
|
---|
490 | {
|
---|
491 | *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
|
---|
492 | }
|
---|
493 |
|
---|
494 | /* Increment read pages number */
|
---|
495 | numpagesread++;
|
---|
496 |
|
---|
497 | /* Decrement pages to read */
|
---|
498 | NumPageToRead--;
|
---|
499 |
|
---|
500 | /* Increment the NAND address */
|
---|
501 | addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
|
---|
502 | }
|
---|
503 |
|
---|
504 | /* Update the NAND controller state */
|
---|
505 | hnand->State = HAL_NAND_STATE_READY;
|
---|
506 |
|
---|
507 | /* Process unlocked */
|
---|
508 | __HAL_UNLOCK(hnand);
|
---|
509 |
|
---|
510 | return HAL_OK;
|
---|
511 |
|
---|
512 | }
|
---|
513 |
|
---|
514 | /**
|
---|
515 | * @brief Write Page(s) to NAND memory block
|
---|
516 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
|
---|
517 | * the configuration information for NAND module.
|
---|
518 | * @param pAddress : pointer to NAND address structure
|
---|
519 | * @param pBuffer : pointer to source buffer to write
|
---|
520 | * @param NumPageToWrite : number of pages to write to block
|
---|
521 | * @retval HAL status
|
---|
522 | */
|
---|
523 | HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
|
---|
524 | {
|
---|
525 | __IO uint32_t index = 0;
|
---|
526 | uint32_t tickstart = 0;
|
---|
527 | uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS;
|
---|
528 | NAND_AddressTypeDef nandaddress;
|
---|
529 | uint32_t addressoffset = 0;
|
---|
530 |
|
---|
531 | /* Process Locked */
|
---|
532 | __HAL_LOCK(hnand);
|
---|
533 |
|
---|
534 | /* Check the NAND controller state */
|
---|
535 | if(hnand->State == HAL_NAND_STATE_BUSY)
|
---|
536 | {
|
---|
537 | return HAL_BUSY;
|
---|
538 | }
|
---|
539 |
|
---|
540 | /* Identify the device address */
|
---|
541 | if(hnand->Init.NandBank == FMC_NAND_BANK2)
|
---|
542 | {
|
---|
543 | deviceaddress = NAND_DEVICE1;
|
---|
544 | }
|
---|
545 | else
|
---|
546 | {
|
---|
547 | deviceaddress = NAND_DEVICE2;
|
---|
548 | }
|
---|
549 |
|
---|
550 | /* Update the NAND controller state */
|
---|
551 | hnand->State = HAL_NAND_STATE_BUSY;
|
---|
552 |
|
---|
553 | /* Save the content of pAddress as it will be modified */
|
---|
554 | nandaddress.Block = pAddress->Block;
|
---|
555 | nandaddress.Page = pAddress->Page;
|
---|
556 | nandaddress.Zone = pAddress->Zone;
|
---|
557 |
|
---|
558 | /* Page(s) write loop */
|
---|
559 | while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
|
---|
560 | {
|
---|
561 | /* update the buffer size */
|
---|
562 | size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
|
---|
563 |
|
---|
564 | /* Get the address offset */
|
---|
565 | addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
|
---|
566 |
|
---|
567 | /* Send write page command sequence */
|
---|
568 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
|
---|
569 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
|
---|
570 |
|
---|
571 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
|
---|
572 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
|
---|
573 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
|
---|
574 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
|
---|
575 |
|
---|
576 | /* for 512 and 1 GB devices, 4th cycle is required */
|
---|
577 | if(hnand->Info.BlockNbr >= 1024)
|
---|
578 | {
|
---|
579 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
|
---|
580 | }
|
---|
581 |
|
---|
582 | /* Write data to memory */
|
---|
583 | for(index = size; index != 0; index--)
|
---|
584 | {
|
---|
585 | *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
|
---|
586 | }
|
---|
587 |
|
---|
588 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
|
---|
589 |
|
---|
590 | /* Get tick */
|
---|
591 | tickstart = HAL_GetTick();
|
---|
592 |
|
---|
593 | /* Read status until NAND is ready */
|
---|
594 | while(HAL_NAND_Read_Status(hnand) != NAND_READY)
|
---|
595 | {
|
---|
596 | if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
|
---|
597 | {
|
---|
598 | return HAL_TIMEOUT;
|
---|
599 | }
|
---|
600 | }
|
---|
601 |
|
---|
602 | /* Increment written pages number */
|
---|
603 | numpageswritten++;
|
---|
604 |
|
---|
605 | /* Decrement pages to write */
|
---|
606 | NumPageToWrite--;
|
---|
607 |
|
---|
608 | /* Increment the NAND address */
|
---|
609 | addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
|
---|
610 | }
|
---|
611 |
|
---|
612 | /* Update the NAND controller state */
|
---|
613 | hnand->State = HAL_NAND_STATE_READY;
|
---|
614 |
|
---|
615 | /* Process unlocked */
|
---|
616 | __HAL_UNLOCK(hnand);
|
---|
617 |
|
---|
618 | return HAL_OK;
|
---|
619 | }
|
---|
620 |
|
---|
621 | /**
|
---|
622 | * @brief Read Spare area(s) from NAND memory
|
---|
623 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
|
---|
624 | * the configuration information for NAND module.
|
---|
625 | * @param pAddress : pointer to NAND address structure
|
---|
626 | * @param pBuffer: pointer to source buffer to write
|
---|
627 | * @param NumSpareAreaToRead: Number of spare area to read
|
---|
628 | * @retval HAL status
|
---|
629 | */
|
---|
630 | HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
|
---|
631 | {
|
---|
632 | __IO uint32_t index = 0;
|
---|
633 | uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS;
|
---|
634 | NAND_AddressTypeDef nandaddress;
|
---|
635 | uint32_t addressoffset = 0;
|
---|
636 |
|
---|
637 | /* Process Locked */
|
---|
638 | __HAL_LOCK(hnand);
|
---|
639 |
|
---|
640 | /* Check the NAND controller state */
|
---|
641 | if(hnand->State == HAL_NAND_STATE_BUSY)
|
---|
642 | {
|
---|
643 | return HAL_BUSY;
|
---|
644 | }
|
---|
645 |
|
---|
646 | /* Identify the device address */
|
---|
647 | if(hnand->Init.NandBank == FMC_NAND_BANK2)
|
---|
648 | {
|
---|
649 | deviceaddress = NAND_DEVICE1;
|
---|
650 | }
|
---|
651 | else
|
---|
652 | {
|
---|
653 | deviceaddress = NAND_DEVICE2;
|
---|
654 | }
|
---|
655 |
|
---|
656 | /* Update the NAND controller state */
|
---|
657 | hnand->State = HAL_NAND_STATE_BUSY;
|
---|
658 |
|
---|
659 | /* Save the content of pAddress as it will be modified */
|
---|
660 | nandaddress.Block = pAddress->Block;
|
---|
661 | nandaddress.Page = pAddress->Page;
|
---|
662 | nandaddress.Zone = pAddress->Zone;
|
---|
663 |
|
---|
664 | /* Spare area(s) read loop */
|
---|
665 | while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
|
---|
666 | {
|
---|
667 | /* update the buffer size */
|
---|
668 | size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
|
---|
669 |
|
---|
670 | /* Get the address offset */
|
---|
671 | addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
|
---|
672 |
|
---|
673 | /* Send read spare area command sequence */
|
---|
674 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
|
---|
675 |
|
---|
676 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
|
---|
677 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
|
---|
678 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
|
---|
679 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
|
---|
680 |
|
---|
681 | /* for 512 and 1 GB devices, 4th cycle is required */
|
---|
682 | if(hnand->Info.BlockNbr >= 1024)
|
---|
683 | {
|
---|
684 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
|
---|
685 | }
|
---|
686 |
|
---|
687 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
|
---|
688 |
|
---|
689 | /* Get Data into Buffer */
|
---|
690 | for (index = size ;index != 0; index--)
|
---|
691 | {
|
---|
692 | *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
|
---|
693 | }
|
---|
694 |
|
---|
695 | /* Increment read spare areas number */
|
---|
696 | num_spare_area_read++;
|
---|
697 |
|
---|
698 | /* Decrement spare areas to read */
|
---|
699 | NumSpareAreaToRead--;
|
---|
700 |
|
---|
701 | /* Increment the NAND address */
|
---|
702 | addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
|
---|
703 | }
|
---|
704 |
|
---|
705 | /* Update the NAND controller state */
|
---|
706 | hnand->State = HAL_NAND_STATE_READY;
|
---|
707 |
|
---|
708 | /* Process unlocked */
|
---|
709 | __HAL_UNLOCK(hnand);
|
---|
710 |
|
---|
711 | return HAL_OK;
|
---|
712 | }
|
---|
713 |
|
---|
714 | /**
|
---|
715 | * @brief Write Spare area(s) to NAND memory
|
---|
716 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
|
---|
717 | * the configuration information for NAND module.
|
---|
718 | * @param pAddress : pointer to NAND address structure
|
---|
719 | * @param pBuffer : pointer to source buffer to write
|
---|
720 | * @param NumSpareAreaTowrite : number of spare areas to write to block
|
---|
721 | * @retval HAL status
|
---|
722 | */
|
---|
723 | HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
|
---|
724 | {
|
---|
725 | __IO uint32_t index = 0;
|
---|
726 | uint32_t tickstart = 0;
|
---|
727 | uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS;
|
---|
728 | NAND_AddressTypeDef nandaddress;
|
---|
729 | uint32_t addressoffset = 0;
|
---|
730 |
|
---|
731 | /* Process Locked */
|
---|
732 | __HAL_LOCK(hnand);
|
---|
733 |
|
---|
734 | /* Check the NAND controller state */
|
---|
735 | if(hnand->State == HAL_NAND_STATE_BUSY)
|
---|
736 | {
|
---|
737 | return HAL_BUSY;
|
---|
738 | }
|
---|
739 |
|
---|
740 | /* Identify the device address */
|
---|
741 | if(hnand->Init.NandBank == FMC_NAND_BANK2)
|
---|
742 | {
|
---|
743 | deviceaddress = NAND_DEVICE1;
|
---|
744 | }
|
---|
745 | else
|
---|
746 | {
|
---|
747 | deviceaddress = NAND_DEVICE2;
|
---|
748 | }
|
---|
749 |
|
---|
750 | /* Update the FMC_NAND controller state */
|
---|
751 | hnand->State = HAL_NAND_STATE_BUSY;
|
---|
752 |
|
---|
753 | /* Save the content of pAddress as it will be modified */
|
---|
754 | nandaddress.Block = pAddress->Block;
|
---|
755 | nandaddress.Page = pAddress->Page;
|
---|
756 | nandaddress.Zone = pAddress->Zone;
|
---|
757 |
|
---|
758 | /* Spare area(s) write loop */
|
---|
759 | while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
|
---|
760 | {
|
---|
761 | /* update the buffer size */
|
---|
762 | size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
|
---|
763 |
|
---|
764 | /* Get the address offset */
|
---|
765 | addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
|
---|
766 |
|
---|
767 | /* Send write Spare area command sequence */
|
---|
768 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
|
---|
769 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
|
---|
770 |
|
---|
771 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
|
---|
772 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
|
---|
773 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
|
---|
774 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
|
---|
775 |
|
---|
776 | /* for 512 and 1 GB devices, 4th cycle is required */
|
---|
777 | if(hnand->Info.BlockNbr >= 1024)
|
---|
778 | {
|
---|
779 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
|
---|
780 | }
|
---|
781 |
|
---|
782 | /* Write data to memory */
|
---|
783 | for(; index < size; index++)
|
---|
784 | {
|
---|
785 | *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
|
---|
786 | }
|
---|
787 |
|
---|
788 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
|
---|
789 |
|
---|
790 | /* Get tick */
|
---|
791 | tickstart = HAL_GetTick();
|
---|
792 |
|
---|
793 | /* Read status until NAND is ready */
|
---|
794 | while(HAL_NAND_Read_Status(hnand) != NAND_READY)
|
---|
795 | {
|
---|
796 | if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
|
---|
797 | {
|
---|
798 | return HAL_TIMEOUT;
|
---|
799 | }
|
---|
800 | }
|
---|
801 |
|
---|
802 | /* Increment written spare areas number */
|
---|
803 | num_spare_area_written++;
|
---|
804 |
|
---|
805 | /* Decrement spare areas to write */
|
---|
806 | NumSpareAreaTowrite--;
|
---|
807 |
|
---|
808 | /* Increment the NAND address */
|
---|
809 | addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
|
---|
810 | }
|
---|
811 |
|
---|
812 | /* Update the NAND controller state */
|
---|
813 | hnand->State = HAL_NAND_STATE_READY;
|
---|
814 |
|
---|
815 | /* Process unlocked */
|
---|
816 | __HAL_UNLOCK(hnand);
|
---|
817 |
|
---|
818 | return HAL_OK;
|
---|
819 | }
|
---|
820 |
|
---|
821 | /**
|
---|
822 | * @brief NAND memory Block erase
|
---|
823 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
|
---|
824 | * the configuration information for NAND module.
|
---|
825 | * @param pAddress : pointer to NAND address structure
|
---|
826 | * @retval HAL status
|
---|
827 | */
|
---|
828 | HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
|
---|
829 | {
|
---|
830 | uint32_t deviceaddress = 0;
|
---|
831 | uint32_t tickstart = 0;
|
---|
832 |
|
---|
833 | /* Process Locked */
|
---|
834 | __HAL_LOCK(hnand);
|
---|
835 |
|
---|
836 | /* Check the NAND controller state */
|
---|
837 | if(hnand->State == HAL_NAND_STATE_BUSY)
|
---|
838 | {
|
---|
839 | return HAL_BUSY;
|
---|
840 | }
|
---|
841 |
|
---|
842 | /* Identify the device address */
|
---|
843 | if(hnand->Init.NandBank == FMC_NAND_BANK2)
|
---|
844 | {
|
---|
845 | deviceaddress = NAND_DEVICE1;
|
---|
846 | }
|
---|
847 | else
|
---|
848 | {
|
---|
849 | deviceaddress = NAND_DEVICE2;
|
---|
850 | }
|
---|
851 |
|
---|
852 | /* Update the NAND controller state */
|
---|
853 | hnand->State = HAL_NAND_STATE_BUSY;
|
---|
854 |
|
---|
855 | /* Send Erase block command sequence */
|
---|
856 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
|
---|
857 |
|
---|
858 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
|
---|
859 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
|
---|
860 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
|
---|
861 |
|
---|
862 | /* for 512 and 1 GB devices, 4th cycle is required */
|
---|
863 | if(hnand->Info.BlockNbr >= 1024)
|
---|
864 | {
|
---|
865 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
|
---|
866 | }
|
---|
867 |
|
---|
868 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
|
---|
869 |
|
---|
870 | /* Update the NAND controller state */
|
---|
871 | hnand->State = HAL_NAND_STATE_READY;
|
---|
872 |
|
---|
873 | /* Get tick */
|
---|
874 | tickstart = HAL_GetTick();
|
---|
875 |
|
---|
876 | /* Read status until NAND is ready */
|
---|
877 | while(HAL_NAND_Read_Status(hnand) != NAND_READY)
|
---|
878 | {
|
---|
879 | if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
|
---|
880 | {
|
---|
881 | /* Process unlocked */
|
---|
882 | __HAL_UNLOCK(hnand);
|
---|
883 |
|
---|
884 | return HAL_TIMEOUT;
|
---|
885 | }
|
---|
886 | }
|
---|
887 |
|
---|
888 | /* Process unlocked */
|
---|
889 | __HAL_UNLOCK(hnand);
|
---|
890 |
|
---|
891 | return HAL_OK;
|
---|
892 | }
|
---|
893 |
|
---|
894 | /**
|
---|
895 | * @brief NAND memory read status
|
---|
896 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
|
---|
897 | * the configuration information for NAND module.
|
---|
898 | * @retval NAND status
|
---|
899 | */
|
---|
900 | uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
|
---|
901 | {
|
---|
902 | uint32_t data = 0;
|
---|
903 | uint32_t deviceaddress = 0;
|
---|
904 |
|
---|
905 | /* Identify the device address */
|
---|
906 | if(hnand->Init.NandBank == FMC_NAND_BANK2)
|
---|
907 | {
|
---|
908 | deviceaddress = NAND_DEVICE1;
|
---|
909 | }
|
---|
910 | else
|
---|
911 | {
|
---|
912 | deviceaddress = NAND_DEVICE2;
|
---|
913 | }
|
---|
914 |
|
---|
915 | /* Send Read status operation command */
|
---|
916 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
|
---|
917 |
|
---|
918 | /* Read status register data */
|
---|
919 | data = *(__IO uint8_t *)deviceaddress;
|
---|
920 |
|
---|
921 | /* Return the status */
|
---|
922 | if((data & NAND_ERROR) == NAND_ERROR)
|
---|
923 | {
|
---|
924 | return NAND_ERROR;
|
---|
925 | }
|
---|
926 | else if((data & NAND_READY) == NAND_READY)
|
---|
927 | {
|
---|
928 | return NAND_READY;
|
---|
929 | }
|
---|
930 |
|
---|
931 | return NAND_BUSY;
|
---|
932 | }
|
---|
933 |
|
---|
934 | /**
|
---|
935 | * @brief Increment the NAND memory address
|
---|
936 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
|
---|
937 | * the configuration information for NAND module.
|
---|
938 | * @param pAddress: pointer to NAND address structure
|
---|
939 | * @retval The new status of the increment address operation. It can be:
|
---|
940 | * - NAND_VALID_ADDRESS: When the new address is valid address
|
---|
941 | * - NAND_INVALID_ADDRESS: When the new address is invalid address
|
---|
942 | */
|
---|
943 | uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
|
---|
944 | {
|
---|
945 | uint32_t status = NAND_VALID_ADDRESS;
|
---|
946 |
|
---|
947 | /* Increment page address */
|
---|
948 | pAddress->Page++;
|
---|
949 |
|
---|
950 | /* Check NAND address is valid */
|
---|
951 | if(pAddress->Page == hnand->Info.BlockSize)
|
---|
952 | {
|
---|
953 | pAddress->Page = 0;
|
---|
954 | pAddress->Block++;
|
---|
955 |
|
---|
956 | if(pAddress->Block == hnand->Info.ZoneSize)
|
---|
957 | {
|
---|
958 | pAddress->Block = 0;
|
---|
959 | pAddress->Zone++;
|
---|
960 |
|
---|
961 | if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
|
---|
962 | {
|
---|
963 | status = NAND_INVALID_ADDRESS;
|
---|
964 | }
|
---|
965 | }
|
---|
966 | }
|
---|
967 |
|
---|
968 | return (status);
|
---|
969 | }
|
---|
970 | /**
|
---|
971 | * @}
|
---|
972 | */
|
---|
973 |
|
---|
974 | /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
|
---|
975 | * @brief management functions
|
---|
976 | *
|
---|
977 | @verbatim
|
---|
978 | ==============================================================================
|
---|
979 | ##### NAND Control functions #####
|
---|
980 | ==============================================================================
|
---|
981 | [..]
|
---|
982 | This subsection provides a set of functions allowing to control dynamically
|
---|
983 | the NAND interface.
|
---|
984 |
|
---|
985 | @endverbatim
|
---|
986 | * @{
|
---|
987 | */
|
---|
988 |
|
---|
989 |
|
---|
990 | /**
|
---|
991 | * @brief Enables dynamically NAND ECC feature.
|
---|
992 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
|
---|
993 | * the configuration information for NAND module.
|
---|
994 | * @retval HAL status
|
---|
995 | */
|
---|
996 | HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
|
---|
997 | {
|
---|
998 | /* Check the NAND controller state */
|
---|
999 | if(hnand->State == HAL_NAND_STATE_BUSY)
|
---|
1000 | {
|
---|
1001 | return HAL_BUSY;
|
---|
1002 | }
|
---|
1003 |
|
---|
1004 | /* Update the NAND state */
|
---|
1005 | hnand->State = HAL_NAND_STATE_BUSY;
|
---|
1006 |
|
---|
1007 | /* Enable ECC feature */
|
---|
1008 | FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
|
---|
1009 |
|
---|
1010 | /* Update the NAND state */
|
---|
1011 | hnand->State = HAL_NAND_STATE_READY;
|
---|
1012 |
|
---|
1013 | return HAL_OK;
|
---|
1014 | }
|
---|
1015 |
|
---|
1016 | /**
|
---|
1017 | * @brief Disables dynamically FMC_NAND ECC feature.
|
---|
1018 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
|
---|
1019 | * the configuration information for NAND module.
|
---|
1020 | * @retval HAL status
|
---|
1021 | */
|
---|
1022 | HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
|
---|
1023 | {
|
---|
1024 | /* Check the NAND controller state */
|
---|
1025 | if(hnand->State == HAL_NAND_STATE_BUSY)
|
---|
1026 | {
|
---|
1027 | return HAL_BUSY;
|
---|
1028 | }
|
---|
1029 |
|
---|
1030 | /* Update the NAND state */
|
---|
1031 | hnand->State = HAL_NAND_STATE_BUSY;
|
---|
1032 |
|
---|
1033 | /* Disable ECC feature */
|
---|
1034 | FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
|
---|
1035 |
|
---|
1036 | /* Update the NAND state */
|
---|
1037 | hnand->State = HAL_NAND_STATE_READY;
|
---|
1038 |
|
---|
1039 | return HAL_OK;
|
---|
1040 | }
|
---|
1041 |
|
---|
1042 | /**
|
---|
1043 | * @brief Disables dynamically NAND ECC feature.
|
---|
1044 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
|
---|
1045 | * the configuration information for NAND module.
|
---|
1046 | * @param ECCval: pointer to ECC value
|
---|
1047 | * @param Timeout: maximum timeout to wait
|
---|
1048 | * @retval HAL status
|
---|
1049 | */
|
---|
1050 | HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
|
---|
1051 | {
|
---|
1052 | HAL_StatusTypeDef status = HAL_OK;
|
---|
1053 |
|
---|
1054 | /* Check the NAND controller state */
|
---|
1055 | if(hnand->State == HAL_NAND_STATE_BUSY)
|
---|
1056 | {
|
---|
1057 | return HAL_BUSY;
|
---|
1058 | }
|
---|
1059 |
|
---|
1060 | /* Update the NAND state */
|
---|
1061 | hnand->State = HAL_NAND_STATE_BUSY;
|
---|
1062 |
|
---|
1063 | /* Get NAND ECC value */
|
---|
1064 | status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
|
---|
1065 |
|
---|
1066 | /* Update the NAND state */
|
---|
1067 | hnand->State = HAL_NAND_STATE_READY;
|
---|
1068 |
|
---|
1069 | return status;
|
---|
1070 | }
|
---|
1071 |
|
---|
1072 | /**
|
---|
1073 | * @}
|
---|
1074 | */
|
---|
1075 |
|
---|
1076 |
|
---|
1077 | /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
|
---|
1078 | * @brief Peripheral State functions
|
---|
1079 | *
|
---|
1080 | @verbatim
|
---|
1081 | ==============================================================================
|
---|
1082 | ##### NAND State functions #####
|
---|
1083 | ==============================================================================
|
---|
1084 | [..]
|
---|
1085 | This subsection permits to get in run-time the status of the NAND controller
|
---|
1086 | and the data flow.
|
---|
1087 |
|
---|
1088 | @endverbatim
|
---|
1089 | * @{
|
---|
1090 | */
|
---|
1091 |
|
---|
1092 | /**
|
---|
1093 | * @brief return the NAND state
|
---|
1094 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
|
---|
1095 | * the configuration information for NAND module.
|
---|
1096 | * @retval HAL state
|
---|
1097 | */
|
---|
1098 | HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
|
---|
1099 | {
|
---|
1100 | return hnand->State;
|
---|
1101 | }
|
---|
1102 |
|
---|
1103 | /**
|
---|
1104 | * @}
|
---|
1105 | */
|
---|
1106 |
|
---|
1107 | /**
|
---|
1108 | * @}
|
---|
1109 | */
|
---|
1110 |
|
---|
1111 | /**
|
---|
1112 | * @}
|
---|
1113 | */
|
---|
1114 |
|
---|
1115 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
|
---|
1116 | STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
|
---|
1117 | STM32F446xx || STM32F469xx || STM32F479xx */
|
---|
1118 | #endif /* HAL_NAND_MODULE_ENABLED */
|
---|
1119 |
|
---|
1120 | /**
|
---|
1121 | * @}
|
---|
1122 | */
|
---|
1123 |
|
---|
1124 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
---|