[303] | 1 | /**
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| 2 | ******************************************************************************
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| 3 | * @file stm32f4xx_hal_eth.c
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| 4 | * @author MCD Application Team
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| 5 | * @version V1.4.1
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| 6 | * @date 09-October-2015
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| 7 | * @brief ETH HAL module driver.
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| 8 | * This file provides firmware functions to manage the following
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| 9 | * functionalities of the Ethernet (ETH) peripheral:
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| 10 | * + Initialization and de-initialization functions
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| 11 | * + IO operation functions
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| 12 | * + Peripheral Control functions
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| 13 | * + Peripheral State and Errors functions
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| 14 | *
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| 15 | @verbatim
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| 16 | ==============================================================================
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| 17 | ##### How to use this driver #####
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| 18 | ==============================================================================
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| 19 | [..]
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| 20 | (#)Declare a ETH_HandleTypeDef handle structure, for example:
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| 21 | ETH_HandleTypeDef heth;
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| 22 |
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| 23 | (#)Fill parameters of Init structure in heth handle
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| 24 |
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| 25 | (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
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| 26 |
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| 27 | (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
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| 28 | (##) Enable the Ethernet interface clock using
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| 29 | (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
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| 30 | (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
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| 31 | (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
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| 32 |
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| 33 | (##) Initialize the related GPIO clocks
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| 34 | (##) Configure Ethernet pin-out
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| 35 | (##) Configure Ethernet NVIC interrupt (IT mode)
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| 36 |
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| 37 | (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
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| 38 | (##) HAL_ETH_DMATxDescListInit(); for Transmission process
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| 39 | (##) HAL_ETH_DMARxDescListInit(); for Reception process
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| 40 |
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| 41 | (#)Enable MAC and DMA transmission and reception:
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| 42 | (##) HAL_ETH_Start();
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| 43 |
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| 44 | (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
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| 45 | the frame to MAC TX FIFO:
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| 46 | (##) HAL_ETH_TransmitFrame();
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| 47 |
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| 48 | (#)Poll for a received frame in ETH RX DMA Descriptors and get received
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| 49 | frame parameters
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| 50 | (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
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| 51 |
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| 52 | (#) Get a received frame when an ETH RX interrupt occurs:
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| 53 | (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
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| 54 |
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| 55 | (#) Communicate with external PHY device:
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| 56 | (##) Read a specific register from the PHY
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| 57 | HAL_ETH_ReadPHYRegister();
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| 58 | (##) Write data to a specific RHY register:
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| 59 | HAL_ETH_WritePHYRegister();
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| 60 |
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| 61 | (#) Configure the Ethernet MAC after ETH peripheral initialization
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| 62 | HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
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| 63 |
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| 64 | (#) Configure the Ethernet DMA after ETH peripheral initialization
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| 65 | HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
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| 66 |
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| 67 | -@- The PTP protocol and the DMA descriptors ring mode are not supported
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| 68 | in this driver
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| 69 |
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| 70 | @endverbatim
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| 71 | ******************************************************************************
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| 72 | * @attention
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| 73 | *
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| 74 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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| 75 | *
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| 76 | * Redistribution and use in source and binary forms, with or without modification,
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| 77 | * are permitted provided that the following conditions are met:
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| 78 | * 1. Redistributions of source code must retain the above copyright notice,
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| 79 | * this list of conditions and the following disclaimer.
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| 80 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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| 81 | * this list of conditions and the following disclaimer in the documentation
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| 82 | * and/or other materials provided with the distribution.
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| 83 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
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| 84 | * may be used to endorse or promote products derived from this software
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| 85 | * without specific prior written permission.
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| 86 | *
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| 87 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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| 88 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| 89 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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| 90 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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| 91 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 92 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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| 93 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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| 94 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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| 95 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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| 96 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 97 | *
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| 98 | ******************************************************************************
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| 99 | */
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| 100 |
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| 101 | /* Includes ------------------------------------------------------------------*/
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| 102 | #include "stm32f4xx_hal.h"
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| 103 |
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| 104 | /** @addtogroup STM32F4xx_HAL_Driver
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| 105 | * @{
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| 106 | */
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| 107 |
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| 108 | /** @defgroup ETH ETH
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| 109 | * @brief ETH HAL module driver
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| 110 | * @{
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| 111 | */
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| 112 |
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| 113 | #ifdef HAL_ETH_MODULE_ENABLED
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| 114 |
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| 115 | #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
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| 116 | defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
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| 117 |
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| 118 | /* Private typedef -----------------------------------------------------------*/
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| 119 | /* Private define ------------------------------------------------------------*/
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| 120 | /** @defgroup ETH_Private_Constants ETH Private Constants
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| 121 | * @{
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| 122 | */
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| 123 | #define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
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| 124 | #define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */
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| 125 |
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| 126 | /**
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| 127 | * @}
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| 128 | */
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| 129 | /* Private macro -------------------------------------------------------------*/
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| 130 | /* Private variables ---------------------------------------------------------*/
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| 131 | /* Private function prototypes -----------------------------------------------*/
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| 132 | /** @defgroup ETH_Private_Functions ETH Private Functions
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| 133 | * @{
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| 134 | */
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| 135 | static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
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| 136 | static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
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| 137 | static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
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| 138 | static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
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| 139 | static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
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| 140 | static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
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| 141 | static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
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| 142 | static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
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| 143 | static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
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| 144 | static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
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| 145 | static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
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| 146 |
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| 147 | /**
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| 148 | * @}
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| 149 | */
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| 150 | /* Private functions ---------------------------------------------------------*/
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| 151 |
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| 152 | /** @defgroup ETH_Exported_Functions ETH Exported Functions
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| 153 | * @{
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| 154 | */
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| 155 |
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| 156 | /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
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| 157 | * @brief Initialization and Configuration functions
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| 158 | *
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| 159 | @verbatim
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| 160 | ===============================================================================
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| 161 | ##### Initialization and de-initialization functions #####
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| 162 | ===============================================================================
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| 163 | [..] This section provides functions allowing to:
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| 164 | (+) Initialize and configure the Ethernet peripheral
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| 165 | (+) De-initialize the Ethernet peripheral
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| 166 |
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| 167 | @endverbatim
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| 168 | * @{
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| 169 | */
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| 170 |
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| 171 | /**
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| 172 | * @brief Initializes the Ethernet MAC and DMA according to default
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| 173 | * parameters.
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| 174 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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| 175 | * the configuration information for ETHERNET module
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| 176 | * @retval HAL status
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| 177 | */
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| 178 | HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
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| 179 | {
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| 180 | uint32_t tmpreg1 = 0, phyreg = 0;
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| 181 | uint32_t hclk = 60000000;
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| 182 | uint32_t tickstart = 0;
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| 183 | uint32_t err = ETH_SUCCESS;
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| 184 |
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| 185 | /* Check the ETH peripheral state */
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| 186 | if(heth == NULL)
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| 187 | {
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| 188 | return HAL_ERROR;
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| 189 | }
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| 190 |
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| 191 | /* Check parameters */
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| 192 | assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
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| 193 | assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
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| 194 | assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
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| 195 | assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
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| 196 |
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| 197 | if(heth->State == HAL_ETH_STATE_RESET)
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| 198 | {
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| 199 | /* Allocate lock resource and initialize it */
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| 200 | heth->Lock = HAL_UNLOCKED;
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| 201 | /* Init the low level hardware : GPIO, CLOCK, NVIC. */
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| 202 | HAL_ETH_MspInit(heth);
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| 203 | }
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| 204 |
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| 205 | /* Enable SYSCFG Clock */
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| 206 | __HAL_RCC_SYSCFG_CLK_ENABLE();
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| 207 |
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| 208 | /* Select MII or RMII Mode*/
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| 209 | SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
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| 210 | SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
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| 211 |
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| 212 | /* Ethernet Software reset */
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| 213 | /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
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| 214 | /* After reset all the registers holds their respective reset values */
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| 215 | (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
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| 216 |
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| 217 | /* Wait for software reset */
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| 218 | while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
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| 219 | {
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| 220 | }
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| 221 |
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| 222 | /*-------------------------------- MAC Initialization ----------------------*/
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| 223 | /* Get the ETHERNET MACMIIAR value */
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| 224 | tmpreg1 = (heth->Instance)->MACMIIAR;
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| 225 | /* Clear CSR Clock Range CR[2:0] bits */
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| 226 | tmpreg1 &= ETH_MACMIIAR_CR_MASK;
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| 227 |
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| 228 | /* Get hclk frequency value */
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| 229 | hclk = HAL_RCC_GetHCLKFreq();
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| 230 |
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| 231 | /* Set CR bits depending on hclk value */
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| 232 | if((hclk >= 20000000)&&(hclk < 35000000))
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| 233 | {
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| 234 | /* CSR Clock Range between 20-35 MHz */
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| 235 | tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16;
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| 236 | }
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| 237 | else if((hclk >= 35000000)&&(hclk < 60000000))
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| 238 | {
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| 239 | /* CSR Clock Range between 35-60 MHz */
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| 240 | tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26;
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| 241 | }
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| 242 | else if((hclk >= 60000000)&&(hclk < 100000000))
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| 243 | {
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| 244 | /* CSR Clock Range between 60-100 MHz */
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| 245 | tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42;
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| 246 | }
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| 247 | else if((hclk >= 100000000)&&(hclk < 150000000))
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| 248 | {
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| 249 | /* CSR Clock Range between 100-150 MHz */
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| 250 | tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
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| 251 | }
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| 252 | else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */
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| 253 | {
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| 254 | /* CSR Clock Range between 150-168 MHz */
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| 255 | tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102;
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| 256 | }
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| 257 |
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| 258 | /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
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| 259 | (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
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| 260 |
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| 261 | /*-------------------- PHY initialization and configuration ----------------*/
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| 262 | /* Put the PHY in reset mode */
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| 263 | if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
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| 264 | {
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| 265 | /* In case of write timeout */
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| 266 | err = ETH_ERROR;
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| 267 |
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| 268 | /* Config MAC and DMA */
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| 269 | ETH_MACDMAConfig(heth, err);
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| 270 |
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| 271 | /* Set the ETH peripheral state to READY */
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| 272 | heth->State = HAL_ETH_STATE_READY;
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| 273 |
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| 274 | /* Return HAL_ERROR */
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| 275 | return HAL_ERROR;
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| 276 | }
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| 277 |
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| 278 | /* Delay to assure PHY reset */
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| 279 | HAL_Delay(PHY_RESET_DELAY);
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| 280 |
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| 281 | if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
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| 282 | {
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| 283 | /* Get tick */
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| 284 | tickstart = HAL_GetTick();
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| 285 |
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| 286 | /* We wait for linked status */
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| 287 | do
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| 288 | {
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| 289 | HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
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| 290 |
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| 291 | /* Check for the Timeout */
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| 292 | if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
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| 293 | {
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| 294 | /* In case of write timeout */
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| 295 | err = ETH_ERROR;
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| 296 |
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| 297 | /* Config MAC and DMA */
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| 298 | ETH_MACDMAConfig(heth, err);
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| 299 |
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| 300 | heth->State= HAL_ETH_STATE_READY;
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| 301 |
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| 302 | /* Process Unlocked */
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| 303 | __HAL_UNLOCK(heth);
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| 304 |
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| 305 | return HAL_TIMEOUT;
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| 306 | }
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| 307 | } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
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| 308 |
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| 309 |
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| 310 | /* Enable Auto-Negotiation */
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| 311 | if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
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| 312 | {
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| 313 | /* In case of write timeout */
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| 314 | err = ETH_ERROR;
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| 315 |
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| 316 | /* Config MAC and DMA */
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| 317 | ETH_MACDMAConfig(heth, err);
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| 318 |
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| 319 | /* Set the ETH peripheral state to READY */
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| 320 | heth->State = HAL_ETH_STATE_READY;
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| 321 |
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| 322 | /* Return HAL_ERROR */
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| 323 | return HAL_ERROR;
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| 324 | }
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| 325 |
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| 326 | /* Get tick */
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| 327 | tickstart = HAL_GetTick();
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| 328 |
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| 329 | /* Wait until the auto-negotiation will be completed */
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| 330 | do
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| 331 | {
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| 332 | HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
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| 333 |
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| 334 | /* Check for the Timeout */
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| 335 | if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
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| 336 | {
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| 337 | /* In case of write timeout */
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| 338 | err = ETH_ERROR;
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| 339 |
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| 340 | /* Config MAC and DMA */
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| 341 | ETH_MACDMAConfig(heth, err);
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| 342 |
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| 343 | heth->State= HAL_ETH_STATE_READY;
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| 344 |
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| 345 | /* Process Unlocked */
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| 346 | __HAL_UNLOCK(heth);
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| 347 |
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| 348 | return HAL_TIMEOUT;
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| 349 | }
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| 350 |
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| 351 | } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
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| 352 |
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| 353 | /* Read the result of the auto-negotiation */
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| 354 | if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
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| 355 | {
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| 356 | /* In case of write timeout */
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| 357 | err = ETH_ERROR;
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| 358 |
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| 359 | /* Config MAC and DMA */
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| 360 | ETH_MACDMAConfig(heth, err);
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| 361 |
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| 362 | /* Set the ETH peripheral state to READY */
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| 363 | heth->State = HAL_ETH_STATE_READY;
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| 364 |
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| 365 | /* Return HAL_ERROR */
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| 366 | return HAL_ERROR;
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| 367 | }
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| 368 |
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| 369 | /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
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| 370 | if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
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| 371 | {
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| 372 | /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
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| 373 | (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
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| 374 | }
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| 375 | else
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| 376 | {
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| 377 | /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
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| 378 | (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
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| 379 | }
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| 380 | /* Configure the MAC with the speed fixed by the auto-negotiation process */
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| 381 | if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
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| 382 | {
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| 383 | /* Set Ethernet speed to 10M following the auto-negotiation */
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| 384 | (heth->Init).Speed = ETH_SPEED_10M;
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| 385 | }
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| 386 | else
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| 387 | {
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| 388 | /* Set Ethernet speed to 100M following the auto-negotiation */
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| 389 | (heth->Init).Speed = ETH_SPEED_100M;
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| 390 | }
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| 391 | }
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| 392 | else /* AutoNegotiation Disable */
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| 393 | {
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| 394 | /* Check parameters */
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| 395 | assert_param(IS_ETH_SPEED(heth->Init.Speed));
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| 396 | assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
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| 397 |
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| 398 | /* Set MAC Speed and Duplex Mode */
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| 399 | if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
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| 400 | (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
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| 401 | {
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| 402 | /* In case of write timeout */
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| 403 | err = ETH_ERROR;
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| 404 |
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| 405 | /* Config MAC and DMA */
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| 406 | ETH_MACDMAConfig(heth, err);
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| 407 |
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| 408 | /* Set the ETH peripheral state to READY */
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| 409 | heth->State = HAL_ETH_STATE_READY;
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| 410 |
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| 411 | /* Return HAL_ERROR */
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| 412 | return HAL_ERROR;
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| 413 | }
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| 414 |
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| 415 | /* Delay to assure PHY configuration */
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| 416 | HAL_Delay(PHY_CONFIG_DELAY);
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| 417 | }
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| 418 |
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| 419 | /* Config MAC and DMA */
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| 420 | ETH_MACDMAConfig(heth, err);
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| 421 |
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| 422 | /* Set ETH HAL State to Ready */
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| 423 | heth->State= HAL_ETH_STATE_READY;
|
---|
| 424 |
|
---|
| 425 | /* Return function status */
|
---|
| 426 | return HAL_OK;
|
---|
| 427 | }
|
---|
| 428 |
|
---|
| 429 | /**
|
---|
| 430 | * @brief De-Initializes the ETH peripheral.
|
---|
| 431 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 432 | * the configuration information for ETHERNET module
|
---|
| 433 | * @retval HAL status
|
---|
| 434 | */
|
---|
| 435 | HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
|
---|
| 436 | {
|
---|
| 437 | /* Set the ETH peripheral state to BUSY */
|
---|
| 438 | heth->State = HAL_ETH_STATE_BUSY;
|
---|
| 439 |
|
---|
| 440 | /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
|
---|
| 441 | HAL_ETH_MspDeInit(heth);
|
---|
| 442 |
|
---|
| 443 | /* Set ETH HAL state to Disabled */
|
---|
| 444 | heth->State= HAL_ETH_STATE_RESET;
|
---|
| 445 |
|
---|
| 446 | /* Release Lock */
|
---|
| 447 | __HAL_UNLOCK(heth);
|
---|
| 448 |
|
---|
| 449 | /* Return function status */
|
---|
| 450 | return HAL_OK;
|
---|
| 451 | }
|
---|
| 452 |
|
---|
| 453 | /**
|
---|
| 454 | * @brief Initializes the DMA Tx descriptors in chain mode.
|
---|
| 455 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 456 | * the configuration information for ETHERNET module
|
---|
| 457 | * @param DMATxDescTab: Pointer to the first Tx desc list
|
---|
| 458 | * @param TxBuff: Pointer to the first TxBuffer list
|
---|
| 459 | * @param TxBuffCount: Number of the used Tx desc in the list
|
---|
| 460 | * @retval HAL status
|
---|
| 461 | */
|
---|
| 462 | HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
|
---|
| 463 | {
|
---|
| 464 | uint32_t i = 0;
|
---|
| 465 | ETH_DMADescTypeDef *dmatxdesc;
|
---|
| 466 |
|
---|
| 467 | /* Process Locked */
|
---|
| 468 | __HAL_LOCK(heth);
|
---|
| 469 |
|
---|
| 470 | /* Set the ETH peripheral state to BUSY */
|
---|
| 471 | heth->State = HAL_ETH_STATE_BUSY;
|
---|
| 472 |
|
---|
| 473 | /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
|
---|
| 474 | heth->TxDesc = DMATxDescTab;
|
---|
| 475 |
|
---|
| 476 | /* Fill each DMATxDesc descriptor with the right values */
|
---|
| 477 | for(i=0; i < TxBuffCount; i++)
|
---|
| 478 | {
|
---|
| 479 | /* Get the pointer on the ith member of the Tx Desc list */
|
---|
| 480 | dmatxdesc = DMATxDescTab + i;
|
---|
| 481 |
|
---|
| 482 | /* Set Second Address Chained bit */
|
---|
| 483 | dmatxdesc->Status = ETH_DMATXDESC_TCH;
|
---|
| 484 |
|
---|
| 485 | /* Set Buffer1 address pointer */
|
---|
| 486 | dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
|
---|
| 487 |
|
---|
| 488 | if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
|
---|
| 489 | {
|
---|
| 490 | /* Set the DMA Tx descriptors checksum insertion */
|
---|
| 491 | dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
|
---|
| 492 | }
|
---|
| 493 |
|
---|
| 494 | /* Initialize the next descriptor with the Next Descriptor Polling Enable */
|
---|
| 495 | if(i < (TxBuffCount-1))
|
---|
| 496 | {
|
---|
| 497 | /* Set next descriptor address register with next descriptor base address */
|
---|
| 498 | dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
|
---|
| 499 | }
|
---|
| 500 | else
|
---|
| 501 | {
|
---|
| 502 | /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
|
---|
| 503 | dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
|
---|
| 504 | }
|
---|
| 505 | }
|
---|
| 506 |
|
---|
| 507 | /* Set Transmit Descriptor List Address Register */
|
---|
| 508 | (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
|
---|
| 509 |
|
---|
| 510 | /* Set ETH HAL State to Ready */
|
---|
| 511 | heth->State= HAL_ETH_STATE_READY;
|
---|
| 512 |
|
---|
| 513 | /* Process Unlocked */
|
---|
| 514 | __HAL_UNLOCK(heth);
|
---|
| 515 |
|
---|
| 516 | /* Return function status */
|
---|
| 517 | return HAL_OK;
|
---|
| 518 | }
|
---|
| 519 |
|
---|
| 520 | /**
|
---|
| 521 | * @brief Initializes the DMA Rx descriptors in chain mode.
|
---|
| 522 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 523 | * the configuration information for ETHERNET module
|
---|
| 524 | * @param DMARxDescTab: Pointer to the first Rx desc list
|
---|
| 525 | * @param RxBuff: Pointer to the first RxBuffer list
|
---|
| 526 | * @param RxBuffCount: Number of the used Rx desc in the list
|
---|
| 527 | * @retval HAL status
|
---|
| 528 | */
|
---|
| 529 | HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
|
---|
| 530 | {
|
---|
| 531 | uint32_t i = 0;
|
---|
| 532 | ETH_DMADescTypeDef *DMARxDesc;
|
---|
| 533 |
|
---|
| 534 | /* Process Locked */
|
---|
| 535 | __HAL_LOCK(heth);
|
---|
| 536 |
|
---|
| 537 | /* Set the ETH peripheral state to BUSY */
|
---|
| 538 | heth->State = HAL_ETH_STATE_BUSY;
|
---|
| 539 |
|
---|
| 540 | /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
|
---|
| 541 | heth->RxDesc = DMARxDescTab;
|
---|
| 542 |
|
---|
| 543 | /* Fill each DMARxDesc descriptor with the right values */
|
---|
| 544 | for(i=0; i < RxBuffCount; i++)
|
---|
| 545 | {
|
---|
| 546 | /* Get the pointer on the ith member of the Rx Desc list */
|
---|
| 547 | DMARxDesc = DMARxDescTab+i;
|
---|
| 548 |
|
---|
| 549 | /* Set Own bit of the Rx descriptor Status */
|
---|
| 550 | DMARxDesc->Status = ETH_DMARXDESC_OWN;
|
---|
| 551 |
|
---|
| 552 | /* Set Buffer1 size and Second Address Chained bit */
|
---|
| 553 | DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
|
---|
| 554 |
|
---|
| 555 | /* Set Buffer1 address pointer */
|
---|
| 556 | DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
|
---|
| 557 |
|
---|
| 558 | if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
|
---|
| 559 | {
|
---|
| 560 | /* Enable Ethernet DMA Rx Descriptor interrupt */
|
---|
| 561 | DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
|
---|
| 562 | }
|
---|
| 563 |
|
---|
| 564 | /* Initialize the next descriptor with the Next Descriptor Polling Enable */
|
---|
| 565 | if(i < (RxBuffCount-1))
|
---|
| 566 | {
|
---|
| 567 | /* Set next descriptor address register with next descriptor base address */
|
---|
| 568 | DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
|
---|
| 569 | }
|
---|
| 570 | else
|
---|
| 571 | {
|
---|
| 572 | /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
|
---|
| 573 | DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
|
---|
| 574 | }
|
---|
| 575 | }
|
---|
| 576 |
|
---|
| 577 | /* Set Receive Descriptor List Address Register */
|
---|
| 578 | (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
|
---|
| 579 |
|
---|
| 580 | /* Set ETH HAL State to Ready */
|
---|
| 581 | heth->State= HAL_ETH_STATE_READY;
|
---|
| 582 |
|
---|
| 583 | /* Process Unlocked */
|
---|
| 584 | __HAL_UNLOCK(heth);
|
---|
| 585 |
|
---|
| 586 | /* Return function status */
|
---|
| 587 | return HAL_OK;
|
---|
| 588 | }
|
---|
| 589 |
|
---|
| 590 | /**
|
---|
| 591 | * @brief Initializes the ETH MSP.
|
---|
| 592 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 593 | * the configuration information for ETHERNET module
|
---|
| 594 | * @retval None
|
---|
| 595 | */
|
---|
| 596 | __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
|
---|
| 597 | {
|
---|
| 598 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
| 599 | the HAL_ETH_MspInit could be implemented in the user file
|
---|
| 600 | */
|
---|
| 601 | }
|
---|
| 602 |
|
---|
| 603 | /**
|
---|
| 604 | * @brief DeInitializes ETH MSP.
|
---|
| 605 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 606 | * the configuration information for ETHERNET module
|
---|
| 607 | * @retval None
|
---|
| 608 | */
|
---|
| 609 | __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
|
---|
| 610 | {
|
---|
| 611 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
| 612 | the HAL_ETH_MspDeInit could be implemented in the user file
|
---|
| 613 | */
|
---|
| 614 | }
|
---|
| 615 |
|
---|
| 616 | /**
|
---|
| 617 | * @}
|
---|
| 618 | */
|
---|
| 619 |
|
---|
| 620 | /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
|
---|
| 621 | * @brief Data transfers functions
|
---|
| 622 | *
|
---|
| 623 | @verbatim
|
---|
| 624 | ==============================================================================
|
---|
| 625 | ##### IO operation functions #####
|
---|
| 626 | ==============================================================================
|
---|
| 627 | [..] This section provides functions allowing to:
|
---|
| 628 | (+) Transmit a frame
|
---|
| 629 | HAL_ETH_TransmitFrame();
|
---|
| 630 | (+) Receive a frame
|
---|
| 631 | HAL_ETH_GetReceivedFrame();
|
---|
| 632 | HAL_ETH_GetReceivedFrame_IT();
|
---|
| 633 | (+) Read from an External PHY register
|
---|
| 634 | HAL_ETH_ReadPHYRegister();
|
---|
| 635 | (+) Write to an External PHY register
|
---|
| 636 | HAL_ETH_WritePHYRegister();
|
---|
| 637 |
|
---|
| 638 | @endverbatim
|
---|
| 639 |
|
---|
| 640 | * @{
|
---|
| 641 | */
|
---|
| 642 |
|
---|
| 643 | /**
|
---|
| 644 | * @brief Sends an Ethernet frame.
|
---|
| 645 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 646 | * the configuration information for ETHERNET module
|
---|
| 647 | * @param FrameLength: Amount of data to be sent
|
---|
| 648 | * @retval HAL status
|
---|
| 649 | */
|
---|
| 650 | HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
|
---|
| 651 | {
|
---|
| 652 | uint32_t bufcount = 0, size = 0, i = 0;
|
---|
| 653 |
|
---|
| 654 | /* Process Locked */
|
---|
| 655 | __HAL_LOCK(heth);
|
---|
| 656 |
|
---|
| 657 | /* Set the ETH peripheral state to BUSY */
|
---|
| 658 | heth->State = HAL_ETH_STATE_BUSY;
|
---|
| 659 |
|
---|
| 660 | if (FrameLength == 0)
|
---|
| 661 | {
|
---|
| 662 | /* Set ETH HAL state to READY */
|
---|
| 663 | heth->State = HAL_ETH_STATE_READY;
|
---|
| 664 |
|
---|
| 665 | /* Process Unlocked */
|
---|
| 666 | __HAL_UNLOCK(heth);
|
---|
| 667 |
|
---|
| 668 | return HAL_ERROR;
|
---|
| 669 | }
|
---|
| 670 |
|
---|
| 671 | /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
|
---|
| 672 | if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
|
---|
| 673 | {
|
---|
| 674 | /* OWN bit set */
|
---|
| 675 | heth->State = HAL_ETH_STATE_BUSY_TX;
|
---|
| 676 |
|
---|
| 677 | /* Process Unlocked */
|
---|
| 678 | __HAL_UNLOCK(heth);
|
---|
| 679 |
|
---|
| 680 | return HAL_ERROR;
|
---|
| 681 | }
|
---|
| 682 |
|
---|
| 683 | /* Get the number of needed Tx buffers for the current frame */
|
---|
| 684 | if (FrameLength > ETH_TX_BUF_SIZE)
|
---|
| 685 | {
|
---|
| 686 | bufcount = FrameLength/ETH_TX_BUF_SIZE;
|
---|
| 687 | if (FrameLength % ETH_TX_BUF_SIZE)
|
---|
| 688 | {
|
---|
| 689 | bufcount++;
|
---|
| 690 | }
|
---|
| 691 | }
|
---|
| 692 | else
|
---|
| 693 | {
|
---|
| 694 | bufcount = 1;
|
---|
| 695 | }
|
---|
| 696 | if (bufcount == 1)
|
---|
| 697 | {
|
---|
| 698 | /* Set LAST and FIRST segment */
|
---|
| 699 | heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
|
---|
| 700 | /* Set frame size */
|
---|
| 701 | heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
|
---|
| 702 | /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
|
---|
| 703 | heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
|
---|
| 704 | /* Point to next descriptor */
|
---|
| 705 | heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
|
---|
| 706 | }
|
---|
| 707 | else
|
---|
| 708 | {
|
---|
| 709 | for (i=0; i< bufcount; i++)
|
---|
| 710 | {
|
---|
| 711 | /* Clear FIRST and LAST segment bits */
|
---|
| 712 | heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
|
---|
| 713 |
|
---|
| 714 | if (i == 0)
|
---|
| 715 | {
|
---|
| 716 | /* Setting the first segment bit */
|
---|
| 717 | heth->TxDesc->Status |= ETH_DMATXDESC_FS;
|
---|
| 718 | }
|
---|
| 719 |
|
---|
| 720 | /* Program size */
|
---|
| 721 | heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
|
---|
| 722 |
|
---|
| 723 | if (i == (bufcount-1))
|
---|
| 724 | {
|
---|
| 725 | /* Setting the last segment bit */
|
---|
| 726 | heth->TxDesc->Status |= ETH_DMATXDESC_LS;
|
---|
| 727 | size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
|
---|
| 728 | heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
|
---|
| 729 | }
|
---|
| 730 |
|
---|
| 731 | /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
|
---|
| 732 | heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
|
---|
| 733 | /* point to next descriptor */
|
---|
| 734 | heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
|
---|
| 735 | }
|
---|
| 736 | }
|
---|
| 737 |
|
---|
| 738 | /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
|
---|
| 739 | if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
|
---|
| 740 | {
|
---|
| 741 | /* Clear TBUS ETHERNET DMA flag */
|
---|
| 742 | (heth->Instance)->DMASR = ETH_DMASR_TBUS;
|
---|
| 743 | /* Resume DMA transmission*/
|
---|
| 744 | (heth->Instance)->DMATPDR = 0;
|
---|
| 745 | }
|
---|
| 746 |
|
---|
| 747 | /* Set ETH HAL State to Ready */
|
---|
| 748 | heth->State = HAL_ETH_STATE_READY;
|
---|
| 749 |
|
---|
| 750 | /* Process Unlocked */
|
---|
| 751 | __HAL_UNLOCK(heth);
|
---|
| 752 |
|
---|
| 753 | /* Return function status */
|
---|
| 754 | return HAL_OK;
|
---|
| 755 | }
|
---|
| 756 |
|
---|
| 757 | /**
|
---|
| 758 | * @brief Checks for received frames.
|
---|
| 759 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 760 | * the configuration information for ETHERNET module
|
---|
| 761 | * @retval HAL status
|
---|
| 762 | */
|
---|
| 763 | HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
|
---|
| 764 | {
|
---|
| 765 | uint32_t framelength = 0;
|
---|
| 766 |
|
---|
| 767 | /* Process Locked */
|
---|
| 768 | __HAL_LOCK(heth);
|
---|
| 769 |
|
---|
| 770 | /* Check the ETH state to BUSY */
|
---|
| 771 | heth->State = HAL_ETH_STATE_BUSY;
|
---|
| 772 |
|
---|
| 773 | /* Check if segment is not owned by DMA */
|
---|
| 774 | /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
|
---|
| 775 | if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
|
---|
| 776 | {
|
---|
| 777 | /* Check if last segment */
|
---|
| 778 | if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
|
---|
| 779 | {
|
---|
| 780 | /* increment segment count */
|
---|
| 781 | (heth->RxFrameInfos).SegCount++;
|
---|
| 782 |
|
---|
| 783 | /* Check if last segment is first segment: one segment contains the frame */
|
---|
| 784 | if ((heth->RxFrameInfos).SegCount == 1)
|
---|
| 785 | {
|
---|
| 786 | (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
|
---|
| 787 | }
|
---|
| 788 |
|
---|
| 789 | heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
|
---|
| 790 |
|
---|
| 791 | /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
|
---|
| 792 | framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
|
---|
| 793 | heth->RxFrameInfos.length = framelength;
|
---|
| 794 |
|
---|
| 795 | /* Get the address of the buffer start address */
|
---|
| 796 | heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
|
---|
| 797 | /* point to next descriptor */
|
---|
| 798 | heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
|
---|
| 799 |
|
---|
| 800 | /* Set HAL State to Ready */
|
---|
| 801 | heth->State = HAL_ETH_STATE_READY;
|
---|
| 802 |
|
---|
| 803 | /* Process Unlocked */
|
---|
| 804 | __HAL_UNLOCK(heth);
|
---|
| 805 |
|
---|
| 806 | /* Return function status */
|
---|
| 807 | return HAL_OK;
|
---|
| 808 | }
|
---|
| 809 | /* Check if first segment */
|
---|
| 810 | else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
|
---|
| 811 | {
|
---|
| 812 | (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
|
---|
| 813 | (heth->RxFrameInfos).LSRxDesc = NULL;
|
---|
| 814 | (heth->RxFrameInfos).SegCount = 1;
|
---|
| 815 | /* Point to next descriptor */
|
---|
| 816 | heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
|
---|
| 817 | }
|
---|
| 818 | /* Check if intermediate segment */
|
---|
| 819 | else
|
---|
| 820 | {
|
---|
| 821 | (heth->RxFrameInfos).SegCount++;
|
---|
| 822 | /* Point to next descriptor */
|
---|
| 823 | heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
|
---|
| 824 | }
|
---|
| 825 | }
|
---|
| 826 |
|
---|
| 827 | /* Set ETH HAL State to Ready */
|
---|
| 828 | heth->State = HAL_ETH_STATE_READY;
|
---|
| 829 |
|
---|
| 830 | /* Process Unlocked */
|
---|
| 831 | __HAL_UNLOCK(heth);
|
---|
| 832 |
|
---|
| 833 | /* Return function status */
|
---|
| 834 | return HAL_ERROR;
|
---|
| 835 | }
|
---|
| 836 |
|
---|
| 837 | /**
|
---|
| 838 | * @brief Gets the Received frame in interrupt mode.
|
---|
| 839 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 840 | * the configuration information for ETHERNET module
|
---|
| 841 | * @retval HAL status
|
---|
| 842 | */
|
---|
| 843 | HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
|
---|
| 844 | {
|
---|
| 845 | uint32_t descriptorscancounter = 0;
|
---|
| 846 |
|
---|
| 847 | /* Process Locked */
|
---|
| 848 | __HAL_LOCK(heth);
|
---|
| 849 |
|
---|
| 850 | /* Set ETH HAL State to BUSY */
|
---|
| 851 | heth->State = HAL_ETH_STATE_BUSY;
|
---|
| 852 |
|
---|
| 853 | /* Scan descriptors owned by CPU */
|
---|
| 854 | while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
|
---|
| 855 | {
|
---|
| 856 | /* Just for security */
|
---|
| 857 | descriptorscancounter++;
|
---|
| 858 |
|
---|
| 859 | /* Check if first segment in frame */
|
---|
| 860 | /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
|
---|
| 861 | if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
|
---|
| 862 | {
|
---|
| 863 | heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
|
---|
| 864 | heth->RxFrameInfos.SegCount = 1;
|
---|
| 865 | /* Point to next descriptor */
|
---|
| 866 | heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
|
---|
| 867 | }
|
---|
| 868 | /* Check if intermediate segment */
|
---|
| 869 | /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
|
---|
| 870 | else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
|
---|
| 871 | {
|
---|
| 872 | /* Increment segment count */
|
---|
| 873 | (heth->RxFrameInfos.SegCount)++;
|
---|
| 874 | /* Point to next descriptor */
|
---|
| 875 | heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
|
---|
| 876 | }
|
---|
| 877 | /* Should be last segment */
|
---|
| 878 | else
|
---|
| 879 | {
|
---|
| 880 | /* Last segment */
|
---|
| 881 | heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
|
---|
| 882 |
|
---|
| 883 | /* Increment segment count */
|
---|
| 884 | (heth->RxFrameInfos.SegCount)++;
|
---|
| 885 |
|
---|
| 886 | /* Check if last segment is first segment: one segment contains the frame */
|
---|
| 887 | if ((heth->RxFrameInfos.SegCount) == 1)
|
---|
| 888 | {
|
---|
| 889 | heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
|
---|
| 890 | }
|
---|
| 891 |
|
---|
| 892 | /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
|
---|
| 893 | heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
|
---|
| 894 |
|
---|
| 895 | /* Get the address of the buffer start address */
|
---|
| 896 | heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
|
---|
| 897 |
|
---|
| 898 | /* Point to next descriptor */
|
---|
| 899 | heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
|
---|
| 900 |
|
---|
| 901 | /* Set HAL State to Ready */
|
---|
| 902 | heth->State = HAL_ETH_STATE_READY;
|
---|
| 903 |
|
---|
| 904 | /* Process Unlocked */
|
---|
| 905 | __HAL_UNLOCK(heth);
|
---|
| 906 |
|
---|
| 907 | /* Return function status */
|
---|
| 908 | return HAL_OK;
|
---|
| 909 | }
|
---|
| 910 | }
|
---|
| 911 |
|
---|
| 912 | /* Set HAL State to Ready */
|
---|
| 913 | heth->State = HAL_ETH_STATE_READY;
|
---|
| 914 |
|
---|
| 915 | /* Process Unlocked */
|
---|
| 916 | __HAL_UNLOCK(heth);
|
---|
| 917 |
|
---|
| 918 | /* Return function status */
|
---|
| 919 | return HAL_ERROR;
|
---|
| 920 | }
|
---|
| 921 |
|
---|
| 922 | /**
|
---|
| 923 | * @brief This function handles ETH interrupt request.
|
---|
| 924 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 925 | * the configuration information for ETHERNET module
|
---|
| 926 | * @retval HAL status
|
---|
| 927 | */
|
---|
| 928 | void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
|
---|
| 929 | {
|
---|
| 930 | /* Frame received */
|
---|
| 931 | if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
|
---|
| 932 | {
|
---|
| 933 | /* Receive complete callback */
|
---|
| 934 | HAL_ETH_RxCpltCallback(heth);
|
---|
| 935 |
|
---|
| 936 | /* Clear the Eth DMA Rx IT pending bits */
|
---|
| 937 | __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
|
---|
| 938 |
|
---|
| 939 | /* Set HAL State to Ready */
|
---|
| 940 | heth->State = HAL_ETH_STATE_READY;
|
---|
| 941 |
|
---|
| 942 | /* Process Unlocked */
|
---|
| 943 | __HAL_UNLOCK(heth);
|
---|
| 944 |
|
---|
| 945 | }
|
---|
| 946 | /* Frame transmitted */
|
---|
| 947 | else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
|
---|
| 948 | {
|
---|
| 949 | /* Transfer complete callback */
|
---|
| 950 | HAL_ETH_TxCpltCallback(heth);
|
---|
| 951 |
|
---|
| 952 | /* Clear the Eth DMA Tx IT pending bits */
|
---|
| 953 | __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
|
---|
| 954 |
|
---|
| 955 | /* Set HAL State to Ready */
|
---|
| 956 | heth->State = HAL_ETH_STATE_READY;
|
---|
| 957 |
|
---|
| 958 | /* Process Unlocked */
|
---|
| 959 | __HAL_UNLOCK(heth);
|
---|
| 960 | }
|
---|
| 961 |
|
---|
| 962 | /* Clear the interrupt flags */
|
---|
| 963 | __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
|
---|
| 964 |
|
---|
| 965 | /* ETH DMA Error */
|
---|
| 966 | if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
|
---|
| 967 | {
|
---|
| 968 | /* Ethernet Error callback */
|
---|
| 969 | HAL_ETH_ErrorCallback(heth);
|
---|
| 970 |
|
---|
| 971 | /* Clear the interrupt flags */
|
---|
| 972 | __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
|
---|
| 973 |
|
---|
| 974 | /* Set HAL State to Ready */
|
---|
| 975 | heth->State = HAL_ETH_STATE_READY;
|
---|
| 976 |
|
---|
| 977 | /* Process Unlocked */
|
---|
| 978 | __HAL_UNLOCK(heth);
|
---|
| 979 | }
|
---|
| 980 | }
|
---|
| 981 |
|
---|
| 982 | /**
|
---|
| 983 | * @brief Tx Transfer completed callbacks.
|
---|
| 984 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 985 | * the configuration information for ETHERNET module
|
---|
| 986 | * @retval None
|
---|
| 987 | */
|
---|
| 988 | __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
|
---|
| 989 | {
|
---|
| 990 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
| 991 | the HAL_ETH_TxCpltCallback could be implemented in the user file
|
---|
| 992 | */
|
---|
| 993 | }
|
---|
| 994 |
|
---|
| 995 | /**
|
---|
| 996 | * @brief Rx Transfer completed callbacks.
|
---|
| 997 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 998 | * the configuration information for ETHERNET module
|
---|
| 999 | * @retval None
|
---|
| 1000 | */
|
---|
| 1001 | __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
|
---|
| 1002 | {
|
---|
| 1003 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
| 1004 | the HAL_ETH_TxCpltCallback could be implemented in the user file
|
---|
| 1005 | */
|
---|
| 1006 | }
|
---|
| 1007 |
|
---|
| 1008 | /**
|
---|
| 1009 | * @brief Ethernet transfer error callbacks
|
---|
| 1010 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 1011 | * the configuration information for ETHERNET module
|
---|
| 1012 | * @retval None
|
---|
| 1013 | */
|
---|
| 1014 | __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
|
---|
| 1015 | {
|
---|
| 1016 | /* NOTE : This function Should not be modified, when the callback is needed,
|
---|
| 1017 | the HAL_ETH_TxCpltCallback could be implemented in the user file
|
---|
| 1018 | */
|
---|
| 1019 | }
|
---|
| 1020 |
|
---|
| 1021 | /**
|
---|
| 1022 | * @brief Reads a PHY register
|
---|
| 1023 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 1024 | * the configuration information for ETHERNET module
|
---|
| 1025 | * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
|
---|
| 1026 | * This parameter can be one of the following values:
|
---|
| 1027 | * PHY_BCR: Transceiver Basic Control Register,
|
---|
| 1028 | * PHY_BSR: Transceiver Basic Status Register.
|
---|
| 1029 | * More PHY register could be read depending on the used PHY
|
---|
| 1030 | * @param RegValue: PHY register value
|
---|
| 1031 | * @retval HAL status
|
---|
| 1032 | */
|
---|
| 1033 | HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
|
---|
| 1034 | {
|
---|
| 1035 | uint32_t tmpreg1 = 0;
|
---|
| 1036 | uint32_t tickstart = 0;
|
---|
| 1037 |
|
---|
| 1038 | /* Check parameters */
|
---|
| 1039 | assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
|
---|
| 1040 |
|
---|
| 1041 | /* Check the ETH peripheral state */
|
---|
| 1042 | if(heth->State == HAL_ETH_STATE_BUSY_RD)
|
---|
| 1043 | {
|
---|
| 1044 | return HAL_BUSY;
|
---|
| 1045 | }
|
---|
| 1046 | /* Set ETH HAL State to BUSY_RD */
|
---|
| 1047 | heth->State = HAL_ETH_STATE_BUSY_RD;
|
---|
| 1048 |
|
---|
| 1049 | /* Get the ETHERNET MACMIIAR value */
|
---|
| 1050 | tmpreg1 = heth->Instance->MACMIIAR;
|
---|
| 1051 |
|
---|
| 1052 | /* Keep only the CSR Clock Range CR[2:0] bits value */
|
---|
| 1053 | tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
|
---|
| 1054 |
|
---|
| 1055 | /* Prepare the MII address register value */
|
---|
| 1056 | tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
|
---|
| 1057 | tmpreg1 |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
|
---|
| 1058 | tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
|
---|
| 1059 | tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
|
---|
| 1060 |
|
---|
| 1061 | /* Write the result value into the MII Address register */
|
---|
| 1062 | heth->Instance->MACMIIAR = tmpreg1;
|
---|
| 1063 |
|
---|
| 1064 | /* Get tick */
|
---|
| 1065 | tickstart = HAL_GetTick();
|
---|
| 1066 |
|
---|
| 1067 | /* Check for the Busy flag */
|
---|
| 1068 | while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
|
---|
| 1069 | {
|
---|
| 1070 | /* Check for the Timeout */
|
---|
| 1071 | if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
|
---|
| 1072 | {
|
---|
| 1073 | heth->State= HAL_ETH_STATE_READY;
|
---|
| 1074 |
|
---|
| 1075 | /* Process Unlocked */
|
---|
| 1076 | __HAL_UNLOCK(heth);
|
---|
| 1077 |
|
---|
| 1078 | return HAL_TIMEOUT;
|
---|
| 1079 | }
|
---|
| 1080 |
|
---|
| 1081 | tmpreg1 = heth->Instance->MACMIIAR;
|
---|
| 1082 | }
|
---|
| 1083 |
|
---|
| 1084 | /* Get MACMIIDR value */
|
---|
| 1085 | *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
|
---|
| 1086 |
|
---|
| 1087 | /* Set ETH HAL State to READY */
|
---|
| 1088 | heth->State = HAL_ETH_STATE_READY;
|
---|
| 1089 |
|
---|
| 1090 | /* Return function status */
|
---|
| 1091 | return HAL_OK;
|
---|
| 1092 | }
|
---|
| 1093 |
|
---|
| 1094 | /**
|
---|
| 1095 | * @brief Writes to a PHY register.
|
---|
| 1096 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 1097 | * the configuration information for ETHERNET module
|
---|
| 1098 | * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
|
---|
| 1099 | * This parameter can be one of the following values:
|
---|
| 1100 | * PHY_BCR: Transceiver Control Register.
|
---|
| 1101 | * More PHY register could be written depending on the used PHY
|
---|
| 1102 | * @param RegValue: the value to write
|
---|
| 1103 | * @retval HAL status
|
---|
| 1104 | */
|
---|
| 1105 | HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
|
---|
| 1106 | {
|
---|
| 1107 | uint32_t tmpreg1 = 0;
|
---|
| 1108 | uint32_t tickstart = 0;
|
---|
| 1109 |
|
---|
| 1110 | /* Check parameters */
|
---|
| 1111 | assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
|
---|
| 1112 |
|
---|
| 1113 | /* Check the ETH peripheral state */
|
---|
| 1114 | if(heth->State == HAL_ETH_STATE_BUSY_WR)
|
---|
| 1115 | {
|
---|
| 1116 | return HAL_BUSY;
|
---|
| 1117 | }
|
---|
| 1118 | /* Set ETH HAL State to BUSY_WR */
|
---|
| 1119 | heth->State = HAL_ETH_STATE_BUSY_WR;
|
---|
| 1120 |
|
---|
| 1121 | /* Get the ETHERNET MACMIIAR value */
|
---|
| 1122 | tmpreg1 = heth->Instance->MACMIIAR;
|
---|
| 1123 |
|
---|
| 1124 | /* Keep only the CSR Clock Range CR[2:0] bits value */
|
---|
| 1125 | tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
|
---|
| 1126 |
|
---|
| 1127 | /* Prepare the MII register address value */
|
---|
| 1128 | tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
|
---|
| 1129 | tmpreg1 |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
|
---|
| 1130 | tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
|
---|
| 1131 | tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
|
---|
| 1132 |
|
---|
| 1133 | /* Give the value to the MII data register */
|
---|
| 1134 | heth->Instance->MACMIIDR = (uint16_t)RegValue;
|
---|
| 1135 |
|
---|
| 1136 | /* Write the result value into the MII Address register */
|
---|
| 1137 | heth->Instance->MACMIIAR = tmpreg1;
|
---|
| 1138 |
|
---|
| 1139 | /* Get tick */
|
---|
| 1140 | tickstart = HAL_GetTick();
|
---|
| 1141 |
|
---|
| 1142 | /* Check for the Busy flag */
|
---|
| 1143 | while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
|
---|
| 1144 | {
|
---|
| 1145 | /* Check for the Timeout */
|
---|
| 1146 | if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
|
---|
| 1147 | {
|
---|
| 1148 | heth->State= HAL_ETH_STATE_READY;
|
---|
| 1149 |
|
---|
| 1150 | /* Process Unlocked */
|
---|
| 1151 | __HAL_UNLOCK(heth);
|
---|
| 1152 |
|
---|
| 1153 | return HAL_TIMEOUT;
|
---|
| 1154 | }
|
---|
| 1155 |
|
---|
| 1156 | tmpreg1 = heth->Instance->MACMIIAR;
|
---|
| 1157 | }
|
---|
| 1158 |
|
---|
| 1159 | /* Set ETH HAL State to READY */
|
---|
| 1160 | heth->State = HAL_ETH_STATE_READY;
|
---|
| 1161 |
|
---|
| 1162 | /* Return function status */
|
---|
| 1163 | return HAL_OK;
|
---|
| 1164 | }
|
---|
| 1165 |
|
---|
| 1166 | /**
|
---|
| 1167 | * @}
|
---|
| 1168 | */
|
---|
| 1169 |
|
---|
| 1170 | /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
|
---|
| 1171 | * @brief Peripheral Control functions
|
---|
| 1172 | *
|
---|
| 1173 | @verbatim
|
---|
| 1174 | ===============================================================================
|
---|
| 1175 | ##### Peripheral Control functions #####
|
---|
| 1176 | ===============================================================================
|
---|
| 1177 | [..] This section provides functions allowing to:
|
---|
| 1178 | (+) Enable MAC and DMA transmission and reception.
|
---|
| 1179 | HAL_ETH_Start();
|
---|
| 1180 | (+) Disable MAC and DMA transmission and reception.
|
---|
| 1181 | HAL_ETH_Stop();
|
---|
| 1182 | (+) Set the MAC configuration in runtime mode
|
---|
| 1183 | HAL_ETH_ConfigMAC();
|
---|
| 1184 | (+) Set the DMA configuration in runtime mode
|
---|
| 1185 | HAL_ETH_ConfigDMA();
|
---|
| 1186 |
|
---|
| 1187 | @endverbatim
|
---|
| 1188 | * @{
|
---|
| 1189 | */
|
---|
| 1190 |
|
---|
| 1191 | /**
|
---|
| 1192 | * @brief Enables Ethernet MAC and DMA reception/transmission
|
---|
| 1193 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 1194 | * the configuration information for ETHERNET module
|
---|
| 1195 | * @retval HAL status
|
---|
| 1196 | */
|
---|
| 1197 | HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
|
---|
| 1198 | {
|
---|
| 1199 | /* Process Locked */
|
---|
| 1200 | __HAL_LOCK(heth);
|
---|
| 1201 |
|
---|
| 1202 | /* Set the ETH peripheral state to BUSY */
|
---|
| 1203 | heth->State = HAL_ETH_STATE_BUSY;
|
---|
| 1204 |
|
---|
| 1205 | /* Enable transmit state machine of the MAC for transmission on the MII */
|
---|
| 1206 | ETH_MACTransmissionEnable(heth);
|
---|
| 1207 |
|
---|
| 1208 | /* Enable receive state machine of the MAC for reception from the MII */
|
---|
| 1209 | ETH_MACReceptionEnable(heth);
|
---|
| 1210 |
|
---|
| 1211 | /* Flush Transmit FIFO */
|
---|
| 1212 | ETH_FlushTransmitFIFO(heth);
|
---|
| 1213 |
|
---|
| 1214 | /* Start DMA transmission */
|
---|
| 1215 | ETH_DMATransmissionEnable(heth);
|
---|
| 1216 |
|
---|
| 1217 | /* Start DMA reception */
|
---|
| 1218 | ETH_DMAReceptionEnable(heth);
|
---|
| 1219 |
|
---|
| 1220 | /* Set the ETH state to READY*/
|
---|
| 1221 | heth->State= HAL_ETH_STATE_READY;
|
---|
| 1222 |
|
---|
| 1223 | /* Process Unlocked */
|
---|
| 1224 | __HAL_UNLOCK(heth);
|
---|
| 1225 |
|
---|
| 1226 | /* Return function status */
|
---|
| 1227 | return HAL_OK;
|
---|
| 1228 | }
|
---|
| 1229 |
|
---|
| 1230 | /**
|
---|
| 1231 | * @brief Stop Ethernet MAC and DMA reception/transmission
|
---|
| 1232 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 1233 | * the configuration information for ETHERNET module
|
---|
| 1234 | * @retval HAL status
|
---|
| 1235 | */
|
---|
| 1236 | HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
|
---|
| 1237 | {
|
---|
| 1238 | /* Process Locked */
|
---|
| 1239 | __HAL_LOCK(heth);
|
---|
| 1240 |
|
---|
| 1241 | /* Set the ETH peripheral state to BUSY */
|
---|
| 1242 | heth->State = HAL_ETH_STATE_BUSY;
|
---|
| 1243 |
|
---|
| 1244 | /* Stop DMA transmission */
|
---|
| 1245 | ETH_DMATransmissionDisable(heth);
|
---|
| 1246 |
|
---|
| 1247 | /* Stop DMA reception */
|
---|
| 1248 | ETH_DMAReceptionDisable(heth);
|
---|
| 1249 |
|
---|
| 1250 | /* Disable receive state machine of the MAC for reception from the MII */
|
---|
| 1251 | ETH_MACReceptionDisable(heth);
|
---|
| 1252 |
|
---|
| 1253 | /* Flush Transmit FIFO */
|
---|
| 1254 | ETH_FlushTransmitFIFO(heth);
|
---|
| 1255 |
|
---|
| 1256 | /* Disable transmit state machine of the MAC for transmission on the MII */
|
---|
| 1257 | ETH_MACTransmissionDisable(heth);
|
---|
| 1258 |
|
---|
| 1259 | /* Set the ETH state*/
|
---|
| 1260 | heth->State = HAL_ETH_STATE_READY;
|
---|
| 1261 |
|
---|
| 1262 | /* Process Unlocked */
|
---|
| 1263 | __HAL_UNLOCK(heth);
|
---|
| 1264 |
|
---|
| 1265 | /* Return function status */
|
---|
| 1266 | return HAL_OK;
|
---|
| 1267 | }
|
---|
| 1268 |
|
---|
| 1269 | /**
|
---|
| 1270 | * @brief Set ETH MAC Configuration.
|
---|
| 1271 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 1272 | * the configuration information for ETHERNET module
|
---|
| 1273 | * @param macconf: MAC Configuration structure
|
---|
| 1274 | * @retval HAL status
|
---|
| 1275 | */
|
---|
| 1276 | HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
|
---|
| 1277 | {
|
---|
| 1278 | uint32_t tmpreg1 = 0;
|
---|
| 1279 |
|
---|
| 1280 | /* Process Locked */
|
---|
| 1281 | __HAL_LOCK(heth);
|
---|
| 1282 |
|
---|
| 1283 | /* Set the ETH peripheral state to BUSY */
|
---|
| 1284 | heth->State= HAL_ETH_STATE_BUSY;
|
---|
| 1285 |
|
---|
| 1286 | assert_param(IS_ETH_SPEED(heth->Init.Speed));
|
---|
| 1287 | assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
|
---|
| 1288 |
|
---|
| 1289 | if (macconf != NULL)
|
---|
| 1290 | {
|
---|
| 1291 | /* Check the parameters */
|
---|
| 1292 | assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
|
---|
| 1293 | assert_param(IS_ETH_JABBER(macconf->Jabber));
|
---|
| 1294 | assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
|
---|
| 1295 | assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
|
---|
| 1296 | assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
|
---|
| 1297 | assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
|
---|
| 1298 | assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
|
---|
| 1299 | assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
|
---|
| 1300 | assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
|
---|
| 1301 | assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
|
---|
| 1302 | assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
|
---|
| 1303 | assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
|
---|
| 1304 | assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
|
---|
| 1305 | assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
|
---|
| 1306 | assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
|
---|
| 1307 | assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
|
---|
| 1308 | assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
|
---|
| 1309 | assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
|
---|
| 1310 | assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
|
---|
| 1311 | assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
|
---|
| 1312 | assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
|
---|
| 1313 | assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
|
---|
| 1314 | assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
|
---|
| 1315 | assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
|
---|
| 1316 | assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
|
---|
| 1317 | assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
|
---|
| 1318 | assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
|
---|
| 1319 |
|
---|
| 1320 | /*------------------------ ETHERNET MACCR Configuration --------------------*/
|
---|
| 1321 | /* Get the ETHERNET MACCR value */
|
---|
| 1322 | tmpreg1 = (heth->Instance)->MACCR;
|
---|
| 1323 | /* Clear WD, PCE, PS, TE and RE bits */
|
---|
| 1324 | tmpreg1 &= ETH_MACCR_CLEAR_MASK;
|
---|
| 1325 |
|
---|
| 1326 | tmpreg1 |= (uint32_t)(macconf->Watchdog |
|
---|
| 1327 | macconf->Jabber |
|
---|
| 1328 | macconf->InterFrameGap |
|
---|
| 1329 | macconf->CarrierSense |
|
---|
| 1330 | (heth->Init).Speed |
|
---|
| 1331 | macconf->ReceiveOwn |
|
---|
| 1332 | macconf->LoopbackMode |
|
---|
| 1333 | (heth->Init).DuplexMode |
|
---|
| 1334 | macconf->ChecksumOffload |
|
---|
| 1335 | macconf->RetryTransmission |
|
---|
| 1336 | macconf->AutomaticPadCRCStrip |
|
---|
| 1337 | macconf->BackOffLimit |
|
---|
| 1338 | macconf->DeferralCheck);
|
---|
| 1339 |
|
---|
| 1340 | /* Write to ETHERNET MACCR */
|
---|
| 1341 | (heth->Instance)->MACCR = (uint32_t)tmpreg1;
|
---|
| 1342 |
|
---|
| 1343 | /* Wait until the write operation will be taken into account :
|
---|
| 1344 | at least four TX_CLK/RX_CLK clock cycles */
|
---|
| 1345 | tmpreg1 = (heth->Instance)->MACCR;
|
---|
| 1346 | HAL_Delay(ETH_REG_WRITE_DELAY);
|
---|
| 1347 | (heth->Instance)->MACCR = tmpreg1;
|
---|
| 1348 |
|
---|
| 1349 | /*----------------------- ETHERNET MACFFR Configuration --------------------*/
|
---|
| 1350 | /* Write to ETHERNET MACFFR */
|
---|
| 1351 | (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
|
---|
| 1352 | macconf->SourceAddrFilter |
|
---|
| 1353 | macconf->PassControlFrames |
|
---|
| 1354 | macconf->BroadcastFramesReception |
|
---|
| 1355 | macconf->DestinationAddrFilter |
|
---|
| 1356 | macconf->PromiscuousMode |
|
---|
| 1357 | macconf->MulticastFramesFilter |
|
---|
| 1358 | macconf->UnicastFramesFilter);
|
---|
| 1359 |
|
---|
| 1360 | /* Wait until the write operation will be taken into account :
|
---|
| 1361 | at least four TX_CLK/RX_CLK clock cycles */
|
---|
| 1362 | tmpreg1 = (heth->Instance)->MACFFR;
|
---|
| 1363 | HAL_Delay(ETH_REG_WRITE_DELAY);
|
---|
| 1364 | (heth->Instance)->MACFFR = tmpreg1;
|
---|
| 1365 |
|
---|
| 1366 | /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
|
---|
| 1367 | /* Write to ETHERNET MACHTHR */
|
---|
| 1368 | (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
|
---|
| 1369 |
|
---|
| 1370 | /* Write to ETHERNET MACHTLR */
|
---|
| 1371 | (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
|
---|
| 1372 | /*----------------------- ETHERNET MACFCR Configuration --------------------*/
|
---|
| 1373 |
|
---|
| 1374 | /* Get the ETHERNET MACFCR value */
|
---|
| 1375 | tmpreg1 = (heth->Instance)->MACFCR;
|
---|
| 1376 | /* Clear xx bits */
|
---|
| 1377 | tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
|
---|
| 1378 |
|
---|
| 1379 | tmpreg1 |= (uint32_t)((macconf->PauseTime << 16) |
|
---|
| 1380 | macconf->ZeroQuantaPause |
|
---|
| 1381 | macconf->PauseLowThreshold |
|
---|
| 1382 | macconf->UnicastPauseFrameDetect |
|
---|
| 1383 | macconf->ReceiveFlowControl |
|
---|
| 1384 | macconf->TransmitFlowControl);
|
---|
| 1385 |
|
---|
| 1386 | /* Write to ETHERNET MACFCR */
|
---|
| 1387 | (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
|
---|
| 1388 |
|
---|
| 1389 | /* Wait until the write operation will be taken into account :
|
---|
| 1390 | at least four TX_CLK/RX_CLK clock cycles */
|
---|
| 1391 | tmpreg1 = (heth->Instance)->MACFCR;
|
---|
| 1392 | HAL_Delay(ETH_REG_WRITE_DELAY);
|
---|
| 1393 | (heth->Instance)->MACFCR = tmpreg1;
|
---|
| 1394 |
|
---|
| 1395 | /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
|
---|
| 1396 | (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
|
---|
| 1397 | macconf->VLANTagIdentifier);
|
---|
| 1398 |
|
---|
| 1399 | /* Wait until the write operation will be taken into account :
|
---|
| 1400 | at least four TX_CLK/RX_CLK clock cycles */
|
---|
| 1401 | tmpreg1 = (heth->Instance)->MACVLANTR;
|
---|
| 1402 | HAL_Delay(ETH_REG_WRITE_DELAY);
|
---|
| 1403 | (heth->Instance)->MACVLANTR = tmpreg1;
|
---|
| 1404 | }
|
---|
| 1405 | else /* macconf == NULL : here we just configure Speed and Duplex mode */
|
---|
| 1406 | {
|
---|
| 1407 | /*------------------------ ETHERNET MACCR Configuration --------------------*/
|
---|
| 1408 | /* Get the ETHERNET MACCR value */
|
---|
| 1409 | tmpreg1 = (heth->Instance)->MACCR;
|
---|
| 1410 |
|
---|
| 1411 | /* Clear FES and DM bits */
|
---|
| 1412 | tmpreg1 &= ~((uint32_t)0x00004800);
|
---|
| 1413 |
|
---|
| 1414 | tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
|
---|
| 1415 |
|
---|
| 1416 | /* Write to ETHERNET MACCR */
|
---|
| 1417 | (heth->Instance)->MACCR = (uint32_t)tmpreg1;
|
---|
| 1418 |
|
---|
| 1419 | /* Wait until the write operation will be taken into account:
|
---|
| 1420 | at least four TX_CLK/RX_CLK clock cycles */
|
---|
| 1421 | tmpreg1 = (heth->Instance)->MACCR;
|
---|
| 1422 | HAL_Delay(ETH_REG_WRITE_DELAY);
|
---|
| 1423 | (heth->Instance)->MACCR = tmpreg1;
|
---|
| 1424 | }
|
---|
| 1425 |
|
---|
| 1426 | /* Set the ETH state to Ready */
|
---|
| 1427 | heth->State= HAL_ETH_STATE_READY;
|
---|
| 1428 |
|
---|
| 1429 | /* Process Unlocked */
|
---|
| 1430 | __HAL_UNLOCK(heth);
|
---|
| 1431 |
|
---|
| 1432 | /* Return function status */
|
---|
| 1433 | return HAL_OK;
|
---|
| 1434 | }
|
---|
| 1435 |
|
---|
| 1436 | /**
|
---|
| 1437 | * @brief Sets ETH DMA Configuration.
|
---|
| 1438 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 1439 | * the configuration information for ETHERNET module
|
---|
| 1440 | * @param dmaconf: DMA Configuration structure
|
---|
| 1441 | * @retval HAL status
|
---|
| 1442 | */
|
---|
| 1443 | HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
|
---|
| 1444 | {
|
---|
| 1445 | uint32_t tmpreg1 = 0;
|
---|
| 1446 |
|
---|
| 1447 | /* Process Locked */
|
---|
| 1448 | __HAL_LOCK(heth);
|
---|
| 1449 |
|
---|
| 1450 | /* Set the ETH peripheral state to BUSY */
|
---|
| 1451 | heth->State= HAL_ETH_STATE_BUSY;
|
---|
| 1452 |
|
---|
| 1453 | /* Check parameters */
|
---|
| 1454 | assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
|
---|
| 1455 | assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
|
---|
| 1456 | assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
|
---|
| 1457 | assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
|
---|
| 1458 | assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
|
---|
| 1459 | assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
|
---|
| 1460 | assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
|
---|
| 1461 | assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
|
---|
| 1462 | assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
|
---|
| 1463 | assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
|
---|
| 1464 | assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
|
---|
| 1465 | assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
|
---|
| 1466 | assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
|
---|
| 1467 | assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
|
---|
| 1468 | assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
|
---|
| 1469 | assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
|
---|
| 1470 |
|
---|
| 1471 | /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
|
---|
| 1472 | /* Get the ETHERNET DMAOMR value */
|
---|
| 1473 | tmpreg1 = (heth->Instance)->DMAOMR;
|
---|
| 1474 | /* Clear xx bits */
|
---|
| 1475 | tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
|
---|
| 1476 |
|
---|
| 1477 | tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
|
---|
| 1478 | dmaconf->ReceiveStoreForward |
|
---|
| 1479 | dmaconf->FlushReceivedFrame |
|
---|
| 1480 | dmaconf->TransmitStoreForward |
|
---|
| 1481 | dmaconf->TransmitThresholdControl |
|
---|
| 1482 | dmaconf->ForwardErrorFrames |
|
---|
| 1483 | dmaconf->ForwardUndersizedGoodFrames |
|
---|
| 1484 | dmaconf->ReceiveThresholdControl |
|
---|
| 1485 | dmaconf->SecondFrameOperate);
|
---|
| 1486 |
|
---|
| 1487 | /* Write to ETHERNET DMAOMR */
|
---|
| 1488 | (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
|
---|
| 1489 |
|
---|
| 1490 | /* Wait until the write operation will be taken into account:
|
---|
| 1491 | at least four TX_CLK/RX_CLK clock cycles */
|
---|
| 1492 | tmpreg1 = (heth->Instance)->DMAOMR;
|
---|
| 1493 | HAL_Delay(ETH_REG_WRITE_DELAY);
|
---|
| 1494 | (heth->Instance)->DMAOMR = tmpreg1;
|
---|
| 1495 |
|
---|
| 1496 | /*----------------------- ETHERNET DMABMR Configuration --------------------*/
|
---|
| 1497 | (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
|
---|
| 1498 | dmaconf->FixedBurst |
|
---|
| 1499 | dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
|
---|
| 1500 | dmaconf->TxDMABurstLength |
|
---|
| 1501 | dmaconf->EnhancedDescriptorFormat |
|
---|
| 1502 | (dmaconf->DescriptorSkipLength << 2) |
|
---|
| 1503 | dmaconf->DMAArbitration |
|
---|
| 1504 | ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
|
---|
| 1505 |
|
---|
| 1506 | /* Wait until the write operation will be taken into account:
|
---|
| 1507 | at least four TX_CLK/RX_CLK clock cycles */
|
---|
| 1508 | tmpreg1 = (heth->Instance)->DMABMR;
|
---|
| 1509 | HAL_Delay(ETH_REG_WRITE_DELAY);
|
---|
| 1510 | (heth->Instance)->DMABMR = tmpreg1;
|
---|
| 1511 |
|
---|
| 1512 | /* Set the ETH state to Ready */
|
---|
| 1513 | heth->State= HAL_ETH_STATE_READY;
|
---|
| 1514 |
|
---|
| 1515 | /* Process Unlocked */
|
---|
| 1516 | __HAL_UNLOCK(heth);
|
---|
| 1517 |
|
---|
| 1518 | /* Return function status */
|
---|
| 1519 | return HAL_OK;
|
---|
| 1520 | }
|
---|
| 1521 |
|
---|
| 1522 | /**
|
---|
| 1523 | * @}
|
---|
| 1524 | */
|
---|
| 1525 |
|
---|
| 1526 | /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
|
---|
| 1527 | * @brief Peripheral State functions
|
---|
| 1528 | *
|
---|
| 1529 | @verbatim
|
---|
| 1530 | ===============================================================================
|
---|
| 1531 | ##### Peripheral State functions #####
|
---|
| 1532 | ===============================================================================
|
---|
| 1533 | [..]
|
---|
| 1534 | This subsection permits to get in run-time the status of the peripheral
|
---|
| 1535 | and the data flow.
|
---|
| 1536 | (+) Get the ETH handle state:
|
---|
| 1537 | HAL_ETH_GetState();
|
---|
| 1538 |
|
---|
| 1539 |
|
---|
| 1540 | @endverbatim
|
---|
| 1541 | * @{
|
---|
| 1542 | */
|
---|
| 1543 |
|
---|
| 1544 | /**
|
---|
| 1545 | * @brief Return the ETH HAL state
|
---|
| 1546 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 1547 | * the configuration information for ETHERNET module
|
---|
| 1548 | * @retval HAL state
|
---|
| 1549 | */
|
---|
| 1550 | HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
|
---|
| 1551 | {
|
---|
| 1552 | /* Return ETH state */
|
---|
| 1553 | return heth->State;
|
---|
| 1554 | }
|
---|
| 1555 |
|
---|
| 1556 | /**
|
---|
| 1557 | * @}
|
---|
| 1558 | */
|
---|
| 1559 |
|
---|
| 1560 | /**
|
---|
| 1561 | * @}
|
---|
| 1562 | */
|
---|
| 1563 |
|
---|
| 1564 | /** @addtogroup ETH_Private_Functions
|
---|
| 1565 | * @{
|
---|
| 1566 | */
|
---|
| 1567 |
|
---|
| 1568 | /**
|
---|
| 1569 | * @brief Configures Ethernet MAC and DMA with default parameters.
|
---|
| 1570 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 1571 | * the configuration information for ETHERNET module
|
---|
| 1572 | * @param err: Ethernet Init error
|
---|
| 1573 | * @retval HAL status
|
---|
| 1574 | */
|
---|
| 1575 | static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
|
---|
| 1576 | {
|
---|
| 1577 | ETH_MACInitTypeDef macinit;
|
---|
| 1578 | ETH_DMAInitTypeDef dmainit;
|
---|
| 1579 | uint32_t tmpreg1 = 0;
|
---|
| 1580 |
|
---|
| 1581 | if (err != ETH_SUCCESS) /* Auto-negotiation failed */
|
---|
| 1582 | {
|
---|
| 1583 | /* Set Ethernet duplex mode to Full-duplex */
|
---|
| 1584 | (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
|
---|
| 1585 |
|
---|
| 1586 | /* Set Ethernet speed to 100M */
|
---|
| 1587 | (heth->Init).Speed = ETH_SPEED_100M;
|
---|
| 1588 | }
|
---|
| 1589 |
|
---|
| 1590 | /* Ethernet MAC default initialization **************************************/
|
---|
| 1591 | macinit.Watchdog = ETH_WATCHDOG_ENABLE;
|
---|
| 1592 | macinit.Jabber = ETH_JABBER_ENABLE;
|
---|
| 1593 | macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
|
---|
| 1594 | macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
|
---|
| 1595 | macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
|
---|
| 1596 | macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
|
---|
| 1597 | if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
|
---|
| 1598 | {
|
---|
| 1599 | macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
|
---|
| 1600 | }
|
---|
| 1601 | else
|
---|
| 1602 | {
|
---|
| 1603 | macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
|
---|
| 1604 | }
|
---|
| 1605 | macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
|
---|
| 1606 | macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
|
---|
| 1607 | macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
|
---|
| 1608 | macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
|
---|
| 1609 | macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
|
---|
| 1610 | macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
|
---|
| 1611 | macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
|
---|
| 1612 | macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
|
---|
| 1613 | macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
|
---|
| 1614 | macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
|
---|
| 1615 | macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
|
---|
| 1616 | macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
|
---|
| 1617 | macinit.HashTableHigh = 0x0;
|
---|
| 1618 | macinit.HashTableLow = 0x0;
|
---|
| 1619 | macinit.PauseTime = 0x0;
|
---|
| 1620 | macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
|
---|
| 1621 | macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
|
---|
| 1622 | macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
|
---|
| 1623 | macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
|
---|
| 1624 | macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
|
---|
| 1625 | macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
|
---|
| 1626 | macinit.VLANTagIdentifier = 0x0;
|
---|
| 1627 |
|
---|
| 1628 | /*------------------------ ETHERNET MACCR Configuration --------------------*/
|
---|
| 1629 | /* Get the ETHERNET MACCR value */
|
---|
| 1630 | tmpreg1 = (heth->Instance)->MACCR;
|
---|
| 1631 | /* Clear WD, PCE, PS, TE and RE bits */
|
---|
| 1632 | tmpreg1 &= ETH_MACCR_CLEAR_MASK;
|
---|
| 1633 | /* Set the WD bit according to ETH Watchdog value */
|
---|
| 1634 | /* Set the JD: bit according to ETH Jabber value */
|
---|
| 1635 | /* Set the IFG bit according to ETH InterFrameGap value */
|
---|
| 1636 | /* Set the DCRS bit according to ETH CarrierSense value */
|
---|
| 1637 | /* Set the FES bit according to ETH Speed value */
|
---|
| 1638 | /* Set the DO bit according to ETH ReceiveOwn value */
|
---|
| 1639 | /* Set the LM bit according to ETH LoopbackMode value */
|
---|
| 1640 | /* Set the DM bit according to ETH Mode value */
|
---|
| 1641 | /* Set the IPCO bit according to ETH ChecksumOffload value */
|
---|
| 1642 | /* Set the DR bit according to ETH RetryTransmission value */
|
---|
| 1643 | /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
|
---|
| 1644 | /* Set the BL bit according to ETH BackOffLimit value */
|
---|
| 1645 | /* Set the DC bit according to ETH DeferralCheck value */
|
---|
| 1646 | tmpreg1 |= (uint32_t)(macinit.Watchdog |
|
---|
| 1647 | macinit.Jabber |
|
---|
| 1648 | macinit.InterFrameGap |
|
---|
| 1649 | macinit.CarrierSense |
|
---|
| 1650 | (heth->Init).Speed |
|
---|
| 1651 | macinit.ReceiveOwn |
|
---|
| 1652 | macinit.LoopbackMode |
|
---|
| 1653 | (heth->Init).DuplexMode |
|
---|
| 1654 | macinit.ChecksumOffload |
|
---|
| 1655 | macinit.RetryTransmission |
|
---|
| 1656 | macinit.AutomaticPadCRCStrip |
|
---|
| 1657 | macinit.BackOffLimit |
|
---|
| 1658 | macinit.DeferralCheck);
|
---|
| 1659 |
|
---|
| 1660 | /* Write to ETHERNET MACCR */
|
---|
| 1661 | (heth->Instance)->MACCR = (uint32_t)tmpreg1;
|
---|
| 1662 |
|
---|
| 1663 | /* Wait until the write operation will be taken into account:
|
---|
| 1664 | at least four TX_CLK/RX_CLK clock cycles */
|
---|
| 1665 | tmpreg1 = (heth->Instance)->MACCR;
|
---|
| 1666 | HAL_Delay(ETH_REG_WRITE_DELAY);
|
---|
| 1667 | (heth->Instance)->MACCR = tmpreg1;
|
---|
| 1668 |
|
---|
| 1669 | /*----------------------- ETHERNET MACFFR Configuration --------------------*/
|
---|
| 1670 | /* Set the RA bit according to ETH ReceiveAll value */
|
---|
| 1671 | /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
|
---|
| 1672 | /* Set the PCF bit according to ETH PassControlFrames value */
|
---|
| 1673 | /* Set the DBF bit according to ETH BroadcastFramesReception value */
|
---|
| 1674 | /* Set the DAIF bit according to ETH DestinationAddrFilter value */
|
---|
| 1675 | /* Set the PR bit according to ETH PromiscuousMode value */
|
---|
| 1676 | /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
|
---|
| 1677 | /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
|
---|
| 1678 | /* Write to ETHERNET MACFFR */
|
---|
| 1679 | (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
|
---|
| 1680 | macinit.SourceAddrFilter |
|
---|
| 1681 | macinit.PassControlFrames |
|
---|
| 1682 | macinit.BroadcastFramesReception |
|
---|
| 1683 | macinit.DestinationAddrFilter |
|
---|
| 1684 | macinit.PromiscuousMode |
|
---|
| 1685 | macinit.MulticastFramesFilter |
|
---|
| 1686 | macinit.UnicastFramesFilter);
|
---|
| 1687 |
|
---|
| 1688 | /* Wait until the write operation will be taken into account:
|
---|
| 1689 | at least four TX_CLK/RX_CLK clock cycles */
|
---|
| 1690 | tmpreg1 = (heth->Instance)->MACFFR;
|
---|
| 1691 | HAL_Delay(ETH_REG_WRITE_DELAY);
|
---|
| 1692 | (heth->Instance)->MACFFR = tmpreg1;
|
---|
| 1693 |
|
---|
| 1694 | /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
|
---|
| 1695 | /* Write to ETHERNET MACHTHR */
|
---|
| 1696 | (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
|
---|
| 1697 |
|
---|
| 1698 | /* Write to ETHERNET MACHTLR */
|
---|
| 1699 | (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
|
---|
| 1700 | /*----------------------- ETHERNET MACFCR Configuration -------------------*/
|
---|
| 1701 |
|
---|
| 1702 | /* Get the ETHERNET MACFCR value */
|
---|
| 1703 | tmpreg1 = (heth->Instance)->MACFCR;
|
---|
| 1704 | /* Clear xx bits */
|
---|
| 1705 | tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
|
---|
| 1706 |
|
---|
| 1707 | /* Set the PT bit according to ETH PauseTime value */
|
---|
| 1708 | /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
|
---|
| 1709 | /* Set the PLT bit according to ETH PauseLowThreshold value */
|
---|
| 1710 | /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
|
---|
| 1711 | /* Set the RFE bit according to ETH ReceiveFlowControl value */
|
---|
| 1712 | /* Set the TFE bit according to ETH TransmitFlowControl value */
|
---|
| 1713 | tmpreg1 |= (uint32_t)((macinit.PauseTime << 16) |
|
---|
| 1714 | macinit.ZeroQuantaPause |
|
---|
| 1715 | macinit.PauseLowThreshold |
|
---|
| 1716 | macinit.UnicastPauseFrameDetect |
|
---|
| 1717 | macinit.ReceiveFlowControl |
|
---|
| 1718 | macinit.TransmitFlowControl);
|
---|
| 1719 |
|
---|
| 1720 | /* Write to ETHERNET MACFCR */
|
---|
| 1721 | (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
|
---|
| 1722 |
|
---|
| 1723 | /* Wait until the write operation will be taken into account:
|
---|
| 1724 | at least four TX_CLK/RX_CLK clock cycles */
|
---|
| 1725 | tmpreg1 = (heth->Instance)->MACFCR;
|
---|
| 1726 | HAL_Delay(ETH_REG_WRITE_DELAY);
|
---|
| 1727 | (heth->Instance)->MACFCR = tmpreg1;
|
---|
| 1728 |
|
---|
| 1729 | /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
|
---|
| 1730 | /* Set the ETV bit according to ETH VLANTagComparison value */
|
---|
| 1731 | /* Set the VL bit according to ETH VLANTagIdentifier value */
|
---|
| 1732 | (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
|
---|
| 1733 | macinit.VLANTagIdentifier);
|
---|
| 1734 |
|
---|
| 1735 | /* Wait until the write operation will be taken into account:
|
---|
| 1736 | at least four TX_CLK/RX_CLK clock cycles */
|
---|
| 1737 | tmpreg1 = (heth->Instance)->MACVLANTR;
|
---|
| 1738 | HAL_Delay(ETH_REG_WRITE_DELAY);
|
---|
| 1739 | (heth->Instance)->MACVLANTR = tmpreg1;
|
---|
| 1740 |
|
---|
| 1741 | /* Ethernet DMA default initialization ************************************/
|
---|
| 1742 | dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
|
---|
| 1743 | dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
|
---|
| 1744 | dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
|
---|
| 1745 | dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
|
---|
| 1746 | dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
|
---|
| 1747 | dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
|
---|
| 1748 | dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
|
---|
| 1749 | dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
|
---|
| 1750 | dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
|
---|
| 1751 | dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
|
---|
| 1752 | dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
|
---|
| 1753 | dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
|
---|
| 1754 | dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
|
---|
| 1755 | dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
|
---|
| 1756 | dmainit.DescriptorSkipLength = 0x0;
|
---|
| 1757 | dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
|
---|
| 1758 |
|
---|
| 1759 | /* Get the ETHERNET DMAOMR value */
|
---|
| 1760 | tmpreg1 = (heth->Instance)->DMAOMR;
|
---|
| 1761 | /* Clear xx bits */
|
---|
| 1762 | tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
|
---|
| 1763 |
|
---|
| 1764 | /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
|
---|
| 1765 | /* Set the RSF bit according to ETH ReceiveStoreForward value */
|
---|
| 1766 | /* Set the DFF bit according to ETH FlushReceivedFrame value */
|
---|
| 1767 | /* Set the TSF bit according to ETH TransmitStoreForward value */
|
---|
| 1768 | /* Set the TTC bit according to ETH TransmitThresholdControl value */
|
---|
| 1769 | /* Set the FEF bit according to ETH ForwardErrorFrames value */
|
---|
| 1770 | /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
|
---|
| 1771 | /* Set the RTC bit according to ETH ReceiveThresholdControl value */
|
---|
| 1772 | /* Set the OSF bit according to ETH SecondFrameOperate value */
|
---|
| 1773 | tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
|
---|
| 1774 | dmainit.ReceiveStoreForward |
|
---|
| 1775 | dmainit.FlushReceivedFrame |
|
---|
| 1776 | dmainit.TransmitStoreForward |
|
---|
| 1777 | dmainit.TransmitThresholdControl |
|
---|
| 1778 | dmainit.ForwardErrorFrames |
|
---|
| 1779 | dmainit.ForwardUndersizedGoodFrames |
|
---|
| 1780 | dmainit.ReceiveThresholdControl |
|
---|
| 1781 | dmainit.SecondFrameOperate);
|
---|
| 1782 |
|
---|
| 1783 | /* Write to ETHERNET DMAOMR */
|
---|
| 1784 | (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
|
---|
| 1785 |
|
---|
| 1786 | /* Wait until the write operation will be taken into account:
|
---|
| 1787 | at least four TX_CLK/RX_CLK clock cycles */
|
---|
| 1788 | tmpreg1 = (heth->Instance)->DMAOMR;
|
---|
| 1789 | HAL_Delay(ETH_REG_WRITE_DELAY);
|
---|
| 1790 | (heth->Instance)->DMAOMR = tmpreg1;
|
---|
| 1791 |
|
---|
| 1792 | /*----------------------- ETHERNET DMABMR Configuration ------------------*/
|
---|
| 1793 | /* Set the AAL bit according to ETH AddressAlignedBeats value */
|
---|
| 1794 | /* Set the FB bit according to ETH FixedBurst value */
|
---|
| 1795 | /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
|
---|
| 1796 | /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
|
---|
| 1797 | /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
|
---|
| 1798 | /* Set the DSL bit according to ETH DesciptorSkipLength value */
|
---|
| 1799 | /* Set the PR and DA bits according to ETH DMAArbitration value */
|
---|
| 1800 | (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
|
---|
| 1801 | dmainit.FixedBurst |
|
---|
| 1802 | dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
|
---|
| 1803 | dmainit.TxDMABurstLength |
|
---|
| 1804 | dmainit.EnhancedDescriptorFormat |
|
---|
| 1805 | (dmainit.DescriptorSkipLength << 2) |
|
---|
| 1806 | dmainit.DMAArbitration |
|
---|
| 1807 | ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
|
---|
| 1808 |
|
---|
| 1809 | /* Wait until the write operation will be taken into account:
|
---|
| 1810 | at least four TX_CLK/RX_CLK clock cycles */
|
---|
| 1811 | tmpreg1 = (heth->Instance)->DMABMR;
|
---|
| 1812 | HAL_Delay(ETH_REG_WRITE_DELAY);
|
---|
| 1813 | (heth->Instance)->DMABMR = tmpreg1;
|
---|
| 1814 |
|
---|
| 1815 | if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
|
---|
| 1816 | {
|
---|
| 1817 | /* Enable the Ethernet Rx Interrupt */
|
---|
| 1818 | __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
|
---|
| 1819 | }
|
---|
| 1820 |
|
---|
| 1821 | /* Initialize MAC address in ethernet MAC */
|
---|
| 1822 | ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
|
---|
| 1823 | }
|
---|
| 1824 |
|
---|
| 1825 | /**
|
---|
| 1826 | * @brief Configures the selected MAC address.
|
---|
| 1827 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 1828 | * the configuration information for ETHERNET module
|
---|
| 1829 | * @param MacAddr: The MAC address to configure
|
---|
| 1830 | * This parameter can be one of the following values:
|
---|
| 1831 | * @arg ETH_MAC_Address0: MAC Address0
|
---|
| 1832 | * @arg ETH_MAC_Address1: MAC Address1
|
---|
| 1833 | * @arg ETH_MAC_Address2: MAC Address2
|
---|
| 1834 | * @arg ETH_MAC_Address3: MAC Address3
|
---|
| 1835 | * @param Addr: Pointer to MAC address buffer data (6 bytes)
|
---|
| 1836 | * @retval HAL status
|
---|
| 1837 | */
|
---|
| 1838 | static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
|
---|
| 1839 | {
|
---|
| 1840 | uint32_t tmpreg1;
|
---|
| 1841 |
|
---|
| 1842 | /* Check the parameters */
|
---|
| 1843 | assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
|
---|
| 1844 |
|
---|
| 1845 | /* Calculate the selected MAC address high register */
|
---|
| 1846 | tmpreg1 = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
|
---|
| 1847 | /* Load the selected MAC address high register */
|
---|
| 1848 | (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
|
---|
| 1849 | /* Calculate the selected MAC address low register */
|
---|
| 1850 | tmpreg1 = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
|
---|
| 1851 |
|
---|
| 1852 | /* Load the selected MAC address low register */
|
---|
| 1853 | (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
|
---|
| 1854 | }
|
---|
| 1855 |
|
---|
| 1856 | /**
|
---|
| 1857 | * @brief Enables the MAC transmission.
|
---|
| 1858 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 1859 | * the configuration information for ETHERNET module
|
---|
| 1860 | * @retval None
|
---|
| 1861 | */
|
---|
| 1862 | static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
|
---|
| 1863 | {
|
---|
| 1864 | __IO uint32_t tmpreg1 = 0;
|
---|
| 1865 |
|
---|
| 1866 | /* Enable the MAC transmission */
|
---|
| 1867 | (heth->Instance)->MACCR |= ETH_MACCR_TE;
|
---|
| 1868 |
|
---|
| 1869 | /* Wait until the write operation will be taken into account:
|
---|
| 1870 | at least four TX_CLK/RX_CLK clock cycles */
|
---|
| 1871 | tmpreg1 = (heth->Instance)->MACCR;
|
---|
| 1872 | HAL_Delay(ETH_REG_WRITE_DELAY);
|
---|
| 1873 | (heth->Instance)->MACCR = tmpreg1;
|
---|
| 1874 | }
|
---|
| 1875 |
|
---|
| 1876 | /**
|
---|
| 1877 | * @brief Disables the MAC transmission.
|
---|
| 1878 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 1879 | * the configuration information for ETHERNET module
|
---|
| 1880 | * @retval None
|
---|
| 1881 | */
|
---|
| 1882 | static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
|
---|
| 1883 | {
|
---|
| 1884 | __IO uint32_t tmpreg1 = 0;
|
---|
| 1885 |
|
---|
| 1886 | /* Disable the MAC transmission */
|
---|
| 1887 | (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
|
---|
| 1888 |
|
---|
| 1889 | /* Wait until the write operation will be taken into account:
|
---|
| 1890 | at least four TX_CLK/RX_CLK clock cycles */
|
---|
| 1891 | tmpreg1 = (heth->Instance)->MACCR;
|
---|
| 1892 | HAL_Delay(ETH_REG_WRITE_DELAY);
|
---|
| 1893 | (heth->Instance)->MACCR = tmpreg1;
|
---|
| 1894 | }
|
---|
| 1895 |
|
---|
| 1896 | /**
|
---|
| 1897 | * @brief Enables the MAC reception.
|
---|
| 1898 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 1899 | * the configuration information for ETHERNET module
|
---|
| 1900 | * @retval None
|
---|
| 1901 | */
|
---|
| 1902 | static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
|
---|
| 1903 | {
|
---|
| 1904 | __IO uint32_t tmpreg1 = 0;
|
---|
| 1905 |
|
---|
| 1906 | /* Enable the MAC reception */
|
---|
| 1907 | (heth->Instance)->MACCR |= ETH_MACCR_RE;
|
---|
| 1908 |
|
---|
| 1909 | /* Wait until the write operation will be taken into account:
|
---|
| 1910 | at least four TX_CLK/RX_CLK clock cycles */
|
---|
| 1911 | tmpreg1 = (heth->Instance)->MACCR;
|
---|
| 1912 | HAL_Delay(ETH_REG_WRITE_DELAY);
|
---|
| 1913 | (heth->Instance)->MACCR = tmpreg1;
|
---|
| 1914 | }
|
---|
| 1915 |
|
---|
| 1916 | /**
|
---|
| 1917 | * @brief Disables the MAC reception.
|
---|
| 1918 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 1919 | * the configuration information for ETHERNET module
|
---|
| 1920 | * @retval None
|
---|
| 1921 | */
|
---|
| 1922 | static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
|
---|
| 1923 | {
|
---|
| 1924 | __IO uint32_t tmpreg1 = 0;
|
---|
| 1925 |
|
---|
| 1926 | /* Disable the MAC reception */
|
---|
| 1927 | (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
|
---|
| 1928 |
|
---|
| 1929 | /* Wait until the write operation will be taken into account:
|
---|
| 1930 | at least four TX_CLK/RX_CLK clock cycles */
|
---|
| 1931 | tmpreg1 = (heth->Instance)->MACCR;
|
---|
| 1932 | HAL_Delay(ETH_REG_WRITE_DELAY);
|
---|
| 1933 | (heth->Instance)->MACCR = tmpreg1;
|
---|
| 1934 | }
|
---|
| 1935 |
|
---|
| 1936 | /**
|
---|
| 1937 | * @brief Enables the DMA transmission.
|
---|
| 1938 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 1939 | * the configuration information for ETHERNET module
|
---|
| 1940 | * @retval None
|
---|
| 1941 | */
|
---|
| 1942 | static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
|
---|
| 1943 | {
|
---|
| 1944 | /* Enable the DMA transmission */
|
---|
| 1945 | (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
|
---|
| 1946 | }
|
---|
| 1947 |
|
---|
| 1948 | /**
|
---|
| 1949 | * @brief Disables the DMA transmission.
|
---|
| 1950 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 1951 | * the configuration information for ETHERNET module
|
---|
| 1952 | * @retval None
|
---|
| 1953 | */
|
---|
| 1954 | static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
|
---|
| 1955 | {
|
---|
| 1956 | /* Disable the DMA transmission */
|
---|
| 1957 | (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
|
---|
| 1958 | }
|
---|
| 1959 |
|
---|
| 1960 | /**
|
---|
| 1961 | * @brief Enables the DMA reception.
|
---|
| 1962 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
---|
| 1963 | * the configuration information for ETHERNET module
|
---|
| 1964 | * @retval None
|
---|
| 1965 | */
|
---|
| 1966 | static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
|
---|
| 1967 | {
|
---|
| 1968 | /* Enable the DMA reception */
|
---|
| 1969 | (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
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| 1970 | }
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| 1971 |
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| 1972 | /**
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| 1973 | * @brief Disables the DMA reception.
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| 1974 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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| 1975 | * the configuration information for ETHERNET module
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| 1976 | * @retval None
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| 1977 | */
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| 1978 | static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
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| 1979 | {
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| 1980 | /* Disable the DMA reception */
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| 1981 | (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
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| 1982 | }
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| 1983 |
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| 1984 | /**
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| 1985 | * @brief Clears the ETHERNET transmit FIFO.
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| 1986 | * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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| 1987 | * the configuration information for ETHERNET module
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| 1988 | * @retval None
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| 1989 | */
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| 1990 | static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
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| 1991 | {
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| 1992 | __IO uint32_t tmpreg1 = 0;
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| 1993 |
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| 1994 | /* Set the Flush Transmit FIFO bit */
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| 1995 | (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
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| 1996 |
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| 1997 | /* Wait until the write operation will be taken into account:
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| 1998 | at least four TX_CLK/RX_CLK clock cycles */
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| 1999 | tmpreg1 = (heth->Instance)->DMAOMR;
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| 2000 | HAL_Delay(ETH_REG_WRITE_DELAY);
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| 2001 | (heth->Instance)->DMAOMR = tmpreg1;
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| 2002 | }
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| 2003 |
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| 2004 | /**
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| 2005 | * @}
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| 2006 | */
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| 2007 |
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| 2008 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
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| 2009 | STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
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| 2010 | #endif /* HAL_ETH_MODULE_ENABLED */
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| 2011 | /**
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| 2012 | * @}
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| 2013 | */
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| 2014 |
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| 2015 | /**
|
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| 2016 | * @}
|
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| 2017 | */
|
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| 2018 |
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| 2019 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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