source: asp3_wo_tecs/trunk/arch/arm_m_gcc/stm32f4xx_stm32cube/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c@ 303

Last change on this file since 303 was 303, checked in by ertl-honda, 7 years ago

nucleo_f401re依存部の追加
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1/**
2 ******************************************************************************
3 * @file stm32f4xx_hal_dsi.c
4 * @author MCD Application Team
5 * @version V1.4.1
6 * @date 09-October-2015
7 * @brief DSI HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the DSI peripheral:
10 * + Initialization and de-initialization functions
11 * + IO operation functions
12 * + Peripheral Control functions
13 * + Peripheral State and Errors functions
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44/* Includes ------------------------------------------------------------------*/
45#include "stm32f4xx_hal.h"
46
47/** @addtogroup STM32F4xx_HAL_Driver
48 * @{
49 */
50/** @addtogroup DSI
51 * @{
52 */
53
54#ifdef HAL_DSI_MODULE_ENABLED
55
56#if defined(STM32F469xx) || defined(STM32F479xx)
57
58/* Private types -------------------------------------------------------------*/
59/* Private defines -----------------------------------------------------------*/
60/** @addtogroup DSI_Private_Constants
61 * @{
62 */
63#define DSI_TIMEOUT_VALUE ((uint32_t)1000) /* 1s */
64
65#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
66 DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
67 DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \
68 DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)
69#define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)
70#define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX
71#define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX
72#define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)
73#define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
74#define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
75#define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
76#define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
77#define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)
78/**
79 * @}
80 */
81
82/* Private variables ---------------------------------------------------------*/
83/* Private constants ---------------------------------------------------------*/
84/* Private macros ------------------------------------------------------------*/
85/* Private function prototypes -----------------------------------------------*/
86static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1);
87
88/* Private functions ---------------------------------------------------------*/
89/**
90 * @brief Generic DSI packet header configuration
91 * @param DSIx: Pointer to DSI register base
92 * @param ChannelID: Virtual channel ID of the header packet
93 * @param DataType: Packet data type of the header packet
94 * This parameter can be any value of :
95 * @ref DSI_SHORT_WRITE_PKT_Data_Type
96 * or @ref DSI_LONG_WRITE_PKT_Data_Type
97 * or @ref DSI_SHORT_READ_PKT_Data_Type
98 * or DSI_MAX_RETURN_PKT_SIZE
99 * @param Data0: Word count LSB
100 * @param Data1: Word count MSB
101 * @retval None
102 */
103static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
104 uint32_t ChannelID,
105 uint32_t DataType,
106 uint32_t Data0,
107 uint32_t Data1)
108{
109 /* Update the DSI packet header with new information */
110 DSIx->GHCR = (DataType | (ChannelID<<6) | (Data0<<8) | (Data1<<16));
111}
112
113/* Exported functions --------------------------------------------------------*/
114/** @addtogroup DSI_Exported_Functions
115 * @{
116 */
117
118/** @defgroup DSI_Group1 Initialization and Configuration functions
119 * @brief Initialization and Configuration functions
120 *
121@verbatim
122 ===============================================================================
123 ##### Initialization and Configuration functions #####
124 ===============================================================================
125 [..] This section provides functions allowing to:
126 (+) Initialize and configure the DSI
127 (+) De-initialize the DSI
128
129@endverbatim
130 * @{
131 */
132
133/**
134 * @brief Initializes the DSI according to the specified
135 * parameters in the DSI_InitTypeDef and create the associated handle.
136 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
137 * the configuration information for the DSI.
138 * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains
139 * the PLL Clock structure definition for the DSI.
140 * @retval HAL status
141 */
142HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
143{
144 uint32_t tickstart = 0;
145 uint32_t unitIntervalx4 = 0;
146 uint32_t tempIDF = 0;
147
148 /* Check the DSI handle allocation */
149 if(hdsi == NULL)
150 {
151 return HAL_ERROR;
152 }
153
154 /* Check function parameters */
155 assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
156 assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
157 assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
158 assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
159 assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
160
161 if(hdsi->State == HAL_DSI_STATE_RESET)
162 {
163 /* Initialize the low level hardware */
164 HAL_DSI_MspInit(hdsi);
165 }
166
167 /* Change DSI peripheral state */
168 hdsi->State = HAL_DSI_STATE_BUSY;
169
170 /**************** Turn on the regulator and enable the DSI PLL ****************/
171
172 /* Enable the regulator */
173 __HAL_DSI_REG_ENABLE(hdsi);
174
175 /* Get tick */
176 tickstart = HAL_GetTick();
177
178 /* Wait until the regulator is ready */
179 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET)
180 {
181 /* Check for the Timeout */
182 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
183 {
184 return HAL_TIMEOUT;
185 }
186 }
187
188 /* Set the PLL division factors */
189 hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
190 hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2) | ((PLLInit->PLLIDF)<<11) | ((PLLInit->PLLODF)<<16));
191
192 /* Enable the DSI PLL */
193 __HAL_DSI_PLL_ENABLE(hdsi);
194
195 /* Get tick */
196 tickstart = HAL_GetTick();
197
198 /* Wait for the lock of the PLL */
199 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
200 {
201 /* Check for the Timeout */
202 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
203 {
204 return HAL_TIMEOUT;
205 }
206 }
207
208 /*************************** Set the PHY parameters ***************************/
209
210 /* D-PHY clock and digital enable*/
211 hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
212
213 /* Clock lane configuration */
214 hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
215 hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
216
217 /* Configure the number of active data lanes */
218 hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
219 hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
220
221 /************************ Set the DSI clock parameters ************************/
222
223 /* Set the TX escape clock division factor */
224 hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
225 hdsi->Instance->CCR = hdsi->Init.TXEscapeCkdiv;
226
227 /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
228 /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
229 /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
230 tempIDF = (PLLInit->PLLIDF > 0) ? PLLInit->PLLIDF : 1;
231 unitIntervalx4 = (4000000 * tempIDF * (1 << PLLInit->PLLODF)) / ((HSE_VALUE/1000) * PLLInit->PLLNDIV);
232
233 /* Set the bit period in high-speed mode */
234 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_UIX4;
235 hdsi->Instance->WPCR[0] |= unitIntervalx4;
236
237 /****************************** Error management *****************************/
238
239 /* Disable all error interrupts and reset the Error Mask */
240 hdsi->Instance->IER[0] = 0;
241 hdsi->Instance->IER[1] = 0;
242 hdsi->ErrorMsk = 0;
243
244 /* Initialise the error code */
245 hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
246
247 /* Initialize the DSI state*/
248 hdsi->State = HAL_DSI_STATE_READY;
249
250 return HAL_OK;
251}
252
253/**
254 * @brief De-initializes the DSI peripheral registers to their default reset
255 * values.
256 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
257 * the configuration information for the DSI.
258 * @retval HAL status
259 */
260HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
261{
262 /* Check the DSI handle allocation */
263 if(hdsi == NULL)
264 {
265 return HAL_ERROR;
266 }
267
268 /* Change DSI peripheral state */
269 hdsi->State = HAL_DSI_STATE_BUSY;
270
271 /* Disable the DSI wrapper */
272 __HAL_DSI_WRAPPER_DISABLE(hdsi);
273
274 /* Disable the DSI host */
275 __HAL_DSI_DISABLE(hdsi);
276
277 /* D-PHY clock and digital disable */
278 hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);
279
280 /* Turn off the DSI PLL */
281 __HAL_DSI_PLL_DISABLE(hdsi);
282
283 /* Disable the regulator */
284 __HAL_DSI_REG_DISABLE(hdsi);
285
286 /* DeInit the low level hardware */
287 HAL_DSI_MspDeInit(hdsi);
288
289 /* Initialise the error code */
290 hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
291
292 /* Initialize the DSI state*/
293 hdsi->State = HAL_DSI_STATE_RESET;
294
295 /* Release Lock */
296 __HAL_UNLOCK(hdsi);
297
298 return HAL_OK;
299}
300
301/**
302 * @brief Return the DSI error code
303 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
304 * the configuration information for the DSI.
305 * @retval DSI Error Code
306 */
307uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
308{
309 /* Get the error code */
310 return hdsi->ErrorCode;
311}
312
313/**
314 * @brief Enable the error monitor flags
315 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
316 * the configuration information for the DSI.
317 * @param ActiveErrors: indicates which error interrupts will be enabled.
318 * This parameter can be any combination of @ref DSI_Error_Data_Type.
319 * @retval HAL status
320 */
321HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
322{
323 /* Process locked */
324 __HAL_LOCK(hdsi);
325
326 hdsi->Instance->IER[0] = 0;
327 hdsi->Instance->IER[1] = 0;
328
329 /* Store active errors to the handle */
330 hdsi->ErrorMsk = ActiveErrors;
331
332 if(ActiveErrors & HAL_DSI_ERROR_ACK)
333 {
334 /* Enable the interrupt generation on selected errors */
335 hdsi->Instance->IER[0] |= DSI_ERROR_ACK_MASK;
336 }
337
338 if(ActiveErrors & HAL_DSI_ERROR_PHY)
339 {
340 /* Enable the interrupt generation on selected errors */
341 hdsi->Instance->IER[0] |= DSI_ERROR_PHY_MASK;
342 }
343
344 if(ActiveErrors & HAL_DSI_ERROR_TX)
345 {
346 /* Enable the interrupt generation on selected errors */
347 hdsi->Instance->IER[1] |= DSI_ERROR_TX_MASK;
348 }
349
350 if(ActiveErrors & HAL_DSI_ERROR_RX)
351 {
352 /* Enable the interrupt generation on selected errors */
353 hdsi->Instance->IER[1] |= DSI_ERROR_RX_MASK;
354 }
355
356 if(ActiveErrors & HAL_DSI_ERROR_ECC)
357 {
358 /* Enable the interrupt generation on selected errors */
359 hdsi->Instance->IER[1] |= DSI_ERROR_ECC_MASK;
360 }
361
362 if(ActiveErrors & HAL_DSI_ERROR_CRC)
363 {
364 /* Enable the interrupt generation on selected errors */
365 hdsi->Instance->IER[1] |= DSI_ERROR_CRC_MASK;
366 }
367
368 if(ActiveErrors & HAL_DSI_ERROR_PSE)
369 {
370 /* Enable the interrupt generation on selected errors */
371 hdsi->Instance->IER[1] |= DSI_ERROR_PSE_MASK;
372 }
373
374 if(ActiveErrors & HAL_DSI_ERROR_EOT)
375 {
376 /* Enable the interrupt generation on selected errors */
377 hdsi->Instance->IER[1] |= DSI_ERROR_EOT_MASK;
378 }
379
380 if(ActiveErrors & HAL_DSI_ERROR_OVF)
381 {
382 /* Enable the interrupt generation on selected errors */
383 hdsi->Instance->IER[1] |= DSI_ERROR_OVF_MASK;
384 }
385
386 if(ActiveErrors & HAL_DSI_ERROR_GEN)
387 {
388 /* Enable the interrupt generation on selected errors */
389 hdsi->Instance->IER[1] |= DSI_ERROR_GEN_MASK;
390 }
391
392 /* Process Unlocked */
393 __HAL_UNLOCK(hdsi);
394
395 return HAL_OK;
396}
397
398/**
399 * @brief Initializes the DSI MSP.
400 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
401 * the configuration information for the DSI.
402 * @retval None
403 */
404__weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)
405{
406 /* NOTE : This function Should not be modified, when the callback is needed,
407 the HAL_DSI_MspInit could be implemented in the user file
408 */
409}
410
411/**
412 * @brief De-initializes the DSI MSP.
413 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
414 * the configuration information for the DSI.
415 * @retval None
416 */
417__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)
418{
419 /* NOTE : This function Should not be modified, when the callback is needed,
420 the HAL_DSI_MspDeInit could be implemented in the user file
421 */
422}
423
424/**
425 * @}
426 */
427
428/** @defgroup DSI_Group2 IO operation functions
429 * @brief IO operation functions
430 *
431@verbatim
432 ===============================================================================
433 ##### IO operation functions #####
434 ===============================================================================
435 [..] This section provides function allowing to:
436 (+) Handle DSI interrupt request
437
438@endverbatim
439 * @{
440 */
441/**
442 * @brief Handles DSI interrupt request.
443 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
444 * the configuration information for the DSI.
445 * @retval HAL status
446 */
447void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
448{
449 uint32_t ErrorStatus0, ErrorStatus1;
450
451 /* Tearing Effect Interrupt management ***************************************/
452 if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET)
453 {
454 if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET)
455 {
456 /* Clear the Tearing Effect Interrupt Flag */
457 __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
458
459 /* Tearing Effect Callback */
460 HAL_DSI_TearingEffectCallback(hdsi);
461 }
462 }
463
464 /* End of Refresh Interrupt management ***************************************/
465 if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET)
466 {
467 if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET)
468 {
469 /* Clear the End of Refresh Interrupt Flag */
470 __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
471
472 /* End of Refresh Callback */
473 HAL_DSI_EndOfRefreshCallback(hdsi);
474 }
475 }
476
477 /* Error Interrupts management ***********************************************/
478 if(hdsi->ErrorMsk != 0)
479 {
480 ErrorStatus0 = hdsi->Instance->ISR[0];
481 ErrorStatus0 &= hdsi->Instance->IER[0];
482 ErrorStatus1 = hdsi->Instance->ISR[1];
483 ErrorStatus1 &= hdsi->Instance->IER[1];
484
485 if(ErrorStatus0 & DSI_ERROR_ACK_MASK)
486 {
487 hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
488 }
489
490 if(ErrorStatus0 & DSI_ERROR_PHY_MASK)
491 {
492 hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
493 }
494
495 if(ErrorStatus1 & DSI_ERROR_TX_MASK)
496 {
497 hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
498 }
499
500 if(ErrorStatus1 & DSI_ERROR_RX_MASK)
501 {
502 hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
503 }
504
505 if(ErrorStatus1 & DSI_ERROR_ECC_MASK)
506 {
507 hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
508 }
509
510 if(ErrorStatus1 & DSI_ERROR_CRC_MASK)
511 {
512 hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
513 }
514
515 if(ErrorStatus1 & DSI_ERROR_PSE_MASK)
516 {
517 hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
518 }
519
520 if(ErrorStatus1 & DSI_ERROR_EOT_MASK)
521 {
522 hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
523 }
524
525 if(ErrorStatus1 & DSI_ERROR_OVF_MASK)
526 {
527 hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
528 }
529
530 if(ErrorStatus1 & DSI_ERROR_GEN_MASK)
531 {
532 hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
533 }
534
535 /* Check only selected errors */
536 if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
537 {
538 /* DSI error interrupt user callback */
539 HAL_DSI_ErrorCallback(hdsi);
540 }
541 }
542}
543
544/**
545 * @brief Tearing Effect DSI callback.
546 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
547 * the configuration information for the DSI.
548 * @retval None
549 */
550__weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
551{
552 /* NOTE : This function Should not be modified, when the callback is needed,
553 the HAL_DSI_TearingEffectCallback could be implemented in the user file
554 */
555}
556
557/**
558 * @brief End of Refresh DSI callback.
559 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
560 * the configuration information for the DSI.
561 * @retval None
562 */
563__weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
564{
565 /* NOTE : This function Should not be modified, when the callback is needed,
566 the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
567 */
568}
569
570/**
571 * @brief Operation Error DSI callback.
572 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
573 * the configuration information for the DSI.
574 * @retval None
575 */
576__weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
577{
578 /* NOTE : This function Should not be modified, when the callback is needed,
579 the HAL_DSI_ErrorCallback could be implemented in the user file
580 */
581}
582
583/**
584 * @}
585 */
586
587/** @defgroup DSI_Group3 Peripheral Control functions
588 * @brief Peripheral Control functions
589 *
590@verbatim
591 ===============================================================================
592 ##### Peripheral Control functions #####
593 ===============================================================================
594 [..] This section provides functions allowing to:
595 (+)
596 (+)
597 (+)
598
599@endverbatim
600 * @{
601 */
602
603/**
604 * @brief Configure the Generic interface read-back Virtual Channel ID.
605 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
606 * the configuration information for the DSI.
607 * @param VirtualChannelID: Virtual channel ID
608 * @retval HAL status
609 */
610HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
611{
612 /* Process locked */
613 __HAL_LOCK(hdsi);
614
615 /* Update the GVCID register */
616 hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;
617 hdsi->Instance->GVCIDR |= VirtualChannelID;
618
619 /* Process unlocked */
620 __HAL_UNLOCK(hdsi);
621
622 return HAL_OK;
623}
624
625/**
626 * @brief Select video mode and configure the corresponding parameters
627 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
628 * the configuration information for the DSI.
629 * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains
630 * the DSI video mode configuration parameters
631 * @retval HAL status
632 */
633HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
634{
635 /* Process locked */
636 __HAL_LOCK(hdsi);
637
638 /* Check the parameters */
639 assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
640 assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
641 assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
642 assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
643 assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
644 assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
645 assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
646 assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
647 assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
648 assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
649 assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
650 assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
651 assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
652 /* Check the LooselyPacked variant only in 18-bit mode */
653 if(VidCfg->ColorCoding == DSI_RGB666)
654 {
655 assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
656 }
657
658 /* Select video mode by resetting CMDM and DSIM bits */
659 hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
660 hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
661
662 /* Configure the video mode transmission type */
663 hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
664 hdsi->Instance->VMCR |= VidCfg->Mode;
665
666 /* Configure the video packet size */
667 hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
668 hdsi->Instance->VPCR |= VidCfg->PacketSize;
669
670 /* Set the chunks number to be transmitted through the DSI link */
671 hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
672 hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;
673
674 /* Set the size of the null packet */
675 hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
676 hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;
677
678 /* Select the virtual channel for the LTDC interface traffic */
679 hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
680 hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;
681
682 /* Configure the polarity of control signals */
683 hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
684 hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);
685
686 /* Select the color coding for the host */
687 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
688 hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;
689
690 /* Select the color coding for the wrapper */
691 hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
692 hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1);
693
694 /* Enable/disable the loosely packed variant to 18-bit configuration */
695 if(VidCfg->ColorCoding == DSI_RGB666)
696 {
697 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
698 hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
699 }
700
701 /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
702 hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
703 hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;
704
705 /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
706 hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
707 hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;
708
709 /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
710 hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
711 hdsi->Instance->VLCR |= VidCfg->HorizontalLine;
712
713 /* Set the Vertical Synchronization Active (VSA) */
714 hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
715 hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;
716
717 /* Set the Vertical Back Porch (VBP)*/
718 hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
719 hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;
720
721 /* Set the Vertical Front Porch (VFP)*/
722 hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
723 hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;
724
725 /* Set the Vertical Active period*/
726 hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
727 hdsi->Instance->VVACR |= VidCfg->VerticalActive;
728
729 /* Configure the command transmission mode */
730 hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
731 hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;
732
733 /* Low power largest packet size */
734 hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
735 hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16);
736
737 /* Low power VACT largest packet size */
738 hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
739 hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;
740
741 /* Enable LP transition in HFP period */
742 hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
743 hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;
744
745 /* Enable LP transition in HBP period */
746 hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
747 hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;
748
749 /* Enable LP transition in VACT period */
750 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
751 hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;
752
753 /* Enable LP transition in VFP period */
754 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
755 hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;
756
757 /* Enable LP transition in VBP period */
758 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
759 hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;
760
761 /* Enable LP transition in vertical sync period */
762 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
763 hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;
764
765 /* Enable the request for an acknowledge response at the end of a frame */
766 hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
767 hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;
768
769 /* Process unlocked */
770 __HAL_UNLOCK(hdsi);
771
772 return HAL_OK;
773}
774
775/**
776 * @brief Select adapted command mode and configure the corresponding parameters
777 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
778 * the configuration information for the DSI.
779 * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains
780 * the DSI command mode configuration parameters
781 * @retval HAL status
782 */
783HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)
784{
785 /* Process locked */
786 __HAL_LOCK(hdsi);
787
788 /* Check the parameters */
789 assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
790 assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
791 assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
792 assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
793 assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
794 assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
795 assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
796 assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
797 assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
798
799 /* Select command mode by setting CMDM and DSIM bits */
800 hdsi->Instance->MCR |= DSI_MCR_CMDM;
801 hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
802 hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;
803
804 /* Select the virtual channel for the LTDC interface traffic */
805 hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
806 hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;
807
808 /* Configure the polarity of control signals */
809 hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
810 hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);
811
812 /* Select the color coding for the host */
813 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
814 hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;
815
816 /* Select the color coding for the wrapper */
817 hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
818 hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1);
819
820 /* Configure the maximum allowed size for write memory command */
821 hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
822 hdsi->Instance->LCCR |= CmdCfg->CommandSize;
823
824 /* Configure the tearing effect source and polarity and select the refresh mode */
825 hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
826 hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol);
827
828 /* Configure the tearing effect acknowledge request */
829 hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
830 hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;
831
832 /* Enable the Tearing Effect interrupt */
833 __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
834
835 /* Enable the End of Refresh interrupt */
836 __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
837
838 /* Process unlocked */
839 __HAL_UNLOCK(hdsi);
840
841 return HAL_OK;
842}
843
844/**
845 * @brief Configure command transmission mode: High-speed or Low-power
846 * and enable/disable acknowledge request after packet transmission
847 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
848 * the configuration information for the DSI.
849 * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains
850 * the DSI command transmission mode configuration parameters
851 * @retval HAL status
852 */
853HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)
854{
855 /* Process locked */
856 __HAL_LOCK(hdsi);
857
858 assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
859 assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
860 assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
861 assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
862 assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
863 assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
864 assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
865 assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
866 assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
867 assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
868 assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
869 assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
870 assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
871
872 /* Select High-speed or Low-power for command transmission */
873 hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\
874 DSI_CMCR_GSW1TX |\
875 DSI_CMCR_GSW2TX |\
876 DSI_CMCR_GSR0TX |\
877 DSI_CMCR_GSR1TX |\
878 DSI_CMCR_GSR2TX |\
879 DSI_CMCR_GLWTX |\
880 DSI_CMCR_DSW0TX |\
881 DSI_CMCR_DSW1TX |\
882 DSI_CMCR_DSR0TX |\
883 DSI_CMCR_DLWTX |\
884 DSI_CMCR_MRDPS);
885 hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\
886 LPCmd->LPGenShortWriteOneP |\
887 LPCmd->LPGenShortWriteTwoP |\
888 LPCmd->LPGenShortReadNoP |\
889 LPCmd->LPGenShortReadOneP |\
890 LPCmd->LPGenShortReadTwoP |\
891 LPCmd->LPGenLongWrite |\
892 LPCmd->LPDcsShortWriteNoP |\
893 LPCmd->LPDcsShortWriteOneP |\
894 LPCmd->LPDcsShortReadNoP |\
895 LPCmd->LPDcsLongWrite |\
896 LPCmd->LPMaxReadPacket);
897
898 /* Configure the acknowledge request after each packet transmission */
899 hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
900 hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;
901
902 /* Process unlocked */
903 __HAL_UNLOCK(hdsi);
904
905 return HAL_OK;
906}
907
908/**
909 * @brief Configure the flow control parameters
910 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
911 * the configuration information for the DSI.
912 * @param FlowControl: flow control feature(s) to be enabled.
913 * This parameter can be any combination of @ref DSI_FlowControl.
914 * @retval HAL status
915 */
916HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
917{
918 /* Process locked */
919 __HAL_LOCK(hdsi);
920
921 /* Check the parameters */
922 assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
923
924 /* Set the DSI Host Protocol Configuration Register */
925 hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
926 hdsi->Instance->PCR |= FlowControl;
927
928 /* Process unlocked */
929 __HAL_UNLOCK(hdsi);
930
931 return HAL_OK;
932}
933
934/**
935 * @brief Configure the DSI PHY timer parameters
936 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
937 * the configuration information for the DSI.
938 * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains
939 * the DSI PHY timing parameters
940 * @retval HAL status
941 */
942HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)
943{
944 uint32_t maxTime;
945 /* Process locked */
946 __HAL_LOCK(hdsi);
947
948 maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime;
949
950 /* Clock lane timer configuration */
951
952 /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
953 High-Speed transmission.
954 To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
955 to Low-Power and from Low-Power to High-Speed.
956 This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
957 But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
958
959 Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
960 */
961 hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
962 hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16));
963
964 /* Data lane timer configuration */
965 hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
966 hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16) | ((PhyTimers->DataLaneHS2LPTime)<<24));
967
968 /* Configure the wait period to request HS transmission after a stop state */
969 hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
970 hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8);
971
972 /* Process unlocked */
973 __HAL_UNLOCK(hdsi);
974
975 return HAL_OK;
976}
977
978/**
979 * @brief Configure the DSI HOST timeout parameters
980 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
981 * the configuration information for the DSI.
982 * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains
983 * the DSI host timeout parameters
984 * @retval HAL status
985 */
986HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)
987{
988 /* Process locked */
989 __HAL_LOCK(hdsi);
990
991 /* Set the timeout clock division factor */
992 hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
993 hdsi->Instance->CCR = ((HostTimeouts->TimeoutCkdiv)<<8);
994
995 /* High-speed transmission timeout */
996 hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_HSTX_TOCNT;
997 hdsi->Instance->TCCR[0] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16);
998
999 /* Low-power reception timeout */
1000 hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_LPRX_TOCNT;
1001 hdsi->Instance->TCCR[0] |= HostTimeouts->LowPowerReceptionTimeout;
1002
1003 /* High-speed read timeout */
1004 hdsi->Instance->TCCR[1] &= ~DSI_TCCR1_HSRD_TOCNT;
1005 hdsi->Instance->TCCR[1] |= HostTimeouts->HighSpeedReadTimeout;
1006
1007 /* Low-power read timeout */
1008 hdsi->Instance->TCCR[2] &= ~DSI_TCCR2_LPRD_TOCNT;
1009 hdsi->Instance->TCCR[2] |= HostTimeouts->LowPowerReadTimeout;
1010
1011 /* High-speed write timeout */
1012 hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_HSWR_TOCNT;
1013 hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWriteTimeout;
1014
1015 /* High-speed write presp mode */
1016 hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_PM;
1017 hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWritePrespMode;
1018
1019 /* Low-speed write timeout */
1020 hdsi->Instance->TCCR[4] &= ~DSI_TCCR4_LPWR_TOCNT;
1021 hdsi->Instance->TCCR[4] |= HostTimeouts->LowPowerWriteTimeout;
1022
1023 /* BTA timeout */
1024 hdsi->Instance->TCCR[5] &= ~DSI_TCCR5_BTA_TOCNT;
1025 hdsi->Instance->TCCR[5] |= HostTimeouts->BTATimeout;
1026
1027 /* Process unlocked */
1028 __HAL_UNLOCK(hdsi);
1029
1030 return HAL_OK;
1031}
1032
1033/**
1034 * @brief Start the DSI module
1035 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1036 * the configuration information for the DSI.
1037 * @retval HAL status
1038 */
1039HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
1040{
1041 /* Process locked */
1042 __HAL_LOCK(hdsi);
1043
1044 /* Enable the DSI host */
1045 __HAL_DSI_ENABLE(hdsi);
1046
1047 /* Enable the DSI wrapper */
1048 __HAL_DSI_WRAPPER_ENABLE(hdsi);
1049
1050 /* Process unlocked */
1051 __HAL_UNLOCK(hdsi);
1052
1053 return HAL_OK;
1054}
1055
1056/**
1057 * @brief Stop the DSI module
1058 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1059 * the configuration information for the DSI.
1060 * @retval HAL status
1061 */
1062HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
1063{
1064 /* Process locked */
1065 __HAL_LOCK(hdsi);
1066
1067 /* Disable the DSI host */
1068 __HAL_DSI_DISABLE(hdsi);
1069
1070 /* Disable the DSI wrapper */
1071 __HAL_DSI_WRAPPER_DISABLE(hdsi);
1072
1073 /* Process unlocked */
1074 __HAL_UNLOCK(hdsi);
1075
1076 return HAL_OK;
1077}
1078
1079/**
1080 * @brief Refresh the display in command mode
1081 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1082 * the configuration information for the DSI.
1083 * @retval HAL status
1084 */
1085HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
1086{
1087 /* Process locked */
1088 __HAL_LOCK(hdsi);
1089
1090 /* Update the display */
1091 hdsi->Instance->WCR |= DSI_WCR_LTDCEN;
1092
1093 /* Process unlocked */
1094 __HAL_UNLOCK(hdsi);
1095
1096 return HAL_OK;
1097}
1098
1099/**
1100 * @brief Controls the display color mode in Video mode
1101 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1102 * the configuration information for the DSI.
1103 * @param ColorMode: Color mode (full or 8-colors).
1104 * This parameter can be any value of @ref DSI_Color_Mode
1105 * @retval HAL status
1106 */
1107HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
1108{
1109 /* Process locked */
1110 __HAL_LOCK(hdsi);
1111
1112 /* Check the parameters */
1113 assert_param(IS_DSI_COLOR_MODE(ColorMode));
1114
1115 /* Update the display color mode */
1116 hdsi->Instance->WCR &= ~DSI_WCR_COLM;
1117 hdsi->Instance->WCR |= ColorMode;
1118
1119 /* Process unlocked */
1120 __HAL_UNLOCK(hdsi);
1121
1122 return HAL_OK;
1123}
1124
1125/**
1126 * @brief Control the display shutdown in Video mode
1127 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1128 * the configuration information for the DSI.
1129 * @param Shutdown: Shut-down (Display-ON or Display-OFF).
1130 * This parameter can be any value of @ref DSI_ShutDown
1131 * @retval HAL status
1132 */
1133HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
1134{
1135 /* Process locked */
1136 __HAL_LOCK(hdsi);
1137
1138 /* Check the parameters */
1139 assert_param(IS_DSI_SHUT_DOWN(Shutdown));
1140
1141 /* Update the display Shutdown */
1142 hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
1143 hdsi->Instance->WCR |= Shutdown;
1144
1145 /* Process unlocked */
1146 __HAL_UNLOCK(hdsi);
1147
1148 return HAL_OK;
1149}
1150
1151/**
1152 * @brief DCS or Generic short write command
1153 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1154 * the configuration information for the DSI.
1155 * @param ChannelID: Virtual channel ID.
1156 * @param Mode: DSI short packet data type.
1157 * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
1158 * @param Param1: DSC command or first generic parameter.
1159 * This parameter can be any value of @ref DSI_DCS_Command or a
1160 * generic command code.
1161 * @param Param2: DSC parameter or second generic parameter.
1162 * @retval HAL status
1163 */
1164HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
1165 uint32_t ChannelID,
1166 uint32_t Mode,
1167 uint32_t Param1,
1168 uint32_t Param2)
1169{
1170 uint32_t tickstart = 0;
1171
1172 /* Process locked */
1173 __HAL_LOCK(hdsi);
1174
1175 /* Check the parameters */
1176 assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
1177
1178 /* Get tick */
1179 tickstart = HAL_GetTick();
1180
1181 /* Wait for Command FIFO Empty */
1182 while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0)
1183 {
1184 /* Check for the Timeout */
1185 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1186 {
1187 /* Process Unlocked */
1188 __HAL_UNLOCK(hdsi);
1189
1190 return HAL_TIMEOUT;
1191 }
1192 }
1193
1194 /* Configure the packet to send a short DCS command with 0 or 1 parameter */
1195 DSI_ConfigPacketHeader(hdsi->Instance,
1196 ChannelID,
1197 Mode,
1198 Param1,
1199 Param2);
1200
1201 /* Process unlocked */
1202 __HAL_UNLOCK(hdsi);
1203
1204 return HAL_OK;
1205}
1206
1207/**
1208 * @brief DCS or Generic long write command
1209 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1210 * the configuration information for the DSI.
1211 * @param ChannelID: Virtual channel ID.
1212 * @param Mode: DSI long packet data type.
1213 * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.
1214 * @param NbParams: Number of parameters.
1215 * @param Param1: DSC command or first generic parameter.
1216 * This parameter can be any value of @ref DSI_DCS_Command or a
1217 * generic command code
1218 * @param ParametersTable: Pointer to parameter values table.
1219 * @retval HAL status
1220 */
1221HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
1222 uint32_t ChannelID,
1223 uint32_t Mode,
1224 uint32_t NbParams,
1225 uint32_t Param1,
1226 uint8_t* ParametersTable)
1227{
1228 uint32_t uicounter = 0;
1229 uint32_t tickstart = 0;
1230
1231 /* Process locked */
1232 __HAL_LOCK(hdsi);
1233
1234 /* Check the parameters */
1235 assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
1236
1237 /* Get tick */
1238 tickstart = HAL_GetTick();
1239
1240 /* Wait for Command FIFO Empty */
1241 while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET)
1242 {
1243 /* Check for the Timeout */
1244 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1245 {
1246 /* Process Unlocked */
1247 __HAL_UNLOCK(hdsi);
1248
1249 return HAL_TIMEOUT;
1250 }
1251 }
1252
1253 /* Set the DCS code hexadecimal on payload byte 1, and the other parameters on the write FIFO command*/
1254 while(uicounter < NbParams)
1255 {
1256 if(uicounter == 0x00)
1257 {
1258 hdsi->Instance->GPDR=(Param1 | \
1259 ((*(ParametersTable+uicounter))<<8) | \
1260 ((*(ParametersTable+uicounter+1))<<16) | \
1261 ((*(ParametersTable+uicounter+2))<<24));
1262 uicounter += 3;
1263 }
1264 else
1265 {
1266 hdsi->Instance->GPDR=((*(ParametersTable+uicounter)) | \
1267 ((*(ParametersTable+uicounter+1))<<8) | \
1268 ((*(ParametersTable+uicounter+2))<<16) | \
1269 ((*(ParametersTable+uicounter+3))<<24));
1270 uicounter+=4;
1271 }
1272 }
1273
1274 /* Configure the packet to send a long DCS command */
1275 DSI_ConfigPacketHeader(hdsi->Instance,
1276 ChannelID,
1277 Mode,
1278 ((NbParams+1)&0x00FF),
1279 (((NbParams+1)&0xFF00)>>8));
1280
1281 /* Process unlocked */
1282 __HAL_UNLOCK(hdsi);
1283
1284 return HAL_OK;
1285}
1286
1287/**
1288 * @brief Read command (DCS or generic)
1289 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1290 * the configuration information for the DSI.
1291 * @param ChannelNbr: Virtual channel ID
1292 * @param Array: pointer to a buffer to store the payload of a read back operation.
1293 * @param Size: Data size to be read (in byte).
1294 * @param Mode: DSI read packet data type.
1295 * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.
1296 * @param DCSCmd: DCS get/read command.
1297 * @param ParametersTable: Pointer to parameter values table.
1298 * @retval HAL status
1299 */
1300HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
1301 uint32_t ChannelNbr,
1302 uint8_t* Array,
1303 uint32_t Size,
1304 uint32_t Mode,
1305 uint32_t DCSCmd,
1306 uint8_t* ParametersTable)
1307{
1308 uint32_t tickstart = 0;
1309
1310 /* Process locked */
1311 __HAL_LOCK(hdsi);
1312
1313 /* Check the parameters */
1314 assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
1315
1316 if(Size > 2)
1317 {
1318 /* set max return packet size */
1319 HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((Size)&0xFF), (((Size)>>8)&0xFF));
1320 }
1321
1322 /* Configure the packet to read command */
1323 if (Mode == DSI_DCS_SHORT_PKT_READ)
1324 {
1325 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0);
1326 }
1327 else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
1328 {
1329 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0, 0);
1330 }
1331 else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
1332 {
1333 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], 0);
1334 }
1335 else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
1336 {
1337 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], ParametersTable[1]);
1338 }
1339
1340 /* Get tick */
1341 tickstart = HAL_GetTick();
1342
1343 /* Check that the payload read FIFO is not empty */
1344 while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE)
1345 {
1346 /* Check for the Timeout */
1347 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1348 {
1349 /* Process Unlocked */
1350 __HAL_UNLOCK(hdsi);
1351
1352 return HAL_TIMEOUT;
1353 }
1354 }
1355
1356 /* Get the first byte */
1357 *((uint32_t *)Array) = (hdsi->Instance->GPDR);
1358 if (Size > 4)
1359 {
1360 Size -= 4;
1361 Array += 4;
1362 }
1363 else
1364 {
1365 /* Process unlocked */
1366 __HAL_UNLOCK(hdsi);
1367
1368 return HAL_OK;
1369 }
1370
1371 /* Get tick */
1372 tickstart = HAL_GetTick();
1373
1374 /* Get the remaining bytes if any */
1375 while(((int)(Size)) > 0)
1376 {
1377 if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0)
1378 {
1379 *((uint32_t *)Array) = (hdsi->Instance->GPDR);
1380 Size -= 4;
1381 Array += 4;
1382 }
1383
1384 /* Check for the Timeout */
1385 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1386 {
1387 /* Process Unlocked */
1388 __HAL_UNLOCK(hdsi);
1389
1390 return HAL_TIMEOUT;
1391 }
1392 }
1393
1394 /* Process unlocked */
1395 __HAL_UNLOCK(hdsi);
1396
1397 return HAL_OK;
1398}
1399
1400/**
1401 * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
1402 * (only data lanes are in ULPM)
1403 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1404 * the configuration information for the DSI.
1405 * @retval HAL status
1406 */
1407HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
1408{
1409 uint32_t tickstart = 0;
1410
1411 /* Process locked */
1412 __HAL_LOCK(hdsi);
1413
1414 /* ULPS Request on Data Lanes */
1415 hdsi->Instance->PUCR |= DSI_PUCR_URDL;
1416
1417 /* Get tick */
1418 tickstart = HAL_GetTick();
1419
1420 /* Wait until the D-PHY active lanes enter into ULPM */
1421 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1422 {
1423 while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET)
1424 {
1425 /* Check for the Timeout */
1426 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1427 {
1428 /* Process Unlocked */
1429 __HAL_UNLOCK(hdsi);
1430
1431 return HAL_TIMEOUT;
1432 }
1433 }
1434 }
1435 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1436 {
1437 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET)
1438 {
1439 /* Check for the Timeout */
1440 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1441 {
1442 /* Process Unlocked */
1443 __HAL_UNLOCK(hdsi);
1444
1445 return HAL_TIMEOUT;
1446 }
1447 }
1448 }
1449
1450 /* Process unlocked */
1451 __HAL_UNLOCK(hdsi);
1452
1453 return HAL_OK;
1454}
1455
1456/**
1457 * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
1458 * (only data lanes are in ULPM)
1459 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1460 * the configuration information for the DSI.
1461 * @retval HAL status
1462 */
1463HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
1464{
1465 uint32_t tickstart = 0;
1466
1467 /* Process locked */
1468 __HAL_LOCK(hdsi);
1469
1470 /* Exit ULPS on Data Lanes */
1471 hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
1472
1473 /* Get tick */
1474 tickstart = HAL_GetTick();
1475
1476 /* Wait until all active lanes exit ULPM */
1477 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1478 {
1479 while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
1480 {
1481 /* Check for the Timeout */
1482 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1483 {
1484 /* Process Unlocked */
1485 __HAL_UNLOCK(hdsi);
1486
1487 return HAL_TIMEOUT;
1488 }
1489 }
1490 }
1491 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1492 {
1493 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
1494 {
1495 /* Check for the Timeout */
1496 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1497 {
1498 /* Process Unlocked */
1499 __HAL_UNLOCK(hdsi);
1500
1501 return HAL_TIMEOUT;
1502 }
1503 }
1504 }
1505
1506 /* De-assert the ULPM requests and the ULPM exit bits */
1507 hdsi->Instance->PUCR = 0;
1508
1509 /* Process unlocked */
1510 __HAL_UNLOCK(hdsi);
1511
1512 return HAL_OK;
1513}
1514
1515/**
1516 * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
1517 * (both data and clock lanes are in ULPM)
1518 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1519 * the configuration information for the DSI.
1520 * @retval HAL status
1521 */
1522HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
1523{
1524 uint32_t tickstart = 0;
1525
1526 /* Process locked */
1527 __HAL_LOCK(hdsi);
1528
1529 /* Clock lane configuration: no more HS request */
1530 hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
1531
1532 /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
1533 __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR);
1534
1535 /* ULPS Request on Clock and Data Lanes */
1536 hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);
1537
1538 /* Get tick */
1539 tickstart = HAL_GetTick();
1540
1541 /* Wait until all active lanes exit ULPM */
1542 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1543 {
1544 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET)
1545 {
1546 /* Check for the Timeout */
1547 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1548 {
1549 /* Process Unlocked */
1550 __HAL_UNLOCK(hdsi);
1551
1552 return HAL_TIMEOUT;
1553 }
1554 }
1555 }
1556 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1557 {
1558 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET)
1559 {
1560 /* Check for the Timeout */
1561 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1562 {
1563 /* Process Unlocked */
1564 __HAL_UNLOCK(hdsi);
1565
1566 return HAL_TIMEOUT;
1567 }
1568 }
1569 }
1570
1571 /* Turn off the DSI PLL */
1572 __HAL_DSI_PLL_DISABLE(hdsi);
1573
1574 /* Process unlocked */
1575 __HAL_UNLOCK(hdsi);
1576
1577 return HAL_OK;
1578}
1579
1580/**
1581 * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
1582 * (both data and clock lanes are in ULPM)
1583 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1584 * the configuration information for the DSI.
1585 * @retval HAL status
1586 */
1587HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
1588{
1589 uint32_t tickstart = 0;
1590
1591 /* Process locked */
1592 __HAL_LOCK(hdsi);
1593
1594 /* Turn on the DSI PLL */
1595 __HAL_DSI_PLL_ENABLE(hdsi);
1596
1597 /* Get tick */
1598 tickstart = HAL_GetTick();
1599
1600 /* Wait for the lock of the PLL */
1601 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
1602 {
1603 /* Check for the Timeout */
1604 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1605 {
1606 /* Process Unlocked */
1607 __HAL_UNLOCK(hdsi);
1608
1609 return HAL_TIMEOUT;
1610 }
1611 }
1612
1613 /* Exit ULPS on Clock and Data Lanes */
1614 hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
1615
1616 /* Get tick */
1617 tickstart = HAL_GetTick();
1618
1619 /* Wait until all active lanes exit ULPM */
1620 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1621 {
1622 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
1623 {
1624 /* Check for the Timeout */
1625 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1626 {
1627 /* Process Unlocked */
1628 __HAL_UNLOCK(hdsi);
1629
1630 return HAL_TIMEOUT;
1631 }
1632 }
1633 }
1634 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1635 {
1636 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC))
1637 {
1638 /* Check for the Timeout */
1639 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1640 {
1641 /* Process Unlocked */
1642 __HAL_UNLOCK(hdsi);
1643
1644 return HAL_TIMEOUT;
1645 }
1646 }
1647 }
1648
1649 /* De-assert the ULPM requests and the ULPM exit bits */
1650 hdsi->Instance->PUCR = 0;
1651
1652 /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
1653 __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
1654
1655 /* Restore clock lane configuration to HS */
1656 hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
1657
1658 /* Process unlocked */
1659 __HAL_UNLOCK(hdsi);
1660
1661 return HAL_OK;
1662}
1663
1664/**
1665 * @brief Start test pattern generation
1666 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1667 * the configuration information for the DSI.
1668 * @param Mode: Pattern generator mode
1669 * This parameter can be one of the following values:
1670 * 0 : Color bars (horizontal or vertical)
1671 * 1 : BER pattern (vertical only)
1672 * @param Orientation: Pattern generator orientation
1673 * This parameter can be one of the following values:
1674 * 0 : Vertical color bars
1675 * 1 : Horizontal color bars
1676 * @retval HAL status
1677 */
1678HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
1679{
1680 /* Process locked */
1681 __HAL_LOCK(hdsi);
1682
1683 /* Configure pattern generator mode and orientation */
1684 hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
1685 hdsi->Instance->VMCR |= ((Mode<<20) | (Orientation<<24));
1686
1687 /* Enable pattern generator by setting PGE bit */
1688 hdsi->Instance->VMCR |= DSI_VMCR_PGE;
1689
1690 /* Process unlocked */
1691 __HAL_UNLOCK(hdsi);
1692
1693 return HAL_OK;
1694}
1695
1696/**
1697 * @brief Stop test pattern generation
1698 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1699 * the configuration information for the DSI.
1700 * @retval HAL status
1701 */
1702HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
1703{
1704 /* Process locked */
1705 __HAL_LOCK(hdsi);
1706
1707 /* Disable pattern generator by clearing PGE bit */
1708 hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
1709
1710 /* Process unlocked */
1711 __HAL_UNLOCK(hdsi);
1712
1713 return HAL_OK;
1714}
1715
1716/**
1717 * @brief Set Slew-Rate And Delay Tuning
1718 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1719 * the configuration information for the DSI.
1720 * @param CommDelay: Communication delay to be adjusted.
1721 * This parameter can be any value of @ref DSI_Communication_Delay
1722 * @param Lane: select between clock or data lanes.
1723 * This parameter can be any value of @ref DSI_Lane_Group
1724 * @param Value: Custom value of the slew-rate or delay
1725 * @retval HAL status
1726 */
1727HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)
1728{
1729 /* Process locked */
1730 __HAL_LOCK(hdsi);
1731
1732 /* Check function parameters */
1733 assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
1734 assert_param(IS_DSI_LANE_GROUP(Lane));
1735
1736 switch(CommDelay)
1737 {
1738 case DSI_SLEW_RATE_HSTX:
1739 if(Lane == DSI_CLOCK_LANE)
1740 {
1741 /* High-Speed Transmission Slew Rate Control on Clock Lane */
1742 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCCL;
1743 hdsi->Instance->WPCR[1] |= Value<<16;
1744 }
1745 else if(Lane == DSI_DATA_LANES)
1746 {
1747 /* High-Speed Transmission Slew Rate Control on Data Lanes */
1748 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCDL;
1749 hdsi->Instance->WPCR[1] |= Value<<18;
1750 }
1751 break;
1752 case DSI_SLEW_RATE_LPTX:
1753 if(Lane == DSI_CLOCK_LANE)
1754 {
1755 /* Low-Power transmission Slew Rate Compensation on Clock Lane */
1756 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCCL;
1757 hdsi->Instance->WPCR[1] |= Value<<6;
1758 }
1759 else if(Lane == DSI_DATA_LANES)
1760 {
1761 /* Low-Power transmission Slew Rate Compensation on Data Lanes */
1762 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCDL;
1763 hdsi->Instance->WPCR[1] |= Value<<8;
1764 }
1765 break;
1766 case DSI_HS_DELAY:
1767 if(Lane == DSI_CLOCK_LANE)
1768 {
1769 /* High-Speed Transmission Delay on Clock Lane */
1770 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDCL;
1771 hdsi->Instance->WPCR[1] |= Value;
1772 }
1773 else if(Lane == DSI_DATA_LANES)
1774 {
1775 /* High-Speed Transmission Delay on Data Lanes */
1776 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDDL;
1777 hdsi->Instance->WPCR[1] |= Value<<2;
1778 }
1779 break;
1780 default:
1781 break;
1782 }
1783
1784 /* Process unlocked */
1785 __HAL_UNLOCK(hdsi);
1786
1787 return HAL_OK;
1788}
1789
1790/**
1791 * @brief Low-Power Reception Filter Tuning
1792 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1793 * the configuration information for the DSI.
1794 * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX
1795 * @retval HAL status
1796 */
1797HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
1798{
1799 /* Process locked */
1800 __HAL_LOCK(hdsi);
1801
1802 /* Low-Power RX low-pass Filtering Tuning */
1803 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPRXFT;
1804 hdsi->Instance->WPCR[1] |= Frequency<<25;
1805
1806 /* Process unlocked */
1807 __HAL_UNLOCK(hdsi);
1808
1809 return HAL_OK;
1810}
1811
1812/**
1813 * @brief Activate an additional current path on all lanes to meet the SDDTx parameter
1814 * defined in the MIPI D-PHY specification
1815 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1816 * the configuration information for the DSI.
1817 * @param State: ENABLE or DISABLE
1818 * @retval HAL status
1819 */
1820HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
1821{
1822 /* Process locked */
1823 __HAL_LOCK(hdsi);
1824
1825 /* Check function parameters */
1826 assert_param(IS_FUNCTIONAL_STATE(State));
1827
1828 /* Activate/Disactivate additional current path on all lanes */
1829 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_SDDC;
1830 hdsi->Instance->WPCR[1] |= State<<12;
1831
1832 /* Process unlocked */
1833 __HAL_UNLOCK(hdsi);
1834
1835 return HAL_OK;
1836}
1837
1838/**
1839 * @brief Custom lane pins configuration
1840 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1841 * the configuration information for the DSI.
1842 * @param CustomLane: Function to be applyed on selected lane.
1843 * This parameter can be any value of @ref DSI_CustomLane
1844 * @param Lane: select between clock or data lane 0 or data lane 1.
1845 * This parameter can be any value of @ref DSI_Lane_Select
1846 * @param State: ENABLE or DISABLE
1847 * @retval HAL status
1848 */
1849HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)
1850{
1851 /* Process locked */
1852 __HAL_LOCK(hdsi);
1853
1854 /* Check function parameters */
1855 assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
1856 assert_param(IS_DSI_LANE(Lane));
1857 assert_param(IS_FUNCTIONAL_STATE(State));
1858
1859 switch(CustomLane)
1860 {
1861 case DSI_SWAP_LANE_PINS:
1862 if(Lane == DSI_CLOCK_LANE)
1863 {
1864 /* Swap pins on clock lane */
1865 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWCL;
1866 hdsi->Instance->WPCR[0] |= (State<<6);
1867 }
1868 else if(Lane == DSI_DATA_LANE0)
1869 {
1870 /* Swap pins on data lane 0 */
1871 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL0;
1872 hdsi->Instance->WPCR[0] |= (State<<7);
1873 }
1874 else if(Lane == DSI_DATA_LANE1)
1875 {
1876 /* Swap pins on data lane 1 */
1877 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL1;
1878 hdsi->Instance->WPCR[0] |= (State<<8);
1879 }
1880 break;
1881 case DSI_INVERT_HS_SIGNAL:
1882 if(Lane == DSI_CLOCK_LANE)
1883 {
1884 /* Invert HS signal on clock lane */
1885 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSICL;
1886 hdsi->Instance->WPCR[0] |= (State<<9);
1887 }
1888 else if(Lane == DSI_DATA_LANE0)
1889 {
1890 /* Invert HS signal on data lane 0 */
1891 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL0;
1892 hdsi->Instance->WPCR[0] |= (State<<10);
1893 }
1894 else if(Lane == DSI_DATA_LANE1)
1895 {
1896 /* Invert HS signal on data lane 1 */
1897 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL1;
1898 hdsi->Instance->WPCR[0] |= (State<<11);
1899 }
1900 break;
1901 default:
1902 break;
1903 }
1904
1905 /* Process unlocked */
1906 __HAL_UNLOCK(hdsi);
1907
1908 return HAL_OK;
1909}
1910
1911/**
1912 * @brief Set custom timing for the PHY
1913 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
1914 * the configuration information for the DSI.
1915 * @param Timing: PHY timing to be adjusted.
1916 * This parameter can be any value of @ref DSI_PHY_Timing
1917 * @param State: ENABLE or DISABLE
1918 * @param Value: Custom value of the timing
1919 * @retval HAL status
1920 */
1921HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
1922{
1923 /* Process locked */
1924 __HAL_LOCK(hdsi);
1925
1926 /* Check function parameters */
1927 assert_param(IS_DSI_PHY_TIMING(Timing));
1928 assert_param(IS_FUNCTIONAL_STATE(State));
1929
1930 switch(Timing)
1931 {
1932 case DSI_TCLK_POST:
1933 /* Enable/Disable custom timing setting */
1934 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPOSTEN;
1935 hdsi->Instance->WPCR[0] |= (State<<27);
1936
1937 if(State)
1938 {
1939 /* Set custom value */
1940 hdsi->Instance->WPCR[4] &= ~DSI_WPCR4_TCLKPOST;
1941 hdsi->Instance->WPCR[4] |= Value;
1942 }
1943
1944 break;
1945 case DSI_TLPX_CLK:
1946 /* Enable/Disable custom timing setting */
1947 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXCEN;
1948 hdsi->Instance->WPCR[0] |= (State<<26);
1949
1950 if(State)
1951 {
1952 /* Set custom value */
1953 hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXC;
1954 hdsi->Instance->WPCR[3] |= Value;
1955 }
1956
1957 break;
1958 case DSI_THS_EXIT:
1959 /* Enable/Disable custom timing setting */
1960 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSEXITEN;
1961 hdsi->Instance->WPCR[0] |= (State<<25);
1962
1963 if(State)
1964 {
1965 /* Set custom value */
1966 hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSEXIT;
1967 hdsi->Instance->WPCR[3] |= Value;
1968 }
1969
1970 break;
1971 case DSI_TLPX_DATA:
1972 /* Enable/Disable custom timing setting */
1973 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXDEN;
1974 hdsi->Instance->WPCR[0] |= (State<<24);
1975
1976 if(State)
1977 {
1978 /* Set custom value */
1979 hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXD;
1980 hdsi->Instance->WPCR[3] |= Value;
1981 }
1982
1983 break;
1984 case DSI_THS_ZERO:
1985 /* Enable/Disable custom timing setting */
1986 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSZEROEN;
1987 hdsi->Instance->WPCR[0] |= (State<<23);
1988
1989 if(State)
1990 {
1991 /* Set custom value */
1992 hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSZERO;
1993 hdsi->Instance->WPCR[3] |= Value;
1994 }
1995
1996 break;
1997 case DSI_THS_TRAIL:
1998 /* Enable/Disable custom timing setting */
1999 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSTRAILEN;
2000 hdsi->Instance->WPCR[0] |= (State<<22);
2001
2002 if(State)
2003 {
2004 /* Set custom value */
2005 hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSTRAIL;
2006 hdsi->Instance->WPCR[2] |= Value;
2007 }
2008
2009 break;
2010 case DSI_THS_PREPARE:
2011 /* Enable/Disable custom timing setting */
2012 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSPREPEN;
2013 hdsi->Instance->WPCR[0] |= (State<<21);
2014
2015 if(State)
2016 {
2017 /* Set custom value */
2018 hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSPREP;
2019 hdsi->Instance->WPCR[2] |= Value;
2020 }
2021
2022 break;
2023 case DSI_TCLK_ZERO:
2024 /* Enable/Disable custom timing setting */
2025 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKZEROEN;
2026 hdsi->Instance->WPCR[0] |= (State<<20);
2027
2028 if(State)
2029 {
2030 /* Set custom value */
2031 hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKZERO;
2032 hdsi->Instance->WPCR[2] |= Value;
2033 }
2034
2035 break;
2036 case DSI_TCLK_PREPARE:
2037 /* Enable/Disable custom timing setting */
2038 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPREPEN;
2039 hdsi->Instance->WPCR[0] |= (State<<19);
2040
2041 if(State)
2042 {
2043 /* Set custom value */
2044 hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKPREP;
2045 hdsi->Instance->WPCR[2] |= Value;
2046 }
2047
2048 break;
2049 default:
2050 break;
2051 }
2052
2053 /* Process unlocked */
2054 __HAL_UNLOCK(hdsi);
2055
2056 return HAL_OK;
2057}
2058
2059/**
2060 * @brief Force the Clock/Data Lane in TX Stop Mode
2061 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
2062 * the configuration information for the DSI.
2063 * @param Lane: select between clock or data lanes.
2064 * This parameter can be any value of @ref DSI_Lane_Group
2065 * @param State: ENABLE or DISABLE
2066 * @retval HAL status
2067 */
2068HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
2069{
2070 /* Process locked */
2071 __HAL_LOCK(hdsi);
2072
2073 /* Check function parameters */
2074 assert_param(IS_DSI_LANE_GROUP(Lane));
2075 assert_param(IS_FUNCTIONAL_STATE(State));
2076
2077 if(Lane == DSI_CLOCK_LANE)
2078 {
2079 /* Force/Unforce the Clock Lane in TX Stop Mode */
2080 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMCL;
2081 hdsi->Instance->WPCR[0] |= (State<<12);
2082 }
2083 else if(Lane == DSI_DATA_LANES)
2084 {
2085 /* Force/Unforce the Data Lanes in TX Stop Mode */
2086 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMDL;
2087 hdsi->Instance->WPCR[0] |= (State<<13);
2088 }
2089
2090 /* Process unlocked */
2091 __HAL_UNLOCK(hdsi);
2092
2093 return HAL_OK;
2094}
2095
2096/**
2097 * @brief Forces LP Receiver in Low-Power Mode
2098 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
2099 * the configuration information for the DSI.
2100 * @param State: ENABLE or DISABLE
2101 * @retval HAL status
2102 */
2103HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
2104{
2105 /* Process locked */
2106 __HAL_LOCK(hdsi);
2107
2108 /* Check function parameters */
2109 assert_param(IS_FUNCTIONAL_STATE(State));
2110
2111 /* Force/Unforce LP Receiver in Low-Power Mode */
2112 hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_FLPRXLPM;
2113 hdsi->Instance->WPCR[1] |= State<<22;
2114
2115 /* Process unlocked */
2116 __HAL_UNLOCK(hdsi);
2117
2118 return HAL_OK;
2119}
2120
2121/**
2122 * @brief Force Data Lanes in RX Mode after a BTA
2123 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
2124 * the configuration information for the DSI.
2125 * @param State: ENABLE or DISABLE
2126 * @retval HAL status
2127 */
2128HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
2129{
2130 /* Process locked */
2131 __HAL_LOCK(hdsi);
2132
2133 /* Check function parameters */
2134 assert_param(IS_FUNCTIONAL_STATE(State));
2135
2136 /* Force Data Lanes in RX Mode */
2137 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TDDL;
2138 hdsi->Instance->WPCR[0] |= State<<16;
2139
2140 /* Process unlocked */
2141 __HAL_UNLOCK(hdsi);
2142
2143 return HAL_OK;
2144}
2145
2146/**
2147 * @brief Enable a pull-down on the lanes to prevent from floating states when unused
2148 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
2149 * the configuration information for the DSI.
2150 * @param State: ENABLE or DISABLE
2151 * @retval HAL status
2152 */
2153HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
2154{
2155 /* Process locked */
2156 __HAL_LOCK(hdsi);
2157
2158 /* Check function parameters */
2159 assert_param(IS_FUNCTIONAL_STATE(State));
2160
2161 /* Enable/Disable pull-down on lanes */
2162 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_PDEN;
2163 hdsi->Instance->WPCR[0] |= State<<18;
2164
2165 /* Process unlocked */
2166 __HAL_UNLOCK(hdsi);
2167
2168 return HAL_OK;
2169}
2170
2171/**
2172 * @brief Switch off the contention detection on data lanes
2173 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
2174 * the configuration information for the DSI.
2175 * @param State: ENABLE or DISABLE
2176 * @retval HAL status
2177 */
2178HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
2179{
2180 /* Process locked */
2181 __HAL_LOCK(hdsi);
2182
2183 /* Check function parameters */
2184 assert_param(IS_FUNCTIONAL_STATE(State));
2185
2186 /* Contention Detection on Data Lanes OFF */
2187 hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_CDOFFDL;
2188 hdsi->Instance->WPCR[0] |= State<<14;
2189
2190 /* Process unlocked */
2191 __HAL_UNLOCK(hdsi);
2192
2193 return HAL_OK;
2194}
2195
2196/**
2197 * @}
2198 */
2199
2200/** @defgroup DSI_Group4 Peripheral State and Errors functions
2201 * @brief Peripheral State and Errors functions
2202 *
2203@verbatim
2204 ===============================================================================
2205 ##### Peripheral State and Errors functions #####
2206 ===============================================================================
2207 [..]
2208 This subsection provides functions allowing to
2209 (+) Check the DSI state.
2210 (+) Get error code.
2211
2212@endverbatim
2213 * @{
2214 */
2215
2216/**
2217 * @brief Return the DSI state
2218 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
2219 * the configuration information for the DSI.
2220 * @retval HAL state
2221 */
2222HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
2223{
2224 return hdsi->State;
2225}
2226
2227/**
2228 * @}
2229 */
2230
2231/**
2232 * @}
2233 */
2234#endif /* STM32F469xx || STM32F479xx */
2235#endif /* HAL_DSI_MODULE_ENABLED */
2236/**
2237 * @}
2238 */
2239
2240/**
2241 * @}
2242 */
2243
2244/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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