source: asp3_wo_tecs/trunk/arch/arm_m_gcc/stm32f4xx_stm32cube/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c@ 303

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nucleo_f401re依存部の追加

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1/**
2 ******************************************************************************
3 * @file stm32f4xx_hal_adc.c
4 * @author MCD Application Team
5 * @version V1.4.1
6 * @date 09-October-2015
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the Analog to Digital Convertor (ADC) peripheral:
9 * + Initialization and de-initialization functions
10 * + IO operation functions
11 * + State and errors functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### ADC Peripheral features #####
16 ==============================================================================
17 [..]
18 (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
19 (#) Interrupt generation at the end of conversion, end of injected conversion,
20 and in case of analog watchdog or overrun events
21 (#) Single and continuous conversion modes.
22 (#) Scan mode for automatic conversion of channel 0 to channel x.
23 (#) Data alignment with in-built data coherency.
24 (#) Channel-wise programmable sampling time.
25 (#) External trigger option with configurable polarity for both regular and
26 injected conversion.
27 (#) Dual/Triple mode (on devices with 2 ADCs or more).
28 (#) Configurable DMA data storage in Dual/Triple ADC mode.
29 (#) Configurable delay between conversions in Dual/Triple interleaved mode.
30 (#) ADC conversion type (refer to the datasheets).
31 (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
32 slower speed.
33 (#) ADC input range: VREF(minus) = VIN = VREF(plus).
34 (#) DMA request generation during regular channel conversion.
35
36
37 ##### How to use this driver #####
38 ==============================================================================
39 [..]
40 (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
41 (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
42 (##) ADC pins configuration
43 (+++) Enable the clock for the ADC GPIOs using the following function:
44 __HAL_RCC_GPIOx_CLK_ENABLE()
45 (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
46 (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
47 (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
48 (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
49 (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
50 (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
51 (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
52 (+++) Configure and enable two DMA streams stream for managing data
53 transfer from peripheral to memory (output stream)
54 (+++) Associate the initialized DMA handle to the CRYP DMA handle
55 using __HAL_LINKDMA()
56 (+++) Configure the priority and enable the NVIC for the transfer complete
57 interrupt on the two DMA Streams. The output stream should have higher
58 priority than the input stream.
59
60 *** Configuration of ADC, groups regular/injected, channels parameters ***
61 ==============================================================================
62 [..]
63 (#) Configure the ADC parameters (resolution, data alignment, ...)
64 and regular group parameters (conversion trigger, sequencer, ...)
65 using function HAL_ADC_Init().
66
67 (#) Configure the channels for regular group parameters (channel number,
68 channel rank into sequencer, ..., into regular group)
69 using function HAL_ADC_ConfigChannel().
70
71 (#) Optionally, configure the injected group parameters (conversion trigger,
72 sequencer, ..., of injected group)
73 and the channels for injected group parameters (channel number,
74 channel rank into sequencer, ..., into injected group)
75 using function HAL_ADCEx_InjectedConfigChannel().
76
77 (#) Optionally, configure the analog watchdog parameters (channels
78 monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
79
80 (#) Optionally, for devices with several ADC instances: configure the
81 multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
82
83 *** Execution of ADC conversions ***
84 ==============================================================================
85 [..]
86 (#) ADC driver can be used among three modes: polling, interruption,
87 transfer by DMA.
88
89 *** Polling mode IO operation ***
90 =================================
91 [..]
92 (+) Start the ADC peripheral using HAL_ADC_Start()
93 (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
94 user can specify the value of timeout according to his end application
95 (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
96 (+) Stop the ADC peripheral using HAL_ADC_Stop()
97
98 *** Interrupt mode IO operation ***
99 ===================================
100 [..]
101 (+) Start the ADC peripheral using HAL_ADC_Start_IT()
102 (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
103 (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
104 add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
105 (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
106 add his own code by customization of function pointer HAL_ADC_ErrorCallback
107 (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
108
109 *** DMA mode IO operation ***
110 ==============================
111 [..]
112 (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
113 of data to be transferred at each end of conversion
114 (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
115 add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
116 (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
117 add his own code by customization of function pointer HAL_ADC_ErrorCallback
118 (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
119
120 *** ADC HAL driver macros list ***
121 =============================================
122 [..]
123 Below the list of most used macros in ADC HAL driver.
124
125 (+) __HAL_ADC_ENABLE : Enable the ADC peripheral
126 (+) __HAL_ADC_DISABLE : Disable the ADC peripheral
127 (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
128 (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
129 (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
130 (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
131 (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
132 (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
133
134 [..]
135 (@) You can refer to the ADC HAL driver header file for more useful macros
136
137 *** Deinitialization of ADC ***
138 ==============================================================================
139 [..]
140 (#) Disable the ADC interface
141 (++) ADC clock can be hard reset and disabled at RCC top level.
142 (++) Hard reset of ADC peripherals
143 using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
144 (++) ADC clock disable using the equivalent macro/functions as configuration step.
145 (+++) Example:
146 Into HAL_ADC_MspDeInit() (recommended code location) or with
147 other device clock parameters configuration:
148 (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
149 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
150 (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
151 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
152
153 (#) ADC pins configuration
154 (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
155
156 (#) Optionally, in case of usage of ADC with interruptions:
157 (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
158
159 (#) Optionally, in case of usage of DMA:
160 (++) Deinitialize the DMA using function HAL_DMA_DeInit().
161 (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
162
163 @endverbatim
164 ******************************************************************************
165 * @attention
166 *
167 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
168 *
169 * Redistribution and use in source and binary forms, with or without modification,
170 * are permitted provided that the following conditions are met:
171 * 1. Redistributions of source code must retain the above copyright notice,
172 * this list of conditions and the following disclaimer.
173 * 2. Redistributions in binary form must reproduce the above copyright notice,
174 * this list of conditions and the following disclaimer in the documentation
175 * and/or other materials provided with the distribution.
176 * 3. Neither the name of STMicroelectronics nor the names of its contributors
177 * may be used to endorse or promote products derived from this software
178 * without specific prior written permission.
179 *
180 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
181 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
182 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
183 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
184 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
185 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
186 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
187 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
188 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
189 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
190 *
191 ******************************************************************************
192 */
193
194/* Includes ------------------------------------------------------------------*/
195#include "stm32f4xx_hal.h"
196
197/** @addtogroup STM32F4xx_HAL_Driver
198 * @{
199 */
200
201/** @defgroup ADC ADC
202 * @brief ADC driver modules
203 * @{
204 */
205
206#ifdef HAL_ADC_MODULE_ENABLED
207
208/* Private typedef -----------------------------------------------------------*/
209/* Private define ------------------------------------------------------------*/
210/* Private macro -------------------------------------------------------------*/
211/* Private variables ---------------------------------------------------------*/
212/** @addtogroup ADC_Private_Functions
213 * @{
214 */
215/* Private function prototypes -----------------------------------------------*/
216static void ADC_Init(ADC_HandleTypeDef* hadc);
217static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
218static void ADC_DMAError(DMA_HandleTypeDef *hdma);
219static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
220/**
221 * @}
222 */
223/* Exported functions --------------------------------------------------------*/
224/** @defgroup ADC_Exported_Functions ADC Exported Functions
225 * @{
226 */
227
228/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
229 * @brief Initialization and Configuration functions
230 *
231@verbatim
232 ===============================================================================
233 ##### Initialization and de-initialization functions #####
234 ===============================================================================
235 [..] This section provides functions allowing to:
236 (+) Initialize and configure the ADC.
237 (+) De-initialize the ADC.
238
239@endverbatim
240 * @{
241 */
242
243/**
244 * @brief Initializes the ADCx peripheral according to the specified parameters
245 * in the ADC_InitStruct and initializes the ADC MSP.
246 *
247 * @note This function is used to configure the global features of the ADC (
248 * ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
249 * the rest of the configuration parameters are specific to the regular
250 * channels group (scan mode activation, continuous mode activation,
251 * External trigger source and edge, DMA continuous request after the
252 * last transfer and End of conversion selection).
253 *
254 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
255 * the configuration information for the specified ADC.
256 * @retval HAL status
257 */
258HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
259{
260 /* Check ADC handle */
261 if(hadc == NULL)
262 {
263 return HAL_ERROR;
264 }
265
266 /* Check the parameters */
267 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
268 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
269 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
270 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
271 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
272 assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
273 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
274 assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
275 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
276 assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
277 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
278
279 if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
280 {
281 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
282 }
283
284 if(hadc->State == HAL_ADC_STATE_RESET)
285 {
286 /* Allocate lock resource and initialize it */
287 hadc->Lock = HAL_UNLOCKED;
288 /* Init the low level hardware */
289 HAL_ADC_MspInit(hadc);
290 }
291
292 /* Initialize the ADC state */
293 hadc->State = HAL_ADC_STATE_BUSY;
294
295 /* Set ADC parameters */
296 ADC_Init(hadc);
297
298 /* Set ADC error code to none */
299 hadc->ErrorCode = HAL_ADC_ERROR_NONE;
300
301 /* Initialize the ADC state */
302 hadc->State = HAL_ADC_STATE_READY;
303
304 /* Release Lock */
305 __HAL_UNLOCK(hadc);
306
307 /* Return function status */
308 return HAL_OK;
309}
310
311/**
312 * @brief Deinitializes the ADCx peripheral registers to their default reset values.
313 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
314 * the configuration information for the specified ADC.
315 * @retval HAL status
316 */
317HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
318{
319 /* Check ADC handle */
320 if(hadc == NULL)
321 {
322 return HAL_ERROR;
323 }
324
325 /* Check the parameters */
326 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
327
328 /* Change ADC state */
329 hadc->State = HAL_ADC_STATE_BUSY;
330
331 /* DeInit the low level hardware */
332 HAL_ADC_MspDeInit(hadc);
333
334 /* Set ADC error code to none */
335 hadc->ErrorCode = HAL_ADC_ERROR_NONE;
336
337 /* Change ADC state */
338 hadc->State = HAL_ADC_STATE_RESET;
339
340 /* Return function status */
341 return HAL_OK;
342}
343
344/**
345 * @brief Initializes the ADC MSP.
346 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
347 * the configuration information for the specified ADC.
348 * @retval None
349 */
350__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
351{
352 /* NOTE : This function Should not be modified, when the callback is needed,
353 the HAL_ADC_MspInit could be implemented in the user file
354 */
355}
356
357/**
358 * @brief DeInitializes the ADC MSP.
359 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
360 * the configuration information for the specified ADC.
361 * @retval None
362 */
363__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
364{
365 /* NOTE : This function Should not be modified, when the callback is needed,
366 the HAL_ADC_MspDeInit could be implemented in the user file
367 */
368}
369
370/**
371 * @}
372 */
373
374/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
375 * @brief IO operation functions
376 *
377@verbatim
378 ===============================================================================
379 ##### IO operation functions #####
380 ===============================================================================
381 [..] This section provides functions allowing to:
382 (+) Start conversion of regular channel.
383 (+) Stop conversion of regular channel.
384 (+) Start conversion of regular channel and enable interrupt.
385 (+) Stop conversion of regular channel and disable interrupt.
386 (+) Start conversion of regular channel and enable DMA transfer.
387 (+) Stop conversion of regular channel and disable DMA transfer.
388 (+) Handle ADC interrupt request.
389
390@endverbatim
391 * @{
392 */
393
394/**
395 * @brief Enables ADC and starts conversion of the regular channels.
396 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
397 * the configuration information for the specified ADC.
398 * @retval HAL status
399 */
400HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
401{
402 __IO uint32_t counter = 0;
403
404 /* Check the parameters */
405 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
406 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
407
408 /* Process locked */
409 __HAL_LOCK(hadc);
410
411 /* Check if an injected conversion is ongoing */
412 if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
413 {
414 /* Change ADC state */
415 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
416 }
417 else
418 {
419 /* Change ADC state */
420 hadc->State = HAL_ADC_STATE_BUSY_REG;
421 }
422
423 /* Check if ADC peripheral is disabled in order to enable it and wait during
424 Tstab time the ADC's stabilization */
425 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
426 {
427 /* Enable the Peripheral */
428 __HAL_ADC_ENABLE(hadc);
429
430 /* Delay for ADC stabilization time */
431 /* Compute number of CPU cycles to wait for */
432 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
433 while(counter != 0)
434 {
435 counter--;
436 }
437 }
438
439 /* Process unlocked */
440 __HAL_UNLOCK(hadc);
441
442 /* Check if Multimode enabled */
443 if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
444 {
445 /* if no external trigger present enable software conversion of regular channels */
446 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
447 {
448 /* Enable the selected ADC software conversion for regular group */
449 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
450 }
451 }
452 else
453 {
454 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
455 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
456 {
457 /* Enable the selected ADC software conversion for regular group */
458 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
459 }
460 }
461
462 /* Return function status */
463 return HAL_OK;
464}
465
466/**
467 * @brief Disables ADC and stop conversion of regular channels.
468 *
469 * @note Caution: This function will stop also injected channels.
470 *
471 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
472 * the configuration information for the specified ADC.
473 *
474 * @retval HAL status.
475 */
476HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
477{
478 /* Disable the Peripheral */
479 __HAL_ADC_DISABLE(hadc);
480
481 /* Change ADC state */
482 hadc->State = HAL_ADC_STATE_READY;
483
484 /* Return function status */
485 return HAL_OK;
486}
487
488/**
489 * @brief Poll for regular conversion complete
490 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
491 * conversion) are cleared by this function.
492 * @note This function cannot be used in a particular setup: ADC configured
493 * in DMA mode and polling for end of each conversion (ADC init
494 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
495 * In this case, DMA resets the flag EOC and polling cannot be
496 * performed on each conversion. Nevertheless, polling can still
497 * be performed on the complete sequence.
498 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
499 * the configuration information for the specified ADC.
500 * @param Timeout: Timeout value in millisecond.
501 * @retval HAL status
502 */
503HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
504{
505 uint32_t tickstart = 0;
506
507 /* Verification that ADC configuration is compliant with polling for */
508 /* each conversion: */
509 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
510 /* several ranks and polling for end of each conversion. */
511 /* For code simplicity sake, this particular case is generalized to */
512 /* ADC configured in DMA mode and polling for end of each conversion. */
513 if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
514 HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
515 {
516 /* Update ADC state machine to error */
517 hadc->State = HAL_ADC_STATE_ERROR;
518
519 /* Process unlocked */
520 __HAL_UNLOCK(hadc);
521
522 return HAL_ERROR;
523 }
524
525 /* Get tick */
526 tickstart = HAL_GetTick();
527
528 /* Check End of conversion flag */
529 while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
530 {
531 /* Check for the Timeout */
532 if(Timeout != HAL_MAX_DELAY)
533 {
534 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
535 {
536 hadc->State= HAL_ADC_STATE_TIMEOUT;
537 /* Process unlocked */
538 __HAL_UNLOCK(hadc);
539 return HAL_TIMEOUT;
540 }
541 }
542 }
543
544 /* Check if an injected conversion is ready */
545 if(hadc->State == HAL_ADC_STATE_EOC_INJ)
546 {
547 /* Change ADC state */
548 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
549 }
550 else
551 {
552 /* Change ADC state */
553 hadc->State = HAL_ADC_STATE_EOC_REG;
554 }
555
556 /* Return ADC state */
557 return HAL_OK;
558}
559
560/**
561 * @brief Poll for conversion event
562 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
563 * the configuration information for the specified ADC.
564 * @param EventType: the ADC event type.
565 * This parameter can be one of the following values:
566 * @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
567 * @arg ADC_OVR_EVENT: ADC Overrun event.
568 * @param Timeout: Timeout value in millisecond.
569 * @retval HAL status
570 */
571HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
572{
573 uint32_t tickstart = 0;
574
575 /* Check the parameters */
576 assert_param(IS_ADC_EVENT_TYPE(EventType));
577
578 /* Get tick */
579 tickstart = HAL_GetTick();
580
581 /* Check selected event flag */
582 while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
583 {
584 /* Check for the Timeout */
585 if(Timeout != HAL_MAX_DELAY)
586 {
587 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
588 {
589 hadc->State= HAL_ADC_STATE_TIMEOUT;
590 /* Process unlocked */
591 __HAL_UNLOCK(hadc);
592 return HAL_TIMEOUT;
593 }
594 }
595 }
596
597 /* Check analog watchdog flag */
598 if(EventType == ADC_AWD_EVENT)
599 {
600 /* Change ADC state */
601 hadc->State = HAL_ADC_STATE_AWD;
602
603 /* Clear the ADCx's analog watchdog flag */
604 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
605 }
606 else
607 {
608 /* Change ADC state */
609 hadc->State = HAL_ADC_STATE_ERROR;
610
611 /* Clear the ADCx's Overrun flag */
612 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
613 }
614
615 /* Return ADC state */
616 return HAL_OK;
617}
618
619
620/**
621 * @brief Enables the interrupt and starts ADC conversion of regular channels.
622 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
623 * the configuration information for the specified ADC.
624 * @retval HAL status.
625 */
626HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
627{
628 __IO uint32_t counter = 0;
629
630 /* Check the parameters */
631 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
632 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
633
634 /* Process locked */
635 __HAL_LOCK(hadc);
636
637 /* Check if an injected conversion is ongoing */
638 if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
639 {
640 /* Change ADC state */
641 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
642 }
643 else
644 {
645 /* Change ADC state */
646 hadc->State = HAL_ADC_STATE_BUSY_REG;
647 }
648
649 /* Set ADC error code to none */
650 hadc->ErrorCode = HAL_ADC_ERROR_NONE;
651
652 /* Check if ADC peripheral is disabled in order to enable it and wait during
653 Tstab time the ADC's stabilization */
654 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
655 {
656 /* Enable the Peripheral */
657 __HAL_ADC_ENABLE(hadc);
658
659 /* Delay for ADC stabilization time */
660 /* Compute number of CPU cycles to wait for */
661 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
662 while(counter != 0)
663 {
664 counter--;
665 }
666 }
667
668 /* Enable the ADC overrun interrupt */
669 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
670
671 /* Enable the ADC end of conversion interrupt for regular group */
672 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
673
674 /* Process unlocked */
675 __HAL_UNLOCK(hadc);
676
677 /* Check if Multimode enabled */
678 if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
679 {
680 /* if no external trigger present enable software conversion of regular channels */
681 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
682 {
683 /* Enable the selected ADC software conversion for regular group */
684 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
685 }
686 }
687 else
688 {
689 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
690 if((hadc->Instance == (ADC_TypeDef*)0x40012000) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
691 {
692 /* Enable the selected ADC software conversion for regular group */
693 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
694 }
695 }
696
697 /* Return function status */
698 return HAL_OK;
699}
700
701/**
702 * @brief Disables the interrupt and stop ADC conversion of regular channels.
703 *
704 * @note Caution: This function will stop also injected channels.
705 *
706 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
707 * the configuration information for the specified ADC.
708 * @retval HAL status.
709 */
710HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
711{
712 /* Disable the ADC end of conversion interrupt for regular group */
713 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
714
715 /* Disable the ADC end of conversion interrupt for injected group */
716 __HAL_ADC_DISABLE_IT(hadc, ADC_CR1_JEOCIE);
717
718 /* Enable the Peripheral */
719 __HAL_ADC_DISABLE(hadc);
720
721 /* Change ADC state */
722 hadc->State = HAL_ADC_STATE_READY;
723
724 /* Return function status */
725 return HAL_OK;
726}
727
728/**
729 * @brief Handles ADC interrupt request
730 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
731 * the configuration information for the specified ADC.
732 * @retval None
733 */
734void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
735{
736 uint32_t tmp1 = 0, tmp2 = 0;
737
738 /* Check the parameters */
739 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
740 assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
741 assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
742
743 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);
744 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);
745 /* Check End of conversion flag for regular channels */
746 if(tmp1 && tmp2)
747 {
748 /* Check if an injected conversion is ready */
749 if(hadc->State == HAL_ADC_STATE_EOC_INJ)
750 {
751 /* Change ADC state */
752 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
753 }
754 else
755 {
756 /* Change ADC state */
757 hadc->State = HAL_ADC_STATE_EOC_REG;
758 }
759
760 if((hadc->Init.ContinuousConvMode == DISABLE) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
761 {
762 if(hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
763 {
764 /* DISABLE the ADC end of conversion interrupt for regular group */
765 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
766
767 /* DISABLE the ADC overrun interrupt */
768 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
769 }
770 else
771 {
772 if (hadc->NbrOfCurrentConversionRank == 0)
773 {
774 hadc->NbrOfCurrentConversionRank = hadc->Init.NbrOfConversion;
775 }
776
777 /* Decrement the number of conversion when an interrupt occurs */
778 hadc->NbrOfCurrentConversionRank--;
779
780 /* Check if all conversions are finished */
781 if(hadc->NbrOfCurrentConversionRank == 0)
782 {
783 /* DISABLE the ADC end of conversion interrupt for regular group */
784 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
785
786 /* DISABLE the ADC overrun interrupt */
787 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
788 }
789 }
790 }
791
792 /* Conversion complete callback */
793 HAL_ADC_ConvCpltCallback(hadc);
794
795 /* Clear the ADCx flag for regular end of conversion */
796 __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_EOC);
797 }
798
799 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);
800 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC);
801 /* Check End of conversion flag for injected channels */
802 if(tmp1 && tmp2)
803 {
804 /* Check if a regular conversion is ready */
805 if(hadc->State == HAL_ADC_STATE_EOC_REG)
806 {
807 /* Change ADC state */
808 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
809 }
810 else
811 {
812 /* Change ADC state */
813 hadc->State = HAL_ADC_STATE_EOC_INJ;
814 }
815
816 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
817 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
818 if(((hadc->Init.ContinuousConvMode == DISABLE) || tmp1) && tmp2)
819 {
820 /* DISABLE the ADC end of conversion interrupt for injected group */
821 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
822 }
823
824 /* Conversion complete callback */
825 HAL_ADCEx_InjectedConvCpltCallback(hadc);
826
827 /* Clear the ADCx flag for injected end of conversion */
828 __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_JEOC);
829 }
830
831 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);
832 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD);
833 /* Check Analog watchdog flag */
834 if(tmp1 && tmp2)
835 {
836 /* Change ADC state */
837 hadc->State = HAL_ADC_STATE_AWD;
838
839 /* Clear the ADCx's Analog watchdog flag */
840 __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD);
841
842 /* Level out of window callback */
843 HAL_ADC_LevelOutOfWindowCallback(hadc);
844 }
845
846 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);
847 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);
848 /* Check Overrun flag */
849 if(tmp1 && tmp2)
850 {
851 /* Change ADC state to overrun state */
852 hadc->State = HAL_ADC_STATE_ERROR;
853
854 /* Set ADC error code to overrun */
855 hadc->ErrorCode |= HAL_ADC_ERROR_OVR;
856
857 /* Clear the Overrun flag */
858 __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_OVR);
859
860 /* Error callback */
861 HAL_ADC_ErrorCallback(hadc);
862 }
863}
864
865/**
866 * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
867 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
868 * the configuration information for the specified ADC.
869 * @param pData: The destination Buffer address.
870 * @param Length: The length of data to be transferred from ADC peripheral to memory.
871 * @retval HAL status
872 */
873HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
874{
875 __IO uint32_t counter = 0;
876
877 /* Check the parameters */
878 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
879 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
880
881 /* Process locked */
882 __HAL_LOCK(hadc);
883
884 /* Enable ADC overrun interrupt */
885 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
886
887 /* Enable ADC DMA mode */
888 hadc->Instance->CR2 |= ADC_CR2_DMA;
889
890 /* Set the DMA transfer complete callback */
891 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
892
893 /* Set the DMA half transfer complete callback */
894 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
895
896 /* Set the DMA error callback */
897 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
898
899 /* Enable the DMA Stream */
900 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
901
902 /* Change ADC state */
903 hadc->State = HAL_ADC_STATE_BUSY_REG;
904
905 /* Process unlocked */
906 __HAL_UNLOCK(hadc);
907
908 /* Check if ADC peripheral is disabled in order to enable it and wait during
909 Tstab time the ADC's stabilization */
910 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
911 {
912 /* Enable the Peripheral */
913 __HAL_ADC_ENABLE(hadc);
914
915 /* Delay for ADC stabilization time */
916 /* Compute number of CPU cycles to wait for */
917 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
918 while(counter != 0)
919 {
920 counter--;
921 }
922 }
923
924 /* if no external trigger present enable software conversion of regular channels */
925 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
926 {
927 /* Enable the selected ADC software conversion for regular group */
928 hadc->Instance->CR2 |= ADC_CR2_SWSTART;
929 }
930
931 /* Return function status */
932 return HAL_OK;
933}
934
935/**
936 * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral
937 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
938 * the configuration information for the specified ADC.
939 * @retval HAL status
940 */
941HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
942{
943 /* Disable the Peripheral */
944 __HAL_ADC_DISABLE(hadc);
945
946 /* Disable ADC overrun interrupt */
947 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
948
949 /* Disable the selected ADC DMA mode */
950 hadc->Instance->CR2 &= ~ADC_CR2_DMA;
951
952 /* Disable the ADC DMA Stream */
953 HAL_DMA_Abort(hadc->DMA_Handle);
954
955 /* Change ADC state */
956 hadc->State = HAL_ADC_STATE_READY;
957
958 /* Return function status */
959 return HAL_OK;
960}
961
962/**
963 * @brief Gets the converted value from data register of regular channel.
964 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
965 * the configuration information for the specified ADC.
966 * @retval Converted value
967 */
968uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
969{
970 /* Return the selected ADC converted value */
971 return hadc->Instance->DR;
972}
973
974/**
975 * @brief Regular conversion complete callback in non blocking mode
976 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
977 * the configuration information for the specified ADC.
978 * @retval None
979 */
980__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
981{
982 /* NOTE : This function Should not be modified, when the callback is needed,
983 the HAL_ADC_ConvCpltCallback could be implemented in the user file
984 */
985}
986
987/**
988 * @brief Regular conversion half DMA transfer callback in non blocking mode
989 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
990 * the configuration information for the specified ADC.
991 * @retval None
992 */
993__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
994{
995 /* NOTE : This function Should not be modified, when the callback is needed,
996 the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
997 */
998}
999
1000/**
1001 * @brief Analog watchdog callback in non blocking mode
1002 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
1003 * the configuration information for the specified ADC.
1004 * @retval None
1005 */
1006__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
1007{
1008 /* NOTE : This function Should not be modified, when the callback is needed,
1009 the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
1010 */
1011}
1012
1013/**
1014 * @brief Error ADC callback.
1015 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
1016 * the configuration information for the specified ADC.
1017 * @retval None
1018 */
1019__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
1020{
1021 /* NOTE : This function Should not be modified, when the callback is needed,
1022 the HAL_ADC_ErrorCallback could be implemented in the user file
1023 */
1024}
1025
1026/**
1027 * @}
1028 */
1029
1030/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
1031 * @brief Peripheral Control functions
1032 *
1033@verbatim
1034 ===============================================================================
1035 ##### Peripheral Control functions #####
1036 ===============================================================================
1037 [..] This section provides functions allowing to:
1038 (+) Configure regular channels.
1039 (+) Configure injected channels.
1040 (+) Configure multimode.
1041 (+) Configure the analog watch dog.
1042
1043@endverbatim
1044 * @{
1045 */
1046
1047 /**
1048 * @brief Configures for the selected ADC regular channel its corresponding
1049 * rank in the sequencer and its sample time.
1050 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
1051 * the configuration information for the specified ADC.
1052 * @param sConfig: ADC configuration structure.
1053 * @retval HAL status
1054 */
1055HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
1056{
1057 __IO uint32_t counter = 0;
1058
1059 /* Check the parameters */
1060 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
1061 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
1062 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
1063
1064 /* Process locked */
1065 __HAL_LOCK(hadc);
1066
1067 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
1068 if (sConfig->Channel > ADC_CHANNEL_9)
1069 {
1070 /* Clear the old sample time */
1071 hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
1072
1073 /* Set the new sample time */
1074 hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
1075 }
1076 else /* ADC_Channel include in ADC_Channel_[0..9] */
1077 {
1078 /* Clear the old sample time */
1079 hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
1080
1081 /* Set the new sample time */
1082 hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
1083 }
1084
1085 /* For Rank 1 to 6 */
1086 if (sConfig->Rank < 7)
1087 {
1088 /* Clear the old SQx bits for the selected rank */
1089 hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
1090
1091 /* Set the SQx bits for the selected rank */
1092 hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
1093 }
1094 /* For Rank 7 to 12 */
1095 else if (sConfig->Rank < 13)
1096 {
1097 /* Clear the old SQx bits for the selected rank */
1098 hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
1099
1100 /* Set the SQx bits for the selected rank */
1101 hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
1102 }
1103 /* For Rank 13 to 16 */
1104 else
1105 {
1106 /* Clear the old SQx bits for the selected rank */
1107 hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
1108
1109 /* Set the SQx bits for the selected rank */
1110 hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
1111 }
1112
1113 /* if ADC1 Channel_18 is selected enable VBAT Channel */
1114 if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
1115 {
1116 /* Enable the VBAT channel*/
1117 ADC->CCR |= ADC_CCR_VBATE;
1118 }
1119
1120 /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
1121 if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
1122 {
1123 /* Enable the TSVREFE channel*/
1124 ADC->CCR |= ADC_CCR_TSVREFE;
1125
1126 if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
1127 {
1128 /* Delay for temperature sensor stabilization time */
1129 /* Compute number of CPU cycles to wait for */
1130 counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
1131 while(counter != 0)
1132 {
1133 counter--;
1134 }
1135 }
1136 }
1137
1138 /* Process unlocked */
1139 __HAL_UNLOCK(hadc);
1140
1141 /* Return function status */
1142 return HAL_OK;
1143}
1144
1145/**
1146 * @brief Configures the analog watchdog.
1147 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
1148 * the configuration information for the specified ADC.
1149 * @param AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure
1150 * that contains the configuration information of ADC analog watchdog.
1151 * @retval HAL status
1152 */
1153HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
1154{
1155#ifdef USE_FULL_ASSERT
1156 uint32_t tmp = 0;
1157#endif /* USE_FULL_ASSERT */
1158
1159 /* Check the parameters */
1160 assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));
1161 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
1162 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
1163
1164#ifdef USE_FULL_ASSERT
1165 tmp = ADC_GET_RESOLUTION(hadc);
1166 assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
1167 assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
1168#endif /* USE_FULL_ASSERT */
1169
1170 /* Process locked */
1171 __HAL_LOCK(hadc);
1172
1173 if(AnalogWDGConfig->ITMode == ENABLE)
1174 {
1175 /* Enable the ADC Analog watchdog interrupt */
1176 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
1177 }
1178 else
1179 {
1180 /* Disable the ADC Analog watchdog interrupt */
1181 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
1182 }
1183
1184 /* Clear AWDEN, JAWDEN and AWDSGL bits */
1185 hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);
1186
1187 /* Set the analog watchdog enable mode */
1188 hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;
1189
1190 /* Set the high threshold */
1191 hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
1192
1193 /* Set the low threshold */
1194 hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
1195
1196 /* Clear the Analog watchdog channel select bits */
1197 hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
1198
1199 /* Set the Analog watchdog channel */
1200 hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
1201
1202 /* Process unlocked */
1203 __HAL_UNLOCK(hadc);
1204
1205 /* Return function status */
1206 return HAL_OK;
1207}
1208
1209/**
1210 * @}
1211 */
1212
1213/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
1214 * @brief ADC Peripheral State functions
1215 *
1216@verbatim
1217 ===============================================================================
1218 ##### Peripheral State and errors functions #####
1219 ===============================================================================
1220 [..]
1221 This subsection provides functions allowing to
1222 (+) Check the ADC state
1223 (+) Check the ADC Error
1224
1225@endverbatim
1226 * @{
1227 */
1228
1229/**
1230 * @brief return the ADC state
1231 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
1232 * the configuration information for the specified ADC.
1233 * @retval HAL state
1234 */
1235HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
1236{
1237 /* Return ADC state */
1238 return hadc->State;
1239}
1240
1241/**
1242 * @brief Return the ADC error code
1243 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
1244 * the configuration information for the specified ADC.
1245 * @retval ADC Error Code
1246 */
1247uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
1248{
1249 return hadc->ErrorCode;
1250}
1251
1252/**
1253 * @}
1254 */
1255
1256/** @addtogroup ADC_Private_Functions
1257 * @{
1258 */
1259
1260/**
1261 * @brief Initializes the ADCx peripheral according to the specified parameters
1262 * in the ADC_InitStruct without initializing the ADC MSP.
1263 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
1264 * the configuration information for the specified ADC.
1265 * @retval None
1266 */
1267static void ADC_Init(ADC_HandleTypeDef* hadc)
1268{
1269 /* Set ADC parameters */
1270 /* Set the ADC clock prescaler */
1271 ADC->CCR &= ~(ADC_CCR_ADCPRE);
1272 ADC->CCR |= hadc->Init.ClockPrescaler;
1273
1274 /* Set ADC scan mode */
1275 hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
1276 hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
1277
1278 /* Set ADC resolution */
1279 hadc->Instance->CR1 &= ~(ADC_CR1_RES);
1280 hadc->Instance->CR1 |= hadc->Init.Resolution;
1281
1282 /* Set ADC data alignment */
1283 hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
1284 hadc->Instance->CR2 |= hadc->Init.DataAlign;
1285
1286 /* Enable external trigger if trigger selection is different of software */
1287 /* start. */
1288 /* Note: This configuration keeps the hardware feature of parameter */
1289 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
1290 /* software start. */
1291 if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
1292 {
1293 /* Select external trigger to start conversion */
1294 hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
1295 hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
1296
1297 /* Select external trigger polarity */
1298 hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
1299 hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
1300 }
1301 else
1302 {
1303 /* Reset the external trigger */
1304 hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
1305 hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
1306 }
1307
1308 /* Enable or disable ADC continuous conversion mode */
1309 hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
1310 hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);
1311
1312 if(hadc->Init.DiscontinuousConvMode != DISABLE)
1313 {
1314 assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
1315
1316 /* Enable the selected ADC regular discontinuous mode */
1317 hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
1318
1319 /* Set the number of channels to be converted in discontinuous mode */
1320 hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
1321 hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
1322 }
1323 else
1324 {
1325 /* Disable the selected ADC regular discontinuous mode */
1326 hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
1327 }
1328
1329 /* Set ADC number of conversion */
1330 hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
1331 hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
1332
1333 /* Enable or disable ADC DMA continuous request */
1334 hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
1335 hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);
1336
1337 /* Enable or disable ADC end of conversion selection */
1338 hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
1339 hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
1340}
1341
1342/**
1343 * @brief DMA transfer complete callback.
1344 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
1345 * the configuration information for the specified DMA module.
1346 * @retval None
1347 */
1348static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
1349{
1350 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1351
1352 /* Check if an injected conversion is ready */
1353 if(hadc->State == HAL_ADC_STATE_EOC_INJ)
1354 {
1355 /* Change ADC state */
1356 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
1357 }
1358 else
1359 {
1360 /* Change ADC state */
1361 hadc->State = HAL_ADC_STATE_EOC_REG;
1362 }
1363
1364 HAL_ADC_ConvCpltCallback(hadc);
1365}
1366
1367/**
1368 * @brief DMA half transfer complete callback.
1369 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
1370 * the configuration information for the specified DMA module.
1371 * @retval None
1372 */
1373static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
1374{
1375 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1376 /* Conversion complete callback */
1377 HAL_ADC_ConvHalfCpltCallback(hadc);
1378}
1379
1380/**
1381 * @brief DMA error callback
1382 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
1383 * the configuration information for the specified DMA module.
1384 * @retval None
1385 */
1386static void ADC_DMAError(DMA_HandleTypeDef *hdma)
1387{
1388 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1389 hadc->State= HAL_ADC_STATE_ERROR;
1390 /* Set ADC error code to DMA error */
1391 hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
1392 HAL_ADC_ErrorCallback(hadc);
1393}
1394
1395/**
1396 * @}
1397 */
1398
1399/**
1400 * @}
1401 */
1402
1403#endif /* HAL_ADC_MODULE_ENABLED */
1404/**
1405 * @}
1406 */
1407
1408/**
1409 * @}
1410 */
1411
1412/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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