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source: asp3_wo_tecs/trunk/arch/arm_m_gcc/stm32f4xx_stm32cube/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h@ 303

Last change on this file since 303 was 303, checked in by ertl-honda, 7 years ago
nucleo_f401re依存部の追加
File size: 38.9 KB

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1	/**
2	******************************************************************************
3	* @file stm32f4xx_ll_sdmmc.h
4	* @author MCD Application Team
5	* @version V1.4.1
6	* @date 09-October-2015
7	* @brief Header file of SDMMC HAL module.
8	******************************************************************************
9	* @attention
10	*
11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
12	*
13	* Redistribution and use in source and binary forms, with or without modification,
14	* are permitted provided that the following conditions are met:
15	* 1. Redistributions of source code must retain the above copyright notice,
16	* this list of conditions and the following disclaimer.
17	* 2. Redistributions in binary form must reproduce the above copyright notice,
18	* this list of conditions and the following disclaimer in the documentation
19	* and/or other materials provided with the distribution.
20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
21	* may be used to endorse or promote products derived from this software
22	* without specific prior written permission.
23	*
24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34	*
35	******************************************************************************
36	*/
37
38	/* Define to prevent recursive inclusion -------------------------------------*/
39	#ifndef __STM32F4xx_LL_SDMMC_H
40	#define __STM32F4xx_LL_SDMMC_H
41
42	#ifdef __cplusplus
43	extern "C" {
44	#endif
45	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
46	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
47	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
48	defined(STM32F469xx) \|\| defined(STM32F479xx)
49	/* Includes ------------------------------------------------------------------*/
50	#include "stm32f4xx_hal_def.h"
51
52	/** @addtogroup STM32F4xx_Driver
53	* @{
54	*/
55
56	/** @addtogroup SDMMC_LL
57	* @{
58	*/
59
60	/* Exported types ------------------------------------------------------------*/
61	/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
62	* @{
63	*/
64
65	/**
66	* @brief SDMMC Configuration Structure definition
67	*/
68	typedef struct
69	{
70	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
71	This parameter can be a value of @ref SDIO_Clock_Edge */
72
73	uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
74	enabled or disabled.
75	This parameter can be a value of @ref SDIO_Clock_Bypass */
76
77	uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
78	disabled when the bus is idle.
79	This parameter can be a value of @ref SDIO_Clock_Power_Save */
80
81	uint32_t BusWide; /*!< Specifies the SDIO bus width.
82	This parameter can be a value of @ref SDIO_Bus_Wide */
83
84	uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
85	This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
86
87	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
88	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
89
90	}SDIO_InitTypeDef;
91
92
93	/**
94	* @brief SDIO Command Control structure
95	*/
96	typedef struct
97	{
98	uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
99	to a card as part of a command message. If a command
100	contains an argument, it must be loaded into this register
101	before writing the command to the command register. */
102
103	uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
104	Max_Data = 64 */
105
106	uint32_t Response; /*!< Specifies the SDIO response type.
107	This parameter can be a value of @ref SDIO_Response_Type */
108
109	uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
110	enabled or disabled.
111	This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
112
113	uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
114	is enabled or disabled.
115	This parameter can be a value of @ref SDIO_CPSM_State */
116	}SDIO_CmdInitTypeDef;
117
118
119	/**
120	* @brief SDIO Data Control structure
121	*/
122	typedef struct
123	{
124	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
125
126	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
127
128	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
129	This parameter can be a value of @ref SDIO_Data_Block_Size */
130
131	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
132	is a read or write.
133	This parameter can be a value of @ref SDIO_Transfer_Direction */
134
135	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
136	This parameter can be a value of @ref SDIO_Transfer_Type */
137
138	uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
139	is enabled or disabled.
140	This parameter can be a value of @ref SDIO_DPSM_State */
141	}SDIO_DataInitTypeDef;
142
143	/**
144	* @}
145	*/
146
147	/* Exported constants --------------------------------------------------------*/
148	/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
149	* @{
150	*/
151
152	/** @defgroup SDIO_Clock_Edge Clock Edge
153	* @{
154	*/
155	#define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
156	#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
157
158	#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) \|\| \
159	((EDGE) == SDIO_CLOCK_EDGE_FALLING))
160	/**
161	* @}
162	*/
163
164	/** @defgroup SDIO_Clock_Bypass Clock Bypass
165	* @{
166	*/
167	#define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
168	#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
169
170	#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) \|\| \
171	((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
172	/**
173	* @}
174	*/
175
176	/** @defgroup SDIO_Clock_Power_Save Clock Power Saving
177	* @{
178	*/
179	#define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
180	#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
181
182	#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) \|\| \
183	((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
184	/**
185	* @}
186	*/
187
188	/** @defgroup SDIO_Bus_Wide Bus Width
189	* @{
190	*/
191	#define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
192	#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
193	#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
194
195	#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) \|\| \
196	((WIDE) == SDIO_BUS_WIDE_4B) \|\| \
197	((WIDE) == SDIO_BUS_WIDE_8B))
198	/**
199	* @}
200	*/
201
202	/** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control
203	* @{
204	*/
205	#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
206	#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
207
208	#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
209	((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
210	/**
211	* @}
212	*/
213
214	/** @defgroup SDIO_Clock_Division Clock Division
215	* @{
216	*/
217	#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
218	/**
219	* @}
220	*/
221
222	/** @defgroup SDIO_Command_Index Command Index
223	* @{
224	*/
225	#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
226	/**
227	* @}
228	*/
229
230	/** @defgroup SDIO_Response_Type Response Type
231	* @{
232	*/
233	#define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
234	#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
235	#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
236
237	#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) \|\| \
238	((RESPONSE) == SDIO_RESPONSE_SHORT) \|\| \
239	((RESPONSE) == SDIO_RESPONSE_LONG))
240	/**
241	* @}
242	*/
243
244	/** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt
245	* @{
246	*/
247	#define SDIO_WAIT_NO ((uint32_t)0x00000000)
248	#define SDIO_WAIT_IT SDIO_CMD_WAITINT
249	#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
250
251	#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) \|\| \
252	((WAIT) == SDIO_WAIT_IT) \|\| \
253	((WAIT) == SDIO_WAIT_PEND))
254	/**
255	* @}
256	*/
257
258	/** @defgroup SDIO_CPSM_State CPSM State
259	* @{
260	*/
261	#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
262	#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
263
264	#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) \|\| \
265	((CPSM) == SDIO_CPSM_ENABLE))
266	/**
267	* @}
268	*/
269
270	/** @defgroup SDIO_Response_Registers Response Register
271	* @{
272	*/
273	#define SDIO_RESP1 ((uint32_t)0x00000000)
274	#define SDIO_RESP2 ((uint32_t)0x00000004)
275	#define SDIO_RESP3 ((uint32_t)0x00000008)
276	#define SDIO_RESP4 ((uint32_t)0x0000000C)
277
278	#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) \|\| \
279	((RESP) == SDIO_RESP2) \|\| \
280	((RESP) == SDIO_RESP3) \|\| \
281	((RESP) == SDIO_RESP4))
282	/**
283	* @}
284	*/
285
286	/** @defgroup SDIO_Data_Length Data Lenght
287	* @{
288	*/
289	#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
290	/**
291	* @}
292	*/
293
294	/** @defgroup SDIO_Data_Block_Size Data Block Size
295	* @{
296	*/
297	#define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
298	#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
299	#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
300	#define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030)
301	#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
302	#define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050)
303	#define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060)
304	#define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070)
305	#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
306	#define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090)
307	#define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0)
308	#define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0)
309	#define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0)
310	#define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0)
311	#define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0)
312
313	#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) \|\| \
314	((SIZE) == SDIO_DATABLOCK_SIZE_2B) \|\| \
315	((SIZE) == SDIO_DATABLOCK_SIZE_4B) \|\| \
316	((SIZE) == SDIO_DATABLOCK_SIZE_8B) \|\| \
317	((SIZE) == SDIO_DATABLOCK_SIZE_16B) \|\| \
318	((SIZE) == SDIO_DATABLOCK_SIZE_32B) \|\| \
319	((SIZE) == SDIO_DATABLOCK_SIZE_64B) \|\| \
320	((SIZE) == SDIO_DATABLOCK_SIZE_128B) \|\| \
321	((SIZE) == SDIO_DATABLOCK_SIZE_256B) \|\| \
322	((SIZE) == SDIO_DATABLOCK_SIZE_512B) \|\| \
323	((SIZE) == SDIO_DATABLOCK_SIZE_1024B) \|\| \
324	((SIZE) == SDIO_DATABLOCK_SIZE_2048B) \|\| \
325	((SIZE) == SDIO_DATABLOCK_SIZE_4096B) \|\| \
326	((SIZE) == SDIO_DATABLOCK_SIZE_8192B) \|\| \
327	((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
328	/**
329	* @}
330	*/
331
332	/** @defgroup SDIO_Transfer_Direction Transfer Direction
333	* @{
334	*/
335	#define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
336	#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
337
338	#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) \|\| \
339	((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
340	/**
341	* @}
342	*/
343
344	/** @defgroup SDIO_Transfer_Type Transfer Type
345	* @{
346	*/
347	#define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
348	#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
349
350	#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) \|\| \
351	((MODE) == SDIO_TRANSFER_MODE_STREAM))
352	/**
353	* @}
354	*/
355
356	/** @defgroup SDIO_DPSM_State DPSM State
357	* @{
358	*/
359	#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
360	#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
361
362	#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) \|\|\
363	((DPSM) == SDIO_DPSM_ENABLE))
364	/**
365	* @}
366	*/
367
368	/** @defgroup SDIO_Read_Wait_Mode Read Wait Mode
369	* @{
370	*/
371	#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000)
372	#define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000001)
373
374	#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) \|\| \
375	((MODE) == SDIO_READ_WAIT_MODE_DATA2))
376	/**
377	* @}
378	*/
379
380	/** @defgroup SDIO_Interrupt_sources Interrupt Sources
381	* @{
382	*/
383	#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
384	#define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
385	#define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
386	#define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
387	#define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
388	#define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
389	#define SDIO_IT_CMDREND SDIO_STA_CMDREND
390	#define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
391	#define SDIO_IT_DATAEND SDIO_STA_DATAEND
392	#define SDIO_IT_STBITERR SDIO_STA_STBITERR
393	#define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
394	#define SDIO_IT_CMDACT SDIO_STA_CMDACT
395	#define SDIO_IT_TXACT SDIO_STA_TXACT
396	#define SDIO_IT_RXACT SDIO_STA_RXACT
397	#define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
398	#define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
399	#define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
400	#define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
401	#define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
402	#define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
403	#define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
404	#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
405	#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
406	#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
407	/**
408	* @}
409	*/
410
411	/** @defgroup SDIO_Flags Flags
412	* @{
413	*/
414	#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
415	#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
416	#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
417	#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
418	#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
419	#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
420	#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
421	#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
422	#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
423	#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
424	#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
425	#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
426	#define SDIO_FLAG_TXACT SDIO_STA_TXACT
427	#define SDIO_FLAG_RXACT SDIO_STA_RXACT
428	#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
429	#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
430	#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
431	#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
432	#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
433	#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
434	#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
435	#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
436	#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
437	#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
438	/**
439	* @}
440	*/
441
442	/**
443	* @}
444	*/
445	/* Exported macro ------------------------------------------------------------*/
446	/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
447	* @{
448	*/
449
450	/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
451	* @{
452	*/
453	/* ------------ SDIO registers bit address in the alias region -------------- */
454	#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
455
456	/* --- CLKCR Register ---*/
457	/* Alias word address of CLKEN bit */
458	#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
459	#define CLKEN_BITNUMBER 0x08
460	#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4))
461
462	/* --- CMD Register ---*/
463	/* Alias word address of SDIOSUSPEND bit */
464	#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
465	#define SDIOSUSPEND_BITNUMBER 0x0B
466	#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4))
467
468	/* Alias word address of ENCMDCOMPL bit */
469	#define ENCMDCOMPL_BITNUMBER 0x0C
470	#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4))
471
472	/* Alias word address of NIEN bit */
473	#define NIEN_BITNUMBER 0x0D
474	#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4))
475
476	/* Alias word address of ATACMD bit */
477	#define ATACMD_BITNUMBER 0x0E
478	#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4))
479
480	/* --- DCTRL Register ---*/
481	/* Alias word address of DMAEN bit */
482	#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
483	#define DMAEN_BITNUMBER 0x03
484	#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4))
485
486	/* Alias word address of RWSTART bit */
487	#define RWSTART_BITNUMBER 0x08
488	#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4))
489
490	/* Alias word address of RWSTOP bit */
491	#define RWSTOP_BITNUMBER 0x09
492	#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4))
493
494	/* Alias word address of RWMOD bit */
495	#define RWMOD_BITNUMBER 0x0A
496	#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4))
497
498	/* Alias word address of SDIOEN bit */
499	#define SDIOEN_BITNUMBER 0x0B
500	#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4))
501	/**
502	* @}
503	*/
504
505	/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
506	* @brief SDMMC_LL registers bit address in the alias region
507	* @{
508	*/
509
510	/* ---------------------- SDIO registers bit mask --------------------------- */
511	/* --- CLKCR Register ---*/
512	/* CLKCR register clear mask */
513	#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV \| SDIO_CLKCR_PWRSAV \|\
514	SDIO_CLKCR_BYPASS \| SDIO_CLKCR_WIDBUS \|\
515	SDIO_CLKCR_NEGEDGE \| SDIO_CLKCR_HWFC_EN))
516
517	/* --- PWRCTRL Register ---*/
518	/* --- DCTRL Register ---*/
519	/* SDIO DCTRL Clear Mask */
520	#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN \| SDIO_DCTRL_DTDIR \|\
521	SDIO_DCTRL_DTMODE \| SDIO_DCTRL_DBLOCKSIZE))
522
523	/* --- CMD Register ---*/
524	/* CMD Register clear mask */
525	#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX \| SDIO_CMD_WAITRESP \|\
526	SDIO_CMD_WAITINT \| SDIO_CMD_WAITPEND \|\
527	SDIO_CMD_CPSMEN \| SDIO_CMD_SDIOSUSPEND))
528
529	/* SDIO RESP Registers Address */
530	#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
531
532	/* SDIO Initialization Frequency (400KHz max) */
533	#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
534
535	/* SDIO Data Transfer Frequency (25MHz max) */
536	#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
537	/**
538	* @}
539	*/
540
541	/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
542	* @brief macros to handle interrupts and specific clock configurations
543	* @{
544	*/
545
546	/**
547	* @brief Enable the SDIO device.
548	* @retval None
549	*/
550	#define __SDIO_ENABLE() ((__IO uint32_t )CLKCR_CLKEN_BB = ENABLE)
551
552	/**
553	* @brief Disable the SDIO device.
554	* @retval None
555	*/
556	#define __SDIO_DISABLE() ((__IO uint32_t )CLKCR_CLKEN_BB = DISABLE)
557
558	/**
559	* @brief Enable the SDIO DMA transfer.
560	* @retval None
561	*/
562	#define __SDIO_DMA_ENABLE() ((__IO uint32_t )DCTRL_DMAEN_BB = ENABLE)
563
564	/**
565	* @brief Disable the SDIO DMA transfer.
566	* @retval None
567	*/
568	#define __SDIO_DMA_DISABLE() ((__IO uint32_t )DCTRL_DMAEN_BB = DISABLE)
569
570	/**
571	* @brief Enable the SDIO device interrupt.
572	* @param __INSTANCE__ : Pointer to SDIO register base
573	* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
574	* This parameter can be one or a combination of the following values:
575	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
576	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
577	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
578	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
579	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
580	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
581	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
582	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
583	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
584	* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
585	* bus mode interrupt
586	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
587	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
588	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
589	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
590	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
591	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
592	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
593	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
594	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
595	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
596	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
597	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
598	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
599	* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
600	* @retval None
601	*/
602	#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
603
604	/**
605	* @brief Disable the SDIO device interrupt.
606	* @param __INSTANCE__ : Pointer to SDIO register base
607	* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
608	* This parameter can be one or a combination of the following values:
609	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
610	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
611	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
612	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
613	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
614	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
615	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
616	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
617	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
618	* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
619	* bus mode interrupt
620	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
621	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
622	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
623	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
624	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
625	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
626	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
627	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
628	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
629	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
630	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
631	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
632	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
633	* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
634	* @retval None
635	*/
636	#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
637
638	/**
639	* @brief Checks whether the specified SDIO flag is set or not.
640	* @param __INSTANCE__ : Pointer to SDIO register base
641	* @param __FLAG__: specifies the flag to check.
642	* This parameter can be one of the following values:
643	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
644	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
645	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
646	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
647	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
648	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
649	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
650	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
651	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
652	* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
653	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
654	* @arg SDIO_FLAG_CMDACT: Command transfer in progress
655	* @arg SDIO_FLAG_TXACT: Data transmit in progress
656	* @arg SDIO_FLAG_RXACT: Data receive in progress
657	* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
658	* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
659	* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
660	* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
661	* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
662	* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
663	* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
664	* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
665	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
666	* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
667	* @retval The new state of SDIO_FLAG (SET or RESET).
668	*/
669	#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
670
671
672	/**
673	* @brief Clears the SDIO pending flags.
674	* @param __INSTANCE__ : Pointer to SDIO register base
675	* @param __FLAG__: specifies the flag to clear.
676	* This parameter can be one or a combination of the following values:
677	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
678	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
679	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
680	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
681	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
682	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
683	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
684	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
685	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
686	* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
687	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
688	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
689	* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
690	* @retval None
691	*/
692	#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
693
694	/**
695	* @brief Checks whether the specified SDIO interrupt has occurred or not.
696	* @param __INSTANCE__ : Pointer to SDIO register base
697	* @param __INTERRUPT__: specifies the SDIO interrupt source to check.
698	* This parameter can be one of the following values:
699	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
700	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
701	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
702	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
703	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
704	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
705	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
706	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
707	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
708	* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
709	* bus mode interrupt
710	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
711	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
712	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
713	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
714	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
715	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
716	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
717	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
718	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
719	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
720	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
721	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
722	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
723	* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
724	* @retval The new state of SDIO_IT (SET or RESET).
725	*/
726	#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
727
728	/**
729	* @brief Clears the SDIO's interrupt pending bits.
730	* @param __INSTANCE__ : Pointer to SDIO register base
731	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
732	* This parameter can be one or a combination of the following values:
733	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
734	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
735	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
736	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
737	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
738	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
739	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
740	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
741	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
742	* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
743	* bus mode interrupt
744	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
745	* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
746	* @retval None
747	*/
748	#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
749
750	/**
751	* @brief Enable Start the SD I/O Read Wait operation.
752	* @retval None
753	*/
754	#define __SDIO_START_READWAIT_ENABLE() ((__IO uint32_t ) DCTRL_RWSTART_BB = ENABLE)
755
756	/**
757	* @brief Disable Start the SD I/O Read Wait operations.
758	* @retval None
759	*/
760	#define __SDIO_START_READWAIT_DISABLE() ((__IO uint32_t ) DCTRL_RWSTART_BB = DISABLE)
761
762	/**
763	* @brief Enable Start the SD I/O Read Wait operation.
764	* @retval None
765	*/
766	#define __SDIO_STOP_READWAIT_ENABLE() ((__IO uint32_t ) DCTRL_RWSTOP_BB = ENABLE)
767
768	/**
769	* @brief Disable Stop the SD I/O Read Wait operations.
770	* @retval None
771	*/
772	#define __SDIO_STOP_READWAIT_DISABLE() ((__IO uint32_t ) DCTRL_RWSTOP_BB = DISABLE)
773
774	/**
775	* @brief Enable the SD I/O Mode Operation.
776	* @retval None
777	*/
778	#define __SDIO_OPERATION_ENABLE() ((__IO uint32_t ) DCTRL_SDIOEN_BB = ENABLE)
779
780	/**
781	* @brief Disable the SD I/O Mode Operation.
782	* @retval None
783	*/
784	#define __SDIO_OPERATION_DISABLE() ((__IO uint32_t ) DCTRL_SDIOEN_BB = DISABLE)
785
786	/**
787	* @brief Enable the SD I/O Suspend command sending.
788	* @retval None
789	*/
790	#define __SDIO_SUSPEND_CMD_ENABLE() ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = ENABLE)
791
792	/**
793	* @brief Disable the SD I/O Suspend command sending.
794	* @retval None
795	*/
796	#define __SDIO_SUSPEND_CMD_DISABLE() ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = DISABLE)
797
798	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
799	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
800	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
801	/**
802	* @brief Enable the command completion signal.
803	* @retval None
804	*/
805	#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = ENABLE)
806
807	/**
808	* @brief Disable the command completion signal.
809	* @retval None
810	*/
811	#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = DISABLE)
812
813	/**
814	* @brief Enable the CE-ATA interrupt.
815	* @retval None
816	*/
817	#define __SDIO_CEATA_ENABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)0)
818
819	/**
820	* @brief Disable the CE-ATA interrupt.
821	* @retval None
822	*/
823	#define __SDIO_CEATA_DISABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)1)
824
825	/**
826	* @brief Enable send CE-ATA command (CMD61).
827	* @retval None
828	*/
829	#define __SDIO_CEATA_SENDCMD_ENABLE() ((__IO uint32_t ) CMD_ATACMD_BB = ENABLE)
830
831	/**
832	* @brief Disable send CE-ATA command (CMD61).
833	* @retval None
834	*/
835	#define __SDIO_CEATA_SENDCMD_DISABLE() ((__IO uint32_t ) CMD_ATACMD_BB = DISABLE)
836	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\|\
837	STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
838	/**
839	* @}
840	*/
841
842	/**
843	* @}
844	*/
845
846	/* Exported functions --------------------------------------------------------*/
847	/** @addtogroup SDMMC_LL_Exported_Functions
848	* @{
849	*/
850
851	/* Initialization/de-initialization functions **********************************/
852	/** @addtogroup HAL_SDMMC_LL_Group1
853	* @{
854	*/
855	HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
856	/**
857	* @}
858	*/
859
860	/* I/O operation functions *****************************************************/
861	/** @addtogroup HAL_SDMMC_LL_Group2
862	* @{
863	*/
864	/* Blocking mode: Polling */
865	uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
866	HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef SDIOx, uint32_t pWriteData);
867	/**
868	* @}
869	*/
870
871	/* Peripheral Control functions ************************************************/
872	/** @addtogroup HAL_SDMMC_LL_Group3
873	* @{
874	*/
875	HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
876	HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
877	uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
878
879	/* Command path state machine (CPSM) management functions */
880	HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef SDIOx, SDIO_CmdInitTypeDef SDIO_CmdInitStruct);
881	uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
882	uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
883
884	/* Data path state machine (DPSM) management functions */
885	HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef SDIOx, SDIO_DataInitTypeDef SDIO_DataInitStruct);
886	uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
887	uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
888
889	/* SDIO IO Cards mode management functions */
890	HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
891
892	/**
893	* @}
894	*/
895
896	/**
897	* @}
898	*/
899
900	/**
901	* @}
902	*/
903
904	/**
905	* @}
906	*/
907	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
908	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
909	#ifdef __cplusplus
910	}
911	#endif
912
913	#endif /* __STM32F4xx_LL_SDMMC_H */
914
915	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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