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source: asp3_wo_tecs/trunk/arch/arm_m_gcc/stm32f4xx_stm32cube/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h@ 303

Last change on this file since 303 was 303, checked in by ertl-honda, 7 years ago
nucleo_f401re依存部の追加
File size: 43.6 KB

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1	/**
2	******************************************************************************
3	* @file stm32f4xx_ll_fsmc.h
4	* @author MCD Application Team
5	* @version V1.4.1
6	* @date 09-October-2015
7	* @brief Header file of FSMC HAL module.
8	******************************************************************************
9	* @attention
10	*
11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
12	*
13	* Redistribution and use in source and binary forms, with or without modification,
14	* are permitted provided that the following conditions are met:
15	* 1. Redistributions of source code must retain the above copyright notice,
16	* this list of conditions and the following disclaimer.
17	* 2. Redistributions in binary form must reproduce the above copyright notice,
18	* this list of conditions and the following disclaimer in the documentation
19	* and/or other materials provided with the distribution.
20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
21	* may be used to endorse or promote products derived from this software
22	* without specific prior written permission.
23	*
24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34	*
35	******************************************************************************
36	*/
37
38	/* Define to prevent recursive inclusion -------------------------------------*/
39	#ifndef __STM32F4xx_LL_FSMC_H
40	#define __STM32F4xx_LL_FSMC_H
41
42	#ifdef __cplusplus
43	extern "C" {
44	#endif
45
46	/* Includes ------------------------------------------------------------------*/
47	#include "stm32f4xx_hal_def.h"
48
49	/** @addtogroup STM32F4xx_HAL_Driver
50	* @{
51	*/
52
53	/** @addtogroup FSMC_LL
54	* @{
55	*/
56
57	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
58	/* Private types -------------------------------------------------------------*/
59	/** @defgroup FSMC_LL_Private_Types FSMC Private Types
60	* @{
61	*/
62
63	/**
64	* @brief FSMC NORSRAM Configuration Structure definition
65	*/
66	typedef struct
67	{
68	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
69	This parameter can be a value of @ref FSMC_NORSRAM_Bank */
70
71	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
72	multiplexed on the data bus or not.
73	This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
74
75	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
76	the corresponding memory device.
77	This parameter can be a value of @ref FSMC_Memory_Type */
78
79	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
80	This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
81
82	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
83	valid only with synchronous burst Flash memories.
84	This parameter can be a value of @ref FSMC_Burst_Access_Mode */
85
86	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
87	the Flash memory in burst mode.
88	This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
89
90	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
91	memory, valid only when accessing Flash memories in burst mode.
92	This parameter can be a value of @ref FSMC_Wrap_Mode */
93
94	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
95	clock cycle before the wait state or during the wait state,
96	valid only when accessing memories in burst mode.
97	This parameter can be a value of @ref FSMC_Wait_Timing */
98
99	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
100	This parameter can be a value of @ref FSMC_Write_Operation */
101
102	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
103	signal, valid for Flash memory access in burst mode.
104	This parameter can be a value of @ref FSMC_Wait_Signal */
105
106	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
107	This parameter can be a value of @ref FSMC_Extended_Mode */
108
109	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
110	valid only with asynchronous Flash memories.
111	This parameter can be a value of @ref FSMC_AsynchronousWait */
112
113	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
114	This parameter can be a value of @ref FSMC_Write_Burst */
115
116	}FSMC_NORSRAM_InitTypeDef;
117
118	/**
119	* @brief FSMC NORSRAM Timing parameters structure definition
120	*/
121	typedef struct
122	{
123	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
124	the duration of the address setup time.
125	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
126	@note This parameter is not used with synchronous NOR Flash memories. */
127
128	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
129	the duration of the address hold time.
130	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
131	@note This parameter is not used with synchronous NOR Flash memories. */
132
133	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
134	the duration of the data setup time.
135	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
136	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
137	NOR Flash memories. */
138
139	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
140	the duration of the bus turnaround.
141	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
142	@note This parameter is only used for multiplexed NOR Flash memories. */
143
144	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
145	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
146	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
147	accesses. */
148
149	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
150	to the memory before getting the first data.
151	The parameter value depends on the memory type as shown below:
152	- It must be set to 0 in case of a CRAM
153	- It is don't care in asynchronous NOR, SRAM or ROM accesses
154	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
155	with synchronous burst mode enable */
156
157	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
158	This parameter can be a value of @ref FSMC_Access_Mode */
159
160	}FSMC_NORSRAM_TimingTypeDef;
161
162	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
163	/**
164	* @brief FSMC NAND Configuration Structure definition
165	*/
166	typedef struct
167	{
168	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
169	This parameter can be a value of @ref FSMC_NAND_Bank */
170
171	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
172	This parameter can be any value of @ref FSMC_Wait_feature */
173
174	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
175	This parameter can be any value of @ref FSMC_NAND_Data_Width */
176
177	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
178	This parameter can be any value of @ref FSMC_ECC */
179
180	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
181	This parameter can be any value of @ref FSMC_ECC_Page_Size */
182
183	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
184	delay between CLE low and RE low.
185	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
186
187	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
188	delay between ALE low and RE low.
189	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
190
191	}FSMC_NAND_InitTypeDef;
192
193	/**
194	* @brief FSMC NAND/PCCARD Timing parameters structure definition
195	*/
196	typedef struct
197	{
198	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
199	the command assertion for NAND-Flash read or write access
200	to common/Attribute or I/O memory space (depending on
201	the memory space timing to be configured).
202	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
203
204	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
205	command for NAND-Flash read or write access to
206	common/Attribute or I/O memory space (depending on the
207	memory space timing to be configured).
208	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
209
210	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
211	(and data for write access) after the command de-assertion
212	for NAND-Flash read or write access to common/Attribute
213	or I/O memory space (depending on the memory space timing
214	to be configured).
215	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
216
217	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
218	data bus is kept in HiZ after the start of a NAND-Flash
219	write access to common/Attribute or I/O memory space (depending
220	on the memory space timing to be configured).
221	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
222
223	}FSMC_NAND_PCC_TimingTypeDef;
224
225	/**
226	* @brief FSMC NAND Configuration Structure definition
227	*/
228	typedef struct
229	{
230	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
231	This parameter can be any value of @ref FSMC_Wait_feature */
232
233	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
234	delay between CLE low and RE low.
235	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
236
237	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
238	delay between ALE low and RE low.
239	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
240
241	}FSMC_PCCARD_InitTypeDef;
242	/**
243	* @}
244	*/
245	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
246
247	/* Private constants ---------------------------------------------------------*/
248	/** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
249	* @{
250	*/
251
252	/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
253	* @{
254	*/
255	/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
256	* @{
257	*/
258	#define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
259	#define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
260	#define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
261	#define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
262	/**
263	* @}
264	*/
265
266	/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
267	* @{
268	*/
269	#define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
270	#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
271	/**
272	* @}
273	*/
274
275	/** @defgroup FSMC_Memory_Type FSMC Memory Type
276	* @{
277	*/
278	#define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
279	#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
280	#define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
281	/**
282	* @}
283	*/
284
285	/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
286	* @{
287	*/
288	#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
289	#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
290	#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
291	/**
292	* @}
293	*/
294
295	/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
296	* @{
297	*/
298	#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
299	#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
300	/**
301	* @}
302	*/
303
304	/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
305	* @{
306	*/
307	#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
308	#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
309	/**
310	* @}
311	*/
312
313	/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
314	* @{
315	*/
316	#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
317	#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
318	/**
319	* @}
320	*/
321
322	/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
323	* @{
324	*/
325	#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
326	#define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
327	/**
328	* @}
329	*/
330
331	/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
332	* @{
333	*/
334	#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
335	#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
336	/**
337	* @}
338	*/
339
340	/** @defgroup FSMC_Write_Operation FSMC Write Operation
341	* @{
342	*/
343	#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
344	#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
345	/**
346	* @}
347	*/
348
349	/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
350	* @{
351	*/
352	#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
353	#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
354	/**
355	* @}
356	*/
357
358	/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
359	* @{
360	*/
361	#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
362	#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
363	/**
364	* @}
365	*/
366
367	/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
368	* @{
369	*/
370	#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
371	#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
372	/**
373	* @}
374	*/
375
376	/** @defgroup FSMC_Write_Burst FSMC Write Burst
377	* @{
378	*/
379	#define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
380	#define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
381	/**
382	* @}
383	*/
384
385	/** @defgroup FSMC_Continous_Clock FSMC Continous Clock
386	* @{
387	*/
388	#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
389	#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
390	/**
391	* @}
392	*/
393
394	/** @defgroup FSMC_Access_Mode FSMC Access Mode
395	* @{
396	*/
397	#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000)
398	#define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000)
399	#define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000)
400	#define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000)
401	/**
402	* @}
403	*/
404	/**
405	* @}
406	*/
407
408	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
409	/** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
410	* @{
411	*/
412	/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
413	* @{
414	*/
415	#define FSMC_NAND_BANK2 ((uint32_t)0x00000010)
416	#define FSMC_NAND_BANK3 ((uint32_t)0x00000100)
417	/**
418	* @}
419	*/
420
421	/** @defgroup FSMC_Wait_feature FSMC Wait feature
422	* @{
423	*/
424	#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
425	#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
426	/**
427	* @}
428	*/
429
430	/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
431	* @{
432	*/
433	#define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
434	#define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
435	/**
436	* @}
437	*/
438
439	/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
440	* @{
441	*/
442	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
443	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
444	/**
445	* @}
446	*/
447
448	/** @defgroup FSMC_ECC FSMC ECC
449	* @{
450	*/
451	#define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
452	#define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
453	/**
454	* @}
455	*/
456
457	/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
458	* @{
459	*/
460	#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
461	#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
462	#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
463	#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
464	#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
465	#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
466	/**
467	* @}
468	*/
469	/**
470	* @}
471	*/
472	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
473
474	/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
475	* @{
476	*/
477	#define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008)
478	#define FSMC_IT_LEVEL ((uint32_t)0x00000010)
479	#define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
480	#define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
481	/**
482	* @}
483	*/
484
485	/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
486	* @{
487	*/
488	#define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
489	#define FSMC_FLAG_LEVEL ((uint32_t)0x00000002)
490	#define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
491	#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
492	/**
493	* @}
494	*/
495
496	/** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
497	* @{
498	*/
499	#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
500	#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
501	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
502	#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
503	#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
504	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
505
506	#define FSMC_NORSRAM_DEVICE FSMC_Bank1
507	#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
508	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
509	#define FSMC_NAND_DEVICE FSMC_Bank2_3
510	#define FSMC_PCCARD_DEVICE FSMC_Bank4
511	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
512
513	#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
514	#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
515	#define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
516	#define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
517
518	#define FMC_NORSRAM_Init FSMC_NORSRAM_Init
519	#define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
520	#define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
521	#define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
522	#define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
523	#define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
524
525	#define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
526	#define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
527
528	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
529	#define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
530	#define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
531	#define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
532
533	#define FMC_NAND_Init FSMC_NAND_Init
534	#define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
535	#define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
536	#define FMC_NAND_DeInit FSMC_NAND_DeInit
537	#define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
538	#define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
539	#define FMC_NAND_GetECC FSMC_NAND_GetECC
540	#define FMC_PCCARD_Init FSMC_PCCARD_Init
541	#define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
542	#define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
543	#define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
544	#define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
545
546	#define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
547	#define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
548	#define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
549	#define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
550	#define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
551	#define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
552	#define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
553	#define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
554	#define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
555	#define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
556	#define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
557	#define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
558	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
559
560	#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
561	#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
562	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
563	#define FMC_NAND_TypeDef FSMC_NAND_TypeDef
564	#define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
565	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
566
567	#define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
568	#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
569	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
570	#define FMC_NAND_DEVICE FSMC_NAND_DEVICE
571	#define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
572
573	#define FMC_NAND_BANK2 FSMC_NAND_BANK2
574	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
575
576	#define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
577	#define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
578	#define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
579
580	#define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
581	#define FMC_IT_LEVEL FSMC_IT_LEVEL
582	#define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
583	#define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
584
585	#define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
586	#define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
587	#define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
588	#define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
589	/**
590	* @}
591	*/
592
593	/**
594	* @}
595	*/
596
597	/* Private macro -------------------------------------------------------------*/
598	/** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
599	* @{
600	*/
601
602	/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
603	* @brief macros to handle NOR device enable/disable and read/write operations
604	* @{
605	*/
606	/**
607	* @brief Enable the NORSRAM device access.
608	* @param __INSTANCE__: FSMC_NORSRAM Instance
609	* @param __BANK__: FSMC_NORSRAM Bank
610	* @retval none
611	*/
612	#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FSMC_BCR1_MBKEN)
613
614	/**
615	* @brief Disable the NORSRAM device access.
616	* @param __INSTANCE__: FSMC_NORSRAM Instance
617	* @param __BANK__: FSMC_NORSRAM Bank
618	* @retval none
619	*/
620	#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
621	/**
622	* @}
623	*/
624
625	/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
626	* @brief macros to handle NAND device enable/disable
627	* @{
628	*/
629	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
630	/**
631	* @brief Enable the NAND device access.
632	* @param __INSTANCE__: FSMC_NAND Instance
633	* @param __BANK__: FSMC_NAND Bank
634	* @retval none
635	*/
636	#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FSMC_PCR2_PBKEN): \
637	((__INSTANCE__)->PCR3 \|= FSMC_PCR3_PBKEN))
638
639	/**
640	* @brief Disable the NAND device access.
641	* @param __INSTANCE__: FSMC_NAND Instance
642	* @param __BANK__: FSMC_NAND Bank
643	* @retval none
644	*/
645	#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
646	((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
647	/**
648	* @}
649	*/
650
651	/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
652	* @brief macros to handle SRAM read/write operations
653	* @{
654	*/
655	/**
656	* @brief Enable the PCCARD device access.
657	* @param __INSTANCE__: FSMC_PCCARD Instance
658	* @retval none
659	*/
660	#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FSMC_PCR4_PBKEN)
661
662	/**
663	* @brief Disable the PCCARD device access.
664	* @param __INSTANCE__: FSMC_PCCARD Instance
665	* @retval none
666	*/
667	#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
668	/**
669	* @}
670	*/
671
672	/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
673	* @brief macros to handle FSMC flags and interrupts
674	* @{
675	*/
676	/**
677	* @brief Enable the NAND device interrupt.
678	* @param __INSTANCE__: FSMC_NAND Instance
679	* @param __BANK__: FSMC_NAND Bank
680	* @param __INTERRUPT__: FSMC_NAND interrupt
681	* This parameter can be any combination of the following values:
682	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
683	* @arg FSMC_IT_LEVEL: Interrupt level.
684	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
685	* @retval None
686	*/
687	#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
688	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
689
690	/**
691	* @brief Disable the NAND device interrupt.
692	* @param __INSTANCE__: FSMC_NAND Instance
693	* @param __BANK__: FSMC_NAND Bank
694	* @param __INTERRUPT__: FSMC_NAND interrupt
695	* This parameter can be any combination of the following values:
696	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
697	* @arg FSMC_IT_LEVEL: Interrupt level.
698	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
699	* @retval None
700	*/
701	#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
702	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
703
704	/**
705	* @brief Get flag status of the NAND device.
706	* @param __INSTANCE__: FSMC_NAND Instance
707	* @param __BANK__ : FSMC_NAND Bank
708	* @param __FLAG__ : FSMC_NAND flag
709	* This parameter can be any combination of the following values:
710	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
711	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
712	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
713	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
714	* @retval The state of FLAG (SET or RESET).
715	*/
716	#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
717	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
718	/**
719	* @brief Clear flag status of the NAND device.
720	* @param __INSTANCE__: FSMC_NAND Instance
721	* @param __BANK__: FSMC_NAND Bank
722	* @param __FLAG__: FSMC_NAND flag
723	* This parameter can be any combination of the following values:
724	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
725	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
726	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
727	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
728	* @retval None
729	*/
730	#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
731	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
732	/**
733	* @brief Enable the PCCARD device interrupt.
734	* @param __INSTANCE__: FSMC_PCCARD Instance
735	* @param __INTERRUPT__: FSMC_PCCARD interrupt
736	* This parameter can be any combination of the following values:
737	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
738	* @arg FSMC_IT_LEVEL: Interrupt level.
739	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
740	* @retval None
741	*/
742	#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
743
744	/**
745	* @brief Disable the PCCARD device interrupt.
746	* @param __INSTANCE__: FSMC_PCCARD Instance
747	* @param __INTERRUPT__: FSMC_PCCARD interrupt
748	* This parameter can be any combination of the following values:
749	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
750	* @arg FSMC_IT_LEVEL: Interrupt level.
751	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
752	* @retval None
753	*/
754	#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
755
756	/**
757	* @brief Get flag status of the PCCARD device.
758	* @param __INSTANCE__: FSMC_PCCARD Instance
759	* @param __FLAG__: FSMC_PCCARD flag
760	* This parameter can be any combination of the following values:
761	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
762	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
763	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
764	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
765	* @retval The state of FLAG (SET or RESET).
766	*/
767	#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
768
769	/**
770	* @brief Clear flag status of the PCCARD device.
771	* @param __INSTANCE__: FSMC_PCCARD Instance
772	* @param __FLAG__: FSMC_PCCARD flag
773	* This parameter can be any combination of the following values:
774	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
775	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
776	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
777	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
778	* @retval None
779	*/
780	#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
781	/**
782	* @}
783	*/
784	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
785
786	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
787	* @{
788	*/
789	#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) \|\| \
790	((__BANK__) == FSMC_NORSRAM_BANK2) \|\| \
791	((__BANK__) == FSMC_NORSRAM_BANK3) \|\| \
792	((__BANK__) == FSMC_NORSRAM_BANK4))
793
794	#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
795	((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
796
797	#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) \|\| \
798	((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)\|\| \
799	((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
800
801	#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
802	((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
803	((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
804
805	#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) \|\| \
806	((__MODE__) == FSMC_ACCESS_MODE_B) \|\| \
807	((__MODE__) == FSMC_ACCESS_MODE_C) \|\| \
808	((__MODE__) == FSMC_ACCESS_MODE_D))
809
810	#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) \|\| \
811	((BANK) == FSMC_NAND_BANK3))
812
813	#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
814	((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
815
816	#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
817	((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
818
819	#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) \|\| \
820	((STATE) == FSMC_NAND_ECC_ENABLE))
821
822	#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
823	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
824	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
825	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
826	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
827	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
828
829	#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
830
831	#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
832
833	#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
834
835	#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
836
837	#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
838
839	#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
840
841	#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
842
843	#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
844
845	#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
846
847	#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
848
849	#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) \|\| \
850	((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
851
852	#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
853	((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
854
855	#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) \|\| \
856	((__MODE__) == FSMC_WRAP_MODE_ENABLE))
857
858	#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) \|\| \
859	((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
860
861	#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) \|\| \
862	((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
863
864	#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) \|\| \
865	((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
866
867	#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) \|\| \
868	((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
869
870	#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
871	((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
872
873	#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
874
875	#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) \|\| \
876	((__BURST__) == FSMC_WRITE_BURST_ENABLE))
877
878	#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
879
880	#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
881
882	#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
883
884	#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
885
886	#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
887	((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
888
889	#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
890
891	/**
892	* @}
893	*/
894	/**
895	* @}
896	*/
897
898	/* Private functions ---------------------------------------------------------*/
899	/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
900	* @{
901	*/
902
903	/** @defgroup FSMC_LL_NORSRAM NOR SRAM
904	* @{
905	*/
906
907	/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
908	* @{
909	*/
910	HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_InitTypeDef Init);
911	HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
912	HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
913	HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
914	/**
915	* @}
916	*/
917
918	/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
919	* @{
920	*/
921	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
922	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
923	/**
924	* @}
925	*/
926	/**
927	* @}
928	*/
929
930	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
931	/** @defgroup FSMC_LL_NAND NAND
932	* @{
933	*/
934	/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
935	* @{
936	*/
937	HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_InitTypeDef Init);
938	HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
939	HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
940	HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
941	/**
942	* @}
943	*/
944
945	/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
946	* @{
947	*/
948	HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
949	HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
950	HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
951	/**
952	* @}
953	*/
954	/**
955	* @}
956	*/
957
958	/** @defgroup FSMC_LL_PCCARD PCCARD
959	* @{
960	*/
961	/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
962	* @{
963	*/
964	HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef Device, FSMC_PCCARD_InitTypeDef Init);
965	HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
966	HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
967	HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
968	HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
969	/**
970	* @}
971	*/
972	/**
973	* @}
974	*/
975	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
976
977	/**
978	* @}
979	*/
980	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
981
982	/**
983	* @}
984	*/
985
986	/**
987	* @}
988	*/
989
990	#ifdef __cplusplus
991	}
992	#endif
993
994	#endif /* __STM32F4xx_LL_FSMC_H */
995
996	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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