[303] | 1 | /**
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| 2 | ******************************************************************************
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| 3 | * @file stm32f4xx_ll_fmc.h
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| 4 | * @author MCD Application Team
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| 5 | * @version V1.4.1
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| 6 | * @date 09-October-2015
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| 7 | * @brief Header file of FMC HAL module.
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| 8 | ******************************************************************************
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| 9 | * @attention
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| 10 | *
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| 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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| 12 | *
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| 13 | * Redistribution and use in source and binary forms, with or without modification,
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| 14 | * are permitted provided that the following conditions are met:
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| 15 | * 1. Redistributions of source code must retain the above copyright notice,
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| 16 | * this list of conditions and the following disclaimer.
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| 17 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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| 18 | * this list of conditions and the following disclaimer in the documentation
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| 19 | * and/or other materials provided with the distribution.
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| 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
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| 21 | * may be used to endorse or promote products derived from this software
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| 22 | * without specific prior written permission.
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| 23 | *
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| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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| 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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| 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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| 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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| 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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| 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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| 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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| 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 34 | *
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| 35 | ******************************************************************************
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| 36 | */
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| 37 |
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| 38 | /* Define to prevent recursive inclusion -------------------------------------*/
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| 39 | #ifndef __STM32F4xx_LL_FMC_H
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| 40 | #define __STM32F4xx_LL_FMC_H
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| 41 |
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| 42 | #ifdef __cplusplus
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| 43 | extern "C" {
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| 44 | #endif
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| 45 |
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| 46 | /* Includes ------------------------------------------------------------------*/
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| 47 | #include "stm32f4xx_hal_def.h"
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| 48 |
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| 49 | /** @addtogroup STM32F4xx_HAL_Driver
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| 50 | * @{
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| 51 | */
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| 52 |
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| 53 | /** @addtogroup FMC_LL
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| 54 | * @{
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| 55 | */
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| 56 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
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| 57 | defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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| 58 | /* Private types -------------------------------------------------------------*/
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| 59 | /** @defgroup FMC_LL_Private_Types FMC Private Types
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| 60 | * @{
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| 61 | */
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| 62 |
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| 63 | /**
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| 64 | * @brief FMC NORSRAM Configuration Structure definition
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| 65 | */
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| 66 | typedef struct
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| 67 | {
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| 68 | uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
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| 69 | This parameter can be a value of @ref FMC_NORSRAM_Bank */
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| 70 |
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| 71 | uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
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| 72 | multiplexed on the data bus or not.
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| 73 | This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
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| 74 |
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| 75 | uint32_t MemoryType; /*!< Specifies the type of external memory attached to
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| 76 | the corresponding memory device.
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| 77 | This parameter can be a value of @ref FMC_Memory_Type */
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| 78 |
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| 79 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
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| 80 | This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
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| 81 |
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| 82 | uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
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| 83 | valid only with synchronous burst Flash memories.
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| 84 | This parameter can be a value of @ref FMC_Burst_Access_Mode */
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| 85 |
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| 86 | uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
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| 87 | the Flash memory in burst mode.
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| 88 | This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
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| 89 |
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| 90 | uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
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| 91 | memory, valid only when accessing Flash memories in burst mode.
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| 92 | This parameter can be a value of @ref FMC_Wrap_Mode
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| 93 | This mode is not available for the STM32F446/467/479xx devices */
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| 94 |
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| 95 | uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
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| 96 | clock cycle before the wait state or during the wait state,
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| 97 | valid only when accessing memories in burst mode.
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| 98 | This parameter can be a value of @ref FMC_Wait_Timing */
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| 99 |
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| 100 | uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
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| 101 | This parameter can be a value of @ref FMC_Write_Operation */
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| 102 |
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| 103 | uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
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| 104 | signal, valid for Flash memory access in burst mode.
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| 105 | This parameter can be a value of @ref FMC_Wait_Signal */
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| 106 |
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| 107 | uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
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| 108 | This parameter can be a value of @ref FMC_Extended_Mode */
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| 109 |
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| 110 | uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
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| 111 | valid only with asynchronous Flash memories.
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| 112 | This parameter can be a value of @ref FMC_AsynchronousWait */
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| 113 |
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| 114 | uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
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| 115 | This parameter can be a value of @ref FMC_Write_Burst */
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| 116 |
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| 117 | uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
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| 118 | This parameter is only enabled through the FMC_BCR1 register, and don't care
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| 119 | through FMC_BCR2..4 registers.
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| 120 | This parameter can be a value of @ref FMC_Continous_Clock */
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| 121 |
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| 122 | uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
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| 123 | This parameter is only enabled through the FMC_BCR1 register, and don't care
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| 124 | through FMC_BCR2..4 registers.
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| 125 | This parameter can be a value of @ref FMC_Write_FIFO
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| 126 | This mode is available only for the STM32F446/469/479xx devices */
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| 127 |
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| 128 | uint32_t PageSize; /*!< Specifies the memory page size.
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| 129 | This parameter can be a value of @ref FMC_Page_Size
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| 130 | This mode is available only for the STM32F446xx devices */
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| 131 |
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| 132 | }FMC_NORSRAM_InitTypeDef;
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| 133 |
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| 134 | /**
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| 135 | * @brief FMC NORSRAM Timing parameters structure definition
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| 136 | */
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| 137 | typedef struct
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| 138 | {
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| 139 | uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
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| 140 | the duration of the address setup time.
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| 141 | This parameter can be a value between Min_Data = 0 and Max_Data = 15.
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| 142 | @note This parameter is not used with synchronous NOR Flash memories. */
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| 143 |
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| 144 | uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
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| 145 | the duration of the address hold time.
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| 146 | This parameter can be a value between Min_Data = 1 and Max_Data = 15.
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| 147 | @note This parameter is not used with synchronous NOR Flash memories. */
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| 148 |
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| 149 | uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
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| 150 | the duration of the data setup time.
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| 151 | This parameter can be a value between Min_Data = 1 and Max_Data = 255.
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| 152 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
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| 153 | NOR Flash memories. */
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| 154 |
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| 155 | uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
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| 156 | the duration of the bus turnaround.
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| 157 | This parameter can be a value between Min_Data = 0 and Max_Data = 15.
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| 158 | @note This parameter is only used for multiplexed NOR Flash memories. */
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| 159 |
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| 160 | uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
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| 161 | HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
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| 162 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
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| 163 | accesses. */
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| 164 |
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| 165 | uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
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| 166 | to the memory before getting the first data.
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| 167 | The parameter value depends on the memory type as shown below:
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| 168 | - It must be set to 0 in case of a CRAM
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| 169 | - It is don't care in asynchronous NOR, SRAM or ROM accesses
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| 170 | - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
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| 171 | with synchronous burst mode enable */
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| 172 |
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| 173 | uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
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| 174 | This parameter can be a value of @ref FMC_Access_Mode */
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| 175 | }FMC_NORSRAM_TimingTypeDef;
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| 176 |
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| 177 | /**
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| 178 | * @brief FMC NAND Configuration Structure definition
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| 179 | */
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| 180 | typedef struct
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| 181 | {
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| 182 | uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
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| 183 | This parameter can be a value of @ref FMC_NAND_Bank */
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| 184 |
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| 185 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
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| 186 | This parameter can be any value of @ref FMC_Wait_feature */
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| 187 |
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| 188 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
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| 189 | This parameter can be any value of @ref FMC_NAND_Data_Width */
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| 190 |
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| 191 | uint32_t EccComputation; /*!< Enables or disables the ECC computation.
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| 192 | This parameter can be any value of @ref FMC_ECC */
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| 193 |
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| 194 | uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
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| 195 | This parameter can be any value of @ref FMC_ECC_Page_Size */
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| 196 |
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| 197 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
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| 198 | delay between CLE low and RE low.
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| 199 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
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| 200 |
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| 201 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
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| 202 | delay between ALE low and RE low.
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| 203 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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| 204 | }FMC_NAND_InitTypeDef;
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| 205 |
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| 206 | /**
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| 207 | * @brief FMC NAND/PCCARD Timing parameters structure definition
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| 208 | */
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| 209 | typedef struct
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| 210 | {
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| 211 | uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
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| 212 | the command assertion for NAND-Flash read or write access
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| 213 | to common/Attribute or I/O memory space (depending on
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| 214 | the memory space timing to be configured).
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| 215 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
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| 216 |
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| 217 | uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
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| 218 | command for NAND-Flash read or write access to
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| 219 | common/Attribute or I/O memory space (depending on the
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| 220 | memory space timing to be configured).
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| 221 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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| 222 |
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| 223 | uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
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| 224 | (and data for write access) after the command de-assertion
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| 225 | for NAND-Flash read or write access to common/Attribute
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| 226 | or I/O memory space (depending on the memory space timing
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| 227 | to be configured).
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| 228 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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| 229 |
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| 230 | uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
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| 231 | data bus is kept in HiZ after the start of a NAND-Flash
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| 232 | write access to common/Attribute or I/O memory space (depending
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| 233 | on the memory space timing to be configured).
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| 234 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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| 235 | }FMC_NAND_PCC_TimingTypeDef;
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| 236 |
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| 237 | /**
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| 238 | * @brief FMC NAND Configuration Structure definition
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| 239 | */
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| 240 | typedef struct
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| 241 | {
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| 242 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
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| 243 | This parameter can be any value of @ref FMC_Wait_feature */
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| 244 |
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| 245 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
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| 246 | delay between CLE low and RE low.
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| 247 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
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| 248 |
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| 249 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
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| 250 | delay between ALE low and RE low.
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| 251 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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| 252 | }FMC_PCCARD_InitTypeDef;
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| 253 |
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| 254 | /**
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| 255 | * @brief FMC SDRAM Configuration Structure definition
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| 256 | */
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| 257 | typedef struct
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| 258 | {
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| 259 | uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
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| 260 | This parameter can be a value of @ref FMC_SDRAM_Bank */
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| 261 |
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| 262 | uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
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| 263 | This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
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| 264 |
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| 265 | uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
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| 266 | This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
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| 267 |
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| 268 | uint32_t MemoryDataWidth; /*!< Defines the memory device width.
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| 269 | This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
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| 270 |
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| 271 | uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
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| 272 | This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
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| 273 |
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| 274 | uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
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| 275 | This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
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| 276 |
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| 277 | uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
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| 278 | This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
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| 279 |
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| 280 | uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
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| 281 | to disable the clock before changing frequency.
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| 282 | This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
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| 283 |
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| 284 | uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
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| 285 | commands during the CAS latency and stores data in the Read FIFO.
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| 286 | This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
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| 287 |
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| 288 | uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
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| 289 | This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
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| 290 | }FMC_SDRAM_InitTypeDef;
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| 291 |
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| 292 | /**
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| 293 | * @brief FMC SDRAM Timing parameters structure definition
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| 294 | */
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| 295 | typedef struct
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| 296 | {
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| 297 | uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
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| 298 | an active or Refresh command in number of memory clock cycles.
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| 299 | This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
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| 300 |
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| 301 | uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
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| 302 | issuing the Activate command in number of memory clock cycles.
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| 303 | This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
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| 304 |
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| 305 | uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
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| 306 | cycles.
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| 307 | This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
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| 308 |
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| 309 | uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
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| 310 | and the delay between two consecutive Refresh commands in number of
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| 311 | memory clock cycles.
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| 312 | This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
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| 313 |
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| 314 | uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
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| 315 | This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
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| 316 |
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| 317 | uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
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| 318 | in number of memory clock cycles.
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| 319 | This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
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| 320 |
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| 321 | uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
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| 322 | command in number of memory clock cycles.
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| 323 | This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
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| 324 | }FMC_SDRAM_TimingTypeDef;
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| 325 |
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| 326 | /**
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| 327 | * @brief SDRAM command parameters structure definition
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| 328 | */
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| 329 | typedef struct
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| 330 | {
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| 331 | uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
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| 332 | This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
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| 333 |
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| 334 | uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
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| 335 | This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
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| 336 |
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| 337 | uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
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| 338 | in auto refresh mode.
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| 339 | This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
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| 340 | uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
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| 341 | }FMC_SDRAM_CommandTypeDef;
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| 342 | /**
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| 343 | * @}
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| 344 | */
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| 345 |
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| 346 | /* Private constants ---------------------------------------------------------*/
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| 347 | /** @defgroup FMC_LL_Private_Constants FMC Private Constants
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| 348 | * @{
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| 349 | */
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| 350 |
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| 351 | /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
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| 352 | * @{
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| 353 | */
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| 354 | /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
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| 355 | * @{
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| 356 | */
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| 357 | #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
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| 358 | #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
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| 359 | #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
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| 360 | #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
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| 361 | /**
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| 362 | * @}
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| 363 | */
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| 364 |
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| 365 | /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
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| 366 | * @{
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| 367 | */
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| 368 | #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
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| 369 | #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
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| 370 | /**
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| 371 | * @}
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| 372 | */
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| 373 |
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| 374 | /** @defgroup FMC_Memory_Type FMC Memory Type
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| 375 | * @{
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| 376 | */
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| 377 | #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
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| 378 | #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
|
---|
| 379 | #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
|
---|
| 380 | /**
|
---|
| 381 | * @}
|
---|
| 382 | */
|
---|
| 383 |
|
---|
| 384 | /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
|
---|
| 385 | * @{
|
---|
| 386 | */
|
---|
| 387 | #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
|
---|
| 388 | #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
|
---|
| 389 | #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
|
---|
| 390 | /**
|
---|
| 391 | * @}
|
---|
| 392 | */
|
---|
| 393 |
|
---|
| 394 | /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
|
---|
| 395 | * @{
|
---|
| 396 | */
|
---|
| 397 | #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
|
---|
| 398 | #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
|
---|
| 399 | /**
|
---|
| 400 | * @}
|
---|
| 401 | */
|
---|
| 402 |
|
---|
| 403 | /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
|
---|
| 404 | * @{
|
---|
| 405 | */
|
---|
| 406 | #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
|
---|
| 407 | #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
|
---|
| 408 | /**
|
---|
| 409 | * @}
|
---|
| 410 | */
|
---|
| 411 |
|
---|
| 412 | /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
|
---|
| 413 | * @{
|
---|
| 414 | */
|
---|
| 415 | #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
|
---|
| 416 | #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
|
---|
| 417 | /**
|
---|
| 418 | * @}
|
---|
| 419 | */
|
---|
| 420 |
|
---|
| 421 | /** @defgroup FMC_Wrap_Mode FMC Wrap Mode
|
---|
| 422 | * @{
|
---|
| 423 | */
|
---|
| 424 | /** @note This mode is not available for the STM32F446/469/479xx devices
|
---|
| 425 | */
|
---|
| 426 | #define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
|
---|
| 427 | #define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
|
---|
| 428 | /**
|
---|
| 429 | * @}
|
---|
| 430 | */
|
---|
| 431 |
|
---|
| 432 | /** @defgroup FMC_Wait_Timing FMC Wait Timing
|
---|
| 433 | * @{
|
---|
| 434 | */
|
---|
| 435 | #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
|
---|
| 436 | #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
|
---|
| 437 | /**
|
---|
| 438 | * @}
|
---|
| 439 | */
|
---|
| 440 |
|
---|
| 441 | /** @defgroup FMC_Write_Operation FMC Write Operation
|
---|
| 442 | * @{
|
---|
| 443 | */
|
---|
| 444 | #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
|
---|
| 445 | #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
|
---|
| 446 | /**
|
---|
| 447 | * @}
|
---|
| 448 | */
|
---|
| 449 |
|
---|
| 450 | /** @defgroup FMC_Wait_Signal FMC Wait Signal
|
---|
| 451 | * @{
|
---|
| 452 | */
|
---|
| 453 | #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
|
---|
| 454 | #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
|
---|
| 455 | /**
|
---|
| 456 | * @}
|
---|
| 457 | */
|
---|
| 458 |
|
---|
| 459 | /** @defgroup FMC_Extended_Mode FMC Extended Mode
|
---|
| 460 | * @{
|
---|
| 461 | */
|
---|
| 462 | #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
|
---|
| 463 | #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
|
---|
| 464 | /**
|
---|
| 465 | * @}
|
---|
| 466 | */
|
---|
| 467 |
|
---|
| 468 | /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
|
---|
| 469 | * @{
|
---|
| 470 | */
|
---|
| 471 | #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
|
---|
| 472 | #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
|
---|
| 473 | /**
|
---|
| 474 | * @}
|
---|
| 475 | */
|
---|
| 476 |
|
---|
| 477 | /** @defgroup FMC_Page_Size FMC Page Size
|
---|
| 478 | * @note These values are available only for the STM32F446/469/479xx devices.
|
---|
| 479 | * @{
|
---|
| 480 | */
|
---|
| 481 | #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
|
---|
| 482 | #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
|
---|
| 483 | #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
|
---|
| 484 | #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
|
---|
| 485 | /**
|
---|
| 486 | * @}
|
---|
| 487 | */
|
---|
| 488 |
|
---|
| 489 | /** @defgroup FMC_Write_FIFO FMC Write FIFO
|
---|
| 490 | * @note These values are available only for the STM32F446/469/479xx devices.
|
---|
| 491 | * @{
|
---|
| 492 | */
|
---|
| 493 | #define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000)
|
---|
| 494 | #define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS)
|
---|
| 495 | /**
|
---|
| 496 | * @}
|
---|
| 497 | */
|
---|
| 498 |
|
---|
| 499 | /** @defgroup FMC_Write_Burst FMC Write Burst
|
---|
| 500 | * @{
|
---|
| 501 | */
|
---|
| 502 | #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
|
---|
| 503 | #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
|
---|
| 504 | /**
|
---|
| 505 | * @}
|
---|
| 506 | */
|
---|
| 507 |
|
---|
| 508 | /** @defgroup FMC_Continous_Clock FMC Continuous Clock
|
---|
| 509 | * @{
|
---|
| 510 | */
|
---|
| 511 | #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
|
---|
| 512 | #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
|
---|
| 513 | /**
|
---|
| 514 | * @}
|
---|
| 515 | */
|
---|
| 516 |
|
---|
| 517 | /** @defgroup FMC_Access_Mode FMC Access Mode
|
---|
| 518 | * @{
|
---|
| 519 | */
|
---|
| 520 | #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
|
---|
| 521 | #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
|
---|
| 522 | #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
|
---|
| 523 | #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
|
---|
| 524 | /**
|
---|
| 525 | * @}
|
---|
| 526 | */
|
---|
| 527 |
|
---|
| 528 | /**
|
---|
| 529 | * @}
|
---|
| 530 | */
|
---|
| 531 |
|
---|
| 532 | /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
|
---|
| 533 | * @{
|
---|
| 534 | */
|
---|
| 535 | /** @defgroup FMC_NAND_Bank FMC NAND Bank
|
---|
| 536 | * @{
|
---|
| 537 | */
|
---|
| 538 | #define FMC_NAND_BANK2 ((uint32_t)0x00000010)
|
---|
| 539 | #define FMC_NAND_BANK3 ((uint32_t)0x00000100)
|
---|
| 540 | /**
|
---|
| 541 | * @}
|
---|
| 542 | */
|
---|
| 543 |
|
---|
| 544 | /** @defgroup FMC_Wait_feature FMC Wait feature
|
---|
| 545 | * @{
|
---|
| 546 | */
|
---|
| 547 | #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
|
---|
| 548 | #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
|
---|
| 549 | /**
|
---|
| 550 | * @}
|
---|
| 551 | */
|
---|
| 552 |
|
---|
| 553 | /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
|
---|
| 554 | * @{
|
---|
| 555 | */
|
---|
| 556 | #define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
|
---|
| 557 | #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
|
---|
| 558 | /**
|
---|
| 559 | * @}
|
---|
| 560 | */
|
---|
| 561 |
|
---|
| 562 | /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
|
---|
| 563 | * @{
|
---|
| 564 | */
|
---|
| 565 | #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
|
---|
| 566 | #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
|
---|
| 567 | /**
|
---|
| 568 | * @}
|
---|
| 569 | */
|
---|
| 570 |
|
---|
| 571 | /** @defgroup FMC_ECC FMC ECC
|
---|
| 572 | * @{
|
---|
| 573 | */
|
---|
| 574 | #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
|
---|
| 575 | #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
|
---|
| 576 | /**
|
---|
| 577 | * @}
|
---|
| 578 | */
|
---|
| 579 |
|
---|
| 580 | /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
|
---|
| 581 | * @{
|
---|
| 582 | */
|
---|
| 583 | #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
|
---|
| 584 | #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
|
---|
| 585 | #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
|
---|
| 586 | #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
|
---|
| 587 | #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
|
---|
| 588 | #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
|
---|
| 589 | /**
|
---|
| 590 | * @}
|
---|
| 591 | */
|
---|
| 592 |
|
---|
| 593 | /**
|
---|
| 594 | * @}
|
---|
| 595 | */
|
---|
| 596 |
|
---|
| 597 | /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
|
---|
| 598 | * @{
|
---|
| 599 | */
|
---|
| 600 | /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
|
---|
| 601 | * @{
|
---|
| 602 | */
|
---|
| 603 | #define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
|
---|
| 604 | #define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
|
---|
| 605 | /**
|
---|
| 606 | * @}
|
---|
| 607 | */
|
---|
| 608 |
|
---|
| 609 | /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
|
---|
| 610 | * @{
|
---|
| 611 | */
|
---|
| 612 | #define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
|
---|
| 613 | #define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
|
---|
| 614 | #define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
|
---|
| 615 | #define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
|
---|
| 616 | /**
|
---|
| 617 | * @}
|
---|
| 618 | */
|
---|
| 619 |
|
---|
| 620 | /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
|
---|
| 621 | * @{
|
---|
| 622 | */
|
---|
| 623 | #define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
|
---|
| 624 | #define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
|
---|
| 625 | #define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
|
---|
| 626 | /**
|
---|
| 627 | * @}
|
---|
| 628 | */
|
---|
| 629 |
|
---|
| 630 | /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
|
---|
| 631 | * @{
|
---|
| 632 | */
|
---|
| 633 | #define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
|
---|
| 634 | #define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
|
---|
| 635 | #define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
|
---|
| 636 | /**
|
---|
| 637 | * @}
|
---|
| 638 | */
|
---|
| 639 |
|
---|
| 640 | /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
|
---|
| 641 | * @{
|
---|
| 642 | */
|
---|
| 643 | #define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
|
---|
| 644 | #define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
|
---|
| 645 | /**
|
---|
| 646 | * @}
|
---|
| 647 | */
|
---|
| 648 |
|
---|
| 649 | /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
|
---|
| 650 | * @{
|
---|
| 651 | */
|
---|
| 652 | #define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
|
---|
| 653 | #define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
|
---|
| 654 | #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
|
---|
| 655 | /**
|
---|
| 656 | * @}
|
---|
| 657 | */
|
---|
| 658 |
|
---|
| 659 | /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
|
---|
| 660 | * @{
|
---|
| 661 | */
|
---|
| 662 | #define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
|
---|
| 663 | #define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
|
---|
| 664 |
|
---|
| 665 | /**
|
---|
| 666 | * @}
|
---|
| 667 | */
|
---|
| 668 |
|
---|
| 669 | /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
|
---|
| 670 | * @{
|
---|
| 671 | */
|
---|
| 672 | #define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
|
---|
| 673 | #define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
|
---|
| 674 | #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
|
---|
| 675 | /**
|
---|
| 676 | * @}
|
---|
| 677 | */
|
---|
| 678 |
|
---|
| 679 | /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
|
---|
| 680 | * @{
|
---|
| 681 | */
|
---|
| 682 | #define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
|
---|
| 683 | #define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
|
---|
| 684 | /**
|
---|
| 685 | * @}
|
---|
| 686 | */
|
---|
| 687 |
|
---|
| 688 | /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
|
---|
| 689 | * @{
|
---|
| 690 | */
|
---|
| 691 | #define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
|
---|
| 692 | #define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
|
---|
| 693 | #define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
|
---|
| 694 | /**
|
---|
| 695 | * @}
|
---|
| 696 | */
|
---|
| 697 |
|
---|
| 698 | /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
|
---|
| 699 | * @{
|
---|
| 700 | */
|
---|
| 701 | #define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
|
---|
| 702 | #define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
|
---|
| 703 | #define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
|
---|
| 704 | #define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
|
---|
| 705 | #define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
|
---|
| 706 | #define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
|
---|
| 707 | #define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
|
---|
| 708 | /**
|
---|
| 709 | * @}
|
---|
| 710 | */
|
---|
| 711 |
|
---|
| 712 | /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
|
---|
| 713 | * @{
|
---|
| 714 | */
|
---|
| 715 | #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
|
---|
| 716 | #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
|
---|
| 717 | #define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
|
---|
| 718 | /**
|
---|
| 719 | * @}
|
---|
| 720 | */
|
---|
| 721 |
|
---|
| 722 | /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
|
---|
| 723 | * @{
|
---|
| 724 | */
|
---|
| 725 | #define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
|
---|
| 726 | #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
|
---|
| 727 | #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
|
---|
| 728 | /**
|
---|
| 729 | * @}
|
---|
| 730 | */
|
---|
| 731 |
|
---|
| 732 | /**
|
---|
| 733 | * @}
|
---|
| 734 | */
|
---|
| 735 |
|
---|
| 736 | /** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
|
---|
| 737 | * @{
|
---|
| 738 | */
|
---|
| 739 | #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
|
---|
| 740 | #define FMC_IT_LEVEL ((uint32_t)0x00000010)
|
---|
| 741 | #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
|
---|
| 742 | #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
|
---|
| 743 | /**
|
---|
| 744 | * @}
|
---|
| 745 | */
|
---|
| 746 |
|
---|
| 747 | /** @defgroup FMC_LL_Flag_definition FMC Flag definition
|
---|
| 748 | * @{
|
---|
| 749 | */
|
---|
| 750 | #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
|
---|
| 751 | #define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
|
---|
| 752 | #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
|
---|
| 753 | #define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
|
---|
| 754 | #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
|
---|
| 755 | #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
|
---|
| 756 | #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
|
---|
| 757 | /**
|
---|
| 758 | * @}
|
---|
| 759 | */
|
---|
| 760 |
|
---|
| 761 | /** @defgroup FMC_LL_Alias_definition FMC Alias definition
|
---|
| 762 | * @{
|
---|
| 763 | */
|
---|
| 764 | #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
---|
| 765 | #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
|
---|
| 766 | #else
|
---|
| 767 | #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
|
---|
| 768 | #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
|
---|
| 769 | #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
|
---|
| 770 | #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
|
---|
| 771 | #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
|
---|
| 772 | #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
|
---|
| 773 |
|
---|
| 774 |
|
---|
| 775 | #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
---|
| 776 | #define FMC_NAND_DEVICE FMC_Bank3
|
---|
| 777 | #else
|
---|
| 778 | #define FMC_NAND_DEVICE FMC_Bank2_3
|
---|
| 779 | #define FMC_PCCARD_DEVICE FMC_Bank4
|
---|
| 780 | #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
|
---|
| 781 | #define FMC_NORSRAM_DEVICE FMC_Bank1
|
---|
| 782 | #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
|
---|
| 783 | #define FMC_SDRAM_DEVICE FMC_Bank5_6
|
---|
| 784 | /**
|
---|
| 785 | * @}
|
---|
| 786 | */
|
---|
| 787 |
|
---|
| 788 | /**
|
---|
| 789 | * @}
|
---|
| 790 | */
|
---|
| 791 |
|
---|
| 792 | /* Private macro -------------------------------------------------------------*/
|
---|
| 793 | /** @defgroup FMC_LL_Private_Macros FMC Private Macros
|
---|
| 794 | * @{
|
---|
| 795 | */
|
---|
| 796 |
|
---|
| 797 | /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
|
---|
| 798 | * @brief macros to handle NOR device enable/disable and read/write operations
|
---|
| 799 | * @{
|
---|
| 800 | */
|
---|
| 801 | /**
|
---|
| 802 | * @brief Enable the NORSRAM device access.
|
---|
| 803 | * @param __INSTANCE__: FMC_NORSRAM Instance
|
---|
| 804 | * @param __BANK__: FMC_NORSRAM Bank
|
---|
| 805 | * @retval None
|
---|
| 806 | */
|
---|
| 807 | #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
|
---|
| 808 |
|
---|
| 809 | /**
|
---|
| 810 | * @brief Disable the NORSRAM device access.
|
---|
| 811 | * @param __INSTANCE__: FMC_NORSRAM Instance
|
---|
| 812 | * @param __BANK__: FMC_NORSRAM Bank
|
---|
| 813 | * @retval None
|
---|
| 814 | */
|
---|
| 815 | #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
|
---|
| 816 | /**
|
---|
| 817 | * @}
|
---|
| 818 | */
|
---|
| 819 |
|
---|
| 820 | /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
|
---|
| 821 | * @brief macros to handle NAND device enable/disable
|
---|
| 822 | * @{
|
---|
| 823 | */
|
---|
| 824 | #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
---|
| 825 | /**
|
---|
| 826 | * @brief Enable the NAND device access.
|
---|
| 827 | * @param __INSTANCE__: FMC_NAND Instance
|
---|
| 828 | * @param __BANK__: FMC_NAND Bank
|
---|
| 829 | * @retval None
|
---|
| 830 | */
|
---|
| 831 | #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
|
---|
| 832 |
|
---|
| 833 | /**
|
---|
| 834 | * @brief Disable the NAND device access.
|
---|
| 835 | * @param __INSTANCE__: FMC_NAND Instance
|
---|
| 836 | * @param __BANK__: FMC_NAND Bank
|
---|
| 837 | * @retval None
|
---|
| 838 | */
|
---|
| 839 | #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
|
---|
| 840 | #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
|
---|
| 841 | /**
|
---|
| 842 | * @brief Enable the NAND device access.
|
---|
| 843 | * @param __INSTANCE__: FMC_NAND Instance
|
---|
| 844 | * @param __BANK__: FMC_NAND Bank
|
---|
| 845 | * @retval None
|
---|
| 846 | */
|
---|
| 847 | #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
|
---|
| 848 | ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
|
---|
| 849 |
|
---|
| 850 | /**
|
---|
| 851 | * @brief Disable the NAND device access.
|
---|
| 852 | * @param __INSTANCE__: FMC_NAND Instance
|
---|
| 853 | * @param __BANK__: FMC_NAND Bank
|
---|
| 854 | * @retval None
|
---|
| 855 | */
|
---|
| 856 | #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
|
---|
| 857 | ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
|
---|
| 858 |
|
---|
| 859 | #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
|
---|
| 860 | /**
|
---|
| 861 | * @}
|
---|
| 862 | */
|
---|
| 863 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
---|
| 864 | /** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
|
---|
| 865 | * @brief macros to handle SRAM read/write operations
|
---|
| 866 | * @{
|
---|
| 867 | */
|
---|
| 868 | /**
|
---|
| 869 | * @brief Enable the PCCARD device access.
|
---|
| 870 | * @param __INSTANCE__: FMC_PCCARD Instance
|
---|
| 871 | * @retval None
|
---|
| 872 | */
|
---|
| 873 | #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
|
---|
| 874 |
|
---|
| 875 | /**
|
---|
| 876 | * @brief Disable the PCCARD device access.
|
---|
| 877 | * @param __INSTANCE__: FMC_PCCARD Instance
|
---|
| 878 | * @retval None
|
---|
| 879 | */
|
---|
| 880 | #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
|
---|
| 881 | /**
|
---|
| 882 | * @}
|
---|
| 883 | */
|
---|
| 884 | #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
|
---|
| 885 |
|
---|
| 886 | /** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
|
---|
| 887 | * @brief macros to handle FMC flags and interrupts
|
---|
| 888 | * @{
|
---|
| 889 | */
|
---|
| 890 | #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
---|
| 891 | /**
|
---|
| 892 | * @brief Enable the NAND device interrupt.
|
---|
| 893 | * @param __INSTANCE__: FMC_NAND instance
|
---|
| 894 | * @param __BANK__: FMC_NAND Bank
|
---|
| 895 | * @param __INTERRUPT__: FMC_NAND interrupt
|
---|
| 896 | * This parameter can be any combination of the following values:
|
---|
| 897 | * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
|
---|
| 898 | * @arg FMC_IT_LEVEL: Interrupt level.
|
---|
| 899 | * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
|
---|
| 900 | * @retval None
|
---|
| 901 | */
|
---|
| 902 | #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
|
---|
| 903 |
|
---|
| 904 | /**
|
---|
| 905 | * @brief Disable the NAND device interrupt.
|
---|
| 906 | * @param __INSTANCE__: FMC_NAND Instance
|
---|
| 907 | * @param __BANK__: FMC_NAND Bank
|
---|
| 908 | * @param __INTERRUPT__: FMC_NAND interrupt
|
---|
| 909 | * This parameter can be any combination of the following values:
|
---|
| 910 | * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
|
---|
| 911 | * @arg FMC_IT_LEVEL: Interrupt level.
|
---|
| 912 | * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
|
---|
| 913 | * @retval None
|
---|
| 914 | */
|
---|
| 915 | #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
|
---|
| 916 |
|
---|
| 917 | /**
|
---|
| 918 | * @brief Get flag status of the NAND device.
|
---|
| 919 | * @param __INSTANCE__: FMC_NAND Instance
|
---|
| 920 | * @param __BANK__: FMC_NAND Bank
|
---|
| 921 | * @param __FLAG__: FMC_NAND flag
|
---|
| 922 | * This parameter can be any combination of the following values:
|
---|
| 923 | * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
---|
| 924 | * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
|
---|
| 925 | * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
---|
| 926 | * @arg FMC_FLAG_FEMPT: FIFO empty flag.
|
---|
| 927 | * @retval The state of FLAG (SET or RESET).
|
---|
| 928 | */
|
---|
| 929 | #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
|
---|
| 930 | /**
|
---|
| 931 | * @brief Clear flag status of the NAND device.
|
---|
| 932 | * @param __INSTANCE__: FMC_NAND Instance
|
---|
| 933 | * @param __BANK__: FMC_NAND Bank
|
---|
| 934 | * @param __FLAG__: FMC_NAND flag
|
---|
| 935 | * This parameter can be any combination of the following values:
|
---|
| 936 | * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
---|
| 937 | * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
|
---|
| 938 | * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
---|
| 939 | * @arg FMC_FLAG_FEMPT: FIFO empty flag.
|
---|
| 940 | * @retval None
|
---|
| 941 | */
|
---|
| 942 | #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
|
---|
| 943 | #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
|
---|
| 944 | /**
|
---|
| 945 | * @brief Enable the NAND device interrupt.
|
---|
| 946 | * @param __INSTANCE__: FMC_NAND instance
|
---|
| 947 | * @param __BANK__: FMC_NAND Bank
|
---|
| 948 | * @param __INTERRUPT__: FMC_NAND interrupt
|
---|
| 949 | * This parameter can be any combination of the following values:
|
---|
| 950 | * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
|
---|
| 951 | * @arg FMC_IT_LEVEL: Interrupt level.
|
---|
| 952 | * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
|
---|
| 953 | * @retval None
|
---|
| 954 | */
|
---|
| 955 | #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
|
---|
| 956 | ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
|
---|
| 957 |
|
---|
| 958 | /**
|
---|
| 959 | * @brief Disable the NAND device interrupt.
|
---|
| 960 | * @param __INSTANCE__: FMC_NAND Instance
|
---|
| 961 | * @param __BANK__: FMC_NAND Bank
|
---|
| 962 | * @param __INTERRUPT__: FMC_NAND interrupt
|
---|
| 963 | * This parameter can be any combination of the following values:
|
---|
| 964 | * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
|
---|
| 965 | * @arg FMC_IT_LEVEL: Interrupt level.
|
---|
| 966 | * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
|
---|
| 967 | * @retval None
|
---|
| 968 | */
|
---|
| 969 | #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
|
---|
| 970 | ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
|
---|
| 971 |
|
---|
| 972 | /**
|
---|
| 973 | * @brief Get flag status of the NAND device.
|
---|
| 974 | * @param __INSTANCE__: FMC_NAND Instance
|
---|
| 975 | * @param __BANK__: FMC_NAND Bank
|
---|
| 976 | * @param __FLAG__: FMC_NAND flag
|
---|
| 977 | * This parameter can be any combination of the following values:
|
---|
| 978 | * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
---|
| 979 | * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
|
---|
| 980 | * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
---|
| 981 | * @arg FMC_FLAG_FEMPT: FIFO empty flag.
|
---|
| 982 | * @retval The state of FLAG (SET or RESET).
|
---|
| 983 | */
|
---|
| 984 | #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
|
---|
| 985 | (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
|
---|
| 986 | /**
|
---|
| 987 | * @brief Clear flag status of the NAND device.
|
---|
| 988 | * @param __INSTANCE__: FMC_NAND Instance
|
---|
| 989 | * @param __BANK__: FMC_NAND Bank
|
---|
| 990 | * @param __FLAG__: FMC_NAND flag
|
---|
| 991 | * This parameter can be any combination of the following values:
|
---|
| 992 | * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
---|
| 993 | * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
|
---|
| 994 | * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
---|
| 995 | * @arg FMC_FLAG_FEMPT: FIFO empty flag.
|
---|
| 996 | * @retval None
|
---|
| 997 | */
|
---|
| 998 | #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
|
---|
| 999 | ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
|
---|
| 1000 | #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
|
---|
| 1001 |
|
---|
| 1002 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
---|
| 1003 | /**
|
---|
| 1004 | * @brief Enable the PCCARD device interrupt.
|
---|
| 1005 | * @param __INSTANCE__: FMC_PCCARD instance
|
---|
| 1006 | * @param __INTERRUPT__: FMC_PCCARD interrupt
|
---|
| 1007 | * This parameter can be any combination of the following values:
|
---|
| 1008 | * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
|
---|
| 1009 | * @arg FMC_IT_LEVEL: Interrupt level.
|
---|
| 1010 | * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
|
---|
| 1011 | * @retval None
|
---|
| 1012 | */
|
---|
| 1013 | #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
|
---|
| 1014 |
|
---|
| 1015 | /**
|
---|
| 1016 | * @brief Disable the PCCARD device interrupt.
|
---|
| 1017 | * @param __INSTANCE__: FMC_PCCARD instance
|
---|
| 1018 | * @param __INTERRUPT__: FMC_PCCARD interrupt
|
---|
| 1019 | * This parameter can be any combination of the following values:
|
---|
| 1020 | * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
|
---|
| 1021 | * @arg FMC_IT_LEVEL: Interrupt level.
|
---|
| 1022 | * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
|
---|
| 1023 | * @retval None
|
---|
| 1024 | */
|
---|
| 1025 | #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
|
---|
| 1026 |
|
---|
| 1027 | /**
|
---|
| 1028 | * @brief Get flag status of the PCCARD device.
|
---|
| 1029 | * @param __INSTANCE__: FMC_PCCARD instance
|
---|
| 1030 | * @param __FLAG__: FMC_PCCARD flag
|
---|
| 1031 | * This parameter can be any combination of the following values:
|
---|
| 1032 | * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
---|
| 1033 | * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
|
---|
| 1034 | * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
---|
| 1035 | * @arg FMC_FLAG_FEMPT: FIFO empty flag.
|
---|
| 1036 | * @retval The state of FLAG (SET or RESET).
|
---|
| 1037 | */
|
---|
| 1038 | #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
|
---|
| 1039 |
|
---|
| 1040 | /**
|
---|
| 1041 | * @brief Clear flag status of the PCCARD device.
|
---|
| 1042 | * @param __INSTANCE__: FMC_PCCARD instance
|
---|
| 1043 | * @param __FLAG__: FMC_PCCARD flag
|
---|
| 1044 | * This parameter can be any combination of the following values:
|
---|
| 1045 | * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
---|
| 1046 | * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
|
---|
| 1047 | * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
---|
| 1048 | * @arg FMC_FLAG_FEMPT: FIFO empty flag.
|
---|
| 1049 | * @retval None
|
---|
| 1050 | */
|
---|
| 1051 | #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
|
---|
| 1052 | #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
|
---|
| 1053 |
|
---|
| 1054 | /**
|
---|
| 1055 | * @brief Enable the SDRAM device interrupt.
|
---|
| 1056 | * @param __INSTANCE__: FMC_SDRAM instance
|
---|
| 1057 | * @param __INTERRUPT__: FMC_SDRAM interrupt
|
---|
| 1058 | * This parameter can be any combination of the following values:
|
---|
| 1059 | * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
|
---|
| 1060 | * @retval None
|
---|
| 1061 | */
|
---|
| 1062 | #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
|
---|
| 1063 |
|
---|
| 1064 | /**
|
---|
| 1065 | * @brief Disable the SDRAM device interrupt.
|
---|
| 1066 | * @param __INSTANCE__: FMC_SDRAM instance
|
---|
| 1067 | * @param __INTERRUPT__: FMC_SDRAM interrupt
|
---|
| 1068 | * This parameter can be any combination of the following values:
|
---|
| 1069 | * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
|
---|
| 1070 | * @retval None
|
---|
| 1071 | */
|
---|
| 1072 | #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
|
---|
| 1073 |
|
---|
| 1074 | /**
|
---|
| 1075 | * @brief Get flag status of the SDRAM device.
|
---|
| 1076 | * @param __INSTANCE__: FMC_SDRAM instance
|
---|
| 1077 | * @param __FLAG__: FMC_SDRAM flag
|
---|
| 1078 | * This parameter can be any combination of the following values:
|
---|
| 1079 | * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
|
---|
| 1080 | * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
|
---|
| 1081 | * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
|
---|
| 1082 | * @retval The state of FLAG (SET or RESET).
|
---|
| 1083 | */
|
---|
| 1084 | #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
|
---|
| 1085 |
|
---|
| 1086 | /**
|
---|
| 1087 | * @brief Clear flag status of the SDRAM device.
|
---|
| 1088 | * @param __INSTANCE__: FMC_SDRAM instance
|
---|
| 1089 | * @param __FLAG__: FMC_SDRAM flag
|
---|
| 1090 | * This parameter can be any combination of the following values:
|
---|
| 1091 | * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
|
---|
| 1092 | * @retval None
|
---|
| 1093 | */
|
---|
| 1094 | #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
|
---|
| 1095 | /**
|
---|
| 1096 | * @}
|
---|
| 1097 | */
|
---|
| 1098 |
|
---|
| 1099 | /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
|
---|
| 1100 | * @{
|
---|
| 1101 | */
|
---|
| 1102 | #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
|
---|
| 1103 | ((BANK) == FMC_NORSRAM_BANK2) || \
|
---|
| 1104 | ((BANK) == FMC_NORSRAM_BANK3) || \
|
---|
| 1105 | ((BANK) == FMC_NORSRAM_BANK4))
|
---|
| 1106 |
|
---|
| 1107 | #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
|
---|
| 1108 | ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
|
---|
| 1109 |
|
---|
| 1110 | #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
|
---|
| 1111 | ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
|
---|
| 1112 | ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
|
---|
| 1113 |
|
---|
| 1114 | #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
|
---|
| 1115 | ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
|
---|
| 1116 | ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
|
---|
| 1117 |
|
---|
| 1118 | #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
|
---|
| 1119 | ((__MODE__) == FMC_ACCESS_MODE_B) || \
|
---|
| 1120 | ((__MODE__) == FMC_ACCESS_MODE_C) || \
|
---|
| 1121 | ((__MODE__) == FMC_ACCESS_MODE_D))
|
---|
| 1122 |
|
---|
| 1123 | #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
|
---|
| 1124 | ((BANK) == FMC_NAND_BANK3))
|
---|
| 1125 |
|
---|
| 1126 | #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
|
---|
| 1127 | ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
|
---|
| 1128 |
|
---|
| 1129 | #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
|
---|
| 1130 | ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
|
---|
| 1131 |
|
---|
| 1132 | #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
|
---|
| 1133 | ((STATE) == FMC_NAND_ECC_ENABLE))
|
---|
| 1134 |
|
---|
| 1135 | #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
|
---|
| 1136 | ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
|
---|
| 1137 | ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
|
---|
| 1138 | ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
|
---|
| 1139 | ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
|
---|
| 1140 | ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
|
---|
| 1141 |
|
---|
| 1142 | #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
|
---|
| 1143 |
|
---|
| 1144 | #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
|
---|
| 1145 |
|
---|
| 1146 | #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
|
---|
| 1147 |
|
---|
| 1148 | #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
|
---|
| 1149 |
|
---|
| 1150 | #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
|
---|
| 1151 |
|
---|
| 1152 | #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
|
---|
| 1153 |
|
---|
| 1154 | #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
|
---|
| 1155 |
|
---|
| 1156 | #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
|
---|
| 1157 |
|
---|
| 1158 | #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
|
---|
| 1159 |
|
---|
| 1160 | #define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
|
---|
| 1161 |
|
---|
| 1162 | #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
|
---|
| 1163 | ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
|
---|
| 1164 |
|
---|
| 1165 | #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
|
---|
| 1166 | ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
|
---|
| 1167 |
|
---|
| 1168 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
---|
| 1169 | #define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
|
---|
| 1170 | ((__MODE__) == FMC_WRAP_MODE_ENABLE))
|
---|
| 1171 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
---|
| 1172 |
|
---|
| 1173 | #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
|
---|
| 1174 | ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
|
---|
| 1175 |
|
---|
| 1176 | #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
|
---|
| 1177 | ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
|
---|
| 1178 |
|
---|
| 1179 | #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
|
---|
| 1180 | ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
|
---|
| 1181 |
|
---|
| 1182 | #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
|
---|
| 1183 | ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
|
---|
| 1184 |
|
---|
| 1185 | #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
|
---|
| 1186 | ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
|
---|
| 1187 |
|
---|
| 1188 | #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
|
---|
| 1189 | ((__BURST__) == FMC_WRITE_BURST_ENABLE))
|
---|
| 1190 |
|
---|
| 1191 | #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
|
---|
| 1192 | ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
|
---|
| 1193 |
|
---|
| 1194 | #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
|
---|
| 1195 |
|
---|
| 1196 | #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
|
---|
| 1197 |
|
---|
| 1198 | #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
|
---|
| 1199 |
|
---|
| 1200 | #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
|
---|
| 1201 |
|
---|
| 1202 | #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
|
---|
| 1203 |
|
---|
| 1204 | #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
|
---|
| 1205 |
|
---|
| 1206 | #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
|
---|
| 1207 | ((BANK) == FMC_SDRAM_BANK2))
|
---|
| 1208 |
|
---|
| 1209 | #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
|
---|
| 1210 | ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
|
---|
| 1211 | ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
|
---|
| 1212 | ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
|
---|
| 1213 |
|
---|
| 1214 | #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
|
---|
| 1215 | ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
|
---|
| 1216 | ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
|
---|
| 1217 |
|
---|
| 1218 | #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
|
---|
| 1219 | ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
|
---|
| 1220 | ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
|
---|
| 1221 |
|
---|
| 1222 | #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
|
---|
| 1223 | ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
|
---|
| 1224 |
|
---|
| 1225 |
|
---|
| 1226 | #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
|
---|
| 1227 | ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
|
---|
| 1228 | ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
|
---|
| 1229 |
|
---|
| 1230 | #define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \
|
---|
| 1231 | ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \
|
---|
| 1232 | ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
|
---|
| 1233 |
|
---|
| 1234 | #define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \
|
---|
| 1235 | ((RBURST) == FMC_SDRAM_RBURST_ENABLE))
|
---|
| 1236 |
|
---|
| 1237 |
|
---|
| 1238 | #define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \
|
---|
| 1239 | ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
|
---|
| 1240 | ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
|
---|
| 1241 |
|
---|
| 1242 | #define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
|
---|
| 1243 |
|
---|
| 1244 | #define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
|
---|
| 1245 |
|
---|
| 1246 | #define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
|
---|
| 1247 |
|
---|
| 1248 | #define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
|
---|
| 1249 |
|
---|
| 1250 | #define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
|
---|
| 1251 |
|
---|
| 1252 | #define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
|
---|
| 1253 |
|
---|
| 1254 | #define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
|
---|
| 1255 |
|
---|
| 1256 | #define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \
|
---|
| 1257 | ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \
|
---|
| 1258 | ((COMMAND) == FMC_SDRAM_CMD_PALL) || \
|
---|
| 1259 | ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
|
---|
| 1260 | ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \
|
---|
| 1261 | ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
|
---|
| 1262 | ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
|
---|
| 1263 |
|
---|
| 1264 | #define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \
|
---|
| 1265 | ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
|
---|
| 1266 | ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
|
---|
| 1267 |
|
---|
| 1268 | #define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
|
---|
| 1269 |
|
---|
| 1270 | #define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
|
---|
| 1271 |
|
---|
| 1272 | #define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
|
---|
| 1273 |
|
---|
| 1274 | #define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
|
---|
| 1275 |
|
---|
| 1276 | #define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
|
---|
| 1277 | ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
|
---|
| 1278 |
|
---|
| 1279 | #if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
---|
| 1280 | #define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) || \
|
---|
| 1281 | ((SIZE) == FMC_PAGE_SIZE_128) || \
|
---|
| 1282 | ((SIZE) == FMC_PAGE_SIZE_256) || \
|
---|
| 1283 | ((SIZE) == FMC_PAGE_SIZE_1024))
|
---|
| 1284 |
|
---|
| 1285 | #define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) || \
|
---|
| 1286 | ((FIFO) == FMC_WRITE_FIFO_ENABLE))
|
---|
| 1287 | #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
|
---|
| 1288 |
|
---|
| 1289 | /**
|
---|
| 1290 | * @}
|
---|
| 1291 | */
|
---|
| 1292 |
|
---|
| 1293 | /**
|
---|
| 1294 | * @}
|
---|
| 1295 | */
|
---|
| 1296 |
|
---|
| 1297 | /* Private functions ---------------------------------------------------------*/
|
---|
| 1298 | /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
|
---|
| 1299 | * @{
|
---|
| 1300 | */
|
---|
| 1301 |
|
---|
| 1302 | /** @defgroup FMC_LL_NORSRAM NOR SRAM
|
---|
| 1303 | * @{
|
---|
| 1304 | */
|
---|
| 1305 | /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
|
---|
| 1306 | * @{
|
---|
| 1307 | */
|
---|
| 1308 | HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
|
---|
| 1309 | HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
|
---|
| 1310 | HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
|
---|
| 1311 | HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
|
---|
| 1312 | /**
|
---|
| 1313 | * @}
|
---|
| 1314 | */
|
---|
| 1315 |
|
---|
| 1316 | /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
|
---|
| 1317 | * @{
|
---|
| 1318 | */
|
---|
| 1319 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
|
---|
| 1320 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
|
---|
| 1321 | /**
|
---|
| 1322 | * @}
|
---|
| 1323 | */
|
---|
| 1324 | /**
|
---|
| 1325 | * @}
|
---|
| 1326 | */
|
---|
| 1327 |
|
---|
| 1328 | /** @defgroup FMC_LL_NAND NAND
|
---|
| 1329 | * @{
|
---|
| 1330 | */
|
---|
| 1331 | /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
|
---|
| 1332 | * @{
|
---|
| 1333 | */
|
---|
| 1334 | HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
|
---|
| 1335 | HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
---|
| 1336 | HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
---|
| 1337 | HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
|
---|
| 1338 | /**
|
---|
| 1339 | * @}
|
---|
| 1340 | */
|
---|
| 1341 |
|
---|
| 1342 | /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
|
---|
| 1343 | * @{
|
---|
| 1344 | */
|
---|
| 1345 | HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
|
---|
| 1346 | HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
|
---|
| 1347 | HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
|
---|
| 1348 |
|
---|
| 1349 | /**
|
---|
| 1350 | * @}
|
---|
| 1351 | */
|
---|
| 1352 | /**
|
---|
| 1353 | * @}
|
---|
| 1354 | */
|
---|
| 1355 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
---|
| 1356 | /** @defgroup FMC_LL_PCCARD PCCARD
|
---|
| 1357 | * @{
|
---|
| 1358 | */
|
---|
| 1359 | /** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
|
---|
| 1360 | * @{
|
---|
| 1361 | */
|
---|
| 1362 | HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
|
---|
| 1363 | HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
|
---|
| 1364 | HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
|
---|
| 1365 | HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
|
---|
| 1366 | HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
|
---|
| 1367 | /**
|
---|
| 1368 | * @}
|
---|
| 1369 | */
|
---|
| 1370 | /**
|
---|
| 1371 | * @}
|
---|
| 1372 | */
|
---|
| 1373 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
---|
| 1374 |
|
---|
| 1375 | /** @defgroup FMC_LL_SDRAM SDRAM
|
---|
| 1376 | * @{
|
---|
| 1377 | */
|
---|
| 1378 | /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
|
---|
| 1379 | * @{
|
---|
| 1380 | */
|
---|
| 1381 | HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
|
---|
| 1382 | HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
|
---|
| 1383 | HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
|
---|
| 1384 | /**
|
---|
| 1385 | * @}
|
---|
| 1386 | */
|
---|
| 1387 |
|
---|
| 1388 | /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
|
---|
| 1389 | * @{
|
---|
| 1390 | */
|
---|
| 1391 | HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
|
---|
| 1392 | HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
|
---|
| 1393 | HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
|
---|
| 1394 | HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
|
---|
| 1395 | HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
|
---|
| 1396 | uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
|
---|
| 1397 | /**
|
---|
| 1398 | * @}
|
---|
| 1399 | */
|
---|
| 1400 | /**
|
---|
| 1401 | * @}
|
---|
| 1402 | */
|
---|
| 1403 |
|
---|
| 1404 | /**
|
---|
| 1405 | * @}
|
---|
| 1406 | */
|
---|
| 1407 |
|
---|
| 1408 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
|
---|
| 1409 | /**
|
---|
| 1410 | * @}
|
---|
| 1411 | */
|
---|
| 1412 |
|
---|
| 1413 | /**
|
---|
| 1414 | * @}
|
---|
| 1415 | */
|
---|
| 1416 | #ifdef __cplusplus
|
---|
| 1417 | }
|
---|
| 1418 | #endif
|
---|
| 1419 |
|
---|
| 1420 | #endif /* __STM32F4xx_LL_FMC_H */
|
---|
| 1421 |
|
---|
| 1422 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
---|