[303] | 1 | /**
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| 2 | ******************************************************************************
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| 3 | * @file stm32f4xx_hal_tim.h
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| 4 | * @author MCD Application Team
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| 5 | * @version V1.4.1
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| 6 | * @date 09-October-2015
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| 7 | * @brief Header file of TIM HAL module.
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| 8 | ******************************************************************************
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| 9 | * @attention
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| 10 | *
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| 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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| 12 | *
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| 13 | * Redistribution and use in source and binary forms, with or without modification,
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| 14 | * are permitted provided that the following conditions are met:
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| 15 | * 1. Redistributions of source code must retain the above copyright notice,
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| 16 | * this list of conditions and the following disclaimer.
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| 17 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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| 18 | * this list of conditions and the following disclaimer in the documentation
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| 19 | * and/or other materials provided with the distribution.
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| 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
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| 21 | * may be used to endorse or promote products derived from this software
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| 22 | * without specific prior written permission.
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| 23 | *
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| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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| 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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| 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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| 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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| 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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| 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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| 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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| 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 34 | *
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| 35 | ******************************************************************************
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| 36 | */
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| 37 |
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| 38 | /* Define to prevent recursive inclusion -------------------------------------*/
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| 39 | #ifndef __STM32F4xx_HAL_TIM_H
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| 40 | #define __STM32F4xx_HAL_TIM_H
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| 41 |
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| 42 | #ifdef __cplusplus
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| 43 | extern "C" {
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| 44 | #endif
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| 45 |
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| 46 | /* Includes ------------------------------------------------------------------*/
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| 47 | #include "stm32f4xx_hal_def.h"
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| 48 |
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| 49 | /** @addtogroup STM32F4xx_HAL_Driver
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| 50 | * @{
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| 51 | */
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| 52 |
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| 53 | /** @addtogroup TIM
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| 54 | * @{
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| 55 | */
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| 56 |
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| 57 | /* Exported types ------------------------------------------------------------*/
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| 58 | /** @defgroup TIM_Exported_Types TIM Exported Types
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| 59 | * @{
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| 60 | */
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| 61 |
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| 62 | /**
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| 63 | * @brief TIM Time base Configuration Structure definition
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| 64 | */
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| 65 | typedef struct
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| 66 | {
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| 67 | uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
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| 68 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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| 69 |
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| 70 | uint32_t CounterMode; /*!< Specifies the counter mode.
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| 71 | This parameter can be a value of @ref TIM_Counter_Mode */
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| 72 |
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| 73 | uint32_t Period; /*!< Specifies the period value to be loaded into the active
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| 74 | Auto-Reload Register at the next update event.
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| 75 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
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| 76 |
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| 77 | uint32_t ClockDivision; /*!< Specifies the clock division.
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| 78 | This parameter can be a value of @ref TIM_ClockDivision */
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| 79 |
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| 80 | uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
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| 81 | reaches zero, an update event is generated and counting restarts
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| 82 | from the RCR value (N).
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| 83 | This means in PWM mode that (N+1) corresponds to:
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| 84 | - the number of PWM periods in edge-aligned mode
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| 85 | - the number of half PWM period in center-aligned mode
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| 86 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
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| 87 | @note This parameter is valid only for TIM1 and TIM8. */
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| 88 | } TIM_Base_InitTypeDef;
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| 89 |
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| 90 | /**
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| 91 | * @brief TIM Output Compare Configuration Structure definition
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| 92 | */
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| 93 |
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| 94 | typedef struct
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| 95 | {
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| 96 | uint32_t OCMode; /*!< Specifies the TIM mode.
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| 97 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
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| 98 |
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| 99 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
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| 100 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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| 101 |
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| 102 | uint32_t OCPolarity; /*!< Specifies the output polarity.
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| 103 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */
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| 104 |
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| 105 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
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| 106 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
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| 107 | @note This parameter is valid only for TIM1 and TIM8. */
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| 108 |
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| 109 | uint32_t OCFastMode; /*!< Specifies the Fast mode state.
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| 110 | This parameter can be a value of @ref TIM_Output_Fast_State
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| 111 | @note This parameter is valid only in PWM1 and PWM2 mode. */
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| 112 |
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| 113 |
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| 114 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
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| 115 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State
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| 116 | @note This parameter is valid only for TIM1 and TIM8. */
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| 117 |
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| 118 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
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| 119 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
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| 120 | @note This parameter is valid only for TIM1 and TIM8. */
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| 121 | } TIM_OC_InitTypeDef;
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| 122 |
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| 123 | /**
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| 124 | * @brief TIM One Pulse Mode Configuration Structure definition
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| 125 | */
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| 126 | typedef struct
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| 127 | {
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| 128 | uint32_t OCMode; /*!< Specifies the TIM mode.
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| 129 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
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| 130 |
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| 131 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
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| 132 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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| 133 |
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| 134 | uint32_t OCPolarity; /*!< Specifies the output polarity.
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| 135 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */
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| 136 |
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| 137 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
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| 138 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
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| 139 | @note This parameter is valid only for TIM1 and TIM8. */
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| 140 |
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| 141 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
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| 142 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State
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| 143 | @note This parameter is valid only for TIM1 and TIM8. */
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| 144 |
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| 145 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
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| 146 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
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| 147 | @note This parameter is valid only for TIM1 and TIM8. */
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| 148 |
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| 149 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
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| 150 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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| 151 |
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| 152 | uint32_t ICSelection; /*!< Specifies the input.
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| 153 | This parameter can be a value of @ref TIM_Input_Capture_Selection */
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| 154 |
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| 155 | uint32_t ICFilter; /*!< Specifies the input capture filter.
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| 156 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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| 157 | } TIM_OnePulse_InitTypeDef;
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| 158 |
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| 159 |
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| 160 | /**
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| 161 | * @brief TIM Input Capture Configuration Structure definition
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| 162 | */
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| 163 |
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| 164 | typedef struct
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| 165 | {
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| 166 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
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| 167 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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| 168 |
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| 169 | uint32_t ICSelection; /*!< Specifies the input.
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| 170 | This parameter can be a value of @ref TIM_Input_Capture_Selection */
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| 171 |
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| 172 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
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| 173 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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| 174 |
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| 175 | uint32_t ICFilter; /*!< Specifies the input capture filter.
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| 176 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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| 177 | } TIM_IC_InitTypeDef;
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| 178 |
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| 179 | /**
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| 180 | * @brief TIM Encoder Configuration Structure definition
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| 181 | */
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| 182 |
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| 183 | typedef struct
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| 184 | {
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| 185 | uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
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| 186 | This parameter can be a value of @ref TIM_Encoder_Mode */
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| 187 |
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| 188 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
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| 189 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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| 190 |
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| 191 | uint32_t IC1Selection; /*!< Specifies the input.
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| 192 | This parameter can be a value of @ref TIM_Input_Capture_Selection */
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| 193 |
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| 194 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
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| 195 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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| 196 |
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| 197 | uint32_t IC1Filter; /*!< Specifies the input capture filter.
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| 198 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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| 199 |
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| 200 | uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
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| 201 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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| 202 |
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| 203 | uint32_t IC2Selection; /*!< Specifies the input.
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| 204 | This parameter can be a value of @ref TIM_Input_Capture_Selection */
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| 205 |
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| 206 | uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
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| 207 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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| 208 |
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| 209 | uint32_t IC2Filter; /*!< Specifies the input capture filter.
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| 210 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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| 211 | } TIM_Encoder_InitTypeDef;
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| 212 |
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| 213 | /**
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| 214 | * @brief Clock Configuration Handle Structure definition
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| 215 | */
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| 216 | typedef struct
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| 217 | {
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| 218 | uint32_t ClockSource; /*!< TIM clock sources.
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| 219 | This parameter can be a value of @ref TIM_Clock_Source */
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| 220 | uint32_t ClockPolarity; /*!< TIM clock polarity.
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| 221 | This parameter can be a value of @ref TIM_Clock_Polarity */
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| 222 | uint32_t ClockPrescaler; /*!< TIM clock prescaler.
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| 223 | This parameter can be a value of @ref TIM_Clock_Prescaler */
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| 224 | uint32_t ClockFilter; /*!< TIM clock filter.
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| 225 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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| 226 | }TIM_ClockConfigTypeDef;
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| 227 |
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| 228 | /**
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| 229 | * @brief Clear Input Configuration Handle Structure definition
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| 230 | */
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| 231 | typedef struct
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| 232 | {
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| 233 | uint32_t ClearInputState; /*!< TIM clear Input state.
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| 234 | This parameter can be ENABLE or DISABLE */
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| 235 | uint32_t ClearInputSource; /*!< TIM clear Input sources.
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| 236 | This parameter can be a value of @ref TIM_ClearInput_Source */
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| 237 | uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
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| 238 | This parameter can be a value of @ref TIM_ClearInput_Polarity */
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| 239 | uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
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| 240 | This parameter can be a value of @ref TIM_ClearInput_Prescaler */
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| 241 | uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
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| 242 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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| 243 | }TIM_ClearInputConfigTypeDef;
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| 244 |
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| 245 | /**
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| 246 | * @brief TIM Slave configuration Structure definition
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| 247 | */
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| 248 | typedef struct {
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| 249 | uint32_t SlaveMode; /*!< Slave mode selection
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| 250 | This parameter can be a value of @ref TIM_Slave_Mode */
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| 251 | uint32_t InputTrigger; /*!< Input Trigger source
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| 252 | This parameter can be a value of @ref TIM_Trigger_Selection */
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| 253 | uint32_t TriggerPolarity; /*!< Input Trigger polarity
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| 254 | This parameter can be a value of @ref TIM_Trigger_Polarity */
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| 255 | uint32_t TriggerPrescaler; /*!< Input trigger prescaler
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| 256 | This parameter can be a value of @ref TIM_Trigger_Prescaler */
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| 257 | uint32_t TriggerFilter; /*!< Input trigger filter
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| 258 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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| 259 |
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| 260 | }TIM_SlaveConfigTypeDef;
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| 261 |
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| 262 | /**
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| 263 | * @brief HAL State structures definition
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| 264 | */
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| 265 | typedef enum
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| 266 | {
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| 267 | HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
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| 268 | HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
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| 269 | HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
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| 270 | HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
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| 271 | HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
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| 272 | }HAL_TIM_StateTypeDef;
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| 273 |
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| 274 | /**
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| 275 | * @brief HAL Active channel structures definition
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| 276 | */
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| 277 | typedef enum
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| 278 | {
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| 279 | HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
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| 280 | HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
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| 281 | HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
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| 282 | HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
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| 283 | HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
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| 284 | }HAL_TIM_ActiveChannel;
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| 285 |
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| 286 | /**
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| 287 | * @brief TIM Time Base Handle Structure definition
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| 288 | */
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| 289 | typedef struct
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| 290 | {
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| 291 | TIM_TypeDef *Instance; /*!< Register base address */
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| 292 | TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
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| 293 | HAL_TIM_ActiveChannel Channel; /*!< Active channel */
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| 294 | DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
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| 295 | This array is accessed by a @ref DMA_Handle_index */
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| 296 | HAL_LockTypeDef Lock; /*!< Locking object */
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| 297 | __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
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| 298 | }TIM_HandleTypeDef;
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| 299 | /**
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| 300 | * @}
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| 301 | */
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| 302 |
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| 303 | /* Exported constants --------------------------------------------------------*/
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| 304 | /** @defgroup TIM_Exported_Constants TIM Exported Constants
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| 305 | * @{
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| 306 | */
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| 307 |
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| 308 | /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
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| 309 | * @{
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| 310 | */
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| 311 | #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
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| 312 | #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
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| 313 | #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
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| 314 | /**
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| 315 | * @}
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| 316 | */
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| 317 |
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| 318 | /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
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| 319 | * @{
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| 320 | */
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| 321 | #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
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| 322 | #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
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| 323 | /**
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| 324 | * @}
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| 325 | */
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| 326 |
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| 327 | /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
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| 328 | * @{
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| 329 | */
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| 330 | #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
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| 331 | #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
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| 332 | #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
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| 333 | #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
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| 334 | /**
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| 335 | * @}
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| 336 | */
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| 337 |
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| 338 | /** @defgroup TIM_Counter_Mode TIM Counter Mode
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| 339 | * @{
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| 340 | */
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| 341 | #define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
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| 342 | #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
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| 343 | #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
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| 344 | #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
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| 345 | #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
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| 346 | /**
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| 347 | * @}
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| 348 | */
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| 349 |
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| 350 | /** @defgroup TIM_ClockDivision TIM Clock Division
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| 351 | * @{
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| 352 | */
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| 353 | #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
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| 354 | #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
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| 355 | #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
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| 356 | /**
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| 357 | * @}
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| 358 | */
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| 359 |
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| 360 | /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
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| 361 | * @{
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| 362 | */
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| 363 | #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
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| 364 | #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
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| 365 | #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
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| 366 | #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
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| 367 | #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
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| 368 | #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
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| 369 | #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
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| 370 | #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
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| 371 |
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| 372 | /**
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| 373 | * @}
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| 374 | */
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| 375 |
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| 376 | /** @defgroup TIM_Output_Fast_State TIM Output Fast State
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| 377 | * @{
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| 378 | */
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| 379 | #define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
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| 380 | #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
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| 381 | /**
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| 382 | * @}
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| 383 | */
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| 384 |
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| 385 | /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
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| 386 | * @{
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| 387 | */
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| 388 | #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
|
---|
| 389 | #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
|
---|
| 390 | /**
|
---|
| 391 | * @}
|
---|
| 392 | */
|
---|
| 393 |
|
---|
| 394 | /** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
|
---|
| 395 | * @{
|
---|
| 396 | */
|
---|
| 397 | #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
|
---|
| 398 | #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
|
---|
| 399 | /**
|
---|
| 400 | * @}
|
---|
| 401 | */
|
---|
| 402 |
|
---|
| 403 | /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
|
---|
| 404 | * @{
|
---|
| 405 | */
|
---|
| 406 | #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
|
---|
| 407 | #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
|
---|
| 408 | /**
|
---|
| 409 | * @}
|
---|
| 410 | */
|
---|
| 411 |
|
---|
| 412 | /** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
|
---|
| 413 | * @{
|
---|
| 414 | */
|
---|
| 415 | #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
|
---|
| 416 | #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
|
---|
| 417 | /**
|
---|
| 418 | * @}
|
---|
| 419 | */
|
---|
| 420 |
|
---|
| 421 | /** @defgroup TIM_Channel TIM Channel
|
---|
| 422 | * @{
|
---|
| 423 | */
|
---|
| 424 | #define TIM_CHANNEL_1 ((uint32_t)0x0000)
|
---|
| 425 | #define TIM_CHANNEL_2 ((uint32_t)0x0004)
|
---|
| 426 | #define TIM_CHANNEL_3 ((uint32_t)0x0008)
|
---|
| 427 | #define TIM_CHANNEL_4 ((uint32_t)0x000C)
|
---|
| 428 | #define TIM_CHANNEL_ALL ((uint32_t)0x0018)
|
---|
| 429 |
|
---|
| 430 | /**
|
---|
| 431 | * @}
|
---|
| 432 | */
|
---|
| 433 |
|
---|
| 434 | /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
|
---|
| 435 | * @{
|
---|
| 436 | */
|
---|
| 437 | #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
|
---|
| 438 | #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
|
---|
| 439 | #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
|
---|
| 440 | /**
|
---|
| 441 | * @}
|
---|
| 442 | */
|
---|
| 443 |
|
---|
| 444 | /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
|
---|
| 445 | * @{
|
---|
| 446 | */
|
---|
| 447 | #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
|
---|
| 448 | connected to IC1, IC2, IC3 or IC4, respectively */
|
---|
| 449 | #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
|
---|
| 450 | connected to IC2, IC1, IC4 or IC3, respectively */
|
---|
| 451 | #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
|
---|
| 452 |
|
---|
| 453 | /**
|
---|
| 454 | * @}
|
---|
| 455 | */
|
---|
| 456 |
|
---|
| 457 | /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
|
---|
| 458 | * @{
|
---|
| 459 | */
|
---|
| 460 | #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
|
---|
| 461 | #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
|
---|
| 462 | #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
|
---|
| 463 | #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
|
---|
| 464 | /**
|
---|
| 465 | * @}
|
---|
| 466 | */
|
---|
| 467 |
|
---|
| 468 | /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
|
---|
| 469 | * @{
|
---|
| 470 | */
|
---|
| 471 | #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
|
---|
| 472 | #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
|
---|
| 473 | /**
|
---|
| 474 | * @}
|
---|
| 475 | */
|
---|
| 476 |
|
---|
| 477 | /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
|
---|
| 478 | * @{
|
---|
| 479 | */
|
---|
| 480 | #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
|
---|
| 481 | #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
|
---|
| 482 | #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
|
---|
| 483 |
|
---|
| 484 | /**
|
---|
| 485 | * @}
|
---|
| 486 | */
|
---|
| 487 |
|
---|
| 488 | /** @defgroup TIM_Interrupt_definition TIM Interrupt definition
|
---|
| 489 | * @{
|
---|
| 490 | */
|
---|
| 491 | #define TIM_IT_UPDATE (TIM_DIER_UIE)
|
---|
| 492 | #define TIM_IT_CC1 (TIM_DIER_CC1IE)
|
---|
| 493 | #define TIM_IT_CC2 (TIM_DIER_CC2IE)
|
---|
| 494 | #define TIM_IT_CC3 (TIM_DIER_CC3IE)
|
---|
| 495 | #define TIM_IT_CC4 (TIM_DIER_CC4IE)
|
---|
| 496 | #define TIM_IT_COM (TIM_DIER_COMIE)
|
---|
| 497 | #define TIM_IT_TRIGGER (TIM_DIER_TIE)
|
---|
| 498 | #define TIM_IT_BREAK (TIM_DIER_BIE)
|
---|
| 499 | /**
|
---|
| 500 | * @}
|
---|
| 501 | */
|
---|
| 502 |
|
---|
| 503 | /** @defgroup TIM_Commutation_Source TIM Commutation Source
|
---|
| 504 | * @{
|
---|
| 505 | */
|
---|
| 506 | #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
|
---|
| 507 | #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
|
---|
| 508 | /**
|
---|
| 509 | * @}
|
---|
| 510 | */
|
---|
| 511 |
|
---|
| 512 | /** @defgroup TIM_DMA_sources TIM DMA sources
|
---|
| 513 | * @{
|
---|
| 514 | */
|
---|
| 515 | #define TIM_DMA_UPDATE (TIM_DIER_UDE)
|
---|
| 516 | #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
|
---|
| 517 | #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
|
---|
| 518 | #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
|
---|
| 519 | #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
|
---|
| 520 | #define TIM_DMA_COM (TIM_DIER_COMDE)
|
---|
| 521 | #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
|
---|
| 522 | /**
|
---|
| 523 | * @}
|
---|
| 524 | */
|
---|
| 525 |
|
---|
| 526 | /** @defgroup TIM_Event_Source TIM Event Source
|
---|
| 527 | * @{
|
---|
| 528 | */
|
---|
| 529 | #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
|
---|
| 530 | #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
|
---|
| 531 | #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
|
---|
| 532 | #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
|
---|
| 533 | #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
|
---|
| 534 | #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
|
---|
| 535 | #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
|
---|
| 536 | #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
|
---|
| 537 |
|
---|
| 538 | /**
|
---|
| 539 | * @}
|
---|
| 540 | */
|
---|
| 541 |
|
---|
| 542 | /** @defgroup TIM_Flag_definition TIM Flag definition
|
---|
| 543 | * @{
|
---|
| 544 | */
|
---|
| 545 | #define TIM_FLAG_UPDATE (TIM_SR_UIF)
|
---|
| 546 | #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
|
---|
| 547 | #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
|
---|
| 548 | #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
|
---|
| 549 | #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
|
---|
| 550 | #define TIM_FLAG_COM (TIM_SR_COMIF)
|
---|
| 551 | #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
|
---|
| 552 | #define TIM_FLAG_BREAK (TIM_SR_BIF)
|
---|
| 553 | #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
|
---|
| 554 | #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
|
---|
| 555 | #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
|
---|
| 556 | #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
|
---|
| 557 | /**
|
---|
| 558 | * @}
|
---|
| 559 | */
|
---|
| 560 |
|
---|
| 561 | /** @defgroup TIM_Clock_Source TIM Clock Source
|
---|
| 562 | * @{
|
---|
| 563 | */
|
---|
| 564 | #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
|
---|
| 565 | #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
|
---|
| 566 | #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
|
---|
| 567 | #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
|
---|
| 568 | #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
|
---|
| 569 | #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
|
---|
| 570 | #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
|
---|
| 571 | #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
|
---|
| 572 | #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
|
---|
| 573 | #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
|
---|
| 574 | /**
|
---|
| 575 | * @}
|
---|
| 576 | */
|
---|
| 577 |
|
---|
| 578 | /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
|
---|
| 579 | * @{
|
---|
| 580 | */
|
---|
| 581 | #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
|
---|
| 582 | #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
|
---|
| 583 | #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
|
---|
| 584 | #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
|
---|
| 585 | #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
|
---|
| 586 | /**
|
---|
| 587 | * @}
|
---|
| 588 | */
|
---|
| 589 |
|
---|
| 590 | /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
|
---|
| 591 | * @{
|
---|
| 592 | */
|
---|
| 593 | #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
|
---|
| 594 | #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
|
---|
| 595 | #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
|
---|
| 596 | #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
|
---|
| 597 | /**
|
---|
| 598 | * @}
|
---|
| 599 | */
|
---|
| 600 |
|
---|
| 601 | /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
|
---|
| 602 | * @{
|
---|
| 603 | */
|
---|
| 604 | #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
|
---|
| 605 | #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
|
---|
| 606 | /**
|
---|
| 607 | * @}
|
---|
| 608 | */
|
---|
| 609 |
|
---|
| 610 | /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
|
---|
| 611 | * @{
|
---|
| 612 | */
|
---|
| 613 | #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
|
---|
| 614 | #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
|
---|
| 615 | /**
|
---|
| 616 | * @}
|
---|
| 617 | */
|
---|
| 618 |
|
---|
| 619 | /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
|
---|
| 620 | * @{
|
---|
| 621 | */
|
---|
| 622 | #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
|
---|
| 623 | #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
|
---|
| 624 | #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
|
---|
| 625 | #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
|
---|
| 626 | /**
|
---|
| 627 | * @}
|
---|
| 628 | */
|
---|
| 629 |
|
---|
| 630 | /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
|
---|
| 631 | * @{
|
---|
| 632 | */
|
---|
| 633 | #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
|
---|
| 634 | #define TIM_OSSR_DISABLE ((uint32_t)0x0000)
|
---|
| 635 | /**
|
---|
| 636 | * @}
|
---|
| 637 | */
|
---|
| 638 |
|
---|
| 639 | /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
|
---|
| 640 | * @{
|
---|
| 641 | */
|
---|
| 642 | #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
|
---|
| 643 | #define TIM_OSSI_DISABLE ((uint32_t)0x0000)
|
---|
| 644 | /**
|
---|
| 645 | * @}
|
---|
| 646 | */
|
---|
| 647 |
|
---|
| 648 | /** @defgroup TIM_Lock_level TIM Lock level
|
---|
| 649 | * @{
|
---|
| 650 | */
|
---|
| 651 | #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
|
---|
| 652 | #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
|
---|
| 653 | #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
|
---|
| 654 | #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
|
---|
| 655 | /**
|
---|
| 656 | * @}
|
---|
| 657 | */
|
---|
| 658 | /** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
|
---|
| 659 | * @{
|
---|
| 660 | */
|
---|
| 661 | #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
|
---|
| 662 | #define TIM_BREAK_DISABLE ((uint32_t)0x0000)
|
---|
| 663 | /**
|
---|
| 664 | * @}
|
---|
| 665 | */
|
---|
| 666 |
|
---|
| 667 | /** @defgroup TIM_Break_Polarity TIM Break Polarity
|
---|
| 668 | * @{
|
---|
| 669 | */
|
---|
| 670 | #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
|
---|
| 671 | #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
|
---|
| 672 | /**
|
---|
| 673 | * @}
|
---|
| 674 | */
|
---|
| 675 |
|
---|
| 676 | /** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
|
---|
| 677 | * @{
|
---|
| 678 | */
|
---|
| 679 | #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
|
---|
| 680 | #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
|
---|
| 681 | /**
|
---|
| 682 | * @}
|
---|
| 683 | */
|
---|
| 684 |
|
---|
| 685 | /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
|
---|
| 686 | * @{
|
---|
| 687 | */
|
---|
| 688 | #define TIM_TRGO_RESET ((uint32_t)0x0000)
|
---|
| 689 | #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
|
---|
| 690 | #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
|
---|
| 691 | #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
|
---|
| 692 | #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
|
---|
| 693 | #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
|
---|
| 694 | #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
|
---|
| 695 | #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
|
---|
| 696 | /**
|
---|
| 697 | * @}
|
---|
| 698 | */
|
---|
| 699 |
|
---|
| 700 | /** @defgroup TIM_Slave_Mode TIM Slave Mode
|
---|
| 701 | * @{
|
---|
| 702 | */
|
---|
| 703 | #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
|
---|
| 704 | #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
|
---|
| 705 | #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
|
---|
| 706 | #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
|
---|
| 707 | #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
|
---|
| 708 | /**
|
---|
| 709 | * @}
|
---|
| 710 | */
|
---|
| 711 |
|
---|
| 712 | /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
|
---|
| 713 | * @{
|
---|
| 714 | */
|
---|
| 715 | #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
|
---|
| 716 | #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
|
---|
| 717 | /**
|
---|
| 718 | * @}
|
---|
| 719 | */
|
---|
| 720 |
|
---|
| 721 | /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
|
---|
| 722 | * @{
|
---|
| 723 | */
|
---|
| 724 | #define TIM_TS_ITR0 ((uint32_t)0x0000)
|
---|
| 725 | #define TIM_TS_ITR1 ((uint32_t)0x0010)
|
---|
| 726 | #define TIM_TS_ITR2 ((uint32_t)0x0020)
|
---|
| 727 | #define TIM_TS_ITR3 ((uint32_t)0x0030)
|
---|
| 728 | #define TIM_TS_TI1F_ED ((uint32_t)0x0040)
|
---|
| 729 | #define TIM_TS_TI1FP1 ((uint32_t)0x0050)
|
---|
| 730 | #define TIM_TS_TI2FP2 ((uint32_t)0x0060)
|
---|
| 731 | #define TIM_TS_ETRF ((uint32_t)0x0070)
|
---|
| 732 | #define TIM_TS_NONE ((uint32_t)0xFFFF)
|
---|
| 733 | /**
|
---|
| 734 | * @}
|
---|
| 735 | */
|
---|
| 736 |
|
---|
| 737 | /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
|
---|
| 738 | * @{
|
---|
| 739 | */
|
---|
| 740 | #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
|
---|
| 741 | #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
|
---|
| 742 | #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
|
---|
| 743 | #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
|
---|
| 744 | #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
|
---|
| 745 | /**
|
---|
| 746 | * @}
|
---|
| 747 | */
|
---|
| 748 |
|
---|
| 749 | /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
|
---|
| 750 | * @{
|
---|
| 751 | */
|
---|
| 752 | #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
|
---|
| 753 | #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
|
---|
| 754 | #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
|
---|
| 755 | #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
|
---|
| 756 | /**
|
---|
| 757 | * @}
|
---|
| 758 | */
|
---|
| 759 |
|
---|
| 760 |
|
---|
| 761 | /** @defgroup TIM_TI1_Selection TIM TI1 Selection
|
---|
| 762 | * @{
|
---|
| 763 | */
|
---|
| 764 | #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
|
---|
| 765 | #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
|
---|
| 766 | /**
|
---|
| 767 | * @}
|
---|
| 768 | */
|
---|
| 769 |
|
---|
| 770 | /** @defgroup TIM_DMA_Base_address TIM DMA Base address
|
---|
| 771 | * @{
|
---|
| 772 | */
|
---|
| 773 | #define TIM_DMABASE_CR1 (0x00000000)
|
---|
| 774 | #define TIM_DMABASE_CR2 (0x00000001)
|
---|
| 775 | #define TIM_DMABASE_SMCR (0x00000002)
|
---|
| 776 | #define TIM_DMABASE_DIER (0x00000003)
|
---|
| 777 | #define TIM_DMABASE_SR (0x00000004)
|
---|
| 778 | #define TIM_DMABASE_EGR (0x00000005)
|
---|
| 779 | #define TIM_DMABASE_CCMR1 (0x00000006)
|
---|
| 780 | #define TIM_DMABASE_CCMR2 (0x00000007)
|
---|
| 781 | #define TIM_DMABASE_CCER (0x00000008)
|
---|
| 782 | #define TIM_DMABASE_CNT (0x00000009)
|
---|
| 783 | #define TIM_DMABASE_PSC (0x0000000A)
|
---|
| 784 | #define TIM_DMABASE_ARR (0x0000000B)
|
---|
| 785 | #define TIM_DMABASE_RCR (0x0000000C)
|
---|
| 786 | #define TIM_DMABASE_CCR1 (0x0000000D)
|
---|
| 787 | #define TIM_DMABASE_CCR2 (0x0000000E)
|
---|
| 788 | #define TIM_DMABASE_CCR3 (0x0000000F)
|
---|
| 789 | #define TIM_DMABASE_CCR4 (0x00000010)
|
---|
| 790 | #define TIM_DMABASE_BDTR (0x00000011)
|
---|
| 791 | #define TIM_DMABASE_DCR (0x00000012)
|
---|
| 792 | #define TIM_DMABASE_OR (0x00000013)
|
---|
| 793 | /**
|
---|
| 794 | * @}
|
---|
| 795 | */
|
---|
| 796 |
|
---|
| 797 | /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
|
---|
| 798 | * @{
|
---|
| 799 | */
|
---|
| 800 | #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
|
---|
| 801 | #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
|
---|
| 802 | #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
|
---|
| 803 | #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
|
---|
| 804 | #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
|
---|
| 805 | #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
|
---|
| 806 | #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
|
---|
| 807 | #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
|
---|
| 808 | #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
|
---|
| 809 | #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
|
---|
| 810 | #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
|
---|
| 811 | #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
|
---|
| 812 | #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
|
---|
| 813 | #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
|
---|
| 814 | #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
|
---|
| 815 | #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
|
---|
| 816 | #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
|
---|
| 817 | #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
|
---|
| 818 | /**
|
---|
| 819 | * @}
|
---|
| 820 | */
|
---|
| 821 |
|
---|
| 822 | /** @defgroup DMA_Handle_index DMA Handle index
|
---|
| 823 | * @{
|
---|
| 824 | */
|
---|
| 825 | #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
|
---|
| 826 | #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
|
---|
| 827 | #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
|
---|
| 828 | #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
|
---|
| 829 | #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
|
---|
| 830 | #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
|
---|
| 831 | #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
|
---|
| 832 | /**
|
---|
| 833 | * @}
|
---|
| 834 | */
|
---|
| 835 |
|
---|
| 836 | /** @defgroup Channel_CC_State Channel CC State
|
---|
| 837 | * @{
|
---|
| 838 | */
|
---|
| 839 | #define TIM_CCx_ENABLE ((uint32_t)0x0001)
|
---|
| 840 | #define TIM_CCx_DISABLE ((uint32_t)0x0000)
|
---|
| 841 | #define TIM_CCxN_ENABLE ((uint32_t)0x0004)
|
---|
| 842 | #define TIM_CCxN_DISABLE ((uint32_t)0x0000)
|
---|
| 843 | /**
|
---|
| 844 | * @}
|
---|
| 845 | */
|
---|
| 846 |
|
---|
| 847 | /**
|
---|
| 848 | * @}
|
---|
| 849 | */
|
---|
| 850 |
|
---|
| 851 | /* Exported macro ------------------------------------------------------------*/
|
---|
| 852 | /** @defgroup TIM_Exported_Macros TIM Exported Macros
|
---|
| 853 | * @{
|
---|
| 854 | */
|
---|
| 855 | /** @brief Reset TIM handle state
|
---|
| 856 | * @param __HANDLE__: TIM handle
|
---|
| 857 | * @retval None
|
---|
| 858 | */
|
---|
| 859 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
|
---|
| 860 |
|
---|
| 861 | /**
|
---|
| 862 | * @brief Enable the TIM peripheral.
|
---|
| 863 | * @param __HANDLE__: TIM handle
|
---|
| 864 | * @retval None
|
---|
| 865 | */
|
---|
| 866 | #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
|
---|
| 867 |
|
---|
| 868 | /**
|
---|
| 869 | * @brief Enable the TIM main Output.
|
---|
| 870 | * @param __HANDLE__: TIM handle
|
---|
| 871 | * @retval None
|
---|
| 872 | */
|
---|
| 873 | #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
|
---|
| 874 |
|
---|
| 875 |
|
---|
| 876 | /**
|
---|
| 877 | * @brief Disable the TIM peripheral.
|
---|
| 878 | * @param __HANDLE__: TIM handle
|
---|
| 879 | * @retval None
|
---|
| 880 | */
|
---|
| 881 | #define __HAL_TIM_DISABLE(__HANDLE__) \
|
---|
| 882 | do { \
|
---|
| 883 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
|
---|
| 884 | { \
|
---|
| 885 | if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
|
---|
| 886 | { \
|
---|
| 887 | (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
|
---|
| 888 | } \
|
---|
| 889 | } \
|
---|
| 890 | } while(0)
|
---|
| 891 |
|
---|
| 892 | /* The Main Output of a timer instance is disabled only if all the CCx and CCxN
|
---|
| 893 | channels have been disabled */
|
---|
| 894 | /**
|
---|
| 895 | * @brief Disable the TIM main Output.
|
---|
| 896 | * @param __HANDLE__: TIM handle
|
---|
| 897 | * @retval None
|
---|
| 898 | */
|
---|
| 899 | #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
|
---|
| 900 | do { \
|
---|
| 901 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
|
---|
| 902 | { \
|
---|
| 903 | if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
|
---|
| 904 | { \
|
---|
| 905 | (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
|
---|
| 906 | } \
|
---|
| 907 | } \
|
---|
| 908 | } while(0)
|
---|
| 909 |
|
---|
| 910 | #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
|
---|
| 911 | #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
|
---|
| 912 | #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
|
---|
| 913 | #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
|
---|
| 914 | #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
|
---|
| 915 | #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
|
---|
| 916 |
|
---|
| 917 | #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
---|
| 918 | #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
|
---|
| 919 |
|
---|
| 920 | #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
|
---|
| 921 | #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
|
---|
| 922 |
|
---|
| 923 | #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
|
---|
| 924 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
|
---|
| 925 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
|
---|
| 926 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
|
---|
| 927 | ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
|
---|
| 928 |
|
---|
| 929 | #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
|
---|
| 930 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
|
---|
| 931 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
|
---|
| 932 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
|
---|
| 933 | ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
|
---|
| 934 |
|
---|
| 935 | #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
|
---|
| 936 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
|
---|
| 937 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
|
---|
| 938 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
|
---|
| 939 | ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
|
---|
| 940 |
|
---|
| 941 | #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
|
---|
| 942 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
|
---|
| 943 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
|
---|
| 944 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
|
---|
| 945 | ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
|
---|
| 946 |
|
---|
| 947 | /**
|
---|
| 948 | * @brief Sets the TIM Capture Compare Register value on runtime without
|
---|
| 949 | * calling another time ConfigChannel function.
|
---|
| 950 | * @param __HANDLE__: TIM handle.
|
---|
| 951 | * @param __CHANNEL__ : TIM Channels to be configured.
|
---|
| 952 | * This parameter can be one of the following values:
|
---|
| 953 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
| 954 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
| 955 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
| 956 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
| 957 | * @param __COMPARE__: specifies the Capture Compare register new value.
|
---|
| 958 | * @retval None
|
---|
| 959 | */
|
---|
| 960 | #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
|
---|
| 961 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
|
---|
| 962 |
|
---|
| 963 | /**
|
---|
| 964 | * @brief Gets the TIM Capture Compare Register value on runtime
|
---|
| 965 | * @param __HANDLE__: TIM handle.
|
---|
| 966 | * @param __CHANNEL__ : TIM Channel associated with the capture compare register
|
---|
| 967 | * This parameter can be one of the following values:
|
---|
| 968 | * @arg TIM_CHANNEL_1: get capture/compare 1 register value
|
---|
| 969 | * @arg TIM_CHANNEL_2: get capture/compare 2 register value
|
---|
| 970 | * @arg TIM_CHANNEL_3: get capture/compare 3 register value
|
---|
| 971 | * @arg TIM_CHANNEL_4: get capture/compare 4 register value
|
---|
| 972 | * @retval None
|
---|
| 973 | */
|
---|
| 974 | #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
|
---|
| 975 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
|
---|
| 976 |
|
---|
| 977 | /**
|
---|
| 978 | * @brief Sets the TIM Counter Register value on runtime.
|
---|
| 979 | * @param __HANDLE__: TIM handle.
|
---|
| 980 | * @param __COUNTER__: specifies the Counter register new value.
|
---|
| 981 | * @retval None
|
---|
| 982 | */
|
---|
| 983 | #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
|
---|
| 984 |
|
---|
| 985 | /**
|
---|
| 986 | * @brief Gets the TIM Counter Register value on runtime.
|
---|
| 987 | * @param __HANDLE__: TIM handle.
|
---|
| 988 | * @retval None
|
---|
| 989 | */
|
---|
| 990 | #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
|
---|
| 991 |
|
---|
| 992 | /**
|
---|
| 993 | * @brief Sets the TIM Autoreload Register value on runtime without calling
|
---|
| 994 | * another time any Init function.
|
---|
| 995 | * @param __HANDLE__: TIM handle.
|
---|
| 996 | * @param __AUTORELOAD__: specifies the Counter register new value.
|
---|
| 997 | * @retval None
|
---|
| 998 | */
|
---|
| 999 | #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
|
---|
| 1000 | do{ \
|
---|
| 1001 | (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
|
---|
| 1002 | (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
|
---|
| 1003 | } while(0)
|
---|
| 1004 | /**
|
---|
| 1005 | * @brief Gets the TIM Autoreload Register value on runtime
|
---|
| 1006 | * @param __HANDLE__: TIM handle.
|
---|
| 1007 | * @retval None
|
---|
| 1008 | */
|
---|
| 1009 | #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
|
---|
| 1010 |
|
---|
| 1011 | /**
|
---|
| 1012 | * @brief Sets the TIM Clock Division value on runtime without calling
|
---|
| 1013 | * another time any Init function.
|
---|
| 1014 | * @param __HANDLE__: TIM handle.
|
---|
| 1015 | * @param __CKD__: specifies the clock division value.
|
---|
| 1016 | * This parameter can be one of the following value:
|
---|
| 1017 | * @arg TIM_CLOCKDIVISION_DIV1
|
---|
| 1018 | * @arg TIM_CLOCKDIVISION_DIV2
|
---|
| 1019 | * @arg TIM_CLOCKDIVISION_DIV4
|
---|
| 1020 | * @retval None
|
---|
| 1021 | */
|
---|
| 1022 | #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
|
---|
| 1023 | do{ \
|
---|
| 1024 | (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
|
---|
| 1025 | (__HANDLE__)->Instance->CR1 |= (__CKD__); \
|
---|
| 1026 | (__HANDLE__)->Init.ClockDivision = (__CKD__); \
|
---|
| 1027 | } while(0)
|
---|
| 1028 | /**
|
---|
| 1029 | * @brief Gets the TIM Clock Division value on runtime
|
---|
| 1030 | * @param __HANDLE__: TIM handle.
|
---|
| 1031 | * @retval None
|
---|
| 1032 | */
|
---|
| 1033 | #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
|
---|
| 1034 |
|
---|
| 1035 | /**
|
---|
| 1036 | * @brief Sets the TIM Input Capture prescaler on runtime without calling
|
---|
| 1037 | * another time HAL_TIM_IC_ConfigChannel() function.
|
---|
| 1038 | * @param __HANDLE__: TIM handle.
|
---|
| 1039 | * @param __CHANNEL__ : TIM Channels to be configured.
|
---|
| 1040 | * This parameter can be one of the following values:
|
---|
| 1041 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
| 1042 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
| 1043 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
| 1044 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
| 1045 | * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
|
---|
| 1046 | * This parameter can be one of the following values:
|
---|
| 1047 | * @arg TIM_ICPSC_DIV1: no prescaler
|
---|
| 1048 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
|
---|
| 1049 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
|
---|
| 1050 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
|
---|
| 1051 | * @retval None
|
---|
| 1052 | */
|
---|
| 1053 | #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
|
---|
| 1054 | do{ \
|
---|
| 1055 | TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
|
---|
| 1056 | TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
|
---|
| 1057 | } while(0)
|
---|
| 1058 |
|
---|
| 1059 | /**
|
---|
| 1060 | * @brief Gets the TIM Input Capture prescaler on runtime
|
---|
| 1061 | * @param __HANDLE__: TIM handle.
|
---|
| 1062 | * @param __CHANNEL__ : TIM Channels to be configured.
|
---|
| 1063 | * This parameter can be one of the following values:
|
---|
| 1064 | * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
|
---|
| 1065 | * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
|
---|
| 1066 | * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
|
---|
| 1067 | * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
|
---|
| 1068 | * @retval None
|
---|
| 1069 | */
|
---|
| 1070 | #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
|
---|
| 1071 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
|
---|
| 1072 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
|
---|
| 1073 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
|
---|
| 1074 | (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
|
---|
| 1075 |
|
---|
| 1076 | /**
|
---|
| 1077 | * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
|
---|
| 1078 | * @param __HANDLE__: TIM handle.
|
---|
| 1079 | * @note When the USR bit of the TIMx_CR1 register is set, only counter
|
---|
| 1080 | * overflow/underflow generates an update interrupt or DMA request (if
|
---|
| 1081 | * enabled)
|
---|
| 1082 | * @retval None
|
---|
| 1083 | */
|
---|
| 1084 | #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
|
---|
| 1085 | ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
|
---|
| 1086 |
|
---|
| 1087 | /**
|
---|
| 1088 | * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
|
---|
| 1089 | * @param __HANDLE__: TIM handle.
|
---|
| 1090 | * @note When the USR bit of the TIMx_CR1 register is reset, any of the
|
---|
| 1091 | * following events generate an update interrupt or DMA request (if
|
---|
| 1092 | * enabled):
|
---|
| 1093 | * Counter overflow/underflow
|
---|
| 1094 | * Setting the UG bit
|
---|
| 1095 | * Update generation through the slave mode controller
|
---|
| 1096 | * @retval None
|
---|
| 1097 | */
|
---|
| 1098 | #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
|
---|
| 1099 | ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
|
---|
| 1100 |
|
---|
| 1101 | /**
|
---|
| 1102 | * @brief Sets the TIM Capture x input polarity on runtime.
|
---|
| 1103 | * @param __HANDLE__: TIM handle.
|
---|
| 1104 | * @param __CHANNEL__: TIM Channels to be configured.
|
---|
| 1105 | * This parameter can be one of the following values:
|
---|
| 1106 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
---|
| 1107 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
---|
| 1108 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
---|
| 1109 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
---|
| 1110 | * @param __POLARITY__: Polarity for TIx source
|
---|
| 1111 | * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
|
---|
| 1112 | * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
|
---|
| 1113 | * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
|
---|
| 1114 | * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
|
---|
| 1115 | * @retval None
|
---|
| 1116 | */
|
---|
| 1117 | #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
|
---|
| 1118 | do{ \
|
---|
| 1119 | TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
|
---|
| 1120 | TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
|
---|
| 1121 | }while(0)
|
---|
| 1122 | /**
|
---|
| 1123 | * @}
|
---|
| 1124 | */
|
---|
| 1125 |
|
---|
| 1126 | /* Include TIM HAL Extension module */
|
---|
| 1127 | #include "stm32f4xx_hal_tim_ex.h"
|
---|
| 1128 |
|
---|
| 1129 | /* Exported functions --------------------------------------------------------*/
|
---|
| 1130 | /** @addtogroup TIM_Exported_Functions
|
---|
| 1131 | * @{
|
---|
| 1132 | */
|
---|
| 1133 |
|
---|
| 1134 | /** @addtogroup TIM_Exported_Functions_Group1
|
---|
| 1135 | * @{
|
---|
| 1136 | */
|
---|
| 1137 |
|
---|
| 1138 | /* Time Base functions ********************************************************/
|
---|
| 1139 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
|
---|
| 1140 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
|
---|
| 1141 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
|
---|
| 1142 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
|
---|
| 1143 | /* Blocking mode: Polling */
|
---|
| 1144 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
|
---|
| 1145 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
|
---|
| 1146 | /* Non-Blocking mode: Interrupt */
|
---|
| 1147 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
|
---|
| 1148 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
|
---|
| 1149 | /* Non-Blocking mode: DMA */
|
---|
| 1150 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
|
---|
| 1151 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
|
---|
| 1152 | /**
|
---|
| 1153 | * @}
|
---|
| 1154 | */
|
---|
| 1155 |
|
---|
| 1156 | /** @addtogroup TIM_Exported_Functions_Group2
|
---|
| 1157 | * @{
|
---|
| 1158 | */
|
---|
| 1159 | /* Timer Output Compare functions **********************************************/
|
---|
| 1160 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
|
---|
| 1161 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
|
---|
| 1162 | void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
|
---|
| 1163 | void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
|
---|
| 1164 | /* Blocking mode: Polling */
|
---|
| 1165 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1166 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1167 | /* Non-Blocking mode: Interrupt */
|
---|
| 1168 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1169 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1170 | /* Non-Blocking mode: DMA */
|
---|
| 1171 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
---|
| 1172 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1173 |
|
---|
| 1174 | /**
|
---|
| 1175 | * @}
|
---|
| 1176 | */
|
---|
| 1177 |
|
---|
| 1178 | /** @addtogroup TIM_Exported_Functions_Group3
|
---|
| 1179 | * @{
|
---|
| 1180 | */
|
---|
| 1181 | /* Timer PWM functions *********************************************************/
|
---|
| 1182 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
|
---|
| 1183 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
|
---|
| 1184 | void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
|
---|
| 1185 | void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
|
---|
| 1186 | /* Blocking mode: Polling */
|
---|
| 1187 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1188 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1189 | /* Non-Blocking mode: Interrupt */
|
---|
| 1190 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1191 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1192 | /* Non-Blocking mode: DMA */
|
---|
| 1193 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
---|
| 1194 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1195 |
|
---|
| 1196 | /**
|
---|
| 1197 | * @}
|
---|
| 1198 | */
|
---|
| 1199 |
|
---|
| 1200 | /** @addtogroup TIM_Exported_Functions_Group4
|
---|
| 1201 | * @{
|
---|
| 1202 | */
|
---|
| 1203 | /* Timer Input Capture functions ***********************************************/
|
---|
| 1204 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
|
---|
| 1205 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
|
---|
| 1206 | void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
|
---|
| 1207 | void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
|
---|
| 1208 | /* Blocking mode: Polling */
|
---|
| 1209 | HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1210 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1211 | /* Non-Blocking mode: Interrupt */
|
---|
| 1212 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1213 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1214 | /* Non-Blocking mode: DMA */
|
---|
| 1215 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
---|
| 1216 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1217 |
|
---|
| 1218 | /**
|
---|
| 1219 | * @}
|
---|
| 1220 | */
|
---|
| 1221 |
|
---|
| 1222 | /** @addtogroup TIM_Exported_Functions_Group5
|
---|
| 1223 | * @{
|
---|
| 1224 | */
|
---|
| 1225 | /* Timer One Pulse functions ***************************************************/
|
---|
| 1226 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
|
---|
| 1227 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
|
---|
| 1228 | void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
|
---|
| 1229 | void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
|
---|
| 1230 | /* Blocking mode: Polling */
|
---|
| 1231 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
---|
| 1232 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
---|
| 1233 |
|
---|
| 1234 | /* Non-Blocking mode: Interrupt */
|
---|
| 1235 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
---|
| 1236 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
---|
| 1237 |
|
---|
| 1238 | /**
|
---|
| 1239 | * @}
|
---|
| 1240 | */
|
---|
| 1241 |
|
---|
| 1242 | /** @addtogroup TIM_Exported_Functions_Group6
|
---|
| 1243 | * @{
|
---|
| 1244 | */
|
---|
| 1245 | /* Timer Encoder functions *****************************************************/
|
---|
| 1246 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
|
---|
| 1247 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
|
---|
| 1248 | void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
|
---|
| 1249 | void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
|
---|
| 1250 | /* Blocking mode: Polling */
|
---|
| 1251 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1252 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1253 | /* Non-Blocking mode: Interrupt */
|
---|
| 1254 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1255 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1256 | /* Non-Blocking mode: DMA */
|
---|
| 1257 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
|
---|
| 1258 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1259 |
|
---|
| 1260 | /**
|
---|
| 1261 | * @}
|
---|
| 1262 | */
|
---|
| 1263 |
|
---|
| 1264 | /** @addtogroup TIM_Exported_Functions_Group7
|
---|
| 1265 | * @{
|
---|
| 1266 | */
|
---|
| 1267 | /* Interrupt Handler functions **********************************************/
|
---|
| 1268 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
|
---|
| 1269 |
|
---|
| 1270 | /**
|
---|
| 1271 | * @}
|
---|
| 1272 | */
|
---|
| 1273 |
|
---|
| 1274 | /** @addtogroup TIM_Exported_Functions_Group8
|
---|
| 1275 | * @{
|
---|
| 1276 | */
|
---|
| 1277 | /* Control functions *********************************************************/
|
---|
| 1278 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
|
---|
| 1279 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
|
---|
| 1280 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
|
---|
| 1281 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
|
---|
| 1282 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
|
---|
| 1283 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
|
---|
| 1284 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
|
---|
| 1285 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
|
---|
| 1286 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
|
---|
| 1287 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
|
---|
| 1288 | uint32_t *BurstBuffer, uint32_t BurstLength);
|
---|
| 1289 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
|
---|
| 1290 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
|
---|
| 1291 | uint32_t *BurstBuffer, uint32_t BurstLength);
|
---|
| 1292 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
|
---|
| 1293 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
|
---|
| 1294 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
|
---|
| 1295 |
|
---|
| 1296 | /**
|
---|
| 1297 | * @}
|
---|
| 1298 | */
|
---|
| 1299 |
|
---|
| 1300 | /** @addtogroup TIM_Exported_Functions_Group9
|
---|
| 1301 | * @{
|
---|
| 1302 | */
|
---|
| 1303 | /* Callback in non blocking modes (Interrupt and DMA) *************************/
|
---|
| 1304 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
|
---|
| 1305 | void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
|
---|
| 1306 | void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
|
---|
| 1307 | void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
|
---|
| 1308 | void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
|
---|
| 1309 | void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
|
---|
| 1310 |
|
---|
| 1311 | /**
|
---|
| 1312 | * @}
|
---|
| 1313 | */
|
---|
| 1314 |
|
---|
| 1315 | /** @addtogroup TIM_Exported_Functions_Group10
|
---|
| 1316 | * @{
|
---|
| 1317 | */
|
---|
| 1318 | /* Peripheral State functions **************************************************/
|
---|
| 1319 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
|
---|
| 1320 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
|
---|
| 1321 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
|
---|
| 1322 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
|
---|
| 1323 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
|
---|
| 1324 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
|
---|
| 1325 |
|
---|
| 1326 | /**
|
---|
| 1327 | * @}
|
---|
| 1328 | */
|
---|
| 1329 |
|
---|
| 1330 | /**
|
---|
| 1331 | * @}
|
---|
| 1332 | */
|
---|
| 1333 |
|
---|
| 1334 | /* Private macros ------------------------------------------------------------*/
|
---|
| 1335 | /** @defgroup TIM_Private_Macros TIM Private Macros
|
---|
| 1336 | * @{
|
---|
| 1337 | */
|
---|
| 1338 |
|
---|
| 1339 | /** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
|
---|
| 1340 | * @{
|
---|
| 1341 | */
|
---|
| 1342 | #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
|
---|
| 1343 | ((MODE) == TIM_COUNTERMODE_DOWN) || \
|
---|
| 1344 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
|
---|
| 1345 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
|
---|
| 1346 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
|
---|
| 1347 |
|
---|
| 1348 | #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
|
---|
| 1349 | ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
|
---|
| 1350 | ((DIV) == TIM_CLOCKDIVISION_DIV4))
|
---|
| 1351 |
|
---|
| 1352 | #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
|
---|
| 1353 | ((MODE) == TIM_OCMODE_PWM2))
|
---|
| 1354 |
|
---|
| 1355 | #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
|
---|
| 1356 | ((MODE) == TIM_OCMODE_ACTIVE) || \
|
---|
| 1357 | ((MODE) == TIM_OCMODE_INACTIVE) || \
|
---|
| 1358 | ((MODE) == TIM_OCMODE_TOGGLE) || \
|
---|
| 1359 | ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
|
---|
| 1360 | ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
|
---|
| 1361 |
|
---|
| 1362 | #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
|
---|
| 1363 | ((STATE) == TIM_OCFAST_ENABLE))
|
---|
| 1364 |
|
---|
| 1365 | #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
|
---|
| 1366 | ((POLARITY) == TIM_OCPOLARITY_LOW))
|
---|
| 1367 |
|
---|
| 1368 | #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
|
---|
| 1369 | ((POLARITY) == TIM_OCNPOLARITY_LOW))
|
---|
| 1370 |
|
---|
| 1371 | #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
|
---|
| 1372 | ((STATE) == TIM_OCIDLESTATE_RESET))
|
---|
| 1373 |
|
---|
| 1374 | #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
|
---|
| 1375 | ((STATE) == TIM_OCNIDLESTATE_RESET))
|
---|
| 1376 |
|
---|
| 1377 | #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
|
---|
| 1378 | ((CHANNEL) == TIM_CHANNEL_2) || \
|
---|
| 1379 | ((CHANNEL) == TIM_CHANNEL_3) || \
|
---|
| 1380 | ((CHANNEL) == TIM_CHANNEL_4) || \
|
---|
| 1381 | ((CHANNEL) == TIM_CHANNEL_ALL))
|
---|
| 1382 |
|
---|
| 1383 | #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
|
---|
| 1384 | ((CHANNEL) == TIM_CHANNEL_2))
|
---|
| 1385 |
|
---|
| 1386 | #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
|
---|
| 1387 | ((CHANNEL) == TIM_CHANNEL_2) || \
|
---|
| 1388 | ((CHANNEL) == TIM_CHANNEL_3))
|
---|
| 1389 |
|
---|
| 1390 | #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
|
---|
| 1391 | ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
|
---|
| 1392 | ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
|
---|
| 1393 |
|
---|
| 1394 | #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
|
---|
| 1395 | ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
|
---|
| 1396 | ((SELECTION) == TIM_ICSELECTION_TRC))
|
---|
| 1397 |
|
---|
| 1398 | #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
|
---|
| 1399 | ((PRESCALER) == TIM_ICPSC_DIV2) || \
|
---|
| 1400 | ((PRESCALER) == TIM_ICPSC_DIV4) || \
|
---|
| 1401 | ((PRESCALER) == TIM_ICPSC_DIV8))
|
---|
| 1402 |
|
---|
| 1403 | #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
|
---|
| 1404 | ((MODE) == TIM_OPMODE_REPETITIVE))
|
---|
| 1405 |
|
---|
| 1406 | #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
|
---|
| 1407 |
|
---|
| 1408 | #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
|
---|
| 1409 | ((MODE) == TIM_ENCODERMODE_TI2) || \
|
---|
| 1410 | ((MODE) == TIM_ENCODERMODE_TI12))
|
---|
| 1411 |
|
---|
| 1412 | #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
|
---|
| 1413 |
|
---|
| 1414 | #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
|
---|
| 1415 | ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
|
---|
| 1416 | ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
|
---|
| 1417 | ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
|
---|
| 1418 | ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
|
---|
| 1419 | ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
|
---|
| 1420 | ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
|
---|
| 1421 | ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
|
---|
| 1422 | ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
|
---|
| 1423 | ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
|
---|
| 1424 |
|
---|
| 1425 | #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
|
---|
| 1426 | ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
|
---|
| 1427 | ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
|
---|
| 1428 | ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
|
---|
| 1429 | ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
|
---|
| 1430 |
|
---|
| 1431 | #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
|
---|
| 1432 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
|
---|
| 1433 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
|
---|
| 1434 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
|
---|
| 1435 |
|
---|
| 1436 | #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
|
---|
| 1437 |
|
---|
| 1438 | #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
|
---|
| 1439 | ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
|
---|
| 1440 |
|
---|
| 1441 | #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
|
---|
| 1442 | ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
|
---|
| 1443 |
|
---|
| 1444 | #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
|
---|
| 1445 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
|
---|
| 1446 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
|
---|
| 1447 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
|
---|
| 1448 |
|
---|
| 1449 | #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
|
---|
| 1450 |
|
---|
| 1451 | #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
|
---|
| 1452 | ((STATE) == TIM_OSSR_DISABLE))
|
---|
| 1453 |
|
---|
| 1454 | #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
|
---|
| 1455 | ((STATE) == TIM_OSSI_DISABLE))
|
---|
| 1456 |
|
---|
| 1457 | #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
|
---|
| 1458 | ((LEVEL) == TIM_LOCKLEVEL_1) || \
|
---|
| 1459 | ((LEVEL) == TIM_LOCKLEVEL_2) || \
|
---|
| 1460 | ((LEVEL) == TIM_LOCKLEVEL_3))
|
---|
| 1461 |
|
---|
| 1462 | #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
|
---|
| 1463 | ((STATE) == TIM_BREAK_DISABLE))
|
---|
| 1464 |
|
---|
| 1465 | #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
|
---|
| 1466 | ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
|
---|
| 1467 |
|
---|
| 1468 | #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
|
---|
| 1469 | ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
|
---|
| 1470 |
|
---|
| 1471 | #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
|
---|
| 1472 | ((SOURCE) == TIM_TRGO_ENABLE) || \
|
---|
| 1473 | ((SOURCE) == TIM_TRGO_UPDATE) || \
|
---|
| 1474 | ((SOURCE) == TIM_TRGO_OC1) || \
|
---|
| 1475 | ((SOURCE) == TIM_TRGO_OC1REF) || \
|
---|
| 1476 | ((SOURCE) == TIM_TRGO_OC2REF) || \
|
---|
| 1477 | ((SOURCE) == TIM_TRGO_OC3REF) || \
|
---|
| 1478 | ((SOURCE) == TIM_TRGO_OC4REF))
|
---|
| 1479 |
|
---|
| 1480 | #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
|
---|
| 1481 | ((MODE) == TIM_SLAVEMODE_GATED) || \
|
---|
| 1482 | ((MODE) == TIM_SLAVEMODE_RESET) || \
|
---|
| 1483 | ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
|
---|
| 1484 | ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
|
---|
| 1485 |
|
---|
| 1486 | #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
|
---|
| 1487 | ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
|
---|
| 1488 |
|
---|
| 1489 | #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
|
---|
| 1490 | ((SELECTION) == TIM_TS_ITR1) || \
|
---|
| 1491 | ((SELECTION) == TIM_TS_ITR2) || \
|
---|
| 1492 | ((SELECTION) == TIM_TS_ITR3) || \
|
---|
| 1493 | ((SELECTION) == TIM_TS_TI1F_ED) || \
|
---|
| 1494 | ((SELECTION) == TIM_TS_TI1FP1) || \
|
---|
| 1495 | ((SELECTION) == TIM_TS_TI2FP2) || \
|
---|
| 1496 | ((SELECTION) == TIM_TS_ETRF))
|
---|
| 1497 |
|
---|
| 1498 | #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
|
---|
| 1499 | ((SELECTION) == TIM_TS_ITR1) || \
|
---|
| 1500 | ((SELECTION) == TIM_TS_ITR2) || \
|
---|
| 1501 | ((SELECTION) == TIM_TS_ITR3) || \
|
---|
| 1502 | ((SELECTION) == TIM_TS_NONE))
|
---|
| 1503 | #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
|
---|
| 1504 | ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
|
---|
| 1505 | ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
|
---|
| 1506 | ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
|
---|
| 1507 | ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
|
---|
| 1508 |
|
---|
| 1509 | #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
|
---|
| 1510 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
|
---|
| 1511 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
|
---|
| 1512 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
|
---|
| 1513 |
|
---|
| 1514 | #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
|
---|
| 1515 |
|
---|
| 1516 | #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
|
---|
| 1517 | ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
|
---|
| 1518 |
|
---|
| 1519 | #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
|
---|
| 1520 | ((BASE) == TIM_DMABASE_CR2) || \
|
---|
| 1521 | ((BASE) == TIM_DMABASE_SMCR) || \
|
---|
| 1522 | ((BASE) == TIM_DMABASE_DIER) || \
|
---|
| 1523 | ((BASE) == TIM_DMABASE_SR) || \
|
---|
| 1524 | ((BASE) == TIM_DMABASE_EGR) || \
|
---|
| 1525 | ((BASE) == TIM_DMABASE_CCMR1) || \
|
---|
| 1526 | ((BASE) == TIM_DMABASE_CCMR2) || \
|
---|
| 1527 | ((BASE) == TIM_DMABASE_CCER) || \
|
---|
| 1528 | ((BASE) == TIM_DMABASE_CNT) || \
|
---|
| 1529 | ((BASE) == TIM_DMABASE_PSC) || \
|
---|
| 1530 | ((BASE) == TIM_DMABASE_ARR) || \
|
---|
| 1531 | ((BASE) == TIM_DMABASE_RCR) || \
|
---|
| 1532 | ((BASE) == TIM_DMABASE_CCR1) || \
|
---|
| 1533 | ((BASE) == TIM_DMABASE_CCR2) || \
|
---|
| 1534 | ((BASE) == TIM_DMABASE_CCR3) || \
|
---|
| 1535 | ((BASE) == TIM_DMABASE_CCR4) || \
|
---|
| 1536 | ((BASE) == TIM_DMABASE_BDTR) || \
|
---|
| 1537 | ((BASE) == TIM_DMABASE_DCR) || \
|
---|
| 1538 | ((BASE) == TIM_DMABASE_OR))
|
---|
| 1539 |
|
---|
| 1540 | #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
|
---|
| 1541 | ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
|
---|
| 1542 | ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
|
---|
| 1543 | ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
|
---|
| 1544 | ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
|
---|
| 1545 | ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
|
---|
| 1546 | ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
|
---|
| 1547 | ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
|
---|
| 1548 | ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
|
---|
| 1549 | ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
|
---|
| 1550 | ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
|
---|
| 1551 | ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
|
---|
| 1552 | ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
|
---|
| 1553 | ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
|
---|
| 1554 | ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
|
---|
| 1555 | ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
|
---|
| 1556 | ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
|
---|
| 1557 | ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
|
---|
| 1558 |
|
---|
| 1559 | #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
|
---|
| 1560 | /**
|
---|
| 1561 | * @}
|
---|
| 1562 | */
|
---|
| 1563 |
|
---|
| 1564 | /** @defgroup TIM_Mask_Definitions TIM Mask Definition
|
---|
| 1565 | * @{
|
---|
| 1566 | */
|
---|
| 1567 | /* The counter of a timer instance is disabled only if all the CCx and CCxN
|
---|
| 1568 | channels have been disabled */
|
---|
| 1569 | #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
|
---|
| 1570 | #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
|
---|
| 1571 | /**
|
---|
| 1572 | * @}
|
---|
| 1573 | */
|
---|
| 1574 |
|
---|
| 1575 | /**
|
---|
| 1576 | * @}
|
---|
| 1577 | */
|
---|
| 1578 |
|
---|
| 1579 | /* Private functions ---------------------------------------------------------*/
|
---|
| 1580 | /** @defgroup TIM_Private_Functions TIM Private Functions
|
---|
| 1581 | * @{
|
---|
| 1582 | */
|
---|
| 1583 | void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
|
---|
| 1584 | void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
|
---|
| 1585 | void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
|
---|
| 1586 | void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
|
---|
| 1587 | void TIM_DMAError(DMA_HandleTypeDef *hdma);
|
---|
| 1588 | void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
|
---|
| 1589 | void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
|
---|
| 1590 | /**
|
---|
| 1591 | * @}
|
---|
| 1592 | */
|
---|
| 1593 |
|
---|
| 1594 | /**
|
---|
| 1595 | * @}
|
---|
| 1596 | */
|
---|
| 1597 |
|
---|
| 1598 | /**
|
---|
| 1599 | * @}
|
---|
| 1600 | */
|
---|
| 1601 |
|
---|
| 1602 | #ifdef __cplusplus
|
---|
| 1603 | }
|
---|
| 1604 | #endif
|
---|
| 1605 |
|
---|
| 1606 | #endif /* __STM32F4xx_HAL_TIM_H */
|
---|
| 1607 |
|
---|
| 1608 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
---|