[303] | 1 | /**
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| 2 | ******************************************************************************
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| 3 | * @file stm32f4xx_hal_rcc.h
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| 4 | * @author MCD Application Team
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| 5 | * @version V1.4.1
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| 6 | * @date 09-October-2015
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| 7 | * @brief Header file of RCC HAL module.
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| 8 | ******************************************************************************
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| 9 | * @attention
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| 10 | *
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| 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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| 12 | *
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| 13 | * Redistribution and use in source and binary forms, with or without modification,
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| 14 | * are permitted provided that the following conditions are met:
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| 15 | * 1. Redistributions of source code must retain the above copyright notice,
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| 16 | * this list of conditions and the following disclaimer.
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| 17 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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| 18 | * this list of conditions and the following disclaimer in the documentation
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| 19 | * and/or other materials provided with the distribution.
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| 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
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| 21 | * may be used to endorse or promote products derived from this software
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| 22 | * without specific prior written permission.
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| 23 | *
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| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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| 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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| 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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| 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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| 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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| 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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| 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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| 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 34 | *
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| 35 | ******************************************************************************
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| 36 | */
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| 37 |
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| 38 | /* Define to prevent recursive inclusion -------------------------------------*/
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| 39 | #ifndef __STM32F4xx_HAL_RCC_H
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| 40 | #define __STM32F4xx_HAL_RCC_H
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| 41 |
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| 42 | #ifdef __cplusplus
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| 43 | extern "C" {
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| 44 | #endif
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| 45 |
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| 46 | /* Includes ------------------------------------------------------------------*/
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| 47 | #include "stm32f4xx_hal_def.h"
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| 48 |
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| 49 | /* Include RCC HAL Extended module */
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| 50 | /* (include on top of file since RCC structures are defined in extended file) */
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| 51 | #include "stm32f4xx_hal_rcc_ex.h"
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| 52 |
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| 53 | /** @addtogroup STM32F4xx_HAL_Driver
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| 54 | * @{
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| 55 | */
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| 56 |
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| 57 | /** @addtogroup RCC
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| 58 | * @{
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| 59 | */
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| 60 |
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| 61 | /* Exported types ------------------------------------------------------------*/
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| 62 | /** @defgroup RCC_Exported_Types RCC Exported Types
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| 63 | * @{
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| 64 | */
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| 65 |
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| 66 | /**
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| 67 | * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
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| 68 | */
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| 69 | typedef struct
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| 70 | {
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| 71 | uint32_t OscillatorType; /*!< The oscillators to be configured.
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| 72 | This parameter can be a value of @ref RCC_Oscillator_Type */
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| 73 |
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| 74 | uint32_t HSEState; /*!< The new state of the HSE.
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| 75 | This parameter can be a value of @ref RCC_HSE_Config */
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| 76 |
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| 77 | uint32_t LSEState; /*!< The new state of the LSE.
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| 78 | This parameter can be a value of @ref RCC_LSE_Config */
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| 79 |
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| 80 | uint32_t HSIState; /*!< The new state of the HSI.
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| 81 | This parameter can be a value of @ref RCC_HSI_Config */
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| 82 |
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| 83 | uint32_t HSICalibrationValue; /*!< The calibration trimming value.
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| 84 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
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| 85 |
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| 86 | uint32_t LSIState; /*!< The new state of the LSI.
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| 87 | This parameter can be a value of @ref RCC_LSI_Config */
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| 88 |
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| 89 | RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
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| 90 |
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| 91 | }RCC_OscInitTypeDef;
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| 92 |
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| 93 | /**
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| 94 | * @brief RCC System, AHB and APB busses clock configuration structure definition
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| 95 | */
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| 96 | typedef struct
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| 97 | {
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| 98 | uint32_t ClockType; /*!< The clock to be configured.
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| 99 | This parameter can be a value of @ref RCC_System_Clock_Type */
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| 100 |
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| 101 | uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
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| 102 | This parameter can be a value of @ref RCC_System_Clock_Source */
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| 103 |
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| 104 | uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
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| 105 | This parameter can be a value of @ref RCC_AHB_Clock_Source */
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| 106 |
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| 107 | uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
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| 108 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
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| 109 |
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| 110 | uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
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| 111 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
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| 112 |
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| 113 | }RCC_ClkInitTypeDef;
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| 114 |
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| 115 | /**
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| 116 | * @}
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| 117 | */
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| 118 |
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| 119 | /* Exported constants --------------------------------------------------------*/
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| 120 | /** @defgroup RCC_Exported_Constants RCC Exported Constants
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| 121 | * @{
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| 122 | */
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| 123 |
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| 124 | /** @defgroup RCC_Oscillator_Type Oscillator Type
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| 125 | * @{
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| 126 | */
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| 127 | #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
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| 128 | #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
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| 129 | #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
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| 130 | #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
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| 131 | #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
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| 132 | /**
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| 133 | * @}
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| 134 | */
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| 135 |
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| 136 | /** @defgroup RCC_HSE_Config HSE Config
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| 137 | * @{
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| 138 | */
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| 139 | #define RCC_HSE_OFF ((uint8_t)0x00)
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| 140 | #define RCC_HSE_ON ((uint8_t)0x01)
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| 141 | #define RCC_HSE_BYPASS ((uint8_t)0x05)
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| 142 | /**
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| 143 | * @}
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| 144 | */
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| 145 |
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| 146 | /** @defgroup RCC_LSE_Config LSE Config
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| 147 | * @{
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| 148 | */
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| 149 | #define RCC_LSE_OFF ((uint8_t)0x00)
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| 150 | #define RCC_LSE_ON ((uint8_t)0x01)
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| 151 | #define RCC_LSE_BYPASS ((uint8_t)0x05)
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| 152 | /**
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| 153 | * @}
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| 154 | */
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| 155 |
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| 156 | /** @defgroup RCC_HSI_Config HSI Config
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| 157 | * @{
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| 158 | */
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| 159 | #define RCC_HSI_OFF ((uint8_t)0x00)
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| 160 | #define RCC_HSI_ON ((uint8_t)0x01)
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| 161 | /**
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| 162 | * @}
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| 163 | */
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| 164 |
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| 165 | /** @defgroup RCC_LSI_Config LSI Config
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| 166 | * @{
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| 167 | */
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| 168 | #define RCC_LSI_OFF ((uint8_t)0x00)
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| 169 | #define RCC_LSI_ON ((uint8_t)0x01)
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| 170 | /**
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| 171 | * @}
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| 172 | */
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| 173 |
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| 174 | /** @defgroup RCC_PLL_Config PLL Config
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| 175 | * @{
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| 176 | */
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| 177 | #define RCC_PLL_NONE ((uint8_t)0x00)
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| 178 | #define RCC_PLL_OFF ((uint8_t)0x01)
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| 179 | #define RCC_PLL_ON ((uint8_t)0x02)
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| 180 | /**
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| 181 | * @}
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| 182 | */
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| 183 |
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| 184 | /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
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| 185 | * @{
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| 186 | */
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| 187 | #define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
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| 188 | #define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
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| 189 | #define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
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| 190 | #define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
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| 191 | /**
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| 192 | * @}
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| 193 | */
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| 194 |
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| 195 | /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
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| 196 | * @{
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| 197 | */
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| 198 | #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
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| 199 | #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
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| 200 | /**
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| 201 | * @}
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| 202 | */
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| 203 |
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| 204 | /** @defgroup RCC_System_Clock_Type System Clock Type
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| 205 | * @{
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| 206 | */
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| 207 | #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
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| 208 | #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
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| 209 | #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
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| 210 | #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
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| 211 | /**
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| 212 | * @}
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| 213 | */
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| 214 |
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| 215 | /** @defgroup RCC_System_Clock_Source System Clock Source
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| 216 | * @{
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| 217 | */
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| 218 | #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
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| 219 | #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
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| 220 | #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
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| 221 | #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
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| 222 | /**
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| 223 | * @}
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| 224 | */
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| 225 |
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| 226 | /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
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| 227 | * @{
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| 228 | */
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| 229 | #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
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| 230 | #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
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| 231 | #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
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| 232 | #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1)) /*!< PLLR used as system clock */
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| 233 | /**
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| 234 | * @}
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| 235 | */
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| 236 |
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| 237 | /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
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| 238 | * @{
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| 239 | */
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| 240 | #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
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| 241 | #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
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| 242 | #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
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| 243 | #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
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| 244 | #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
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| 245 | #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
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| 246 | #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
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| 247 | #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
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| 248 | #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
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| 249 | /**
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| 250 | * @}
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| 251 | */
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| 252 |
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| 253 | /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
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| 254 | * @{
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| 255 | */
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| 256 | #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
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| 257 | #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
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| 258 | #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
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| 259 | #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
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| 260 | #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
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| 261 | /**
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| 262 | * @}
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| 263 | */
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| 264 |
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| 265 | /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
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| 266 | * @{
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| 267 | */
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| 268 | #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
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| 269 | #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
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| 270 | #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
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| 271 | #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
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| 272 | #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
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| 273 | #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
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| 274 | #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
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| 275 | #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
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| 276 | #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
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| 277 | #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
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| 278 | #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
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| 279 | #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
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| 280 | #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
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| 281 | #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
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| 282 | #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
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| 283 | #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
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| 284 | #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
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| 285 | #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
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| 286 | #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
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| 287 | #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
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| 288 | #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
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| 289 | #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
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| 290 | #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
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| 291 | #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
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| 292 | #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
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| 293 | #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
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| 294 | #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
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| 295 | #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
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| 296 | #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
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| 297 | #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
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| 298 | #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
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| 299 | #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
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| 300 | /**
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| 301 | * @}
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| 302 | */
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| 303 |
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| 304 | /** @defgroup RCC_MCO_Index MCO Index
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| 305 | * @{
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| 306 | */
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| 307 | #define RCC_MCO1 ((uint32_t)0x00000000)
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| 308 | #define RCC_MCO2 ((uint32_t)0x00000001)
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| 309 | /**
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| 310 | * @}
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| 311 | */
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| 312 |
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| 313 | /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
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| 314 | * @{
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| 315 | */
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| 316 | #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
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| 317 | #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
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| 318 | #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
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| 319 | #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
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| 320 | /**
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| 321 | * @}
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| 322 | */
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| 323 |
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| 324 | /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
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| 325 | * @{
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| 326 | */
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| 327 | #define RCC_MCODIV_1 ((uint32_t)0x00000000)
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| 328 | #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
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| 329 | #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
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| 330 | #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
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| 331 | #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
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| 332 | /**
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| 333 | * @}
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| 334 | */
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| 335 |
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| 336 | /** @defgroup RCC_Interrupt Interrupts
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| 337 | * @{
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| 338 | */
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| 339 | #define RCC_IT_LSIRDY ((uint8_t)0x01)
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| 340 | #define RCC_IT_LSERDY ((uint8_t)0x02)
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| 341 | #define RCC_IT_HSIRDY ((uint8_t)0x04)
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| 342 | #define RCC_IT_HSERDY ((uint8_t)0x08)
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| 343 | #define RCC_IT_PLLRDY ((uint8_t)0x10)
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| 344 | #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
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| 345 | #define RCC_IT_CSS ((uint8_t)0x80)
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| 346 | /**
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| 347 | * @}
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| 348 | */
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| 349 |
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| 350 | /** @defgroup RCC_Flag Flags
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| 351 | * Elements values convention: 0XXYYYYYb
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| 352 | * - YYYYY : Flag position in the register
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| 353 | * - 0XX : Register index
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| 354 | * - 01: CR register
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| 355 | * - 10: BDCR register
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| 356 | * - 11: CSR register
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| 357 | * @{
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| 358 | */
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| 359 | /* Flags in the CR register */
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| 360 | #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
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| 361 | #define RCC_FLAG_HSERDY ((uint8_t)0x31)
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| 362 | #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
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| 363 | #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
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| 364 |
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| 365 | /* Flags in the BDCR register */
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| 366 | #define RCC_FLAG_LSERDY ((uint8_t)0x41)
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| 367 |
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| 368 | /* Flags in the CSR register */
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| 369 | #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
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| 370 | #define RCC_FLAG_BORRST ((uint8_t)0x79)
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| 371 | #define RCC_FLAG_PINRST ((uint8_t)0x7A)
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| 372 | #define RCC_FLAG_PORRST ((uint8_t)0x7B)
|
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| 373 | #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
|
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| 374 | #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
|
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| 375 | #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
|
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| 376 | #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
|
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| 377 | /**
|
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| 378 | * @}
|
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| 379 | */
|
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| 380 |
|
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| 381 | /**
|
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| 382 | * @}
|
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| 383 | */
|
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| 384 |
|
---|
| 385 | /* Exported macro ------------------------------------------------------------*/
|
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| 386 | /** @defgroup RCC_Exported_Macros RCC Exported Macros
|
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| 387 | * @{
|
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| 388 | */
|
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| 389 |
|
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| 390 | /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
|
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| 391 | * @brief Enable or disable the AHB1 peripheral clock.
|
---|
| 392 | * @note After reset, the peripheral clock (used for registers read/write access)
|
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| 393 | * is disabled and the application software has to enable this clock before
|
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| 394 | * using it.
|
---|
| 395 | * @{
|
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| 396 | */
|
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| 397 | #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
|
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| 398 | __IO uint32_t tmpreg; \
|
---|
| 399 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
|
---|
| 400 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 401 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
|
---|
| 402 | UNUSED(tmpreg); \
|
---|
| 403 | } while(0)
|
---|
| 404 | #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
|
---|
| 405 | __IO uint32_t tmpreg; \
|
---|
| 406 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
|
---|
| 407 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 408 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
|
---|
| 409 | UNUSED(tmpreg); \
|
---|
| 410 | } while(0)
|
---|
| 411 | #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
|
---|
| 412 | __IO uint32_t tmpreg; \
|
---|
| 413 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
|
---|
| 414 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 415 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
|
---|
| 416 | UNUSED(tmpreg); \
|
---|
| 417 | } while(0)
|
---|
| 418 | #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
|
---|
| 419 | __IO uint32_t tmpreg; \
|
---|
| 420 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
|
---|
| 421 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 422 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
|
---|
| 423 | UNUSED(tmpreg); \
|
---|
| 424 | } while(0)
|
---|
| 425 | #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
|
---|
| 426 | __IO uint32_t tmpreg; \
|
---|
| 427 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
|
---|
| 428 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 429 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
|
---|
| 430 | UNUSED(tmpreg); \
|
---|
| 431 | } while(0)
|
---|
| 432 | #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
|
---|
| 433 | __IO uint32_t tmpreg; \
|
---|
| 434 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
|
---|
| 435 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 436 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
|
---|
| 437 | UNUSED(tmpreg); \
|
---|
| 438 | } while(0)
|
---|
| 439 |
|
---|
| 440 | #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
|
---|
| 441 | #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
|
---|
| 442 | #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
|
---|
| 443 | #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
|
---|
| 444 | #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
|
---|
| 445 | #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
|
---|
| 446 |
|
---|
| 447 | /**
|
---|
| 448 | * @}
|
---|
| 449 | */
|
---|
| 450 |
|
---|
| 451 | /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
|
---|
| 452 | * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
|
---|
| 453 | * @note After reset, the peripheral clock (used for registers read/write access)
|
---|
| 454 | * is disabled and the application software has to enable this clock before
|
---|
| 455 | * using it.
|
---|
| 456 | * @{
|
---|
| 457 | */
|
---|
| 458 | #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
|
---|
| 459 | __IO uint32_t tmpreg; \
|
---|
| 460 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
|
---|
| 461 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 462 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
|
---|
| 463 | UNUSED(tmpreg); \
|
---|
| 464 | } while(0)
|
---|
| 465 | #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
|
---|
| 466 | __IO uint32_t tmpreg; \
|
---|
| 467 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
|
---|
| 468 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 469 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
|
---|
| 470 | UNUSED(tmpreg); \
|
---|
| 471 | } while(0)
|
---|
| 472 | #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
|
---|
| 473 | __IO uint32_t tmpreg; \
|
---|
| 474 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
|
---|
| 475 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 476 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
|
---|
| 477 | UNUSED(tmpreg); \
|
---|
| 478 | } while(0)
|
---|
| 479 | #define __HAL_RCC_USART2_CLK_ENABLE() do { \
|
---|
| 480 | __IO uint32_t tmpreg; \
|
---|
| 481 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
|
---|
| 482 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 483 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
|
---|
| 484 | UNUSED(tmpreg); \
|
---|
| 485 | } while(0)
|
---|
| 486 | #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
|
---|
| 487 | __IO uint32_t tmpreg; \
|
---|
| 488 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
|
---|
| 489 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 490 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
|
---|
| 491 | UNUSED(tmpreg); \
|
---|
| 492 | } while(0)
|
---|
| 493 | #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
|
---|
| 494 | __IO uint32_t tmpreg; \
|
---|
| 495 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
|
---|
| 496 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 497 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
|
---|
| 498 | UNUSED(tmpreg); \
|
---|
| 499 | } while(0)
|
---|
| 500 | #define __HAL_RCC_PWR_CLK_ENABLE() do { \
|
---|
| 501 | __IO uint32_t tmpreg; \
|
---|
| 502 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
|
---|
| 503 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 504 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
|
---|
| 505 | UNUSED(tmpreg); \
|
---|
| 506 | } while(0)
|
---|
| 507 |
|
---|
| 508 | #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
|
---|
| 509 | #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
|
---|
| 510 | #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
|
---|
| 511 | #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
|
---|
| 512 | #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
|
---|
| 513 | #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
|
---|
| 514 | #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
|
---|
| 515 | /**
|
---|
| 516 | * @}
|
---|
| 517 | */
|
---|
| 518 |
|
---|
| 519 | /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
|
---|
| 520 | * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
|
---|
| 521 | * @note After reset, the peripheral clock (used for registers read/write access)
|
---|
| 522 | * is disabled and the application software has to enable this clock before
|
---|
| 523 | * using it.
|
---|
| 524 | * @{
|
---|
| 525 | */
|
---|
| 526 | #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
|
---|
| 527 | __IO uint32_t tmpreg; \
|
---|
| 528 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
|
---|
| 529 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 530 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
|
---|
| 531 | UNUSED(tmpreg); \
|
---|
| 532 | } while(0)
|
---|
| 533 | #define __HAL_RCC_USART1_CLK_ENABLE() do { \
|
---|
| 534 | __IO uint32_t tmpreg; \
|
---|
| 535 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
|
---|
| 536 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 537 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
|
---|
| 538 | UNUSED(tmpreg); \
|
---|
| 539 | } while(0)
|
---|
| 540 | #define __HAL_RCC_USART6_CLK_ENABLE() do { \
|
---|
| 541 | __IO uint32_t tmpreg; \
|
---|
| 542 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
|
---|
| 543 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 544 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
|
---|
| 545 | UNUSED(tmpreg); \
|
---|
| 546 | } while(0)
|
---|
| 547 | #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
|
---|
| 548 | __IO uint32_t tmpreg; \
|
---|
| 549 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
|
---|
| 550 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 551 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
|
---|
| 552 | UNUSED(tmpreg); \
|
---|
| 553 | } while(0)
|
---|
| 554 | #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
|
---|
| 555 | __IO uint32_t tmpreg; \
|
---|
| 556 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
|
---|
| 557 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 558 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
|
---|
| 559 | UNUSED(tmpreg); \
|
---|
| 560 | } while(0)
|
---|
| 561 | #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
|
---|
| 562 | __IO uint32_t tmpreg; \
|
---|
| 563 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
|
---|
| 564 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 565 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
|
---|
| 566 | UNUSED(tmpreg); \
|
---|
| 567 | } while(0)
|
---|
| 568 | #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
|
---|
| 569 | __IO uint32_t tmpreg; \
|
---|
| 570 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
|
---|
| 571 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 572 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
|
---|
| 573 | UNUSED(tmpreg); \
|
---|
| 574 | } while(0)
|
---|
| 575 | #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
|
---|
| 576 | __IO uint32_t tmpreg; \
|
---|
| 577 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
|
---|
| 578 | /* Delay after an RCC peripheral clock enabling */ \
|
---|
| 579 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
|
---|
| 580 | UNUSED(tmpreg); \
|
---|
| 581 | } while(0)
|
---|
| 582 |
|
---|
| 583 | #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
|
---|
| 584 | #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
|
---|
| 585 | #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
|
---|
| 586 | #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
|
---|
| 587 | #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
|
---|
| 588 | #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
|
---|
| 589 | #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
|
---|
| 590 | #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
|
---|
| 591 | /**
|
---|
| 592 | * @}
|
---|
| 593 | */
|
---|
| 594 |
|
---|
| 595 | /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
|
---|
| 596 | * @brief Force or release AHB1 peripheral reset.
|
---|
| 597 | * @{
|
---|
| 598 | */
|
---|
| 599 | #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
|
---|
| 600 | #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
|
---|
| 601 | #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
|
---|
| 602 | #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
|
---|
| 603 | #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
|
---|
| 604 | #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
|
---|
| 605 | #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
|
---|
| 606 |
|
---|
| 607 | #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
|
---|
| 608 | #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
|
---|
| 609 | #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
|
---|
| 610 | #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
|
---|
| 611 | #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
|
---|
| 612 | #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
|
---|
| 613 | #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
|
---|
| 614 | /**
|
---|
| 615 | * @}
|
---|
| 616 | */
|
---|
| 617 |
|
---|
| 618 | /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
|
---|
| 619 | * @brief Force or release APB1 peripheral reset.
|
---|
| 620 | * @{
|
---|
| 621 | */
|
---|
| 622 | #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
|
---|
| 623 | #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
|
---|
| 624 | #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
|
---|
| 625 | #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
|
---|
| 626 | #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
|
---|
| 627 | #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
|
---|
| 628 | #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
|
---|
| 629 | #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
|
---|
| 630 |
|
---|
| 631 | #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
|
---|
| 632 | #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
|
---|
| 633 | #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
|
---|
| 634 | #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
|
---|
| 635 | #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
|
---|
| 636 | #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
|
---|
| 637 | #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
|
---|
| 638 | #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
|
---|
| 639 | /**
|
---|
| 640 | * @}
|
---|
| 641 | */
|
---|
| 642 |
|
---|
| 643 | /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
|
---|
| 644 | * @brief Force or release APB2 peripheral reset.
|
---|
| 645 | * @{
|
---|
| 646 | */
|
---|
| 647 | #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
|
---|
| 648 | #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
|
---|
| 649 | #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
|
---|
| 650 | #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
|
---|
| 651 | #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
|
---|
| 652 | #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
|
---|
| 653 | #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
|
---|
| 654 | #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
|
---|
| 655 | #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
|
---|
| 656 |
|
---|
| 657 | #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
|
---|
| 658 | #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
|
---|
| 659 | #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
|
---|
| 660 | #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
|
---|
| 661 | #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
|
---|
| 662 | #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
|
---|
| 663 | #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
|
---|
| 664 | #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
|
---|
| 665 | #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
|
---|
| 666 | /**
|
---|
| 667 | * @}
|
---|
| 668 | */
|
---|
| 669 |
|
---|
| 670 | /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
|
---|
| 671 | * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
|
---|
| 672 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
---|
| 673 | * power consumption.
|
---|
| 674 | * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
|
---|
| 675 | * @note By default, all peripheral clocks are enabled during SLEEP mode.
|
---|
| 676 | * @{
|
---|
| 677 | */
|
---|
| 678 | #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
|
---|
| 679 | #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
|
---|
| 680 | #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
|
---|
| 681 | #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
|
---|
| 682 | #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
|
---|
| 683 | #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
|
---|
| 684 |
|
---|
| 685 | #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
|
---|
| 686 | #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
|
---|
| 687 | #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
|
---|
| 688 | #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
|
---|
| 689 | #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
|
---|
| 690 | #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
|
---|
| 691 | /**
|
---|
| 692 | * @}
|
---|
| 693 | */
|
---|
| 694 |
|
---|
| 695 | /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
|
---|
| 696 | * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
|
---|
| 697 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
---|
| 698 | * power consumption.
|
---|
| 699 | * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
|
---|
| 700 | * @note By default, all peripheral clocks are enabled during SLEEP mode.
|
---|
| 701 | * @{
|
---|
| 702 | */
|
---|
| 703 | #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
|
---|
| 704 | #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
|
---|
| 705 | #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
|
---|
| 706 | #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
|
---|
| 707 | #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
|
---|
| 708 | #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
|
---|
| 709 | #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
|
---|
| 710 |
|
---|
| 711 | #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
|
---|
| 712 | #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
|
---|
| 713 | #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
|
---|
| 714 | #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
|
---|
| 715 | #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
|
---|
| 716 | #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
|
---|
| 717 | #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
|
---|
| 718 | /**
|
---|
| 719 | * @}
|
---|
| 720 | */
|
---|
| 721 |
|
---|
| 722 | /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
|
---|
| 723 | * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
|
---|
| 724 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
---|
| 725 | * power consumption.
|
---|
| 726 | * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
|
---|
| 727 | * @note By default, all peripheral clocks are enabled during SLEEP mode.
|
---|
| 728 | * @{
|
---|
| 729 | */
|
---|
| 730 | #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
|
---|
| 731 | #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
|
---|
| 732 | #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
|
---|
| 733 | #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
|
---|
| 734 | #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
|
---|
| 735 | #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
|
---|
| 736 | #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
|
---|
| 737 | #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
|
---|
| 738 |
|
---|
| 739 | #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
|
---|
| 740 | #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
|
---|
| 741 | #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
|
---|
| 742 | #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
|
---|
| 743 | #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
|
---|
| 744 | #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
|
---|
| 745 | #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
|
---|
| 746 | #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
|
---|
| 747 | /**
|
---|
| 748 | * @}
|
---|
| 749 | */
|
---|
| 750 |
|
---|
| 751 | /** @defgroup RCC_HSI_Configuration HSI Configuration
|
---|
| 752 | * @{
|
---|
| 753 | */
|
---|
| 754 |
|
---|
| 755 | /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
|
---|
| 756 | * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
|
---|
| 757 | * It is used (enabled by hardware) as system clock source after startup
|
---|
| 758 | * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
|
---|
| 759 | * of the HSE used directly or indirectly as system clock (if the Clock
|
---|
| 760 | * Security System CSS is enabled).
|
---|
| 761 | * @note HSI can not be stopped if it is used as system clock source. In this case,
|
---|
| 762 | * you have to select another source of the system clock then stop the HSI.
|
---|
| 763 | * @note After enabling the HSI, the application software should wait on HSIRDY
|
---|
| 764 | * flag to be set indicating that HSI clock is stable and can be used as
|
---|
| 765 | * system clock source.
|
---|
| 766 | * This parameter can be: ENABLE or DISABLE.
|
---|
| 767 | * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
|
---|
| 768 | * clock cycles.
|
---|
| 769 | */
|
---|
| 770 | #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
|
---|
| 771 | #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
|
---|
| 772 |
|
---|
| 773 | /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
|
---|
| 774 | * @note The calibration is used to compensate for the variations in voltage
|
---|
| 775 | * and temperature that influence the frequency of the internal HSI RC.
|
---|
| 776 | * @param __HSICalibrationValue__: specifies the calibration trimming value.
|
---|
| 777 | * This parameter must be a number between 0 and 0x1F.
|
---|
| 778 | */
|
---|
| 779 | #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
|
---|
| 780 | RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
|
---|
| 781 | /**
|
---|
| 782 | * @}
|
---|
| 783 | */
|
---|
| 784 |
|
---|
| 785 | /** @defgroup RCC_LSI_Configuration LSI Configuration
|
---|
| 786 | * @{
|
---|
| 787 | */
|
---|
| 788 |
|
---|
| 789 | /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
|
---|
| 790 | * @note After enabling the LSI, the application software should wait on
|
---|
| 791 | * LSIRDY flag to be set indicating that LSI clock is stable and can
|
---|
| 792 | * be used to clock the IWDG and/or the RTC.
|
---|
| 793 | * @note LSI can not be disabled if the IWDG is running.
|
---|
| 794 | * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
|
---|
| 795 | * clock cycles.
|
---|
| 796 | */
|
---|
| 797 | #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
|
---|
| 798 | #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
|
---|
| 799 | /**
|
---|
| 800 | * @}
|
---|
| 801 | */
|
---|
| 802 |
|
---|
| 803 | /** @defgroup RCC_HSE_Configuration HSE Configuration
|
---|
| 804 | * @{
|
---|
| 805 | */
|
---|
| 806 |
|
---|
| 807 | /**
|
---|
| 808 | * @brief Macro to configure the External High Speed oscillator (HSE).
|
---|
| 809 | * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
|
---|
| 810 | * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
|
---|
| 811 | * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
|
---|
| 812 | * software should wait on HSERDY flag to be set indicating that HSE clock
|
---|
| 813 | * is stable and can be used to clock the PLL and/or system clock.
|
---|
| 814 | * @note HSE state can not be changed if it is used directly or through the
|
---|
| 815 | * PLL as system clock. In this case, you have to select another source
|
---|
| 816 | * of the system clock then change the HSE state (ex. disable it).
|
---|
| 817 | * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
|
---|
| 818 | * @note This function reset the CSSON bit, so if the clock security system(CSS)
|
---|
| 819 | * was previously enabled you have to enable it again after calling this
|
---|
| 820 | * function.
|
---|
| 821 | * @param __STATE__: specifies the new state of the HSE.
|
---|
| 822 | * This parameter can be one of the following values:
|
---|
| 823 | * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
|
---|
| 824 | * 6 HSE oscillator clock cycles.
|
---|
| 825 | * @arg RCC_HSE_ON: turn ON the HSE oscillator.
|
---|
| 826 | * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
|
---|
| 827 | */
|
---|
| 828 | #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))
|
---|
| 829 | /**
|
---|
| 830 | * @}
|
---|
| 831 | */
|
---|
| 832 |
|
---|
| 833 | /** @defgroup RCC_LSE_Configuration LSE Configuration
|
---|
| 834 | * @{
|
---|
| 835 | */
|
---|
| 836 |
|
---|
| 837 | /**
|
---|
| 838 | * @brief Macro to configure the External Low Speed oscillator (LSE).
|
---|
| 839 | * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
|
---|
| 840 | * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
|
---|
| 841 | * @note As the LSE is in the Backup domain and write access is denied to
|
---|
| 842 | * this domain after reset, you have to enable write access using
|
---|
| 843 | * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
|
---|
| 844 | * (to be done once after reset).
|
---|
| 845 | * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
|
---|
| 846 | * software should wait on LSERDY flag to be set indicating that LSE clock
|
---|
| 847 | * is stable and can be used to clock the RTC.
|
---|
| 848 | * @param __STATE__: specifies the new state of the LSE.
|
---|
| 849 | * This parameter can be one of the following values:
|
---|
| 850 | * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
|
---|
| 851 | * 6 LSE oscillator clock cycles.
|
---|
| 852 | * @arg RCC_LSE_ON: turn ON the LSE oscillator.
|
---|
| 853 | * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
|
---|
| 854 | */
|
---|
| 855 | #define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
|
---|
| 856 |
|
---|
| 857 | /**
|
---|
| 858 | * @}
|
---|
| 859 | */
|
---|
| 860 |
|
---|
| 861 | /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
|
---|
| 862 | * @{
|
---|
| 863 | */
|
---|
| 864 |
|
---|
| 865 | /** @brief Macros to enable or disable the RTC clock.
|
---|
| 866 | * @note These macros must be used only after the RTC clock source was selected.
|
---|
| 867 | */
|
---|
| 868 | #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
|
---|
| 869 | #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
|
---|
| 870 |
|
---|
| 871 | /** @brief Macros to configure the RTC clock (RTCCLK).
|
---|
| 872 | * @note As the RTC clock configuration bits are in the Backup domain and write
|
---|
| 873 | * access is denied to this domain after reset, you have to enable write
|
---|
| 874 | * access using the Power Backup Access macro before to configure
|
---|
| 875 | * the RTC clock source (to be done once after reset).
|
---|
| 876 | * @note Once the RTC clock is configured it can't be changed unless the
|
---|
| 877 | * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
|
---|
| 878 | * a Power On Reset (POR).
|
---|
| 879 | * @param __RTCCLKSource__: specifies the RTC clock source.
|
---|
| 880 | * This parameter can be one of the following values:
|
---|
| 881 | * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
|
---|
| 882 | * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
|
---|
| 883 | * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
|
---|
| 884 | * as RTC clock, where x:[2,31]
|
---|
| 885 | * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
|
---|
| 886 | * work in STOP and STANDBY modes, and can be used as wake-up source.
|
---|
| 887 | * However, when the HSE clock is used as RTC clock source, the RTC
|
---|
| 888 | * cannot be used in STOP and STANDBY modes.
|
---|
| 889 | * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
|
---|
| 890 | * RTC clock source).
|
---|
| 891 | */
|
---|
| 892 | #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
|
---|
| 893 | MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
|
---|
| 894 |
|
---|
| 895 | #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
|
---|
| 896 | RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
|
---|
| 897 | } while (0)
|
---|
| 898 |
|
---|
| 899 | /** @brief Macros to force or release the Backup domain reset.
|
---|
| 900 | * @note This function resets the RTC peripheral (including the backup registers)
|
---|
| 901 | * and the RTC clock source selection in RCC_CSR register.
|
---|
| 902 | * @note The BKPSRAM is not affected by this reset.
|
---|
| 903 | */
|
---|
| 904 | #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
|
---|
| 905 | #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
|
---|
| 906 | /**
|
---|
| 907 | * @}
|
---|
| 908 | */
|
---|
| 909 |
|
---|
| 910 | /** @defgroup RCC_PLL_Configuration PLL Configuration
|
---|
| 911 | * @{
|
---|
| 912 | */
|
---|
| 913 |
|
---|
| 914 | /** @brief Macros to enable or disable the main PLL.
|
---|
| 915 | * @note After enabling the main PLL, the application software should wait on
|
---|
| 916 | * PLLRDY flag to be set indicating that PLL clock is stable and can
|
---|
| 917 | * be used as system clock source.
|
---|
| 918 | * @note The main PLL can not be disabled if it is used as system clock source
|
---|
| 919 | * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
|
---|
| 920 | */
|
---|
| 921 | #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
|
---|
| 922 | #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
|
---|
| 923 |
|
---|
| 924 | /** @brief Macro to configure the PLL clock source.
|
---|
| 925 | * @note This function must be used only when the main PLL is disabled.
|
---|
| 926 | * @param __PLLSOURCE__: specifies the PLL entry clock source.
|
---|
| 927 | * This parameter can be one of the following values:
|
---|
| 928 | * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
|
---|
| 929 | * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
|
---|
| 930 | *
|
---|
| 931 | */
|
---|
| 932 | #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
|
---|
| 933 |
|
---|
| 934 | /** @brief Macro to configure the PLL multiplication factor.
|
---|
| 935 | * @note This function must be used only when the main PLL is disabled.
|
---|
| 936 | * @param __PLLM__: specifies the division factor for PLL VCO input clock
|
---|
| 937 | * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
|
---|
| 938 | * @note You have to set the PLLM parameter correctly to ensure that the VCO input
|
---|
| 939 | * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
|
---|
| 940 | * of 2 MHz to limit PLL jitter.
|
---|
| 941 | *
|
---|
| 942 | */
|
---|
| 943 | #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
|
---|
| 944 | /**
|
---|
| 945 | * @}
|
---|
| 946 | */
|
---|
| 947 |
|
---|
| 948 | /** @defgroup RCC_Get_Clock_source Get Clock source
|
---|
| 949 | * @{
|
---|
| 950 | */
|
---|
| 951 | /**
|
---|
| 952 | * @brief Macro to configure the system clock source.
|
---|
| 953 | * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
|
---|
| 954 | * This parameter can be one of the following values:
|
---|
| 955 | * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
|
---|
| 956 | * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
|
---|
| 957 | * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
|
---|
| 958 | * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source.
|
---|
| 959 | */
|
---|
| 960 | #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
|
---|
| 961 |
|
---|
| 962 | /** @brief Macro to get the clock source used as system clock.
|
---|
| 963 | * @retval The clock source used as system clock. The returned value can be one
|
---|
| 964 | * of the following:
|
---|
| 965 | * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
|
---|
| 966 | * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
|
---|
| 967 | * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
|
---|
| 968 | * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock.
|
---|
| 969 | */
|
---|
| 970 | #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
|
---|
| 971 |
|
---|
| 972 | /** @brief Macro to get the oscillator used as PLL clock source.
|
---|
| 973 | * @retval The oscillator used as PLL clock source. The returned value can be one
|
---|
| 974 | * of the following:
|
---|
| 975 | * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
|
---|
| 976 | * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
|
---|
| 977 | */
|
---|
| 978 | #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
|
---|
| 979 | /**
|
---|
| 980 | * @}
|
---|
| 981 | */
|
---|
| 982 |
|
---|
| 983 | /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
|
---|
| 984 | * @{
|
---|
| 985 | */
|
---|
| 986 |
|
---|
| 987 | /** @brief Macro to configure the MCO1 clock.
|
---|
| 988 | * @param __MCOCLKSOURCE__ specifies the MCO clock source.
|
---|
| 989 | * This parameter can be one of the following values:
|
---|
| 990 | * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
|
---|
| 991 | * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
|
---|
| 992 | * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
|
---|
| 993 | * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
|
---|
| 994 | * @param __MCODIV__ specifies the MCO clock prescaler.
|
---|
| 995 | * This parameter can be one of the following values:
|
---|
| 996 | * @arg RCC_MCODIV_1: no division applied to MCOx clock
|
---|
| 997 | * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
|
---|
| 998 | * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
|
---|
| 999 | * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
|
---|
| 1000 | * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
|
---|
| 1001 | */
|
---|
| 1002 |
|
---|
| 1003 | #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
|
---|
| 1004 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
|
---|
| 1005 |
|
---|
| 1006 | /** @brief Macro to configure the MCO2 clock.
|
---|
| 1007 | * @param __MCOCLKSOURCE__ specifies the MCO clock source.
|
---|
| 1008 | * This parameter can be one of the following values:
|
---|
| 1009 | * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
|
---|
| 1010 | * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
|
---|
| 1011 | * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
|
---|
| 1012 | * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
|
---|
| 1013 | * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
|
---|
| 1014 | * @param __MCODIV__ specifies the MCO clock prescaler.
|
---|
| 1015 | * This parameter can be one of the following values:
|
---|
| 1016 | * @arg RCC_MCODIV_1: no division applied to MCOx clock
|
---|
| 1017 | * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
|
---|
| 1018 | * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
|
---|
| 1019 | * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
|
---|
| 1020 | * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
|
---|
| 1021 | * @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
|
---|
| 1022 | * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
|
---|
| 1023 | */
|
---|
| 1024 |
|
---|
| 1025 | #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
|
---|
| 1026 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (__MCOCLKSOURCE__ | (__MCODIV__ << 3)));
|
---|
| 1027 | /**
|
---|
| 1028 | * @}
|
---|
| 1029 | */
|
---|
| 1030 |
|
---|
| 1031 | /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
|
---|
| 1032 | * @brief macros to manage the specified RCC Flags and interrupts.
|
---|
| 1033 | * @{
|
---|
| 1034 | */
|
---|
| 1035 |
|
---|
| 1036 | /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
|
---|
| 1037 | * the selected interrupts).
|
---|
| 1038 | * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
|
---|
| 1039 | * This parameter can be any combination of the following values:
|
---|
| 1040 | * @arg RCC_IT_LSIRDY: LSI ready interrupt.
|
---|
| 1041 | * @arg RCC_IT_LSERDY: LSE ready interrupt.
|
---|
| 1042 | * @arg RCC_IT_HSIRDY: HSI ready interrupt.
|
---|
| 1043 | * @arg RCC_IT_HSERDY: HSE ready interrupt.
|
---|
| 1044 | * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
|
---|
| 1045 | * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
|
---|
| 1046 | */
|
---|
| 1047 | #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
|
---|
| 1048 |
|
---|
| 1049 | /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
|
---|
| 1050 | * the selected interrupts).
|
---|
| 1051 | * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
|
---|
| 1052 | * This parameter can be any combination of the following values:
|
---|
| 1053 | * @arg RCC_IT_LSIRDY: LSI ready interrupt.
|
---|
| 1054 | * @arg RCC_IT_LSERDY: LSE ready interrupt.
|
---|
| 1055 | * @arg RCC_IT_HSIRDY: HSI ready interrupt.
|
---|
| 1056 | * @arg RCC_IT_HSERDY: HSE ready interrupt.
|
---|
| 1057 | * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
|
---|
| 1058 | * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
|
---|
| 1059 | */
|
---|
| 1060 | #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
|
---|
| 1061 |
|
---|
| 1062 | /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
|
---|
| 1063 | * bits to clear the selected interrupt pending bits.
|
---|
| 1064 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
|
---|
| 1065 | * This parameter can be any combination of the following values:
|
---|
| 1066 | * @arg RCC_IT_LSIRDY: LSI ready interrupt.
|
---|
| 1067 | * @arg RCC_IT_LSERDY: LSE ready interrupt.
|
---|
| 1068 | * @arg RCC_IT_HSIRDY: HSI ready interrupt.
|
---|
| 1069 | * @arg RCC_IT_HSERDY: HSE ready interrupt.
|
---|
| 1070 | * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
|
---|
| 1071 | * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
|
---|
| 1072 | * @arg RCC_IT_CSS: Clock Security System interrupt
|
---|
| 1073 | */
|
---|
| 1074 | #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
|
---|
| 1075 |
|
---|
| 1076 | /** @brief Check the RCC's interrupt has occurred or not.
|
---|
| 1077 | * @param __INTERRUPT__: specifies the RCC interrupt source to check.
|
---|
| 1078 | * This parameter can be one of the following values:
|
---|
| 1079 | * @arg RCC_IT_LSIRDY: LSI ready interrupt.
|
---|
| 1080 | * @arg RCC_IT_LSERDY: LSE ready interrupt.
|
---|
| 1081 | * @arg RCC_IT_HSIRDY: HSI ready interrupt.
|
---|
| 1082 | * @arg RCC_IT_HSERDY: HSE ready interrupt.
|
---|
| 1083 | * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
|
---|
| 1084 | * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
|
---|
| 1085 | * @arg RCC_IT_CSS: Clock Security System interrupt
|
---|
| 1086 | * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
---|
| 1087 | */
|
---|
| 1088 | #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
|
---|
| 1089 |
|
---|
| 1090 | /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
|
---|
| 1091 | * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
|
---|
| 1092 | */
|
---|
| 1093 | #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
|
---|
| 1094 |
|
---|
| 1095 | /** @brief Check RCC flag is set or not.
|
---|
| 1096 | * @param __FLAG__: specifies the flag to check.
|
---|
| 1097 | * This parameter can be one of the following values:
|
---|
| 1098 | * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
|
---|
| 1099 | * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
|
---|
| 1100 | * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
|
---|
| 1101 | * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
|
---|
| 1102 | * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
|
---|
| 1103 | * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
|
---|
| 1104 | * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
|
---|
| 1105 | * @arg RCC_FLAG_PINRST: Pin reset.
|
---|
| 1106 | * @arg RCC_FLAG_PORRST: POR/PDR reset.
|
---|
| 1107 | * @arg RCC_FLAG_SFTRST: Software reset.
|
---|
| 1108 | * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
|
---|
| 1109 | * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
|
---|
| 1110 | * @arg RCC_FLAG_LPWRRST: Low Power reset.
|
---|
| 1111 | * @retval The new state of __FLAG__ (TRUE or FALSE).
|
---|
| 1112 | */
|
---|
| 1113 | #define RCC_FLAG_MASK ((uint8_t)0x1F)
|
---|
| 1114 | #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
|
---|
| 1115 |
|
---|
| 1116 | /**
|
---|
| 1117 | * @}
|
---|
| 1118 | */
|
---|
| 1119 |
|
---|
| 1120 | /**
|
---|
| 1121 | * @}
|
---|
| 1122 | */
|
---|
| 1123 |
|
---|
| 1124 | /* Exported functions --------------------------------------------------------*/
|
---|
| 1125 | /** @addtogroup RCC_Exported_Functions
|
---|
| 1126 | * @{
|
---|
| 1127 | */
|
---|
| 1128 |
|
---|
| 1129 | /** @addtogroup RCC_Exported_Functions_Group1
|
---|
| 1130 | * @{
|
---|
| 1131 | */
|
---|
| 1132 | /* Initialization and de-initialization functions ******************************/
|
---|
| 1133 | void HAL_RCC_DeInit(void);
|
---|
| 1134 | HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
|
---|
| 1135 | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
|
---|
| 1136 | /**
|
---|
| 1137 | * @}
|
---|
| 1138 | */
|
---|
| 1139 |
|
---|
| 1140 | /** @addtogroup RCC_Exported_Functions_Group2
|
---|
| 1141 | * @{
|
---|
| 1142 | */
|
---|
| 1143 | /* Peripheral Control functions ************************************************/
|
---|
| 1144 | void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
|
---|
| 1145 | void HAL_RCC_EnableCSS(void);
|
---|
| 1146 | void HAL_RCC_DisableCSS(void);
|
---|
| 1147 | uint32_t HAL_RCC_GetSysClockFreq(void);
|
---|
| 1148 | uint32_t HAL_RCC_GetHCLKFreq(void);
|
---|
| 1149 | uint32_t HAL_RCC_GetPCLK1Freq(void);
|
---|
| 1150 | uint32_t HAL_RCC_GetPCLK2Freq(void);
|
---|
| 1151 | void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
|
---|
| 1152 | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
|
---|
| 1153 |
|
---|
| 1154 | /* CSS NMI IRQ handler */
|
---|
| 1155 | void HAL_RCC_NMI_IRQHandler(void);
|
---|
| 1156 |
|
---|
| 1157 | /* User Callbacks in non blocking mode (IT mode) */
|
---|
| 1158 | void HAL_RCC_CSSCallback(void);
|
---|
| 1159 |
|
---|
| 1160 | /**
|
---|
| 1161 | * @}
|
---|
| 1162 | */
|
---|
| 1163 |
|
---|
| 1164 | /**
|
---|
| 1165 | * @}
|
---|
| 1166 | */
|
---|
| 1167 |
|
---|
| 1168 | /* Private types -------------------------------------------------------------*/
|
---|
| 1169 | /* Private variables ---------------------------------------------------------*/
|
---|
| 1170 | /* Private constants ---------------------------------------------------------*/
|
---|
| 1171 | /** @defgroup RCC_Private_Constants RCC Private Constants
|
---|
| 1172 | * @{
|
---|
| 1173 | */
|
---|
| 1174 |
|
---|
| 1175 | /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
|
---|
| 1176 | * @brief RCC registers bit address in the alias region
|
---|
| 1177 | * @{
|
---|
| 1178 | */
|
---|
| 1179 | #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
|
---|
| 1180 | /* --- CR Register ---*/
|
---|
| 1181 | /* Alias word address of HSION bit */
|
---|
| 1182 | #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
|
---|
| 1183 | #define RCC_HSION_BIT_NUMBER 0x00
|
---|
| 1184 | #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_HSION_BIT_NUMBER * 4))
|
---|
| 1185 | /* Alias word address of CSSON bit */
|
---|
| 1186 | #define RCC_CSSON_BIT_NUMBER 0x13
|
---|
| 1187 | #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_CSSON_BIT_NUMBER * 4))
|
---|
| 1188 | /* Alias word address of PLLON bit */
|
---|
| 1189 | #define RCC_PLLON_BIT_NUMBER 0x18
|
---|
| 1190 | #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLON_BIT_NUMBER * 4))
|
---|
| 1191 |
|
---|
| 1192 | /* --- BDCR Register ---*/
|
---|
| 1193 | /* Alias word address of RTCEN bit */
|
---|
| 1194 | #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
|
---|
| 1195 | #define RCC_RTCEN_BIT_NUMBER 0x0F
|
---|
| 1196 | #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_RTCEN_BIT_NUMBER * 4))
|
---|
| 1197 | /* Alias word address of BDRST bit */
|
---|
| 1198 | #define RCC_BDRST_BIT_NUMBER 0x10
|
---|
| 1199 | #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_BDRST_BIT_NUMBER * 4))
|
---|
| 1200 |
|
---|
| 1201 | /* --- CSR Register ---*/
|
---|
| 1202 | /* Alias word address of LSION bit */
|
---|
| 1203 | #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
|
---|
| 1204 | #define RCC_LSION_BIT_NUMBER 0x00
|
---|
| 1205 | #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RCC_LSION_BIT_NUMBER * 4))
|
---|
| 1206 |
|
---|
| 1207 | /* CR register byte 3 (Bits[23:16]) base address */
|
---|
| 1208 | #define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
|
---|
| 1209 |
|
---|
| 1210 | /* CIR register byte 2 (Bits[15:8]) base address */
|
---|
| 1211 | #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
|
---|
| 1212 |
|
---|
| 1213 | /* CIR register byte 3 (Bits[23:16]) base address */
|
---|
| 1214 | #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
|
---|
| 1215 |
|
---|
| 1216 | /* BDCR register base address */
|
---|
| 1217 | #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
|
---|
| 1218 |
|
---|
| 1219 | #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
|
---|
| 1220 | #define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
|
---|
| 1221 |
|
---|
| 1222 | #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
|
---|
| 1223 | #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
|
---|
| 1224 | #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
|
---|
| 1225 |
|
---|
| 1226 | /**
|
---|
| 1227 | * @}
|
---|
| 1228 | */
|
---|
| 1229 |
|
---|
| 1230 | /**
|
---|
| 1231 | * @}
|
---|
| 1232 | */
|
---|
| 1233 |
|
---|
| 1234 | /* Private macros ------------------------------------------------------------*/
|
---|
| 1235 | /** @addtogroup RCC_Private_Macros RCC Private Macros
|
---|
| 1236 | * @{
|
---|
| 1237 | */
|
---|
| 1238 |
|
---|
| 1239 | /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
|
---|
| 1240 | * @{
|
---|
| 1241 | */
|
---|
| 1242 | #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
|
---|
| 1243 |
|
---|
| 1244 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
|
---|
| 1245 | ((HSE) == RCC_HSE_BYPASS))
|
---|
| 1246 |
|
---|
| 1247 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
|
---|
| 1248 | ((LSE) == RCC_LSE_BYPASS))
|
---|
| 1249 |
|
---|
| 1250 | #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
|
---|
| 1251 |
|
---|
| 1252 | #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
|
---|
| 1253 |
|
---|
| 1254 | #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
|
---|
| 1255 |
|
---|
| 1256 | #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
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| 1257 | ((SOURCE) == RCC_PLLSOURCE_HSE))
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| 1258 |
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| 1259 | #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
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| 1260 | ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
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| 1261 | ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
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| 1262 | ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
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| 1263 |
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| 1264 | #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
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| 1265 |
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| 1266 | #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
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| 1267 |
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| 1268 | #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
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| 1269 |
|
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| 1270 | #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
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| 1271 |
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| 1272 | #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
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| 1273 | ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
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| 1274 | ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
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| 1275 | ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
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| 1276 | ((HCLK) == RCC_SYSCLK_DIV512))
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| 1277 |
|
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| 1278 | #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
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| 1279 |
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| 1280 | #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
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| 1281 | ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
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| 1282 | ((PCLK) == RCC_HCLK_DIV16))
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| 1283 |
|
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| 1284 | #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
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| 1285 |
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| 1286 | #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
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| 1287 | ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
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| 1288 |
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| 1289 | #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
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| 1290 | ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
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| 1291 | ((DIV) == RCC_MCODIV_5))
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| 1292 | #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
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| 1293 |
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| 1294 | /**
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| 1295 | * @}
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| 1296 | */
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| 1297 |
|
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| 1298 | /**
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| 1299 | * @}
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| 1300 | */
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| 1301 |
|
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| 1302 | /**
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| 1303 | * @}
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| 1304 | */
|
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| 1305 |
|
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| 1306 | /**
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| 1307 | * @}
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| 1308 | */
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| 1309 |
|
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| 1310 | #ifdef __cplusplus
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| 1311 | }
|
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| 1312 | #endif
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| 1313 |
|
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| 1314 | #endif /* __STM32F4xx_HAL_RCC_H */
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| 1315 |
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| 1316 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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