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source: asp3_wo_tecs/trunk/arch/arm_m_gcc/stm32f4xx_stm32cube/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h@ 303

Last change on this file since 303 was 303, checked in by ertl-honda, 7 years ago
nucleo_f401re依存部の追加
File size: 36.0 KB

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1	/**
2	******************************************************************************
3	* @file stm32f4xx_hal_qspi.h
4	* @author MCD Application Team
5	* @version V1.4.1
6	* @date 09-October-2015
7	* @brief Header file of QSPI HAL module.
8	******************************************************************************
9	* @attention
10	*
11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
12	*
13	* Redistribution and use in source and binary forms, with or without modification,
14	* are permitted provided that the following conditions are met:
15	* 1. Redistributions of source code must retain the above copyright notice,
16	* this list of conditions and the following disclaimer.
17	* 2. Redistributions in binary form must reproduce the above copyright notice,
18	* this list of conditions and the following disclaimer in the documentation
19	* and/or other materials provided with the distribution.
20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
21	* may be used to endorse or promote products derived from this software
22	* without specific prior written permission.
23	*
24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34	*
35	******************************************************************************
36	*/
37
38	/* Define to prevent recursive inclusion -------------------------------------*/
39	#ifndef __STM32F4xx_HAL_QSPI_H
40	#define __STM32F4xx_HAL_QSPI_H
41
42	#ifdef __cplusplus
43	extern "C" {
44	#endif
45
46	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
47	/* Includes ------------------------------------------------------------------*/
48	#include "stm32f4xx_hal_def.h"
49
50	/** @addtogroup STM32F4xx_HAL_Driver
51	* @{
52	*/
53
54	/** @addtogroup QSPI
55	* @{
56	*/
57
58	/* Exported types ------------------------------------------------------------*/
59	/** @defgroup QSPI_Exported_Types QSPI Exported Types
60	* @{
61	*/
62
63	/**
64	* @brief QSPI Init structure definition
65	*/
66
67	typedef struct
68	{
69	uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
70	This parameter can be a number between 0 and 255 */
71
72	uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
73	This parameter can be a value between 1 and 32 */
74
75	uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
76	take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
77	This parameter can be a value of @ref QSPI_SampleShifting */
78
79	uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
80	required to address the flash memory. The flash capacity can be up to 4GB
81	(addressed using 32 bits) in indirect mode, but the addressable space in
82	memory-mapped mode is limited to 256MB
83	This parameter can be a number between 0 and 31 */
84
85	uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
86	of clock cycles which the chip select must remain high between commands.
87	This parameter can be a value of @ref QSPI_ChipSelectHighTime */
88
89	uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
90	This parameter can be a value of @ref QSPI_ClockMode */
91
92	uint32_t FlashID; /* Specifies the Flash which will be used,
93	This parameter can be a value of @ref QSPI_Flash_Select */
94
95	uint32_t DualFlash; /* Specifies the Dual Flash Mode State
96	This parameter can be a value of @ref QSPI_DualFlash_Mode */
97	}QSPI_InitTypeDef;
98
99	/**
100	* @brief HAL QSPI State structures definition
101	*/
102	typedef enum
103	{
104	HAL_QSPI_STATE_RESET = 0x00, /!< Peripheral not initialized /
105	HAL_QSPI_STATE_READY = 0x01, /!< Peripheral initialized and ready for use /
106	HAL_QSPI_STATE_BUSY = 0x02, /!< Peripheral in indirect mode and busy /
107	HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /!< Peripheral in indirect mode with transmission ongoing /
108	HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /!< Peripheral in indirect mode with reception ongoing /
109	HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /!< Peripheral in auto polling mode ongoing /
110	HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /!< Peripheral in memory mapped mode ongoing /
111	HAL_QSPI_STATE_ERROR = 0x04 /!< Peripheral in error /
112	}HAL_QSPI_StateTypeDef;
113
114	/**
115	* @brief QSPI Handle Structure definition
116	*/
117	typedef struct
118	{
119	QUADSPI_TypeDef Instance; / QSPI registers base address */
120	QSPI_InitTypeDef Init; /* QSPI communication parameters */
121	uint8_t pTxBuffPtr; / Pointer to QSPI Tx transfer Buffer */
122	__IO uint16_t TxXferSize; /* QSPI Tx Transfer size */
123	__IO uint16_t TxXferCount; /* QSPI Tx Transfer Counter */
124	uint8_t pRxBuffPtr; / Pointer to QSPI Rx transfer Buffer */
125	__IO uint16_t RxXferSize; /* QSPI Rx Transfer size */
126	__IO uint16_t RxXferCount; /* QSPI Rx Transfer Counter */
127	DMA_HandleTypeDef hdma; / QSPI Rx/Tx DMA Handle parameters */
128	__IO HAL_LockTypeDef Lock; /* Locking object */
129	__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
130	__IO uint32_t ErrorCode; /* QSPI Error code */
131	uint32_t Timeout; /* Timeout for the QSPI memory access */
132	}QSPI_HandleTypeDef;
133
134	/**
135	* @brief QSPI Command structure definition
136	*/
137	typedef struct
138	{
139	uint32_t Instruction; /* Specifies the Instruction to be sent
140	This parameter can be a value (8-bit) between 0x00 and 0xFF */
141	uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
142	This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
143	uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
144	This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
145	uint32_t AddressSize; /* Specifies the Address Size
146	This parameter can be a value of @ref QSPI_AddressSize */
147	uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
148	This parameter can be a value of @ref QSPI_AlternateBytesSize */
149	uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
150	This parameter can be a number between 0 and 31 */
151	uint32_t InstructionMode; /* Specifies the Instruction Mode
152	This parameter can be a value of @ref QSPI_InstructionMode */
153	uint32_t AddressMode; /* Specifies the Address Mode
154	This parameter can be a value of @ref QSPI_AddressMode */
155	uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
156	This parameter can be a value of @ref QSPI_AlternateBytesMode */
157	uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
158	This parameter can be a value of @ref QSPI_DataMode */
159	uint32_t NbData; /* Specifies the number of data to transfer.
160	This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
161	until end of memory)*/
162	uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
163	This parameter can be a value of @ref QSPI_DdrMode */
164	uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
165	system clock in DDR mode.
166	This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
167	uint32_t SIOOMode; /* Specifies the send instruction only once mode
168	This parameter can be a value of @ref QSPI_SIOOMode */
169	}QSPI_CommandTypeDef;
170
171	/**
172	* @brief QSPI Auto Polling mode configuration structure definition
173	*/
174	typedef struct
175	{
176	uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
177	This parameter can be any value between 0 and 0xFFFFFFFF */
178	uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
179	This parameter can be any value between 0 and 0xFFFFFFFF */
180	uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
181	This parameter can be any value between 0 and 0xFFFF */
182	uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
183	This parameter can be any value between 1 and 4 */
184	uint32_t MatchMode; /* Specifies the method used for determining a match.
185	This parameter can be a value of @ref QSPI_MatchMode */
186	uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
187	This parameter can be a value of @ref QSPI_AutomaticStop */
188	}QSPI_AutoPollingTypeDef;
189
190	/**
191	* @brief QSPI Memory Mapped mode configuration structure definition
192	*/
193	typedef struct
194	{
195	uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
196	This parameter can be any value between 0 and 0xFFFF */
197	uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
198	This parameter can be a value of @ref QSPI_TimeOutActivation */
199	}QSPI_MemoryMappedTypeDef;
200	/**
201	* @}
202	*/
203
204	/* Exported constants --------------------------------------------------------*/
205	/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
206	* @{
207	*/
208	/** @defgroup QSPI_ErrorCode QSPI Error Code
209	* @{
210	*/
211	#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /!< No error /
212	#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /!< Timeout error /
213	#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /!< Transfer error /
214	#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /!< DMA transfer error /
215	/**
216	* @}
217	*/
218
219	/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
220	* @{
221	*/
222	#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /!<No clock cycle shift to sample data/
223	#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /!<1/2 clock cycle shift to sample data/
224	/**
225	* @}
226	*/
227
228	/** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
229	* @{
230	*/
231	#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000) /!<nCS stay high for at least 1 clock cycle between commands/
232	#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /!<nCS stay high for at least 2 clock cycles between commands/
233	#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /!<nCS stay high for at least 3 clock cycles between commands/
234	#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 \| QUADSPI_DCR_CSHT_1) /!<nCS stay high for at least 4 clock cycles between commands/
235	#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /!<nCS stay high for at least 5 clock cycles between commands/
236	#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 \| QUADSPI_DCR_CSHT_0) /!<nCS stay high for at least 6 clock cycles between commands/
237	#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 \| QUADSPI_DCR_CSHT_1) /!<nCS stay high for at least 7 clock cycles between commands/
238	#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /!<nCS stay high for at least 8 clock cycles between commands/
239	/**
240	* @}
241	*/
242
243	/** @defgroup QSPI_ClockMode QSPI Clock Mode
244	* @{
245	*/
246	#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /!<Clk stays low while nCS is released/
247	#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /!<Clk goes high while nCS is released/
248	/**
249	* @}
250	*/
251
252	/** @defgroup QSPI_Flash_Select QSPI Flash Select
253	* @{
254	*/
255	#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000)
256	#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
257	/**
258	* @}
259	*/
260
261	/** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
262	* @{
263	*/
264	#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
265	#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000)
266	/**
267	* @}
268	*/
269
270	/** @defgroup QSPI_AddressSize QSPI Address Size
271	* @{
272	*/
273	#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /!<8-bit address/
274	#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /!<16-bit address/
275	#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /!<24-bit address/
276	#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /!<32-bit address/
277	/**
278	* @}
279	*/
280
281	/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
282	* @{
283	*/
284	#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /!<8-bit alternate bytes/
285	#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /!<16-bit alternate bytes/
286	#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /!<24-bit alternate bytes/
287	#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /!<32-bit alternate bytes/
288	/**
289	* @}
290	*/
291
292	/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
293	* @{
294	*/
295	#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /!<No instruction/
296	#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /!<Instruction on a single line/
297	#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /!<Instruction on two lines/
298	#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /!<Instruction on four lines/
299	/**
300	* @}
301	*/
302
303	/** @defgroup QSPI_AddressMode QSPI Address Mode
304	* @{
305	*/
306	#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /!<No address/
307	#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /!<Address on a single line/
308	#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /!<Address on two lines/
309	#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /!<Address on four lines/
310	/**
311	* @}
312	*/
313
314	/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
315	* @{
316	*/
317	#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /!<No alternate bytes/
318	#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /!<Alternate bytes on a single line/
319	#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /!<Alternate bytes on two lines/
320	#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /!<Alternate bytes on four lines/
321	/**
322	* @}
323	*/
324
325	/** @defgroup QSPI_DataMode QSPI Data Mode
326	* @{
327	*/
328	#define QSPI_DATA_NONE ((uint32_t)0X00000000) /!<No data/
329	#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /!<Data on a single line/
330	#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /!<Data on two lines/
331	#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /!<Data on four lines/
332	/**
333	* @}
334	*/
335
336	/** @defgroup QSPI_DdrMode QSPI Ddr Mode
337	* @{
338	*/
339	#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /!<Double data rate mode disabled/
340	#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /!<Double data rate mode enabled/
341	/**
342	* @}
343	*/
344
345	/** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
346	* @{
347	*/
348	#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /!<Delay the data output using analog delay in DDR mode/
349	#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /!<Delay the data output by 1/2 clock cycle in DDR mode/
350	/**
351	* @}
352	*/
353
354	/** @defgroup QSPI_SIOOMode QSPI SIOO Mode
355	* @{
356	*/
357	#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /!<Send instruction on every transaction/
358	#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /!<Send instruction only for the first command/
359	/**
360	* @}
361	*/
362
363	/** @defgroup QSPI_MatchMode QSPI Match Mode
364	* @{
365	*/
366	#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /!<AND match mode between unmasked bits/
367	#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /!<OR match mode between unmasked bits/
368	/**
369	* @}
370	*/
371
372	/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
373	* @{
374	*/
375	#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /!<AutoPolling stops only with abort or QSPI disabling/
376	#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /!<AutoPolling stops as soon as there is a match/
377	/**
378	* @}
379	*/
380
381	/** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
382	* @{
383	*/
384	#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /!<Timeout counter disabled, nCS remains active/
385	#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /!<Timeout counter enabled, nCS released when timeout expires/
386	/**
387	* @}
388	*/
389
390	/** @defgroup QSPI_Flags QSPI Flags
391	* @{
392	*/
393	#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /!<Busy flag: operation is ongoing/
394	#define QSPI_FLAG_TO QUADSPI_SR_TOF /!<Timeout flag: timeout occurs in memory-mapped mode/
395	#define QSPI_FLAG_SM QUADSPI_SR_SMF /!<Status match flag: received data matches in autopolling mode/
396	#define QSPI_FLAG_FT QUADSPI_SR_FTF /!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete/
397	#define QSPI_FLAG_TC QUADSPI_SR_TCF /!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted/
398	#define QSPI_FLAG_TE QUADSPI_SR_TEF /!<Transfer error flag: invalid address is being accessed/
399	/**
400	* @}
401	*/
402
403	/** @defgroup QSPI_Interrupts QSPI Interrupts
404	* @{
405	*/
406	#define QSPI_IT_TO QUADSPI_CR_TOIE /!<Interrupt on the timeout flag/
407	#define QSPI_IT_SM QUADSPI_CR_SMIE /!<Interrupt on the status match flag/
408	#define QSPI_IT_FT QUADSPI_CR_FTIE /!<Interrupt on the fifo threshold flag/
409	#define QSPI_IT_TC QUADSPI_CR_TCIE /!<Interrupt on the transfer complete flag/
410	#define QSPI_IT_TE QUADSPI_CR_TEIE /!<Interrupt on the transfer error flag/
411	/**
412	* @}
413	*/
414
415	/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
416	* @{
417	*/
418	#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
419	/**
420	* @}
421	*/
422
423	/**
424	* @}
425	*/
426
427	/* Exported macros -----------------------------------------------------------*/
428	/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
429	* @{
430	*/
431
432	/** @brief Reset QSPI handle state
433	* @param __HANDLE__: QSPI handle.
434	* @retval None
435	*/
436	#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
437
438	/** @brief Enable QSPI
439	* @param __HANDLE__: specifies the QSPI Handle.
440	* @retval None
441	*/
442	#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
443
444	/** @brief Disable QSPI
445	* @param __HANDLE__: specifies the QSPI Handle.
446	* @retval None
447	*/
448	#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
449
450	/** @brief Enables the specified QSPI interrupt.
451	* @param __HANDLE__: specifies the QSPI Handle.
452	* @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
453	* This parameter can be one of the following values:
454	* @arg QSPI_IT_TO: QSPI Time out interrupt
455	* @arg QSPI_IT_SM: QSPI Status match interrupt
456	* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
457	* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
458	* @arg QSPI_IT_TE: QSPI Transfer error interrupt
459	* @retval None
460	*/
461	#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
462
463
464	/** @brief Disables the specified QSPI interrupt.
465	* @param __HANDLE__: specifies the QSPI Handle.
466	* @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
467	* This parameter can be one of the following values:
468	* @arg QSPI_IT_TO: QSPI Timeout interrupt
469	* @arg QSPI_IT_SM: QSPI Status match interrupt
470	* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
471	* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
472	* @arg QSPI_IT_TE: QSPI Transfer error interrupt
473	* @retval None
474	*/
475	#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
476
477	/** @brief Checks whether the specified QSPI interrupt source is enabled.
478	* @param __HANDLE__: specifies the QSPI Handle.
479	* @param __INTERRUPT__: specifies the QSPI interrupt source to check.
480	* This parameter can be one of the following values:
481	* @arg QSPI_IT_TO: QSPI Time out interrupt
482	* @arg QSPI_IT_SM: QSPI Status match interrupt
483	* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
484	* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
485	* @arg QSPI_IT_TE: QSPI Transfer error interrupt
486	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
487	*/
488	#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
489
490	/**
491	* @brief Get the selected QSPI's flag status.
492	* @param __HANDLE__: specifies the QSPI Handle.
493	* @param __FLAG__: specifies the QSPI flag to check.
494	* This parameter can be one of the following values:
495	* @arg QSPI_FLAG_BUSY: QSPI Busy flag
496	* @arg QSPI_FLAG_TO: QSPI Time out flag
497	* @arg QSPI_FLAG_SM: QSPI Status match flag
498	* @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
499	* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
500	* @arg QSPI_FLAG_TE: QSPI Transfer error flag
501	* @retval None
502	*/
503	#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
504
505	/** @brief Clears the specified QSPI's flag status.
506	* @param __HANDLE__: specifies the QSPI Handle.
507	* @param __FLAG__: specifies the QSPI clear register flag that needs to be set
508	* This parameter can be one of the following values:
509	* @arg QSPI_FLAG_TO: QSPI Time out flag
510	* @arg QSPI_FLAG_SM: QSPI Status match flag
511	* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
512	* @arg QSPI_FLAG_TE: QSPI Transfer error flag
513	* @retval None
514	*/
515	#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
516	/**
517	* @}
518	*/
519
520	/* Exported functions --------------------------------------------------------*/
521	/** @addtogroup QSPI_Exported_Functions
522	* @{
523	*/
524
525	/** @addtogroup QSPI_Exported_Functions_Group1
526	* @{
527	*/
528	/* Initialization/de-initialization functions ********************************/
529	HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
530	HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
531	void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
532	void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
533	/**
534	* @}
535	*/
536
537	/** @addtogroup QSPI_Exported_Functions_Group2
538	* @{
539	*/
540	/* IO operation functions *****************************************************/
541	/* QSPI IRQ handler method */
542	void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
543
544	/* QSPI indirect mode */
545	HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t Timeout);
546	HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout);
547	HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout);
548	HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd);
549	HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef hqspi, uint8_t pData);
550	HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef hqspi, uint8_t pData);
551	HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef hqspi, uint8_t pData);
552	HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef hqspi, uint8_t pData);
553
554	/* QSPI status flag polling mode */
555	HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
556	HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg);
557
558	/* QSPI memory-mapped mode */
559	HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_MemoryMappedTypeDef *cfg);
560	/**
561	* @}
562	*/
563
564	/** @addtogroup QSPI_Exported_Functions_Group3
565	* @{
566	*/
567	/* Callback functions in non-blocking modes ***********************************/
568	void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
569	void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
570
571	/* QSPI indirect mode */
572	void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
573	void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
574	void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
575	void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
576	void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
577
578	/* QSPI status flag polling mode */
579	void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
580
581	/* QSPI memory-mapped mode */
582	void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
583	/**
584	* @}
585	*/
586
587	/** @addtogroup QSPI_Exported_Functions_Group4
588	* @{
589	*/
590	/* Peripheral Control and State functions ************************************/
591	HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi);
592	uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi);
593	HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
594	void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
595	/**
596	* @}
597	*/
598
599	/**
600	* @}
601	*/
602
603	/* Private types -------------------------------------------------------------*/
604	/* Private variables ---------------------------------------------------------*/
605	/* Private constants ---------------------------------------------------------*/
606	/** @defgroup QSPI_Private_Constants QSPI Private Constants
607	* @{
608	*/
609
610	/**
611	* @}
612	*/
613
614	/* Private macros ------------------------------------------------------------*/
615	/** @defgroup QSPI_Private_Macros QSPI Private Macros
616	* @{
617	*/
618	/** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
619	* @{
620	*/
621	#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
622	/**
623	* @}
624	*/
625
626	/** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold
627	* @{
628	*/
629	#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32))
630	/**
631	* @}
632	*/
633
634	#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) \|\| \
635	((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
636
637	/** @defgroup QSPI_FlashSize QSPI Flash Size
638	* @{
639	*/
640	#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
641	/**
642	* @}
643	*/
644
645	#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) \|\| \
646	((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) \|\| \
647	((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) \|\| \
648	((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) \|\| \
649	((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) \|\| \
650	((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) \|\| \
651	((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) \|\| \
652	((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
653
654	#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) \|\| \
655	((CLKMODE) == QSPI_CLOCK_MODE_3))
656
657	#define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) \|\| \
658	((FLA) == QSPI_FLASH_ID_2))
659
660	#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) \|\| \
661	((MODE) == QSPI_DUALFLASH_DISABLE))
662
663
664	/** @defgroup QSPI_Instruction QSPI Instruction
665	* @{
666	*/
667	#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
668	/**
669	* @}
670	*/
671
672	#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) \|\| \
673	((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) \|\| \
674	((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) \|\| \
675	((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
676
677	#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) \|\| \
678	((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) \|\| \
679	((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) \|\| \
680	((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
681
682
683	/** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
684	* @{
685	*/
686	#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
687	/**
688	* @}
689	*/
690
691	#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) \|\| \
692	((MODE) == QSPI_INSTRUCTION_1_LINE) \|\| \
693	((MODE) == QSPI_INSTRUCTION_2_LINES) \|\| \
694	((MODE) == QSPI_INSTRUCTION_4_LINES))
695
696	#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) \|\| \
697	((MODE) == QSPI_ADDRESS_1_LINE) \|\| \
698	((MODE) == QSPI_ADDRESS_2_LINES) \|\| \
699	((MODE) == QSPI_ADDRESS_4_LINES))
700
701	#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) \|\| \
702	((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) \|\| \
703	((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) \|\| \
704	((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
705
706	#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) \|\| \
707	((MODE) == QSPI_DATA_1_LINE) \|\| \
708	((MODE) == QSPI_DATA_2_LINES) \|\| \
709	((MODE) == QSPI_DATA_4_LINES))
710
711	#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) \|\| \
712	((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
713
714	#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) \|\| \
715	((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
716
717	#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) \|\| \
718	((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
719
720	/** @defgroup QSPI_Interval QSPI Interval
721	* @{
722	*/
723	#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
724	/**
725	* @}
726	*/
727
728	/** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
729	* @{
730	*/
731	#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
732	/**
733	* @}
734	*/
735	#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) \|\| \
736	((MODE) == QSPI_MATCH_MODE_OR))
737
738	#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) \|\| \
739	((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
740
741	#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) \|\| \
742	((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
743
744	/** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period
745	* @{
746	*/
747	#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)
748	/**
749	* @}
750	*/
751
752	#define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) \|\| \
753	((FLAG) == QSPI_FLAG_TO) \|\| \
754	((FLAG) == QSPI_FLAG_SM) \|\| \
755	((FLAG) == QSPI_FLAG_FT) \|\| \
756	((FLAG) == QSPI_FLAG_TC) \|\| \
757	((FLAG) == QSPI_FLAG_TE))
758
759	#define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFF) == 0x00000000) && ((IT) != 0x00000000))
760	/**
761	* @}
762	*/
763
764	/* Private functions ---------------------------------------------------------*/
765	/** @defgroup QSPI_Private_Functions QSPI Private Functions
766	* @{
767	*/
768
769	/**
770	* @}
771	*/
772
773	/**
774	* @}
775	*/
776
777	/**
778	* @}
779	*/
780	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
781
782	#ifdef __cplusplus
783	}
784	#endif
785
786	#endif /* __STM32F4xx_HAL_QSPI_H */
787
788	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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