source: asp3_wo_tecs/trunk/arch/arm_m_gcc/stm32f4xx_stm32cube/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h@ 303

Last change on this file since 303 was 303, checked in by ertl-honda, 7 years ago

nucleo_f401re依存部の追加
File size: 11.7 KB
Line 
1/**
2 ******************************************************************************
3 * @file stm32f4xx_hal_nand.h
4 * @author MCD Application Team
5 * @version V1.4.1
6 * @date 09-October-2015
7 * @brief Header file of NAND HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38/* Define to prevent recursive inclusion -------------------------------------*/
39#ifndef __STM32F4xx_HAL_NAND_H
40#define __STM32F4xx_HAL_NAND_H
41
42#ifdef __cplusplus
43 extern "C" {
44#endif
45
46/* Includes ------------------------------------------------------------------*/
47#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
48 #include "stm32f4xx_ll_fsmc.h"
49#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
50
51#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
52 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
53 #include "stm32f4xx_ll_fmc.h"
54#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
55 STM32F479xx */
56
57/** @addtogroup STM32F4xx_HAL_Driver
58 * @{
59 */
60
61/** @addtogroup NAND
62 * @{
63 */
64
65#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
66 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
67 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
68
69/* Exported typedef ----------------------------------------------------------*/
70/* Exported types ------------------------------------------------------------*/
71/** @defgroup NAND_Exported_Types NAND Exported Types
72 * @{
73 */
74
75/**
76 * @brief HAL NAND State structures definition
77 */
78typedef enum
79{
80 HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
81 HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
82 HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
83 HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
84}HAL_NAND_StateTypeDef;
85
86/**
87 * @brief NAND Memory electronic signature Structure definition
88 */
89typedef struct
90{
91 /*<! NAND memory electronic signature maker and device IDs */
92
93 uint8_t Maker_Id;
94
95 uint8_t Device_Id;
96
97 uint8_t Third_Id;
98
99 uint8_t Fourth_Id;
100}NAND_IDTypeDef;
101
102/**
103 * @brief NAND Memory address Structure definition
104 */
105typedef struct
106{
107 uint16_t Page; /*!< NAND memory Page address */
108
109 uint16_t Zone; /*!< NAND memory Zone address */
110
111 uint16_t Block; /*!< NAND memory Block address */
112
113}NAND_AddressTypeDef;
114
115/**
116 * @brief NAND Memory info Structure definition
117 */
118typedef struct
119{
120 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
121
122 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
123
124 uint32_t BlockSize; /*!< NAND memory block size number of pages */
125
126 uint32_t BlockNbr; /*!< NAND memory number of blocks */
127
128 uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
129}NAND_InfoTypeDef;
130
131/**
132 * @brief NAND handle Structure definition
133 */
134typedef struct
135{
136 FMC_NAND_TypeDef *Instance; /*!< Register base address */
137
138 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
139
140 HAL_LockTypeDef Lock; /*!< NAND locking object */
141
142 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
143
144 NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
145}NAND_HandleTypeDef;
146/**
147 * @}
148 */
149
150/* Exported constants --------------------------------------------------------*/
151/* Exported macros ------------------------------------------------------------*/
152/** @defgroup NAND_Exported_Macros NAND Exported Macros
153 * @{
154 */
155
156/** @brief Reset NAND handle state
157 * @param __HANDLE__: specifies the NAND handle.
158 * @retval None
159 */
160#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
161
162/**
163 * @}
164 */
165
166/* Exported functions --------------------------------------------------------*/
167/** @addtogroup NAND_Exported_Functions NAND Exported Functions
168 * @{
169 */
170
171/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
172 * @{
173 */
174
175/* Initialization/de-initialization functions ********************************/
176HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
177HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
178void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
179void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
180void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
181void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
182
183/**
184 * @}
185 */
186
187/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
188 * @{
189 */
190
191/* IO operation functions ****************************************************/
192HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
193HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
194HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
195HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
196HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
197HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
198HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
199uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
200uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
201
202/**
203 * @}
204 */
205
206/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
207 * @{
208 */
209
210/* NAND Control functions ****************************************************/
211HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
212HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
213HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
214
215/**
216 * @}
217 */
218
219/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
220 * @{
221 */
222/* NAND State functions *******************************************************/
223HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
224uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
225/**
226 * @}
227 */
228
229/**
230 * @}
231 */
232
233/* Private types -------------------------------------------------------------*/
234/* Private variables ---------------------------------------------------------*/
235/* Private constants ---------------------------------------------------------*/
236/** @defgroup NAND_Private_Constants NAND Private Constants
237 * @{
238 */
239#define NAND_DEVICE1 ((uint32_t)0x70000000)
240#define NAND_DEVICE2 ((uint32_t)0x80000000)
241#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)
242
243#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
244#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
245
246#define NAND_CMD_AREA_A ((uint8_t)0x00)
247#define NAND_CMD_AREA_B ((uint8_t)0x01)
248#define NAND_CMD_AREA_C ((uint8_t)0x50)
249#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
250
251#define NAND_CMD_WRITE0 ((uint8_t)0x80)
252#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
253#define NAND_CMD_ERASE0 ((uint8_t)0x60)
254#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
255#define NAND_CMD_READID ((uint8_t)0x90)
256#define NAND_CMD_STATUS ((uint8_t)0x70)
257#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
258#define NAND_CMD_RESET ((uint8_t)0xFF)
259
260/* NAND memory status */
261#define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
262#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
263#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
264#define NAND_BUSY ((uint32_t)0x00000000)
265#define NAND_ERROR ((uint32_t)0x00000001)
266#define NAND_READY ((uint32_t)0x00000040)
267/**
268 * @}
269 */
270
271/* Private macros ------------------------------------------------------------*/
272/** @defgroup NAND_Private_Macros NAND Private Macros
273 * @{
274 */
275
276/**
277 * @brief NAND memory address computation.
278 * @param __ADDRESS__: NAND memory address.
279 * @param __HANDLE__: NAND handle.
280 * @retval NAND Raw address value
281 */
282#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
283 (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
284
285/**
286 * @brief NAND memory address cycling.
287 * @param __ADDRESS__: NAND memory address.
288 * @retval NAND address cycling value.
289 */
290#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
291#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
292#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
293#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
294/**
295 * @}
296 */
297#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
298 STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
299 STM32F446xx || STM32F469xx || STM32F479xx */
300
301/**
302 * @}
303 */
304/**
305 * @}
306 */
307
308/**
309 * @}
310 */
311
312#ifdef __cplusplus
313}
314#endif
315
316#endif /* __STM32F4xx_HAL_NAND_H */
317
318/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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