source: asp3_wo_tecs/trunk/arch/arm_m_gcc/stm32f4xx_stm32cube/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h@ 303

Last change on this file since 303 was 303, checked in by ertl-honda, 7 years ago

nucleo_f401re依存部の追加
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1/**
2 ******************************************************************************
3 * @file stm32f4xx_hal_eth.h
4 * @author MCD Application Team
5 * @version V1.4.1
6 * @date 09-October-2015
7 * @brief Header file of ETH HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38/* Define to prevent recursive inclusion -------------------------------------*/
39#ifndef __STM32F4xx_HAL_ETH_H
40#define __STM32F4xx_HAL_ETH_H
41
42#ifdef __cplusplus
43 extern "C" {
44#endif
45
46#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
47 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
48/* Includes ------------------------------------------------------------------*/
49#include "stm32f4xx_hal_def.h"
50
51/** @addtogroup STM32F4xx_HAL_Driver
52 * @{
53 */
54
55/** @addtogroup ETH
56 * @{
57 */
58
59/** @addtogroup ETH_Private_Macros
60 * @{
61 */
62#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
63#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
64 ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
65#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
66 ((SPEED) == ETH_SPEED_100M))
67#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
68 ((MODE) == ETH_MODE_HALFDUPLEX))
69#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
70 ((MODE) == ETH_RXINTERRUPT_MODE))
71#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
72 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
73#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
74 ((MODE) == ETH_MEDIA_INTERFACE_RMII))
75#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
76 ((CMD) == ETH_WATCHDOG_DISABLE))
77#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
78 ((CMD) == ETH_JABBER_DISABLE))
79#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
80 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
81 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
82 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
83 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
84 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
85 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
86 ((GAP) == ETH_INTERFRAMEGAP_40BIT))
87#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
88 ((CMD) == ETH_CARRIERSENCE_DISABLE))
89#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
90 ((CMD) == ETH_RECEIVEOWN_DISABLE))
91#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
92 ((CMD) == ETH_LOOPBACKMODE_DISABLE))
93#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
94 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
95#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
96 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
97#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
98 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
99#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
100 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
101 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
102 ((LIMIT) == ETH_BACKOFFLIMIT_1))
103#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
104 ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
105#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
106 ((CMD) == ETH_RECEIVEAll_DISABLE))
107#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
108 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
109 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
110#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
111 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
112 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
113#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
114 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
115#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
116 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
117#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
118 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
119#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
120 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
121 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
122 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
123#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
124 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
125 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
126#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
127#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
128 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
129#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
130 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
131 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
132 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
133#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
134 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
135#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
136 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
137#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
138 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
139#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
140 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
141#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
142#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
143 ((ADDRESS) == ETH_MAC_ADDRESS1) || \
144 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
145 ((ADDRESS) == ETH_MAC_ADDRESS3))
146#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
147 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
148 ((ADDRESS) == ETH_MAC_ADDRESS3))
149#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
150 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
151#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
152 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
153 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
154 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
155 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
156 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
157#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
158 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
159#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
160 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
161#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
162 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
163#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
164 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
165#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
166 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
167 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
168 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
169 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
170 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
171 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
172 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
173#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
174 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
175#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
176 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
177#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
178 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
179 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
180 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
181#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
182 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
183#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
184 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
185#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
186 ((CMD) == ETH_FIXEDBURST_DISABLE))
187#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
188 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
189 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
190 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
191 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
192 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
193 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
194 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
195 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
196 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
197 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
198 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
199#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
200 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
201 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
202 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
203 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
204 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
205 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
206 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
207 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
208 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
209 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
210 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
211#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
212#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
213 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
214 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
215 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
216 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
217#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
218 ((FLAG) == ETH_DMATXDESC_IC) || \
219 ((FLAG) == ETH_DMATXDESC_LS) || \
220 ((FLAG) == ETH_DMATXDESC_FS) || \
221 ((FLAG) == ETH_DMATXDESC_DC) || \
222 ((FLAG) == ETH_DMATXDESC_DP) || \
223 ((FLAG) == ETH_DMATXDESC_TTSE) || \
224 ((FLAG) == ETH_DMATXDESC_TER) || \
225 ((FLAG) == ETH_DMATXDESC_TCH) || \
226 ((FLAG) == ETH_DMATXDESC_TTSS) || \
227 ((FLAG) == ETH_DMATXDESC_IHE) || \
228 ((FLAG) == ETH_DMATXDESC_ES) || \
229 ((FLAG) == ETH_DMATXDESC_JT) || \
230 ((FLAG) == ETH_DMATXDESC_FF) || \
231 ((FLAG) == ETH_DMATXDESC_PCE) || \
232 ((FLAG) == ETH_DMATXDESC_LCA) || \
233 ((FLAG) == ETH_DMATXDESC_NC) || \
234 ((FLAG) == ETH_DMATXDESC_LCO) || \
235 ((FLAG) == ETH_DMATXDESC_EC) || \
236 ((FLAG) == ETH_DMATXDESC_VF) || \
237 ((FLAG) == ETH_DMATXDESC_CC) || \
238 ((FLAG) == ETH_DMATXDESC_ED) || \
239 ((FLAG) == ETH_DMATXDESC_UF) || \
240 ((FLAG) == ETH_DMATXDESC_DB))
241#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
242 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
243#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
244 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
245 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
246 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
247#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
248#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
249 ((FLAG) == ETH_DMARXDESC_AFM) || \
250 ((FLAG) == ETH_DMARXDESC_ES) || \
251 ((FLAG) == ETH_DMARXDESC_DE) || \
252 ((FLAG) == ETH_DMARXDESC_SAF) || \
253 ((FLAG) == ETH_DMARXDESC_LE) || \
254 ((FLAG) == ETH_DMARXDESC_OE) || \
255 ((FLAG) == ETH_DMARXDESC_VLAN) || \
256 ((FLAG) == ETH_DMARXDESC_FS) || \
257 ((FLAG) == ETH_DMARXDESC_LS) || \
258 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
259 ((FLAG) == ETH_DMARXDESC_LC) || \
260 ((FLAG) == ETH_DMARXDESC_FT) || \
261 ((FLAG) == ETH_DMARXDESC_RWT) || \
262 ((FLAG) == ETH_DMARXDESC_RE) || \
263 ((FLAG) == ETH_DMARXDESC_DBE) || \
264 ((FLAG) == ETH_DMARXDESC_CE) || \
265 ((FLAG) == ETH_DMARXDESC_MAMPCE))
266#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
267 ((BUFFER) == ETH_DMARXDESC_BUFFER2))
268#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
269 ((FLAG) == ETH_PMT_FLAG_MPR))
270#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
271#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
272 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
273 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
274 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
275 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
276 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
277 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
278 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
279 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
280 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
281 ((FLAG) == ETH_DMA_FLAG_T))
282#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))
283#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
284 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
285 ((IT) == ETH_MAC_IT_PMT))
286#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
287 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
288 ((FLAG) == ETH_MAC_FLAG_PMT))
289#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
290#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
291 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
292 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
293 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
294 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
295 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
296 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
297 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
298 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
299#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
300 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
301#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
302 ((IT) != 0x00))
303#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
304 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
305 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
306#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
307 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
308
309
310/**
311 * @}
312 */
313
314/** @addtogroup ETH_Private_Defines
315 * @{
316 */
317/* Delay to wait when writing to some Ethernet registers */
318#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
319
320/* ETHERNET Errors */
321#define ETH_SUCCESS ((uint32_t)0)
322#define ETH_ERROR ((uint32_t)1)
323
324/* ETHERNET DMA Tx descriptors Collision Count Shift */
325#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
326
327/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
328#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
329
330/* ETHERNET DMA Rx descriptors Frame Length Shift */
331#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
332
333/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
334#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
335
336/* ETHERNET DMA Rx descriptors Frame length Shift */
337#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
338
339/* ETHERNET MAC address offsets */
340#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
341#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
342
343/* ETHERNET MACMIIAR register Mask */
344#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
345
346/* ETHERNET MACCR register Mask */
347#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
348
349/* ETHERNET MACFCR register Mask */
350#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
351
352/* ETHERNET DMAOMR register Mask */
353#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
354
355/* ETHERNET Remote Wake-up frame register length */
356#define ETH_WAKEUP_REGISTER_LENGTH 8
357
358/* ETHERNET Missed frames counter Shift */
359#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
360 /**
361 * @}
362 */
363
364/* Exported types ------------------------------------------------------------*/
365/** @defgroup ETH_Exported_Types ETH Exported Types
366 * @{
367 */
368
369/**
370 * @brief HAL State structures definition
371 */
372typedef enum
373{
374 HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */
375 HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
376 HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
377 HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
378 HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
379 HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
380 HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */
381 HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */
382 HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */
383 HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
384}HAL_ETH_StateTypeDef;
385
386/**
387 * @brief ETH Init Structure definition
388 */
389
390typedef struct
391{
392 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
393 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
394 and the mode (half/full-duplex).
395 This parameter can be a value of @ref ETH_AutoNegotiation */
396
397 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
398 This parameter can be a value of @ref ETH_Speed */
399
400 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
401 This parameter can be a value of @ref ETH_Duplex_Mode */
402
403 uint16_t PhyAddress; /*!< Ethernet PHY address.
404 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
405
406 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
407
408 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
409 This parameter can be a value of @ref ETH_Rx_Mode */
410
411 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
412 This parameter can be a value of @ref ETH_Checksum_Mode */
413
414 uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
415 This parameter can be a value of @ref ETH_Media_Interface */
416
417} ETH_InitTypeDef;
418
419
420 /**
421 * @brief ETH MAC Configuration Structure definition
422 */
423
424typedef struct
425{
426 uint32_t Watchdog; /*!< Selects or not the Watchdog timer
427 When enabled, the MAC allows no more then 2048 bytes to be received.
428 When disabled, the MAC can receive up to 16384 bytes.
429 This parameter can be a value of @ref ETH_Watchdog */
430
431 uint32_t Jabber; /*!< Selects or not Jabber timer
432 When enabled, the MAC allows no more then 2048 bytes to be sent.
433 When disabled, the MAC can send up to 16384 bytes.
434 This parameter can be a value of @ref ETH_Jabber */
435
436 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
437 This parameter can be a value of @ref ETH_Inter_Frame_Gap */
438
439 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
440 This parameter can be a value of @ref ETH_Carrier_Sense */
441
442 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
443 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
444 in Half-Duplex mode.
445 This parameter can be a value of @ref ETH_Receive_Own */
446
447 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
448 This parameter can be a value of @ref ETH_Loop_Back_Mode */
449
450 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
451 This parameter can be a value of @ref ETH_Checksum_Offload */
452
453 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
454 when a collision occurs (Half-Duplex mode).
455 This parameter can be a value of @ref ETH_Retry_Transmission */
456
457 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
458 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
459
460 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
461 This parameter can be a value of @ref ETH_Back_Off_Limit */
462
463 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
464 This parameter can be a value of @ref ETH_Deferral_Check */
465
466 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
467 This parameter can be a value of @ref ETH_Receive_All */
468
469 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
470 This parameter can be a value of @ref ETH_Source_Addr_Filter */
471
472 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
473 This parameter can be a value of @ref ETH_Pass_Control_Frames */
474
475 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
476 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
477
478 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
479 This parameter can be a value of @ref ETH_Destination_Addr_Filter */
480
481 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
482 This parameter can be a value of @ref ETH_Promiscuous_Mode */
483
484 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
485 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
486
487 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
488 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
489
490 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
491 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
492
493 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
494 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
495
496 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
497 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
498
499 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
500 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
501
502 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
503 automatic retransmission of PAUSE Frame.
504 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
505
506 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
507 unicast address and unique multicast address).
508 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
509
510 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
511 disable its transmitter for a specified time (Pause Time)
512 This parameter can be a value of @ref ETH_Receive_Flow_Control */
513
514 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
515 or the MAC back-pressure operation (Half-Duplex mode)
516 This parameter can be a value of @ref ETH_Transmit_Flow_Control */
517
518 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
519 comparison and filtering.
520 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
521
522 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
523
524} ETH_MACInitTypeDef;
525
526
527/**
528 * @brief ETH DMA Configuration Structure definition
529 */
530
531typedef struct
532{
533 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
534 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
535
536 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
537 This parameter can be a value of @ref ETH_Receive_Store_Forward */
538
539 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
540 This parameter can be a value of @ref ETH_Flush_Received_Frame */
541
542 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
543 This parameter can be a value of @ref ETH_Transmit_Store_Forward */
544
545 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
546 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
547
548 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
549 This parameter can be a value of @ref ETH_Forward_Error_Frames */
550
551 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
552 and length less than 64 bytes) including pad-bytes and CRC)
553 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
554
555 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
556 This parameter can be a value of @ref ETH_Receive_Threshold_Control */
557
558 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
559 frame of Transmit data even before obtaining the status for the first frame.
560 This parameter can be a value of @ref ETH_Second_Frame_Operate */
561
562 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
563 This parameter can be a value of @ref ETH_Address_Aligned_Beats */
564
565 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
566 This parameter can be a value of @ref ETH_Fixed_Burst */
567
568 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
569 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
570
571 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
572 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
573
574 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
575 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
576
577 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
578 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
579
580 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
581 This parameter can be a value of @ref ETH_DMA_Arbitration */
582} ETH_DMAInitTypeDef;
583
584
585/**
586 * @brief ETH DMA Descriptors data structure definition
587 */
588
589typedef struct
590{
591 __IO uint32_t Status; /*!< Status */
592
593 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
594
595 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
596
597 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
598
599 /*!< Enhanced ETHERNET DMA PTP Descriptors */
600 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
601
602 uint32_t Reserved1; /*!< Reserved */
603
604 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
605
606 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
607
608} ETH_DMADescTypeDef;
609
610
611/**
612 * @brief Received Frame Informations structure definition
613 */
614typedef struct
615{
616 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
617
618 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
619
620 uint32_t SegCount; /*!< Segment count */
621
622 uint32_t length; /*!< Frame length */
623
624 uint32_t buffer; /*!< Frame buffer */
625
626} ETH_DMARxFrameInfos;
627
628
629/**
630 * @brief ETH Handle Structure definition
631 */
632
633typedef struct
634{
635 ETH_TypeDef *Instance; /*!< Register base address */
636
637 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
638
639 uint32_t LinkStatus; /*!< Ethernet link status */
640
641 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
642
643 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
644
645 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
646
647 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
648
649 HAL_LockTypeDef Lock; /*!< ETH Lock */
650
651} ETH_HandleTypeDef;
652
653 /**
654 * @}
655 */
656
657/* Exported constants --------------------------------------------------------*/
658/** @defgroup ETH_Exported_Constants ETH Exported Constants
659 * @{
660 */
661
662/** @defgroup ETH_Buffers_setting ETH Buffers setting
663 * @{
664 */
665#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
666#define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
667#define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */
668#define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */
669#define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
670#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
671#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
672#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
673
674 /* Ethernet driver receive buffers are organized in a chained linked-list, when
675 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
676 to the driver receive buffers memory.
677
678 Depending on the size of the received ethernet packet and the size of
679 each ethernet driver receive buffer, the received packet can take one or more
680 ethernet driver receive buffer.
681
682 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
683 and the total count of the driver receive buffers ETH_RXBUFNB.
684
685 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
686 example, they can be reconfigured in the application layer to fit the application
687 needs */
688
689/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
690 packet */
691#ifndef ETH_RX_BUF_SIZE
692 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
693#endif
694
695/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
696#ifndef ETH_RXBUFNB
697 #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
698#endif
699
700
701 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
702 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
703 driver transmit buffers memory to the TxFIFO.
704
705 Depending on the size of the Ethernet packet to be transmitted and the size of
706 each ethernet driver transmit buffer, the packet to be transmitted can take
707 one or more ethernet driver transmit buffer.
708
709 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
710 and the total count of the driver transmit buffers ETH_TXBUFNB.
711
712 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
713 example, they can be reconfigured in the application layer to fit the application
714 needs */
715
716/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
717 packet */
718#ifndef ETH_TX_BUF_SIZE
719 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
720#endif
721
722/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
723#ifndef ETH_TXBUFNB
724 #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
725#endif
726
727 /**
728 * @}
729 */
730
731/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
732 * @{
733 */
734
735/*
736 DMA Tx Descriptor
737 -----------------------------------------------------------------------------------------------
738 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
739 -----------------------------------------------------------------------------------------------
740 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
741 -----------------------------------------------------------------------------------------------
742 TDES2 | Buffer1 Address [31:0] |
743 -----------------------------------------------------------------------------------------------
744 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
745 -----------------------------------------------------------------------------------------------
746*/
747
748/**
749 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
750 */
751#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
752#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
753#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */
754#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */
755#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */
756#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */
757#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
758#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
759#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
760#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
761#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
762#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
763#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
764#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
765#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
766#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
767#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
768#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
769#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
770#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
771#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */
772#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */
773#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
774#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
775#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
776#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */
777#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
778#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
779#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
780
781/**
782 * @brief Bit definition of TDES1 register
783 */
784#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
785#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
786
787/**
788 * @brief Bit definition of TDES2 register
789 */
790#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
791
792/**
793 * @brief Bit definition of TDES3 register
794 */
795#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
796
797 /*---------------------------------------------------------------------------------------------
798 TDES6 | Transmit Time Stamp Low [31:0] |
799 -----------------------------------------------------------------------------------------------
800 TDES7 | Transmit Time Stamp High [31:0] |
801 ----------------------------------------------------------------------------------------------*/
802
803/* Bit definition of TDES6 register */
804 #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
805
806/* Bit definition of TDES7 register */
807 #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
808
809/**
810 * @}
811 */
812/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
813 * @{
814 */
815
816/*
817 DMA Rx Descriptor
818 --------------------------------------------------------------------------------------------------------------------
819 RDES0 | OWN(31) | Status [30:0] |
820 ---------------------------------------------------------------------------------------------------------------------
821 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
822 ---------------------------------------------------------------------------------------------------------------------
823 RDES2 | Buffer1 Address [31:0] |
824 ---------------------------------------------------------------------------------------------------------------------
825 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
826 ---------------------------------------------------------------------------------------------------------------------
827*/
828
829/**
830 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
831 */
832#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
833#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
834#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
835#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
836#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */
837#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
838#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
839#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
840#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
841#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
842#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
843#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
844#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
845#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
846#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
847#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
848#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
849#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */
850#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
851
852/**
853 * @brief Bit definition of RDES1 register
854 */
855#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
856#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
857#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
858#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
859#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
860
861/**
862 * @brief Bit definition of RDES2 register
863 */
864#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
865
866/**
867 * @brief Bit definition of RDES3 register
868 */
869#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
870
871/*---------------------------------------------------------------------------------------------------------------------
872 RDES4 | Reserved[31:15] | Extended Status [14:0] |
873 ---------------------------------------------------------------------------------------------------------------------
874 RDES5 | Reserved[31:0] |
875 ---------------------------------------------------------------------------------------------------------------------
876 RDES6 | Receive Time Stamp Low [31:0] |
877 ---------------------------------------------------------------------------------------------------------------------
878 RDES7 | Receive Time Stamp High [31:0] |
879 --------------------------------------------------------------------------------------------------------------------*/
880
881/* Bit definition of RDES4 register */
882#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
883#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
884#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
885 #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
886 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
887 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
888 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
889 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
890 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
891 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
892#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
893#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
894#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
895#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
896#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
897#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
898 #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
899 #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
900 #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
901
902/* Bit definition of RDES6 register */
903#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
904
905/* Bit definition of RDES7 register */
906#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
907/**
908 * @}
909 */
910 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
911 * @{
912 */
913#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
914#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
915
916/**
917 * @}
918 */
919/** @defgroup ETH_Speed ETH Speed
920 * @{
921 */
922#define ETH_SPEED_10M ((uint32_t)0x00000000)
923#define ETH_SPEED_100M ((uint32_t)0x00004000)
924
925/**
926 * @}
927 */
928/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
929 * @{
930 */
931#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
932#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
933/**
934 * @}
935 */
936/** @defgroup ETH_Rx_Mode ETH Rx Mode
937 * @{
938 */
939#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
940#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
941/**
942 * @}
943 */
944
945/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
946 * @{
947 */
948#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
949#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
950/**
951 * @}
952 */
953
954/** @defgroup ETH_Media_Interface ETH Media Interface
955 * @{
956 */
957#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
958#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
959/**
960 * @}
961 */
962
963/** @defgroup ETH_Watchdog ETH Watchdog
964 * @{
965 */
966#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
967#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
968/**
969 * @}
970 */
971
972/** @defgroup ETH_Jabber ETH Jabber
973 * @{
974 */
975#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
976#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
977/**
978 * @}
979 */
980
981/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
982 * @{
983 */
984#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
985#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
986#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
987#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
988#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
989#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
990#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
991#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
992/**
993 * @}
994 */
995
996/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
997 * @{
998 */
999#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
1000#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
1001/**
1002 * @}
1003 */
1004
1005/** @defgroup ETH_Receive_Own ETH Receive Own
1006 * @{
1007 */
1008#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
1009#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
1010/**
1011 * @}
1012 */
1013
1014/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
1015 * @{
1016 */
1017#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
1018#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
1019/**
1020 * @}
1021 */
1022
1023/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
1024 * @{
1025 */
1026#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
1027#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
1028/**
1029 * @}
1030 */
1031
1032/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
1033 * @{
1034 */
1035#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
1036#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
1037/**
1038 * @}
1039 */
1040
1041/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
1042 * @{
1043 */
1044#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
1045#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
1046/**
1047 * @}
1048 */
1049
1050/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
1051 * @{
1052 */
1053#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
1054#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
1055#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
1056#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
1057/**
1058 * @}
1059 */
1060
1061/** @defgroup ETH_Deferral_Check ETH Deferral Check
1062 * @{
1063 */
1064#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
1065#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
1066/**
1067 * @}
1068 */
1069
1070/** @defgroup ETH_Receive_All ETH Receive All
1071 * @{
1072 */
1073#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
1074#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
1075/**
1076 * @}
1077 */
1078
1079/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
1080 * @{
1081 */
1082#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
1083#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
1084#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
1085/**
1086 * @}
1087 */
1088
1089/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
1090 * @{
1091 */
1092#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
1093#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
1094#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
1095/**
1096 * @}
1097 */
1098
1099/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
1100 * @{
1101 */
1102#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
1103#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
1104/**
1105 * @}
1106 */
1107
1108/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
1109 * @{
1110 */
1111#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
1112#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
1113/**
1114 * @}
1115 */
1116
1117/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
1118 * @{
1119 */
1120#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
1121#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
1122/**
1123 * @}
1124 */
1125
1126/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
1127 * @{
1128 */
1129#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
1130#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
1131#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
1132#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
1133/**
1134 * @}
1135 */
1136
1137/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
1138 * @{
1139 */
1140#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
1141#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
1142#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
1143/**
1144 * @}
1145 */
1146
1147/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
1148 * @{
1149 */
1150#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
1151#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
1152/**
1153 * @}
1154 */
1155
1156/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
1157 * @{
1158 */
1159#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
1160#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
1161#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
1162#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
1163/**
1164 * @}
1165 */
1166
1167/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
1168 * @{
1169 */
1170#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
1171#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
1172/**
1173 * @}
1174 */
1175
1176/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
1177 * @{
1178 */
1179#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
1180#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
1181/**
1182 * @}
1183 */
1184
1185/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
1186 * @{
1187 */
1188#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
1189#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
1190/**
1191 * @}
1192 */
1193
1194/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
1195 * @{
1196 */
1197#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
1198#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
1199/**
1200 * @}
1201 */
1202
1203/** @defgroup ETH_MAC_addresses ETH MAC addresses
1204 * @{
1205 */
1206#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
1207#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
1208#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
1209#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
1210/**
1211 * @}
1212 */
1213
1214/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
1215 * @{
1216 */
1217#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
1218#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
1219/**
1220 * @}
1221 */
1222
1223/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
1224 * @{
1225 */
1226#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
1227#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
1228#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
1229#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
1230#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
1231#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
1232/**
1233 * @}
1234 */
1235
1236/** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags
1237 * @{
1238 */
1239#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
1240#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
1241#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
1242#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
1243#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
1244#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
1245#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
1246#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
1247#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
1248#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
1249#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
1250#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
1251#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
1252#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
1253#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
1254#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
1255#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
1256#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
1257#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
1258#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
1259#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
1260#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
1261#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
1262#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
1263#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
1264#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
1265#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
1266/**
1267 * @}
1268 */
1269
1270/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
1271 * @{
1272 */
1273#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
1274#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
1275/**
1276 * @}
1277 */
1278
1279/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
1280 * @{
1281 */
1282#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
1283#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
1284/**
1285 * @}
1286 */
1287
1288/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
1289 * @{
1290 */
1291#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
1292#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
1293/**
1294 * @}
1295 */
1296
1297/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
1298 * @{
1299 */
1300#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
1301#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
1302/**
1303 * @}
1304 */
1305
1306/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
1307 * @{
1308 */
1309#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
1310#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
1311#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
1312#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
1313#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
1314#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
1315#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
1316#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
1317/**
1318 * @}
1319 */
1320
1321/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
1322 * @{
1323 */
1324#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
1325#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
1326/**
1327 * @}
1328 */
1329
1330/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
1331 * @{
1332 */
1333#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
1334#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
1335/**
1336 * @}
1337 */
1338
1339/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
1340 * @{
1341 */
1342#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
1343#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
1344#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
1345#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
1346/**
1347 * @}
1348 */
1349
1350/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
1351 * @{
1352 */
1353#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
1354#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
1355/**
1356 * @}
1357 */
1358
1359/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
1360 * @{
1361 */
1362#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
1363#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
1364/**
1365 * @}
1366 */
1367
1368/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
1369 * @{
1370 */
1371#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
1372#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
1373/**
1374 * @}
1375 */
1376
1377/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
1378 * @{
1379 */
1380#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
1381#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
1382#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
1383#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
1384#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
1385#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
1386#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
1387#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
1388#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
1389#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
1390#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
1391#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
1392/**
1393 * @}
1394 */
1395
1396/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
1397 * @{
1398 */
1399#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
1400#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
1401#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
1402#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
1403#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
1404#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
1405#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
1406#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
1407#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
1408#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
1409#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
1410#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
1411/**
1412 * @}
1413 */
1414
1415/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
1416 * @{
1417 */
1418#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
1419#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
1420/**
1421 * @}
1422 */
1423
1424/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
1425 * @{
1426 */
1427#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
1428#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
1429#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
1430#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
1431#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
1432/**
1433 * @}
1434 */
1435
1436/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
1437 * @{
1438 */
1439#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
1440#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
1441/**
1442 * @}
1443 */
1444
1445/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
1446 * @{
1447 */
1448#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */
1449#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
1450#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
1451#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
1452/**
1453 * @}
1454 */
1455
1456/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
1457 * @{
1458 */
1459#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
1460#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
1461/**
1462 * @}
1463 */
1464
1465/** @defgroup ETH_PMT_Flags ETH PMT Flags
1466 * @{
1467 */
1468#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
1469#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
1470#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
1471/**
1472 * @}
1473 */
1474
1475/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
1476 * @{
1477 */
1478#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
1479#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
1480#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
1481/**
1482 * @}
1483 */
1484
1485/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
1486 * @{
1487 */
1488#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
1489#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
1490#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
1491/**
1492 * @}
1493 */
1494
1495/** @defgroup ETH_MAC_Flags ETH MAC Flags
1496 * @{
1497 */
1498#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
1499#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
1500#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
1501#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
1502#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
1503/**
1504 * @}
1505 */
1506
1507/** @defgroup ETH_DMA_Flags ETH DMA Flags
1508 * @{
1509 */
1510#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
1511#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
1512#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
1513#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
1514#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write transfer, 1-read transfer */
1515#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
1516#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
1517#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
1518#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
1519#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
1520#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
1521#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
1522#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
1523#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
1524#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
1525#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
1526#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
1527#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
1528#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
1529#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
1530#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
1531/**
1532 * @}
1533 */
1534
1535/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
1536 * @{
1537 */
1538#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
1539#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
1540#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
1541#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
1542#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
1543/**
1544 * @}
1545 */
1546
1547/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
1548 * @{
1549 */
1550#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
1551#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
1552#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
1553#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
1554#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
1555#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
1556#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
1557#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
1558#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
1559#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
1560#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
1561#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
1562#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
1563#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
1564#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
1565#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
1566#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
1567#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
1568/**
1569 * @}
1570 */
1571
1572/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
1573 * @{
1574 */
1575#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
1576#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
1577#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */
1578#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
1579#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */
1580#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
1581
1582/**
1583 * @}
1584 */
1585
1586
1587/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
1588 * @{
1589 */
1590#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
1591#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
1592#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */
1593#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */
1594#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
1595#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */
1596
1597/**
1598 * @}
1599 */
1600
1601/** @defgroup ETH_DMA_overflow ETH DMA overflow
1602 * @{
1603 */
1604#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
1605#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
1606/**
1607 * @}
1608 */
1609
1610/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
1611 * @{
1612 */
1613#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
1614
1615/**
1616 * @}
1617 */
1618
1619/**
1620 * @}
1621 */
1622
1623/* Exported macro ------------------------------------------------------------*/
1624/** @defgroup ETH_Exported_Macros ETH Exported Macros
1625 * @brief macros to handle interrupts and specific clock configurations
1626 * @{
1627 */
1628
1629/** @brief Reset ETH handle state
1630 * @param __HANDLE__: specifies the ETH handle.
1631 * @retval None
1632 */
1633#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
1634
1635/**
1636 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
1637 * @param __HANDLE__: ETH Handle
1638 * @param __FLAG__: specifies the flag of TDES0 to check.
1639 * @retval the ETH_DMATxDescFlag (SET or RESET).
1640 */
1641#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
1642
1643/**
1644 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
1645 * @param __HANDLE__: ETH Handle
1646 * @param __FLAG__: specifies the flag of RDES0 to check.
1647 * @retval the ETH_DMATxDescFlag (SET or RESET).
1648 */
1649#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
1650
1651/**
1652 * @brief Enables the specified DMA Rx Desc receive interrupt.
1653 * @param __HANDLE__: ETH Handle
1654 * @retval None
1655 */
1656#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
1657
1658/**
1659 * @brief Disables the specified DMA Rx Desc receive interrupt.
1660 * @param __HANDLE__: ETH Handle
1661 * @retval None
1662 */
1663#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
1664
1665/**
1666 * @brief Set the specified DMA Rx Desc Own bit.
1667 * @param __HANDLE__: ETH Handle
1668 * @retval None
1669 */
1670#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
1671
1672/**
1673 * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
1674 * @param __HANDLE__: ETH Handle
1675 * @retval The Transmit descriptor collision counter value.
1676 */
1677#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
1678
1679/**
1680 * @brief Set the specified DMA Tx Desc Own bit.
1681 * @param __HANDLE__: ETH Handle
1682 * @retval None
1683 */
1684#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
1685
1686/**
1687 * @brief Enables the specified DMA Tx Desc Transmit interrupt.
1688 * @param __HANDLE__: ETH Handle
1689 * @retval None
1690 */
1691#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
1692
1693/**
1694 * @brief Disables the specified DMA Tx Desc Transmit interrupt.
1695 * @param __HANDLE__: ETH Handle
1696 * @retval None
1697 */
1698#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
1699
1700/**
1701 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
1702 * @param __HANDLE__: ETH Handle
1703 * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
1704 * This parameter can be one of the following values:
1705 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
1706 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
1707 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
1708 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
1709 * @retval None
1710 */
1711#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
1712
1713/**
1714 * @brief Enables the DMA Tx Desc CRC.
1715 * @param __HANDLE__: ETH Handle
1716 * @retval None
1717 */
1718#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
1719
1720/**
1721 * @brief Disables the DMA Tx Desc CRC.
1722 * @param __HANDLE__: ETH Handle
1723 * @retval None
1724 */
1725#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
1726
1727/**
1728 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
1729 * @param __HANDLE__: ETH Handle
1730 * @retval None
1731 */
1732#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
1733
1734/**
1735 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
1736 * @param __HANDLE__: ETH Handle
1737 * @retval None
1738 */
1739#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
1740
1741/**
1742 * @brief Enables the specified ETHERNET MAC interrupts.
1743 * @param __HANDLE__ : ETH Handle
1744 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1745 * enabled or disabled.
1746 * This parameter can be any combination of the following values:
1747 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
1748 * @arg ETH_MAC_IT_PMT : PMT interrupt
1749 * @retval None
1750 */
1751#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
1752
1753/**
1754 * @brief Disables the specified ETHERNET MAC interrupts.
1755 * @param __HANDLE__ : ETH Handle
1756 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1757 * enabled or disabled.
1758 * This parameter can be any combination of the following values:
1759 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
1760 * @arg ETH_MAC_IT_PMT : PMT interrupt
1761 * @retval None
1762 */
1763#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
1764
1765/**
1766 * @brief Initiate a Pause Control Frame (Full-duplex only).
1767 * @param __HANDLE__: ETH Handle
1768 * @retval None
1769 */
1770#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1771
1772/**
1773 * @brief Checks whether the ETHERNET flow control busy bit is set or not.
1774 * @param __HANDLE__: ETH Handle
1775 * @retval The new state of flow control busy status bit (SET or RESET).
1776 */
1777#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
1778
1779/**
1780 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
1781 * @param __HANDLE__: ETH Handle
1782 * @retval None
1783 */
1784#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1785
1786/**
1787 * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
1788 * @param __HANDLE__: ETH Handle
1789 * @retval None
1790 */
1791#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
1792
1793/**
1794 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
1795 * @param __HANDLE__: ETH Handle
1796 * @param __FLAG__: specifies the flag to check.
1797 * This parameter can be one of the following values:
1798 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
1799 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
1800 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
1801 * @arg ETH_MAC_FLAG_MMC : MMC flag
1802 * @arg ETH_MAC_FLAG_PMT : PMT flag
1803 * @retval The state of ETHERNET MAC flag.
1804 */
1805#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
1806
1807/**
1808 * @brief Enables the specified ETHERNET DMA interrupts.
1809 * @param __HANDLE__ : ETH Handle
1810 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1811 * enabled @ref ETH_DMA_Interrupts
1812 * @retval None
1813 */
1814#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
1815
1816/**
1817 * @brief Disables the specified ETHERNET DMA interrupts.
1818 * @param __HANDLE__ : ETH Handle
1819 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1820 * disabled. @ref ETH_DMA_Interrupts
1821 * @retval None
1822 */
1823#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
1824
1825/**
1826 * @brief Clears the ETHERNET DMA IT pending bit.
1827 * @param __HANDLE__ : ETH Handle
1828 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
1829 * @retval None
1830 */
1831#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
1832
1833/**
1834 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
1835* @param __HANDLE__: ETH Handle
1836 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
1837 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
1838 */
1839#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
1840
1841/**
1842 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
1843 * @param __HANDLE__: ETH Handle
1844 * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
1845 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
1846 */
1847#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
1848
1849/**
1850 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
1851 * @param __HANDLE__: ETH Handle
1852 * @param __OVERFLOW__: specifies the DMA overflow flag to check.
1853 * This parameter can be one of the following values:
1854 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
1855 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
1856 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
1857 */
1858#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
1859
1860/**
1861 * @brief Set the DMA Receive status watchdog timer register value
1862 * @param __HANDLE__: ETH Handle
1863 * @param __VALUE__: DMA Receive status watchdog timer register value
1864 * @retval None
1865 */
1866#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
1867
1868/**
1869 * @brief Enables any unicast packet filtered by the MAC address
1870 * recognition to be a wake-up frame.
1871 * @param __HANDLE__: ETH Handle.
1872 * @retval None
1873 */
1874#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
1875
1876/**
1877 * @brief Disables any unicast packet filtered by the MAC address
1878 * recognition to be a wake-up frame.
1879 * @param __HANDLE__: ETH Handle.
1880 * @retval None
1881 */
1882#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
1883
1884/**
1885 * @brief Enables the MAC Wake-Up Frame Detection.
1886 * @param __HANDLE__: ETH Handle.
1887 * @retval None
1888 */
1889#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
1890
1891/**
1892 * @brief Disables the MAC Wake-Up Frame Detection.
1893 * @param __HANDLE__: ETH Handle.
1894 * @retval None
1895 */
1896#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1897
1898/**
1899 * @brief Enables the MAC Magic Packet Detection.
1900 * @param __HANDLE__: ETH Handle.
1901 * @retval None
1902 */
1903#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
1904
1905/**
1906 * @brief Disables the MAC Magic Packet Detection.
1907 * @param __HANDLE__: ETH Handle.
1908 * @retval None
1909 */
1910#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1911
1912/**
1913 * @brief Enables the MAC Power Down.
1914 * @param __HANDLE__: ETH Handle
1915 * @retval None
1916 */
1917#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
1918
1919/**
1920 * @brief Disables the MAC Power Down.
1921 * @param __HANDLE__: ETH Handle
1922 * @retval None
1923 */
1924#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
1925
1926/**
1927 * @brief Checks whether the specified ETHERNET PMT flag is set or not.
1928 * @param __HANDLE__: ETH Handle.
1929 * @param __FLAG__: specifies the flag to check.
1930 * This parameter can be one of the following values:
1931 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
1932 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
1933 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
1934 * @retval The new state of ETHERNET PMT Flag (SET or RESET).
1935 */
1936#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
1937
1938/**
1939 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
1940 * @param __HANDLE__: ETH Handle.
1941 * @retval None
1942 */
1943#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
1944
1945/**
1946 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
1947 * @param __HANDLE__: ETH Handle.
1948 * @retval None
1949 */
1950#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
1951 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
1952
1953/**
1954 * @brief Enables the MMC Counter Freeze.
1955 * @param __HANDLE__: ETH Handle.
1956 * @retval None
1957 */
1958#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
1959
1960/**
1961 * @brief Disables the MMC Counter Freeze.
1962 * @param __HANDLE__: ETH Handle.
1963 * @retval None
1964 */
1965#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
1966
1967/**
1968 * @brief Enables the MMC Reset On Read.
1969 * @param __HANDLE__: ETH Handle.
1970 * @retval None
1971 */
1972#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
1973
1974/**
1975 * @brief Disables the MMC Reset On Read.
1976 * @param __HANDLE__: ETH Handle.
1977 * @retval None
1978 */
1979#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
1980
1981/**
1982 * @brief Enables the MMC Counter Stop Rollover.
1983 * @param __HANDLE__: ETH Handle.
1984 * @retval None
1985 */
1986#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
1987
1988/**
1989 * @brief Disables the MMC Counter Stop Rollover.
1990 * @param __HANDLE__: ETH Handle.
1991 * @retval None
1992 */
1993#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
1994
1995/**
1996 * @brief Resets the MMC Counters.
1997 * @param __HANDLE__: ETH Handle.
1998 * @retval None
1999 */
2000#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
2001
2002/**
2003 * @brief Enables the specified ETHERNET MMC Rx interrupts.
2004 * @param __HANDLE__: ETH Handle.
2005 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
2006 * This parameter can be one of the following values:
2007 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
2008 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
2009 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
2010 * @retval None
2011 */
2012#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
2013/**
2014 * @brief Disables the specified ETHERNET MMC Rx interrupts.
2015 * @param __HANDLE__: ETH Handle.
2016 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
2017 * This parameter can be one of the following values:
2018 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
2019 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
2020 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
2021 * @retval None
2022 */
2023#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
2024/**
2025 * @brief Enables the specified ETHERNET MMC Tx interrupts.
2026 * @param __HANDLE__: ETH Handle.
2027 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
2028 * This parameter can be one of the following values:
2029 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
2030 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
2031 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
2032 * @retval None
2033 */
2034#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
2035
2036/**
2037 * @brief Disables the specified ETHERNET MMC Tx interrupts.
2038 * @param __HANDLE__: ETH Handle.
2039 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
2040 * This parameter can be one of the following values:
2041 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
2042 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
2043 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
2044 * @retval None
2045 */
2046#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
2047
2048/**
2049 * @brief Enables the ETH External interrupt line.
2050 * @retval None
2051 */
2052#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
2053
2054/**
2055 * @brief Disables the ETH External interrupt line.
2056 * @retval None
2057 */
2058#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
2059
2060/**
2061 * @brief Enable event on ETH External event line.
2062 * @retval None.
2063 */
2064#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
2065
2066/**
2067 * @brief Disable event on ETH External event line
2068 * @retval None.
2069 */
2070#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
2071
2072/**
2073 * @brief Get flag of the ETH External interrupt line.
2074 * @retval None
2075 */
2076#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
2077
2078/**
2079 * @brief Clear flag of the ETH External interrupt line.
2080 * @retval None
2081 */
2082#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
2083
2084/**
2085 * @brief Enables rising edge trigger to the ETH External interrupt line.
2086 * @retval None
2087 */
2088#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
2089
2090/**
2091 * @brief Disables the rising edge trigger to the ETH External interrupt line.
2092 * @retval None
2093 */
2094#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2095
2096/**
2097 * @brief Enables falling edge trigger to the ETH External interrupt line.
2098 * @retval None
2099 */
2100#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
2101
2102/**
2103 * @brief Disables falling edge trigger to the ETH External interrupt line.
2104 * @retval None
2105 */
2106#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2107
2108/**
2109 * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
2110 * @retval None
2111 */
2112#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
2113 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
2114
2115/**
2116 * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
2117 * @retval None
2118 */
2119#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
2120 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2121
2122/**
2123 * @brief Generate a Software interrupt on selected EXTI line.
2124 * @retval None.
2125 */
2126#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
2127
2128/**
2129 * @}
2130 */
2131/* Exported functions --------------------------------------------------------*/
2132
2133/** @addtogroup ETH_Exported_Functions
2134 * @{
2135 */
2136
2137/* Initialization and de-initialization functions ****************************/
2138
2139/** @addtogroup ETH_Exported_Functions_Group1
2140 * @{
2141 */
2142HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
2143HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
2144void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
2145void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
2146HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
2147HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
2148
2149/**
2150 * @}
2151 */
2152/* IO operation functions ****************************************************/
2153
2154/** @addtogroup ETH_Exported_Functions_Group2
2155 * @{
2156 */
2157HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
2158HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
2159/* Communication with PHY functions*/
2160HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
2161HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
2162/* Non-Blocking mode: Interrupt */
2163HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
2164void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
2165/* Callback in non blocking modes (Interrupt) */
2166void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
2167void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
2168void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
2169/**
2170 * @}
2171 */
2172
2173/* Peripheral Control functions **********************************************/
2174
2175/** @addtogroup ETH_Exported_Functions_Group3
2176 * @{
2177 */
2178
2179HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
2180HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
2181HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
2182HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
2183/**
2184 * @}
2185 */
2186
2187/* Peripheral State functions ************************************************/
2188
2189/** @addtogroup ETH_Exported_Functions_Group4
2190 * @{
2191 */
2192HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
2193/**
2194 * @}
2195 */
2196
2197/**
2198 * @}
2199 */
2200
2201/**
2202 * @}
2203 */
2204
2205/**
2206 * @}
2207 */
2208
2209#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
2210 STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
2211
2212#ifdef __cplusplus
2213}
2214#endif
2215
2216#endif /* __STM32F4xx_HAL_ETH_H */
2217
2218
2219/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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