source: asp3_wo_tecs/trunk/arch/arm_m_gcc/stm32f4xx_stm32cube/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h@ 303

Last change on this file since 303 was 303, checked in by ertl-honda, 7 years ago

nucleo_f401re依存部の追加
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1/**
2 ******************************************************************************
3 * @file stm32f4xx_hal_dma.h
4 * @author MCD Application Team
5 * @version V1.4.1
6 * @date 09-October-2015
7 * @brief Header file of DMA HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38/* Define to prevent recursive inclusion -------------------------------------*/
39#ifndef __STM32F4xx_HAL_DMA_H
40#define __STM32F4xx_HAL_DMA_H
41
42#ifdef __cplusplus
43 extern "C" {
44#endif
45
46/* Includes ------------------------------------------------------------------*/
47#include "stm32f4xx_hal_def.h"
48
49/** @addtogroup STM32F4xx_HAL_Driver
50 * @{
51 */
52
53/** @addtogroup DMA
54 * @{
55 */
56
57/* Exported types ------------------------------------------------------------*/
58
59/** @defgroup DMA_Exported_Types DMA Exported Types
60 * @brief DMA Exported Types
61 * @{
62 */
63
64/**
65 * @brief DMA Configuration Structure definition
66 */
67typedef struct
68{
69 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
70 This parameter can be a value of @ref DMA_Channel_selection */
71
72 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
73 from memory to memory or from peripheral to memory.
74 This parameter can be a value of @ref DMA_Data_transfer_direction */
75
76 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
77 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
78
79 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
80 This parameter can be a value of @ref DMA_Memory_incremented_mode */
81
82 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
83 This parameter can be a value of @ref DMA_Peripheral_data_size */
84
85 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
86 This parameter can be a value of @ref DMA_Memory_data_size */
87
88 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
89 This parameter can be a value of @ref DMA_mode
90 @note The circular buffer mode cannot be used if the memory-to-memory
91 data transfer is configured on the selected Stream */
92
93 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
94 This parameter can be a value of @ref DMA_Priority_level */
95
96 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
97 This parameter can be a value of @ref DMA_FIFO_direct_mode
98 @note The Direct mode (FIFO mode disabled) cannot be used if the
99 memory-to-memory data transfer is configured on the selected stream */
100
101 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
102 This parameter can be a value of @ref DMA_FIFO_threshold_level */
103
104 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
105 It specifies the amount of data to be transferred in a single non interruptible
106 transaction.
107 This parameter can be a value of @ref DMA_Memory_burst
108 @note The burst mode is possible only if the address Increment mode is enabled. */
109
110 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
111 It specifies the amount of data to be transferred in a single non interruptable
112 transaction.
113 This parameter can be a value of @ref DMA_Peripheral_burst
114 @note The burst mode is possible only if the address Increment mode is enabled. */
115}DMA_InitTypeDef;
116
117
118/**
119 * @brief HAL DMA State structures definition
120 */
121typedef enum
122{
123 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
124 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
125 HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */
126 HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
127 HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */
128 HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
129 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
130 HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */
131 HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
132 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
133 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
134}HAL_DMA_StateTypeDef;
135
136/**
137 * @brief HAL DMA Error Code structure definition
138 */
139typedef enum
140{
141 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
142 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
143}HAL_DMA_LevelCompleteTypeDef;
144
145/**
146 * @brief DMA handle Structure definition
147 */
148typedef struct __DMA_HandleTypeDef
149{
150 DMA_Stream_TypeDef *Instance; /*!< Register base address */
151
152 DMA_InitTypeDef Init; /*!< DMA communication parameters */
153
154 HAL_LockTypeDef Lock; /*!< DMA locking object */
155
156 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
157
158 void *Parent; /*!< Parent object state */
159
160 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
161
162 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
163
164 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
165
166 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
167
168 __IO uint32_t ErrorCode; /*!< DMA Error code */
169
170 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
171
172 uint32_t StreamIndex; /*!< DMA Stream Index */
173}DMA_HandleTypeDef;
174
175/**
176 * @}
177 */
178
179/* Exported constants --------------------------------------------------------*/
180
181/** @defgroup DMA_Exported_Constants DMA Exported Constants
182 * @brief DMA Exported constants
183 * @{
184 */
185
186/** @defgroup DMA_Error_Code DMA Error Code
187 * @brief DMA Error Code
188 * @{
189 */
190#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
191#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
192#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
193#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */
194#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
195/**
196 * @}
197 */
198
199/** @defgroup DMA_Channel_selection DMA Channel selection
200 * @brief DMA channel selection
201 * @{
202 */
203#define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */
204#define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */
205#define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */
206#define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */
207#define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */
208#define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */
209#define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */
210#define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */
211/**
212 * @}
213 */
214
215/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
216 * @brief DMA data transfer direction
217 * @{
218 */
219#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
220#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
221#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
222/**
223 * @}
224 */
225
226/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
227 * @brief DMA peripheral incremented mode
228 * @{
229 */
230#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
231#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */
232/**
233 * @}
234 */
235
236/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
237 * @brief DMA memory incremented mode
238 * @{
239 */
240#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
241#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */
242/**
243 * @}
244 */
245
246/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
247 * @brief DMA peripheral data size
248 * @{
249 */
250#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
251#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
252#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
253/**
254 * @}
255 */
256
257/** @defgroup DMA_Memory_data_size DMA Memory data size
258 * @brief DMA memory data size
259 * @{
260 */
261#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
262#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
263#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
264/**
265 * @}
266 */
267
268/** @defgroup DMA_mode DMA mode
269 * @brief DMA mode
270 * @{
271 */
272#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
273#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
274#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
275/**
276 * @}
277 */
278
279/** @defgroup DMA_Priority_level DMA Priority level
280 * @brief DMA priority levels
281 * @{
282 */
283#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */
284#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
285#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
286#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
287/**
288 * @}
289 */
290
291/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
292 * @brief DMA FIFO direct mode
293 * @{
294 */
295#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */
296#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
297/**
298 * @}
299 */
300
301/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
302 * @brief DMA FIFO level
303 * @{
304 */
305#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */
306#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
307#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
308#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
309/**
310 * @}
311 */
312
313/** @defgroup DMA_Memory_burst DMA Memory burst
314 * @brief DMA memory burst
315 * @{
316 */
317#define DMA_MBURST_SINGLE ((uint32_t)0x00000000)
318#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
319#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
320#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
321/**
322 * @}
323 */
324
325/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
326 * @brief DMA peripheral burst
327 * @{
328 */
329#define DMA_PBURST_SINGLE ((uint32_t)0x00000000)
330#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
331#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
332#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
333/**
334 * @}
335 */
336
337/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
338 * @brief DMA interrupts definition
339 * @{
340 */
341#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
342#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
343#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
344#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
345#define DMA_IT_FE ((uint32_t)0x00000080)
346/**
347 * @}
348 */
349
350/** @defgroup DMA_flag_definitions DMA flag definitions
351 * @brief DMA flag definitions
352 * @{
353 */
354#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
355#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)
356#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)
357#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)
358#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)
359#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)
360#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)
361#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)
362#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)
363#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)
364#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)
365#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)
366#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)
367#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)
368#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)
369#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)
370#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)
371#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)
372#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)
373#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)
374/**
375 * @}
376 */
377
378/**
379 * @}
380 */
381
382/* Exported macro ------------------------------------------------------------*/
383
384/** @brief Reset DMA handle state
385 * @param __HANDLE__: specifies the DMA handle.
386 * @retval None
387 */
388#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
389
390/**
391 * @brief Return the current DMA Stream FIFO filled level.
392 * @param __HANDLE__: DMA handle
393 * @retval The FIFO filling state.
394 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
395 * and not empty.
396 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
397 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
398 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
399 * - DMA_FIFOStatus_Empty: when FIFO is empty
400 * - DMA_FIFOStatus_Full: when FIFO is full
401 */
402#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
403
404/**
405 * @brief Enable the specified DMA Stream.
406 * @param __HANDLE__: DMA handle
407 * @retval None
408 */
409#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
410
411/**
412 * @brief Disable the specified DMA Stream.
413 * @param __HANDLE__: DMA handle
414 * @retval None
415 */
416#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
417
418/* Interrupt & Flag management */
419
420/**
421 * @brief Return the current DMA Stream transfer complete flag.
422 * @param __HANDLE__: DMA handle
423 * @retval The specified transfer complete flag index.
424 */
425#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
426(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
427 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
428 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
429 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
430 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
431 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
432 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
433 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
434 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
435 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
436 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
437 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
438 DMA_FLAG_TCIF3_7)
439
440/**
441 * @brief Return the current DMA Stream half transfer complete flag.
442 * @param __HANDLE__: DMA handle
443 * @retval The specified half transfer complete flag index.
444 */
445#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
446(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
447 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
448 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
449 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
458 DMA_FLAG_HTIF3_7)
459
460/**
461 * @brief Return the current DMA Stream transfer error flag.
462 * @param __HANDLE__: DMA handle
463 * @retval The specified transfer error flag index.
464 */
465#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
466(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
478 DMA_FLAG_TEIF3_7)
479
480/**
481 * @brief Return the current DMA Stream FIFO error flag.
482 * @param __HANDLE__: DMA handle
483 * @retval The specified FIFO error flag index.
484 */
485#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
486(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
498 DMA_FLAG_FEIF3_7)
499
500/**
501 * @brief Return the current DMA Stream direct mode error flag.
502 * @param __HANDLE__: DMA handle
503 * @retval The specified direct mode error flag index.
504 */
505#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
506(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
518 DMA_FLAG_DMEIF3_7)
519
520/**
521 * @brief Get the DMA Stream pending flags.
522 * @param __HANDLE__: DMA handle
523 * @param __FLAG__: Get the specified flag.
524 * This parameter can be any combination of the following values:
525 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
526 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
527 * @arg DMA_FLAG_TEIFx: Transfer error flag.
528 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
529 * @arg DMA_FLAG_FEIFx: FIFO error flag.
530 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
531 * @retval The state of FLAG (SET or RESET).
532 */
533#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
534(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
535 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
536 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
537
538/**
539 * @brief Clear the DMA Stream pending flags.
540 * @param __HANDLE__: DMA handle
541 * @param __FLAG__: specifies the flag to clear.
542 * This parameter can be any combination of the following values:
543 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
544 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
545 * @arg DMA_FLAG_TEIFx: Transfer error flag.
546 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
547 * @arg DMA_FLAG_FEIFx: FIFO error flag.
548 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
549 * @retval None
550 */
551#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
552(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
553 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
554 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
555
556/**
557 * @brief Enable the specified DMA Stream interrupts.
558 * @param __HANDLE__: DMA handle
559 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
560 * This parameter can be any combination of the following values:
561 * @arg DMA_IT_TC: Transfer complete interrupt mask.
562 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
563 * @arg DMA_IT_TE: Transfer error interrupt mask.
564 * @arg DMA_IT_FE: FIFO error interrupt mask.
565 * @arg DMA_IT_DME: Direct mode error interrupt.
566 * @retval None
567 */
568#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
569((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
570
571/**
572 * @brief Disable the specified DMA Stream interrupts.
573 * @param __HANDLE__: DMA handle
574 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
575 * This parameter can be any combination of the following values:
576 * @arg DMA_IT_TC: Transfer complete interrupt mask.
577 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
578 * @arg DMA_IT_TE: Transfer error interrupt mask.
579 * @arg DMA_IT_FE: FIFO error interrupt mask.
580 * @arg DMA_IT_DME: Direct mode error interrupt.
581 * @retval None
582 */
583#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
584((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
585
586/**
587 * @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
588 * @param __HANDLE__: DMA handle
589 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
590 * This parameter can be one of the following values:
591 * @arg DMA_IT_TC: Transfer complete interrupt mask.
592 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
593 * @arg DMA_IT_TE: Transfer error interrupt mask.
594 * @arg DMA_IT_FE: FIFO error interrupt mask.
595 * @arg DMA_IT_DME: Direct mode error interrupt.
596 * @retval The state of DMA_IT.
597 */
598#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
599 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
600 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
601
602/**
603 * @brief Writes the number of data units to be transferred on the DMA Stream.
604 * @param __HANDLE__: DMA handle
605 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
606 * Number of data items depends only on the Peripheral data format.
607 *
608 * @note If Peripheral data format is Bytes: number of data units is equal
609 * to total number of bytes to be transferred.
610 *
611 * @note If Peripheral data format is Half-Word: number of data units is
612 * equal to total number of bytes to be transferred / 2.
613 *
614 * @note If Peripheral data format is Word: number of data units is equal
615 * to total number of bytes to be transferred / 4.
616 *
617 * @retval The number of remaining data units in the current DMAy Streamx transfer.
618 */
619#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
620
621/**
622 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
623 * @param __HANDLE__: DMA handle
624 *
625 * @retval The number of remaining data units in the current DMA Stream transfer.
626 */
627#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
628
629
630/* Include DMA HAL Extension module */
631#include "stm32f4xx_hal_dma_ex.h"
632
633/* Exported functions --------------------------------------------------------*/
634
635/** @defgroup DMA_Exported_Functions DMA Exported Functions
636 * @brief DMA Exported functions
637 * @{
638 */
639
640/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
641 * @brief Initialization and de-initialization functions
642 * @{
643 */
644HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
645HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
646/**
647 * @}
648 */
649
650/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
651 * @brief I/O operation functions
652 * @{
653 */
654HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
655HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
656HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
657HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
658void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
659/**
660 * @}
661 */
662
663/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
664 * @brief Peripheral State functions
665 * @{
666 */
667HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
668uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
669/**
670 * @}
671 */
672/**
673 * @}
674 */
675/* Private Constants -------------------------------------------------------------*/
676/** @defgroup DMA_Private_Constants DMA Private Constants
677 * @brief DMA private defines and constants
678 * @{
679 */
680/**
681 * @}
682 */
683
684/* Private macros ------------------------------------------------------------*/
685/** @defgroup DMA_Private_Macros DMA Private Macros
686 * @brief DMA private macros
687 * @{
688 */
689#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
690 ((CHANNEL) == DMA_CHANNEL_1) || \
691 ((CHANNEL) == DMA_CHANNEL_2) || \
692 ((CHANNEL) == DMA_CHANNEL_3) || \
693 ((CHANNEL) == DMA_CHANNEL_4) || \
694 ((CHANNEL) == DMA_CHANNEL_5) || \
695 ((CHANNEL) == DMA_CHANNEL_6) || \
696 ((CHANNEL) == DMA_CHANNEL_7))
697
698#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
699 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
700 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
701
702#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
703
704#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
705 ((STATE) == DMA_PINC_DISABLE))
706
707#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
708 ((STATE) == DMA_MINC_DISABLE))
709
710#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
711 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
712 ((SIZE) == DMA_PDATAALIGN_WORD))
713
714#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
715 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
716 ((SIZE) == DMA_MDATAALIGN_WORD ))
717
718#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
719 ((MODE) == DMA_CIRCULAR) || \
720 ((MODE) == DMA_PFCTRL))
721
722#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
723 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
724 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
725 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
726
727#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
728 ((STATE) == DMA_FIFOMODE_ENABLE))
729
730#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
731 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
732 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
733 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
734
735#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
736 ((BURST) == DMA_MBURST_INC4) || \
737 ((BURST) == DMA_MBURST_INC8) || \
738 ((BURST) == DMA_MBURST_INC16))
739
740#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
741 ((BURST) == DMA_PBURST_INC4) || \
742 ((BURST) == DMA_PBURST_INC8) || \
743 ((BURST) == DMA_PBURST_INC16))
744/**
745 * @}
746 */
747
748/* Private functions ---------------------------------------------------------*/
749/** @defgroup DMA_Private_Functions DMA Private Functions
750 * @brief DMA private functions
751 * @{
752 */
753/**
754 * @}
755 */
756
757/**
758 * @}
759 */
760
761/**
762 * @}
763 */
764
765#ifdef __cplusplus
766}
767#endif
768
769#endif /* __STM32F4xx_HAL_DMA_H */
770
771/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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