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source: asp3_wo_tecs/trunk/arch/arm_m_gcc/stm32f4xx_stm32cube/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h@ 303

Last change on this file since 303 was 303, checked in by ertl-honda, 7 years ago
nucleo_f401re依存部の追加
File size: 20.4 KB

Line
1	/**
2	******************************************************************************
3	* @file stm32f4xx_hal_cortex.h
4	* @author MCD Application Team
5	* @version V1.4.1
6	* @date 09-October-2015
7	* @brief Header file of CORTEX HAL module.
8	******************************************************************************
9	* @attention
10	*
11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
12	*
13	* Redistribution and use in source and binary forms, with or without modification,
14	* are permitted provided that the following conditions are met:
15	* 1. Redistributions of source code must retain the above copyright notice,
16	* this list of conditions and the following disclaimer.
17	* 2. Redistributions in binary form must reproduce the above copyright notice,
18	* this list of conditions and the following disclaimer in the documentation
19	* and/or other materials provided with the distribution.
20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
21	* may be used to endorse or promote products derived from this software
22	* without specific prior written permission.
23	*
24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34	*
35	******************************************************************************
36	*/
37
38	/* Define to prevent recursive inclusion -------------------------------------*/
39	#ifndef __STM32F4xx_HAL_CORTEX_H
40	#define __STM32F4xx_HAL_CORTEX_H
41
42	#ifdef __cplusplus
43	extern "C" {
44	#endif
45
46	/* Includes ------------------------------------------------------------------*/
47	#include "stm32f4xx_hal_def.h"
48
49	/** @addtogroup STM32F4xx_HAL_Driver
50	* @{
51	*/
52
53	/** @addtogroup CORTEX
54	* @{
55	*/
56	/* Exported types ------------------------------------------------------------*/
57	/** @defgroup CORTEX_Exported_Types Cortex Exported Types
58	* @{
59	*/
60
61	#if (__MPU_PRESENT == 1)
62	/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
63	* @brief MPU Region initialization structure
64	* @{
65	*/
66	typedef struct
67	{
68	uint8_t Enable; /*!< Specifies the status of the region.
69	This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
70	uint8_t Number; /*!< Specifies the number of the region to protect.
71	This parameter can be a value of @ref CORTEX_MPU_Region_Number */
72	uint32_t BaseAddress; /!< Specifies the base address of the region to protect. /
73	uint8_t Size; /*!< Specifies the size of the region to protect.
74	This parameter can be a value of @ref CORTEX_MPU_Region_Size */
75	uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
76	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
77	uint8_t TypeExtField; /*!< Specifies the TEX field level.
78	This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
79	uint8_t AccessPermission; /*!< Specifies the region access permission type.
80	This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
81	uint8_t DisableExec; /*!< Specifies the instruction access status.
82	This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
83	uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
84	This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
85	uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
86	This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
87	uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
88	This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
89	}MPU_Region_InitTypeDef;
90	/**
91	* @}
92	*/
93	#endif /* __MPU_PRESENT */
94
95	/**
96	* @}
97	*/
98
99	/* Exported constants --------------------------------------------------------*/
100
101	/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
102	* @{
103	*/
104
105	/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
106	* @{
107	*/
108	#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
109	4 bits for subpriority */
110	#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
111	3 bits for subpriority */
112	#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
113	2 bits for subpriority */
114	#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
115	1 bits for subpriority */
116	#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
117	0 bits for subpriority */
118	/**
119	* @}
120	*/
121
122	/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
123	* @{
124	*/
125	#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
126	#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
127
128	/**
129	* @}
130	*/
131
132	#if (__MPU_PRESENT == 1)
133	/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
134	* @{
135	*/
136	#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
137	#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
138	#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
139	#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
140	/**
141	* @}
142	*/
143
144	/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
145	* @{
146	*/
147	#define MPU_REGION_ENABLE ((uint8_t)0x01)
148	#define MPU_REGION_DISABLE ((uint8_t)0x00)
149	/**
150	* @}
151	*/
152
153	/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
154	* @{
155	*/
156	#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
157	#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
158	/**
159	* @}
160	*/
161
162	/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
163	* @{
164	*/
165	#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
166	#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
167	/**
168	* @}
169	*/
170
171	/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
172	* @{
173	*/
174	#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
175	#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
176	/**
177	* @}
178	*/
179
180	/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
181	* @{
182	*/
183	#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
184	#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
185	/**
186	* @}
187	*/
188
189	/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
190	* @{
191	*/
192	#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
193	#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
194	#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
195	/**
196	* @}
197	*/
198
199	/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
200	* @{
201	*/
202	#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
203	#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
204	#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
205	#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
206	#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
207	#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
208	#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
209	#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
210	#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
211	#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
212	#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
213	#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
214	#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
215	#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
216	#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
217	#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
218	#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
219	#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
220	#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
221	#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
222	#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
223	#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
224	#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
225	#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
226	#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
227	#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
228	#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
229	#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
230	/**
231	* @}
232	*/
233
234	/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
235	* @{
236	*/
237	#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
238	#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
239	#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
240	#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
241	#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
242	#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
243	/**
244	* @}
245	*/
246
247	/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
248	* @{
249	*/
250	#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
251	#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
252	#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
253	#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
254	#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
255	#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
256	#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
257	#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
258	/**
259	* @}
260	*/
261	#endif /* __MPU_PRESENT */
262
263	/**
264	* @}
265	*/
266
267
268	/* Exported Macros -----------------------------------------------------------*/
269	/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
270	* @{
271	*/
272
273	/** @brief Configures the SysTick clock source.
274	* @param __CLKSRC__: specifies the SysTick clock source.
275	* This parameter can be one of the following values:
276	* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
277	* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
278	* @retval None
279	*/
280	#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \
281	do { \
282	if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \
283	{ \
284	SysTick->CTRL \|= SYSTICK_CLKSOURCE_HCLK; \
285	} \
286	else \
287	SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \
288	} while(0)
289	/**
290	* @}
291	*/
292
293	/* Exported functions --------------------------------------------------------*/
294	/** @addtogroup CORTEX_Exported_Functions
295	* @{
296	*/
297
298	/** @addtogroup CORTEX_Exported_Functions_Group1
299	* @{
300	*/
301	/* Initialization and de-initialization functions *****************************/
302	void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
303	void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
304	void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
305	void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
306	void HAL_NVIC_SystemReset(void);
307	uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
308	/**
309	* @}
310	*/
311
312	/** @addtogroup CORTEX_Exported_Functions_Group2
313	* @{
314	*/
315	/* Peripheral Control functions ***********************************************/
316	#if (__MPU_PRESENT == 1)
317	void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
318	#endif /* __MPU_PRESENT */
319	uint32_t HAL_NVIC_GetPriorityGrouping(void);
320	void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
321	uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
322	void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
323	void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
324	uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
325	void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
326	void HAL_SYSTICK_IRQHandler(void);
327	void HAL_SYSTICK_Callback(void);
328	/**
329	* @}
330	*/
331
332	/**
333	* @}
334	*/
335
336	/* Private types -------------------------------------------------------------*/
337	/* Private variables ---------------------------------------------------------*/
338	/* Private constants ---------------------------------------------------------*/
339	/* Private macros ------------------------------------------------------------*/
340	/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
341	* @{
342	*/
343	#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) \|\| \
344	((GROUP) == NVIC_PRIORITYGROUP_1) \|\| \
345	((GROUP) == NVIC_PRIORITYGROUP_2) \|\| \
346	((GROUP) == NVIC_PRIORITYGROUP_3) \|\| \
347	((GROUP) == NVIC_PRIORITYGROUP_4))
348
349	#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
350
351	#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
352
353	#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
354
355	#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) \|\| \
356	((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
357
358	#if (__MPU_PRESENT == 1)
359	#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) \|\| \
360	((STATE) == MPU_REGION_DISABLE))
361
362	#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) \|\| \
363	((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
364
365	#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) \|\| \
366	((STATE) == MPU_ACCESS_NOT_SHAREABLE))
367
368	#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) \|\| \
369	((STATE) == MPU_ACCESS_NOT_CACHEABLE))
370
371	#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) \|\| \
372	((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
373
374	#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) \|\| \
375	((TYPE) == MPU_TEX_LEVEL1) \|\| \
376	((TYPE) == MPU_TEX_LEVEL2))
377
378	#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) \|\| \
379	((TYPE) == MPU_REGION_PRIV_RW) \|\| \
380	((TYPE) == MPU_REGION_PRIV_RW_URO) \|\| \
381	((TYPE) == MPU_REGION_FULL_ACCESS) \|\| \
382	((TYPE) == MPU_REGION_PRIV_RO) \|\| \
383	((TYPE) == MPU_REGION_PRIV_RO_URO))
384
385	#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) \|\| \
386	((NUMBER) == MPU_REGION_NUMBER1) \|\| \
387	((NUMBER) == MPU_REGION_NUMBER2) \|\| \
388	((NUMBER) == MPU_REGION_NUMBER3) \|\| \
389	((NUMBER) == MPU_REGION_NUMBER4) \|\| \
390	((NUMBER) == MPU_REGION_NUMBER5) \|\| \
391	((NUMBER) == MPU_REGION_NUMBER6) \|\| \
392	((NUMBER) == MPU_REGION_NUMBER7))
393
394	#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) \|\| \
395	((SIZE) == MPU_REGION_SIZE_64B) \|\| \
396	((SIZE) == MPU_REGION_SIZE_128B) \|\| \
397	((SIZE) == MPU_REGION_SIZE_256B) \|\| \
398	((SIZE) == MPU_REGION_SIZE_512B) \|\| \
399	((SIZE) == MPU_REGION_SIZE_1KB) \|\| \
400	((SIZE) == MPU_REGION_SIZE_2KB) \|\| \
401	((SIZE) == MPU_REGION_SIZE_4KB) \|\| \
402	((SIZE) == MPU_REGION_SIZE_8KB) \|\| \
403	((SIZE) == MPU_REGION_SIZE_16KB) \|\| \
404	((SIZE) == MPU_REGION_SIZE_32KB) \|\| \
405	((SIZE) == MPU_REGION_SIZE_64KB) \|\| \
406	((SIZE) == MPU_REGION_SIZE_128KB) \|\| \
407	((SIZE) == MPU_REGION_SIZE_256KB) \|\| \
408	((SIZE) == MPU_REGION_SIZE_512KB) \|\| \
409	((SIZE) == MPU_REGION_SIZE_1MB) \|\| \
410	((SIZE) == MPU_REGION_SIZE_2MB) \|\| \
411	((SIZE) == MPU_REGION_SIZE_4MB) \|\| \
412	((SIZE) == MPU_REGION_SIZE_8MB) \|\| \
413	((SIZE) == MPU_REGION_SIZE_16MB) \|\| \
414	((SIZE) == MPU_REGION_SIZE_32MB) \|\| \
415	((SIZE) == MPU_REGION_SIZE_64MB) \|\| \
416	((SIZE) == MPU_REGION_SIZE_128MB) \|\| \
417	((SIZE) == MPU_REGION_SIZE_256MB) \|\| \
418	((SIZE) == MPU_REGION_SIZE_512MB) \|\| \
419	((SIZE) == MPU_REGION_SIZE_1GB) \|\| \
420	((SIZE) == MPU_REGION_SIZE_2GB) \|\| \
421	((SIZE) == MPU_REGION_SIZE_4GB))
422
423	#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
424	#endif /* __MPU_PRESENT */
425
426	/**
427	* @}
428	*/
429
430	/* Private functions ---------------------------------------------------------*/
431	/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
432	* @brief CORTEX private functions
433	* @{
434	*/
435
436	#if (__MPU_PRESENT == 1)
437	/**
438	* @brief Disables the MPU
439	* @retval None
440	*/
441	__STATIC_INLINE void HAL_MPU_Disable(void)
442	{
443	/* Disable fault exceptions */
444	SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
445
446	/* Disable the MPU */
447	MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
448	}
449
450	/**
451	* @brief Enables the MPU
452	* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
453	* NMI, FAULTMASK and privileged access to the default memory
454	* This parameter can be one of the following values:
455	* @arg MPU_HFNMI_PRIVDEF_NONE
456	* @arg MPU_HARDFAULT_NMI
457	* @arg MPU_PRIVILEGED_DEFAULT
458	* @arg MPU_HFNMI_PRIVDEF
459	* @retval None
460	*/
461	__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
462	{
463	/* Enable the MPU */
464	MPU->CTRL = MPU_Control \| MPU_CTRL_ENABLE_Msk;
465
466	/* Enable fault exceptions */
467	SCB->SHCSR \|= SCB_SHCSR_MEMFAULTENA_Msk;
468	}
469	#endif /* __MPU_PRESENT */
470
471	/**
472	* @}
473	*/
474
475	/**
476	* @}
477	*/
478
479	/**
480	* @}
481	*/
482
483	#ifdef __cplusplus
484	}
485	#endif
486
487	#endif /* __STM32F4xx_HAL_CORTEX_H */
488
489
490	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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