source: asp3_wo_tecs/trunk/arch/arm_m_gcc/stm32f4xx_stm32cube/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h@ 303

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1/**
2 ******************************************************************************
3 * @file stm32f4xx_hal_cec.h
4 * @author MCD Application Team
5 * @version V1.4.1
6 * @date 09-October-2015
7 * @brief Header file of CEC HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38/* Define to prevent recursive inclusion -------------------------------------*/
39#ifndef __STM32F4xx_HAL_CEC_H
40#define __STM32F4xx_HAL_CEC_H
41
42#ifdef __cplusplus
43 extern "C" {
44#endif
45
46#if defined(STM32F446xx)
47/* Includes ------------------------------------------------------------------*/
48#include "stm32f4xx_hal_def.h"
49
50/** @addtogroup STM32F4xx_HAL_Driver
51 * @{
52 */
53
54/** @addtogroup CEC
55 * @{
56 */
57
58/* Exported types ------------------------------------------------------------*/
59/** @defgroup CEC_Exported_Types CEC Exported Types
60 * @{
61 */
62
63/**
64 * @brief CEC Init Structure definition
65 */
66typedef struct
67{
68 uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
69 It can be one of @ref CEC_Signal_Free_Time
70 and belongs to the set {0,...,7} where
71 0x0 is the default configuration
72 else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
73
74 uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
75 it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
76 or CEC_EXTENDED_TOLERANCE */
77
78 uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
79 CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
80 CEC_RX_STOP_ON_BRE: reception is stopped. */
81
82 uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
83 CEC line upon Bit Rising Error detection.
84 CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
85 CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
86
87 uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
88 CEC line upon Long Bit Period Error detection.
89 CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
90 CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
91
92 uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
93 upon an error detected on a broadcast message.
94
95 It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
96
97 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
98 a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
99 and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
100 b) LBPE detection: error-bit generation on the CEC line
101 if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
102
103 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
104 no error-bit generation in case neither a) nor b) are satisfied. Additionally,
105 there is no error-bit generation in case of Short Bit Period Error detection in
106 a broadcast message while LSTN bit is set. */
107
108 uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
109 CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
110 CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
111
112 uint32_t OwnAddress; /*!< Set OAR field, specifies CEC device address within a 15-bit long field */
113
114 uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
115
116 CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
117 own address (OAR). Messages addressed to different destination are ignored.
118 Broadcast messages are always received.
119
120 CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
121 address (OAR) with positive acknowledge. Messages addressed to different destination
122 are received, but without interfering with the CEC bus: no acknowledge sent. */
123
124 uint8_t InitiatorAddress; /* Initiator address (source logical address, sent in each header) */
125
126}CEC_InitTypeDef;
127
128/**
129 * @brief HAL CEC State structures definition
130 */
131typedef enum
132{
133 HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */
134 HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
135 HAL_CEC_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
136 HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
137 HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
138 HAL_CEC_STATE_STANDBY_RX = 0x05, /*!< IP ready to receive, doesn't prevent IP to transmit */
139 HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */
140 HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */
141}HAL_CEC_StateTypeDef;
142
143/**
144 * @brief CEC handle Structure definition
145 */
146typedef struct
147{
148 CEC_TypeDef *Instance; /* CEC registers base address */
149
150 CEC_InitTypeDef Init; /* CEC communication parameters */
151
152 uint8_t *pTxBuffPtr; /* Pointer to CEC Tx transfer Buffer */
153
154 uint16_t TxXferCount; /* CEC Tx Transfer Counter */
155
156 uint8_t *pRxBuffPtr; /* Pointer to CEC Rx transfer Buffer */
157
158 uint16_t RxXferSize; /* CEC Rx Transfer size, 0: header received only */
159
160 uint32_t ErrorCode; /* For errors handling purposes, copy of ISR register
161 in case error is reported */
162
163 HAL_LockTypeDef Lock; /* Locking object */
164
165 HAL_CEC_StateTypeDef State; /* CEC communication state */
166
167}CEC_HandleTypeDef;
168/**
169 * @}
170 */
171
172/* Exported constants --------------------------------------------------------*/
173/** @defgroup CEC_Exported_Constants CEC Exported Constants
174 * @{
175 */
176
177/** @defgroup CEC_Error_Code CEC Error Code
178 * @{
179 */
180#define HAL_CEC_ERROR_NONE (uint32_t) 0x0 /*!< no error */
181#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
182#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
183#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
184#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
185#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
186#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
187#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
188#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
189#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
190/**
191 * @}
192 */
193
194/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
195 * @{
196 */
197#define CEC_DEFAULT_SFT ((uint32_t)0x00000000)
198#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001)
199#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002)
200#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003)
201#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004)
202#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005)
203#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006)
204#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007)
205/**
206 * @}
207 */
208
209/** @defgroup CEC_Tolerance CEC Receiver Tolerance
210 * @{
211 */
212#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000)
213#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
214/**
215 * @}
216 */
217
218/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
219 * @{
220 */
221#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000)
222#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
223/**
224 * @}
225 */
226
227/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
228 * @{
229 */
230#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
231#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
232/**
233 * @}
234 */
235
236/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
237 * @{
238 */
239#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
240#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
241/**
242 * @}
243 */
244
245/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
246 * @{
247 */
248#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000)
249#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
250/**
251 * @}
252 */
253
254/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
255 * @{
256 */
257#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000)
258#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
259/**
260 * @}
261 */
262
263/** @defgroup CEC_Listening_Mode CEC Listening mode option
264 * @{
265 */
266#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000)
267#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
268/**
269 * @}
270 */
271
272/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
273 * @{
274 */
275#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16)
276/**
277 * @}
278 */
279
280/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
281 * @{
282 */
283#define CEC_INITIATOR_LSB_POS ((uint32_t) 4)
284/**
285 * @}
286 */
287
288/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
289 * @{
290 */
291#define CEC_IT_TXACKE CEC_IER_TXACKEIE
292#define CEC_IT_TXERR CEC_IER_TXERRIE
293#define CEC_IT_TXUDR CEC_IER_TXUDRIE
294#define CEC_IT_TXEND CEC_IER_TXENDIE
295#define CEC_IT_TXBR CEC_IER_TXBRIE
296#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
297#define CEC_IT_RXACKE CEC_IER_RXACKEIE
298#define CEC_IT_LBPE CEC_IER_LBPEIE
299#define CEC_IT_SBPE CEC_IER_SBPEIE
300#define CEC_IT_BRE CEC_IER_BREIE
301#define CEC_IT_RXOVR CEC_IER_RXOVRIE
302#define CEC_IT_RXEND CEC_IER_RXENDIE
303#define CEC_IT_RXBR CEC_IER_RXBRIE
304/**
305 * @}
306 */
307
308/** @defgroup CEC_Flags_Definitions CEC Flags definition
309 * @{
310 */
311#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
312#define CEC_FLAG_TXERR CEC_ISR_TXERR
313#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
314#define CEC_FLAG_TXEND CEC_ISR_TXEND
315#define CEC_FLAG_TXBR CEC_ISR_TXBR
316#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
317#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
318#define CEC_FLAG_LBPE CEC_ISR_LBPE
319#define CEC_FLAG_SBPE CEC_ISR_SBPE
320#define CEC_FLAG_BRE CEC_ISR_BRE
321#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
322#define CEC_FLAG_RXEND CEC_ISR_RXEND
323#define CEC_FLAG_RXBR CEC_ISR_RXBR
324/**
325 * @}
326 */
327
328/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
329 * @{
330 */
331#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
332 CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
333/**
334 * @}
335 */
336
337/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
338 * @{
339 */
340#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
341/**
342 * @}
343 */
344
345/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
346 * @{
347 */
348#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
349/**
350 * @}
351 */
352
353/**
354 * @}
355 */
356
357/* Exported macros -----------------------------------------------------------*/
358/** @defgroup CEC_Exported_Macros CEC Exported Macros
359 * @{
360 */
361
362/** @brief Reset CEC handle state
363 * @param __HANDLE__: CEC handle.
364 * @retval None
365 */
366#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
367
368/** @brief Checks whether or not the specified CEC interrupt flag is set.
369 * @param __HANDLE__: specifies the CEC Handle.
370 * @param __FLAG__: specifies the interrupt to check.
371 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
372 * @arg CEC_FLAG_TXERR: Tx Error.
373 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
374 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
375 * @arg CEC_FLAG_TXBR: Tx-Byte Request.
376 * @arg CEC_FLAG_ARBLST: Arbitration Lost
377 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
378 * @arg CEC_FLAG_LBPE: Rx Long period Error
379 * @arg CEC_FLAG_SBPE: Rx Short period Error
380 * @arg CEC_FLAG_BRE: Rx Bit Rissing Error
381 * @arg CEC_FLAG_RXOVR: Rx Overrun.
382 * @arg CEC_FLAG_RXEND: End Of Reception.
383 * @arg CEC_FLAG_RXBR: Rx-Byte Received.
384 * @retval ITStatus
385 */
386#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
387
388/** @brief Clears the interrupt or status flag when raised (write at 1)
389 * @param __HANDLE__: specifies the CEC Handle.
390 * @param __FLAG__: specifies the interrupt/status flag to clear.
391 * This parameter can be one of the following values:
392 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
393 * @arg CEC_FLAG_TXERR: Tx Error.
394 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
395 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
396 * @arg CEC_FLAG_TXBR: Tx-Byte Request.
397 * @arg CEC_FLAG_ARBLST: Arbitration Lost
398 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
399 * @arg CEC_FLAG_LBPE: Rx Long period Error
400 * @arg CEC_FLAG_SBPE: Rx Short period Error
401 * @arg CEC_FLAG_BRE: Rx Bit Rissing Error
402 * @arg CEC_FLAG_RXOVR: Rx Overrun.
403 * @arg CEC_FLAG_RXEND: End Of Reception.
404 * @arg CEC_FLAG_RXBR: Rx-Byte Received.
405 * @retval none
406 */
407#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
408
409/** @brief Enables the specified CEC interrupt.
410 * @param __HANDLE__: specifies the CEC Handle.
411 * @param __INTERRUPT__: specifies the CEC interrupt to enable.
412 * This parameter can be one of the following values:
413 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
414 * @arg CEC_IT_TXERR: Tx Error IT Enable
415 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
416 * @arg CEC_IT_TXEND: End of transmission IT Enable
417 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
418 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
419 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
420 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
421 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
422 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
423 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
424 * @arg CEC_IT_RXEND: End Of Reception IT Enable
425 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
426 * @retval none
427 */
428#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
429
430/** @brief Disables the specified CEC interrupt.
431 * @param __HANDLE__: specifies the CEC Handle.
432 * @param __INTERRUPT__: specifies the CEC interrupt to disable.
433 * This parameter can be one of the following values:
434 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
435 * @arg CEC_IT_TXERR: Tx Error IT Enable
436 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
437 * @arg CEC_IT_TXEND: End of transmission IT Enable
438 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
439 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
440 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
441 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
442 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
443 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
444 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
445 * @arg CEC_IT_RXEND: End Of Reception IT Enable
446 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
447 * @retval none
448 */
449#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
450
451/** @brief Checks whether or not the specified CEC interrupt is enabled.
452 * @param __HANDLE__: specifies the CEC Handle.
453 * @param __INTERRUPT__: specifies the CEC interrupt to check.
454 * This parameter can be one of the following values:
455 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
456 * @arg CEC_IT_TXERR: Tx Error IT Enable
457 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
458 * @arg CEC_IT_TXEND: End of transmission IT Enable
459 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
460 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
461 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
462 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
463 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
464 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
465 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
466 * @arg CEC_IT_RXEND: End Of Reception IT Enable
467 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
468 * @retval FlagStatus
469 */
470#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
471
472/** @brief Enables the CEC device
473 * @param __HANDLE__: specifies the CEC Handle.
474 * @retval none
475 */
476#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
477
478/** @brief Disables the CEC device
479 * @param __HANDLE__: specifies the CEC Handle.
480 * @retval none
481 */
482#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
483
484/** @brief Set Transmission Start flag
485 * @param __HANDLE__: specifies the CEC Handle.
486 * @retval none
487 */
488#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
489
490/** @brief Set Transmission End flag
491 * @param __HANDLE__: specifies the CEC Handle.
492 * @retval none
493 * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
494 */
495#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
496
497/** @brief Get Transmission Start flag
498 * @param __HANDLE__: specifies the CEC Handle.
499 * @retval FlagStatus
500 */
501#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
502
503/** @brief Get Transmission End flag
504 * @param __HANDLE__: specifies the CEC Handle.
505 * @retval FlagStatus
506 */
507#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
508
509/** @brief Clear OAR register
510 * @param __HANDLE__: specifies the CEC Handle.
511 * @retval none
512 */
513#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
514
515/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
516 * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
517 * @param __HANDLE__: specifies the CEC Handle.
518 * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
519 * @retval none
520 */
521#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
522
523/**
524 * @}
525 */
526
527/* Exported functions --------------------------------------------------------*/
528/** @addtogroup CEC_Exported_Functions
529 * @{
530 */
531
532/** @addtogroup CEC_Exported_Functions_Group1
533 * @{
534 */
535/* Initialization and de-initialization functions ****************************/
536HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
537HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
538void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
539void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
540/**
541 * @}
542 */
543
544/** @addtogroup CEC_Exported_Functions_Group2
545 * @{
546 */
547/* I/O operation functions ***************************************************/
548HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
549HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
550HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
551HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
552uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec);
553void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
554void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
555void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
556void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
557/**
558 * @}
559 */
560
561/** @addtogroup CEC_Exported_Functions_Group3
562 * @{
563 */
564/* Peripheral State functions ************************************************/
565HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
566uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
567/**
568 * @}
569 */
570
571/**
572 * @}
573 */
574
575/* Private types -------------------------------------------------------------*/
576/** @defgroup CEC_Private_Types CEC Private Types
577 * @{
578 */
579
580/**
581 * @}
582 */
583
584/* Private variables ---------------------------------------------------------*/
585/** @defgroup CEC_Private_Variables CEC Private Variables
586 * @{
587 */
588
589/**
590 * @}
591 */
592
593/* Private constants ---------------------------------------------------------*/
594/** @defgroup CEC_Private_Constants CEC Private Constants
595 * @{
596 */
597
598/**
599 * @}
600 */
601
602/* Private macros ------------------------------------------------------------*/
603/** @defgroup CEC_Private_Macros CEC Private Macros
604 * @{
605 */
606
607#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
608
609#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
610 ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
611
612#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
613 ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
614
615#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
616 ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
617
618#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
619 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
620
621#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
622 ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
623
624#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
625 ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
626
627#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
628 ((__MODE__) == CEC_FULL_LISTENING_MODE))
629
630/** @brief Check CEC device Own Address Register (OAR) setting.
631 * OAR address is written in a 15-bit field within CEC_CFGR register.
632 * @param __ADDRESS__: CEC own address.
633 * @retval Test result (TRUE or FALSE).
634 */
635#define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF)
636
637/** @brief Check CEC initiator or destination logical address setting.
638 * Initiator and destination addresses are coded over 4 bits.
639 * @param __ADDRESS__: CEC initiator or logical address.
640 * @retval Test result (TRUE or FALSE).
641 */
642#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
643
644/** @brief Check CEC message size.
645 * The message size is the payload size: without counting the header,
646 * it varies from 0 byte (ping operation, one header only, no payload) to
647 * 15 bytes (1 opcode and up to 14 operands following the header).
648 * @param __SIZE__: CEC message size.
649 * @retval Test result (TRUE or FALSE).
650 */
651#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
652
653/**
654 * @}
655 */
656
657/* Private functions ---------------------------------------------------------*/
658/** @defgroup CEC_Private_Functions CEC Private Functions
659 * @{
660 */
661
662/**
663 * @}
664 */
665
666/**
667 * @}
668 */
669
670/**
671 * @}
672 */
673#endif /* STM32F446xx */
674
675#ifdef __cplusplus
676}
677#endif
678
679#endif /* __STM32F4xx_HAL_CEC_H */
680
681/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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